Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first region, a second region and a third region, the first region and the second region are adjacent, and the third region is located between the first region and the second region; the first channel structure is located on the first region, the second channel structure is located on the second region, and the first channel structure comprises a plurality of first channel layers which are overlapped in the direction perpendicular to the surface of the substrate and are separated from one another; the second channel structure comprises a plurality of second channel layers which are overlapped in the direction perpendicular to the surface of the substrate and are separated from one another; the grid electrode stretches across the first channel structure and the second channel structure, the grid electrode is further located between the adjacent first channel layers and between the adjacent second channel layers, the surface of the third region is provided with an isolation structure, or the surface of the third region is in direct contact with the grid electrode. According to the semiconductor structure and the forming method thereof, the structure defect of the full-surrounding gate field effect transistor is reduced, the process window is improved, and the device performance is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As integrated circuits become increasingly integrated, their device sizes are shrinking. In recent years, transistor structures, exemplified by gate-all-around (GAA) field-effect transistors, have been adopted in various semiconductor devices. A gate-all-around field-effect transistor consists of multiple, separated and stacked channel layers. A metal gate completely surrounds the channel layers, effectively reducing leakage and controlling current flow, resulting in devices with improved performance and lower power consumption.

[0003] Because the channel layers of a gate-all-around field-effect transistor are stacked on top of each other, with a gate gap between them, the gate dielectric layer, work function layer, and gate electrode all surround the channel layers, thus filling the gate gap. The thickness and material of the work function layer control the threshold voltage of different transistors, allowing different regions of the device to perform corresponding functions.

[0004] However, in the prior art, all-around gate field-effect transistors have many structural defects and a small process window, resulting in a need to improve device performance. Summary of the Invention

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a method for forming the same, which reduces the structural defects of the all-around gate field-effect transistor, improves the process window, and enhances the device performance.

[0006] To solve the above-mentioned technical problems, the technical solution of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region, a second region and a third region located between the first region and the second region; a first channel structure located on the first region and a second channel structure located on the second region, the first channel structure comprising a plurality of first channel layers that overlap and are separated from each other in a direction perpendicular to the substrate surface, the second channel structure comprising a plurality of second channel layers that overlap and are separated from each other in a direction perpendicular to the substrate surface; a gate spanning the first channel structure and the second channel structure, the gate being further located between adjacent first channel layers and between adjacent second channel layers, the surface of the third region having an isolation structure, or the surface of the third region being in direct contact with the gate.

[0007] Optionally, the isolation structure includes an isolation sidewall and a first work function layer and a second work function layer respectively located on sidewall surfaces on opposite sides of the isolation sidewall.

[0008] Optionally, the isolation structure includes: a first work function layer and a second work function layer located on a surface of the first work function layer.

[0009] Correspondingly, the technical solution of the present application also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region, a second region and a third region located between the first region and the second region; forming a plurality of first initial channel structures located on the first region and a plurality of second initial channel structures located on the second region, the first initial channel structure comprising a plurality of first channel layers that overlap and are separated from each other in a direction perpendicular to the substrate surface and a first sacrificial layer between adjacent first channel layers, the second initial channel structure comprising a plurality of second channel layers that overlap and are separated from each other in a direction perpendicular to the substrate surface and a second sacrificial layer between adjacent second channel layers; forming an initial dummy gate material layer on the substrate, the first initial channel structure and the second initial channel structure, the initial dummy gate material layer having an initial isolation layer located on the third region; patterning the initial dummy gate material layer to form a A dummy gate spanning the first initial channel structure and the second initial channel structure, the initial isolation layer in the initial dummy gate material layer becomes an isolation sidewall; the dummy gate on the first region is removed, a first gate opening is formed in the dummy gate, the first gate opening exposes the first initial channel structure and the surface of the isolation sidewall; the first sacrificial layer is removed, the first gate opening exposes the surface of the first channel layer; after removing the first sacrificial layer, a first work function layer is formed on the surface of the first channel layer; the dummy gate on the second region is removed, a second gate opening is formed in the dummy gate, the second gate opening exposes the second initial channel structure and the surface of the isolation sidewall; the second sacrificial layer is removed, the second gate opening exposes the surface of the second channel layer; after removing the second sacrificial layer, a second work function layer is formed on the surface of the second channel layer, the thickness of the second work function layer is different from that of the first work function layer.

[0010] Optionally, the method for forming the initial pseudo gate material layer includes: forming a first material layer on the substrate, the first initial channel structure and the second initial channel structure; performing patterning on the first material layer to form an initial opening in the first material layer, the initial opening exposing the surfaces of the second region and the third region; forming an initial isolation layer located on the third region on the sidewall of the initial opening; filling the second material layer in the initial opening, the first material layer, the second material layer and the initial isolation layer constitute the initial pseudo gate material layer.

[0011] Optionally, the method for patterning the initial pseudo gate material layer includes: forming a mask structure on the initial pseudo gate material layer, the mask structure exposing a portion of the surface of the initial pseudo gate material layer; using the mask structure as a mask, etching the initial pseudo gate material layer to form a pseudo gate on the substrate, and the initial isolation layer within the initial pseudo gate material layer becomes an isolation side wall within the pseudo gate.

[0012] Optionally, after patterning the initial dummy gate material layer, the method further includes: planarizing the dummy gate until the surface of the isolation sidewall is exposed.

[0013] Optionally, after forming the dummy gate and before forming the first gate opening, it also includes: forming a gate sidewall on the sidewalls of the first initial channel structure and the second initial channel structure; etching the first initial channel structure and the second initial channel structure on both sides of the dummy gate to form a source and drain region on the substrate on both sides of the dummy gate, and the gate sidewall is located between the source and drain region and the dummy gate.

[0014] Optionally, the thickness of the isolation sidewall is in the range of 5 nanometers to 20 nanometers.

[0015] Optionally, the method for forming the first gate opening includes: forming a first mask layer on the dummy gate, the first mask layer exposing the dummy gate surface on the first region; using the first mask layer as a mask, etching the dummy gate on the first region to form the first gate opening.

[0016] Optionally, after forming the first work function layer and before forming the second gate opening, the method further includes: filling the first gate opening with a first covering layer.

[0017] Optionally, the method for forming the second gate opening includes: forming a second mask layer on the dummy gate, the second mask layer exposing the dummy gate surface on the second region; using the second mask layer as a mask, etching the dummy gate on the second region to form the second gate opening.

[0018] Optionally, after removing the first sacrificial layer and before forming the first work function layer, the method further includes: forming a first gate dielectric layer on the surface of the first channel layer; after removing the second sacrificial layer and before forming the second work function layer, the method further includes: forming a second gate dielectric layer on the surface of the second channel layer, and the thickness of the first gate dielectric layer is the same as or different from the thickness of the second gate dielectric layer.

[0019] Optionally, after forming the second work function layer, the method further includes: etching back the isolation sidewalls to form an isolation structure on the third region.

[0020] Optionally, the height of the isolation structure in a direction perpendicular to the substrate surface is less than 100 nanometers.

[0021] Optionally, after forming the second work function layer, the method further includes: removing the isolation sidewalls on the third region.

[0022] Optionally, after forming the first work function layer and the second work function layer, the method further includes: removing the dummy gate; and forming a gate on the substrate, wherein the gate is also located between adjacent first channel layers and between adjacent second channel layers.

[0023] Optionally, after forming the second gate opening and before forming the second work function layer, the method further includes: removing the isolation sidewalls on the third region.

[0024] Optionally, the method for removing the dummy gate on the first region includes an isotropic wet etching process or an isotropic dry etching process; the method for removing the dummy gate on the second region includes an isotropic wet etching process or an isotropic dry etching process.

[0025] Compared with the prior art, the technical solution of the embodiment of the present application has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present application, since the dummy gate has an isolation sidewall located on the third region, in the subsequent process of removing the dummy gate on the first region and removing the first sacrificial layer, the isolation sidewall acts as a barrier layer in the etching process to avoid affecting the dummy gate and the second sacrificial layer on the second region, thereby improving the morphology of the first gate opening and reducing structural defects. At the same time, the presence of the isolation sidewall also provides a larger process window for the patterning process of the first gate opening. In addition, by successively removing the dummy gate and the sacrificial layer on different regions of the substrate, the work function layers on different regions are formed separately, and their formation processes are independent of each other, thereby being able to control the thickness of the work function layers on different regions separately, thereby achieving a difference in the thickness of the work function layers on different regions, and thus meeting the transistor device requirements in different regions. Based on this, the transistor structures formed in different regions have fewer defects and more uniform morphology, thereby improving the process window and enhancing device performance.

[0027] Furthermore, the thickness of the isolation sidewall ranges from 5 nanometers to 20 nanometers. At this thickness, the isolation sidewall can ensure its protective effect in the process of forming the first gate opening, avoiding adverse effects on the pseudo gate and the second sacrificial layer on the second region. This thickness also ensures that the formation process of the first mask layer has a larger process window, reduces the process difficulty, and reduces process defects.

[0028] Furthermore, by successively removing the dummy gate and sacrificial layer on different areas of the substrate to form a work function layer located on the surface of the channel layer, other areas of the substrate are not covered by the work function layer, thereby increasing the filling rate in the subsequent gate formation process and improving the electrical performance of the device.

[0029] In the semiconductor structure provided by the technical solution of the present application, the presence of the isolation structure reduces the structural defects of the work function layers on different device regions, increases the filling rate of the gate, and improves the electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The present invention is a schematic diagram of a cross-sectional structure of a transistor forming process;

[0031] Figures 2 to 13 is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present application;

[0032] Figures 14 to 18 It is a schematic cross-sectional structural diagram of the formation process of a semiconductor structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0033] As described in the background art, under the existing technology, all-around gate field effect transistors have many structural defects and a small process window, resulting in the need to improve device performance.

[0034] Figure 1 This is a cross-sectional diagram of the transistor formation process. Figure 1 The formation process includes: providing a substrate 100, wherein the substrate 100 includes a first region I and a second region II, wherein the first region I and the second region II are used to form transistors with different threshold voltages; forming a plurality of initial channel structures (not shown) on the first region I and the second region II, wherein the initial channel structures include a plurality of channel layers 102 overlapping in a direction perpendicular to the surface of the substrate 100 and a sacrificial layer (not shown) between adjacent channel layers 102; forming a dummy gate (not shown) across the initial channel structure; removing the dummy gate to form a gate opening (not shown); removing the sacrificial layer; forming a gate dielectric layer (not shown) and a work function layer 103 on the surface of the channel layer 102 on the first region I and the second region II within the gate opening; patterning and removing the work function layer 103 on the first region I, thereby making the thickness of the work function layer 103 on the first region I and the second region II different, thereby making the devices on the first region I and the second region II have different threshold voltages.

[0035] However, during the process of patterning and removing the work function layer 103 on the first region I, due to the gap between the channel layers 102 (eg Figure 1The work function layer 103 on the surface of the channel layer 102 is relatively narrow, so it is difficult to completely remove the work function layer 103 on the surface of the channel layer 102, thereby introducing structural defects. In addition, excessive removal can easily cause damage to the gate dielectric layer and other structures, resulting in a significant impact on device performance. In other embodiments, the dummy gate and sacrificial layer on the first and second regions can be removed in sequence, and the work function layer of the required thickness can be deposited on the surface of the channel layer in the corresponding regions to meet the different threshold voltage requirements of transistors in different regions. However, in such a process, the process of removing the dummy gates on the first and second regions in sequence can easily affect adjacent regions, thereby causing boundary displacement of different device regions, introducing structural defects, and affecting device performance.

[0036] To solve the above-mentioned technical problems, the technical solution of the present application provides a method for forming a semiconductor structure, wherein the formed dummy gate spans the initial channel structure on the first and second regions, and the dummy gate has an isolation sidewall located on the third region. Therefore, during the subsequent removal of the dummy gate and sacrificial layer on the first region, the isolation sidewall acts as a barrier layer in the etching process, avoiding any impact on the dummy gate and sacrificial layer on the second region, thereby reducing structural defects. In addition, by successively removing the dummy gate and sacrificial layer on different regions of the substrate, work function layers on different regions are formed separately, and their formation processes are independent of each other. As a result, the thickness of the work function layers on different regions can be controlled separately, thereby meeting the transistor device requirements of different regions, reducing structural defects, and improving device performance.

[0037] In order to make the above-mentioned objectives, features and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0038] Figures 2 to 13 This is a cross-sectional structural diagram of the formation process of a semiconductor structure according to an embodiment of the present application. Figure 2 , providing a substrate 200, wherein the substrate 200 includes an adjacent first region I, a second region II, and a third region III located between the first region I and the second region II.

[0039] The substrate 200 may be made of silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. Specifically, in this embodiment, the substrate 200 is made of silicon. In this embodiment, the substrate 200 includes a base (not shown) and a plurality of fin structures (not shown) located on the base.

[0040] In this embodiment, the first region I and the second region II are device regions, and the first region I and the second region II are used to form different transistor structures. The threshold voltage of the transistor structure on the first region I is different from the threshold voltage of the transistor structure on the second region II.

[0041] In this embodiment, the third region III provides a platform for the subsequent formation of an isolation structure. The isolation structure assists the patterning process of the structures on the first region I and the second region II, reducing defects that may be introduced during the patterning process.

[0042] In this embodiment, the substrate 200 also includes: a fourth region IV located on both sides of the first region I and the second region II, and the fourth region IV is a non-device region; a fifth region V located between the first region I and the fourth region IV and between the second region II and the fourth region IV, and the fifth region V provides space for an isolation structure between the device region and the non-device region.

[0043] Next, a bottom isolation layer 201 is formed between the fin structures; a plurality of first initial channel structures 205 are formed on the first region I and a plurality of second initial channel structures 210 are formed on the second region II, wherein the first initial channel structure 205 includes a plurality of first channel layers 204 that overlap and separate from each other in a direction perpendicular to the surface of the substrate 200 and a first sacrificial layer 203 between adjacent first channel layers 204, and the second initial channel structure 210 includes a plurality of second channel layers 212 that overlap and separate from each other in a direction perpendicular to the surface of the substrate 200 and a second sacrificial layer 211 between adjacent second channel layers 212.

[0044] In this embodiment, each of the first initial channel structures 205 and the second initial channel structure 210 extends along a first direction parallel to the surface of the substrate 200. Specifically, the method for forming the first initial channel structure 205 and the second initial channel structure 210 includes: forming a plurality of stacked sacrificial material layers (not shown) and channel material layers (not shown) on the substrate 200 and the isolation structure 260; and patterning the sacrificial material layers and the channel material layers to form a plurality of first initial channel structures 205 located on the first region I and a plurality of second initial channel structures 210 located on the second region II, wherein the first initial channel structure 205 includes a plurality of first channel layers 204 and first sacrificial layers 203 between adjacent first channel layers 204, and the second initial channel structure 210 includes a plurality of second channel layers 212 and second sacrificial layers 211 between adjacent second channel layers 212. In this embodiment, the sacrificial material layers and the channel material layers are made of different materials.

[0045] Next, an initial dummy gate material layer is formed on the substrate 200, the first initial channel structure 205 and the second initial channel structure 210. The initial dummy gate material layer includes an initial isolation layer located on the third region III and the fifth region V. The specific formation process is as follows: Figures 3 to 5 shown.

[0046] Please refer to Figure 3 A first material layer 215 is formed on the substrate 200, the first preliminary channel structure 205, and the second preliminary channel structure 210. In this embodiment, the material of the first material layer 215 is polysilicon. In this embodiment, the first material layer 215 is located on the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V of the substrate 200.

[0047] Please refer to Figure 4 , the first material layer 215 is patterned to form an initial opening (not marked) in the first material layer 215, and the initial opening exposes the second region II, the third region III, the fifth region V and part of the surface of the fourth region IV; an initial isolation layer 220 is formed on the sidewall of the initial opening and located on the third region III and the fifth region V.

[0048] In this embodiment, the initial opening extends along the first direction. The function of the initial opening is to locate the formation position of the initial isolation layer 220. The initial isolation layer 220 is located between the first zone I and the second zone II, between the first zone I and the fourth zone IV, and between the second zone II and the fourth zone IV, so that the boundaries of the first zone I and the second zone II both have an initial isolation layer 220.

[0049] In this embodiment, the process for forming the initial opening in the first material layer 215 includes an anisotropic dry etching process. In this embodiment, the material of the initial isolation layer 220 includes silicon nitride or silicon oxide. In this embodiment, the process for forming the initial isolation layer 220 includes an atomic layer deposition process or a chemical vapor deposition process.

[0050] Please refer to Figure 5 The initial opening is filled with a second material layer 216. The first material layer 215, the second material layer 216, and the initial isolation layer 220 constitute an initial dummy gate material layer 221. In this embodiment, the first material layer 215 and the second material layer 216 are made of the same material, polycrystalline silicon. In this embodiment, the second material layer 216 completely fills the initial opening and is also located on the first material layer 215, so that the surface of the initial isolation layer 220 is covered by the second material layer 216.

[0051] Please refer to Figure 6 , the initial dummy gate material layer 221 is patterned, and a dummy gate 225 spanning the first initial channel structure 205 and the second initial channel structure 210 is formed on the substrate 200 , and the initial isolation layer 220 in the initial dummy gate material layer 221 becomes an isolation sidewall 223 .

[0052] In this embodiment, the dummy gate 225 extends along a second direction, which is parallel to the surface of the substrate 200 and perpendicular to the first direction. Specifically, the method for patterning the initial dummy gate material layer 221 includes: forming a mask structure (not shown) on the initial dummy gate material layer 221, wherein the mask structure exposes a portion of the surface of the initial dummy gate material layer 221; using the mask structure as a mask, etching the initial dummy gate material layer 221 and the initial isolation layer 220 included therein to form a dummy gate 225 on the substrate 200, wherein the initial isolation layer 220 within the initial dummy gate material layer 221 becomes an isolation sidewall 223 within the dummy gate 225. In this embodiment, the isolation sidewall 223 provides a larger process window for the subsequent patterning process of the first gate opening, thereby protecting the structure on the second region II from being affected by the etching process.

[0053] In this embodiment, after patterning the initial dummy gate material layer 221 , the process further includes planarizing the dummy gate 225 until the surface of the isolation spacer 223 is exposed.

[0054] Next, gate sidewalls (not shown) are formed on the sidewalls of the first initial channel structure 205 and the second initial channel structure 210; the first initial channel structure 205 and the second initial channel structure 210 on both sides of the dummy gate 225 are etched to form source and drain regions (not shown) on the substrate 200 on both sides of the dummy gate 225, and the gate sidewalls are located between the source and drain regions and the dummy gate 225.

[0055] Next, an interlayer dielectric layer (not shown) is formed on the substrate 200 to surround the dummy gate 225 .

[0056] Please refer to Figure 7 A first mask layer 230 is formed on the dummy gate 225. The first mask layer 230 exposes the surface of the dummy gate 225 in the first region I. In this embodiment, the first mask layer 230 is used as a mask for a subsequent etching process to remove the dummy gate 225 in the first region I. In this embodiment, a portion of the first mask layer 230 is also located on the top surface of the isolation spacer 223 in the third region III and the fifth region V.

[0057] In this embodiment, the isolation sidewall 223 needs to have a certain thickness so that it can play a protective role in the subsequent formation of the first gate opening, preventing the dummy gate 225 on the second region II and the second sacrificial layer 211 from being adversely affected; at the same time, this thickness also ensures that the formation process of the first mask layer 230 has a larger process window. If the thickness of the isolation sidewall 223 is too thin, the offset of the photolithographic pattern of the first mask layer 230 will easily cause the dummy gate 225 on the second region II to be exposed, thereby removing the dummy gate 225 on the second region II during the formation of the first gate opening 232, thereby introducing structural defects. Therefore, the presence of the isolation sidewall 223 reduces the process difficulty and reduces process defects. Specifically, in this embodiment, the thickness H of the isolation sidewall 223 ranges from 5 nanometers to 20 nanometers.

[0058] Please refer to Figure 8 , using the first mask layer 230 as a mask, etch the dummy gate 225 on the first region I to form a first gate opening 232, the first gate opening 232 exposing the first initial channel structure 205 and the surface of the isolation sidewall 223; remove the first sacrificial layer 203, and the first gate opening 232 exposes the surface of the first channel layer 204.

[0059] In this embodiment, the method for removing the dummy gate 225 on the first region I includes an isotropic wet etching process or an isotropic dry etching process. In this embodiment, the process for removing the first sacrificial layer 203 includes a wet etching process. In this embodiment, due to the presence of the isolation spacer 223, during the process of removing the dummy gate 225 on the first region I and removing the first sacrificial layer 203, the isolation spacer 223 acts as a barrier layer in the etching process, avoiding the impact on the dummy gate 225 and the second sacrificial layer 211 on the second region II, thereby improving the morphology of the first gate opening 232 and reducing structural defects.

[0060] Please refer to Figure 9 A first gate dielectric layer 241 is formed on the surface of the first channel layer 204, and a first work function layer 242 is formed on the surface of the first gate dielectric layer 241. In this embodiment, the material of the first work function layer 242 includes titanium nitride, tantalum nitride, or a combination of the two.

[0061] In this embodiment, the first gate dielectric layer 241 is formed by an atomic layer deposition process or a chemical vapor deposition process; and the first work function layer 242 is formed by an atomic layer deposition process or a chemical vapor deposition process.

[0062] In this embodiment, by adjusting the thickness of the first work function layer 242, the threshold voltage of the transistor in the first region I can be adjusted. In this embodiment, the first gate dielectric layer 241 and the first work function layer 242 are also located on the surface of the first region I, the surface of the isolation spacer 223 in the third region III, and the surface of the isolation spacer 223 in the fifth region V.

[0063] Please refer to Figure 10 A first capping layer 243 is filled in the first gate opening 232. In this embodiment, the material of the first capping layer 243 is silicon. The function of the first capping layer 243 is to protect the first gate dielectric layer 241 and the first work function layer 242 in the first region I from being affected during the subsequent removal of the dummy gate 225 in the second region II. In addition, the first capping layer 243 is also used to protect the first work function layer 242 from oxidation during the subsequent annealing process.

[0064] Please refer to Figure 11 , remove the dummy gate 225 on the second region II, and form a second gate opening (not shown) in the dummy gate 225, the second gate opening exposing the second initial channel structure 210 and the surface of the isolation sidewall 223; remove the second sacrificial layer 211, and the second gate opening exposes the surface of the second channel layer 212; form a second gate dielectric layer 244 on the surface of the second channel layer 212; form a second work function layer 245 on the surface of the second gate dielectric layer 244, and the thickness of the second work function layer 245 is different from the thickness of the first work function layer 242.

[0065] In this embodiment, since the thickness of the second work function layer 245 is different from the thickness of the first work function layer 242, the transistors in the first region I and the transistors in the second region II can have different threshold voltages, thereby meeting different device design requirements. In this embodiment, the thickness of the first gate dielectric layer 241 and the second gate dielectric layer 244 can be the same or different.

[0066] Specifically, in this embodiment, the method for forming the second gate opening includes: forming a second mask layer (not shown) on the dummy gate 225, the second mask layer exposing the surface of the dummy gate 225 in the second region II; and etching the dummy gate 225 in the second region II using the second mask layer as a mask to form the second gate opening. The method for removing the dummy gate 225 in the second region II includes an isotropic wet etching process or an isotropic dry etching process; and the process for removing the second sacrificial layer 211 includes a wet etching process.

[0067] In this embodiment, the pseudo gate 225 and the sacrificial layer on the first region I and the second region II are successively removed, so that the work function layers on the first region I and the second region II are formed respectively, and their formation processes are independent of each other. Therefore, the deposition thickness of the work function layer on the first region I and the second region II can be controlled respectively, thereby achieving the thickness difference of the work function layer in different regions, and then meeting the threshold voltage requirements of transistor devices in different regions, without having to remove the work function layer on some regions in a graphical manner to achieve the thickness difference of the work function layer in different regions, so that the transistor structures formed in different regions have fewer defects and more uniform morphology, thereby improving the process window and enhancing device performance.

[0068] In this embodiment, the second gate dielectric layer 244 and the second work function layer 245 are also located on the surface of the second region II, the surface of the isolation spacer 223 on the third region III, and the surface of the isolation spacer 223 on the fifth region V.

[0069] Next, a second capping layer 246 is filled in the second gate opening, and an annealing process is performed on the structure on the first region I and the second region II. During the annealing process, the first capping layer 243 and the second capping layer 246 are used to protect the first work function layer 242 and the second work function layer 245 from oxidation.

[0070] Please refer to Figure 12 , the isolation spacer 223 is etched back to form an isolation structure 260 on the third region III and the fifth region V. In this embodiment, the isolation structure 260 on the third region III includes: an isolation spacer 223, and a first gate dielectric layer 241, a first work function layer 242, a second gate dielectric layer 244, and a second work function layer 245 respectively located on the sidewall surfaces of opposite sides of the isolation spacer 223.

[0071] During the etching back of the isolation spacer 223, the first gate dielectric layer 241, the first work function layer 242, the second gate dielectric layer 244, and the second work function layer 245 on the surface of the isolation spacer 223 are also etched back. Specifically, the height of the isolation structure 260 in a direction perpendicular to the surface of the substrate 200 is less than 100 nanometers.

[0072] In this embodiment, the isolation structure (not labeled) on the fifth region V adjacent to the first region I includes an isolation spacer 223 and a first gate dielectric layer 241 and a first work function layer 242 located on the sidewall surface of one side of the isolation spacer 223. The isolation structure (not labeled) on the fifth region V adjacent to the second region II includes an isolation spacer 223 and a second gate dielectric layer 244 and a second work function layer 245 located on the sidewall surface of one side of the isolation spacer 223. Specifically, the height of the isolation structure on the fifth region V is equal to the height of the isolation structure 260 on the third region III. In this embodiment, by etching back the isolation spacer 223, more space is released, thereby increasing the subsequent gate fill rate and improving device performance.

[0073] Please refer to Figure 13 , removing the dummy gate 225; and forming a gate 250 on the substrate 200. In this embodiment, the gate 250 is also located between adjacent first channel layers 204 and between adjacent second channel layers 212, thereby forming a full-surround gate transistor on the first region I and the second region II, and the transistor has a stronger control capability for the channel current. Specifically, the method of forming the gate 250 includes: removing the dummy gate 225; forming a gate material layer (not shown) on the substrate 200; and planarizing the gate material layer to form the gate 250.

[0074] In this embodiment, the non-device region of the substrate 200 , ie, the fourth region IV, is not covered by the work function layer. Therefore, the filling rate during the formation of the gate 250 is increased, and the electrical performance of the device is improved.

[0075] In another embodiment, the isolation sidewalls on the third region III and the fifth region V, as well as the first gate dielectric layer, the first work function layer, the second gate dielectric layer and the second work function layer on the surface of the isolation sidewalls can be etched back until they are completely removed, so that the surface of the third region III and the surface of the fifth region V are in direct contact with the gate, thereby further freeing up space on the substrate surface, thereby increasing the gate fill rate and improving device performance.

[0076] In another embodiment, after the isolation spacers, the first gate dielectric layer, the first work function layer, the second gate dielectric layer, and the second work function layer are formed, they may not be etched back, thereby simplifying the process flow.

[0077] Accordingly, the embodiment of the present application also provides a method of Figures 2 to 13 The semiconductor structure formed by the semiconductor structure forming method.

[0078] Please continue to refer to Figure 13The semiconductor structure includes: a substrate 200, the substrate 200 including a first region I, a second region II, and a third region III located between the first region I and the second region II; a first channel structure (not labeled) located on the first region I and a second channel structure (not labeled) located on the second region II, the first channel structure including a plurality of first channel layers 204 that overlap and are separated from each other in a direction perpendicular to the surface of the substrate 200, the second channel structure including a plurality of second channel layers 212 that overlap and are separated from each other in a direction perpendicular to the surface of the substrate 200; a gate 250 spanning the first channel structure and the second channel structure, the gate 250 also being located between adjacent first channel layers 204 and adjacent second channel layers 212, and the surface of the third region III having an isolation structure 260.

[0079] In this embodiment, the isolation structure 260 on the third region III includes an isolation spacer 223, and a first gate dielectric layer 241, a first work function layer 242, a second gate dielectric layer 244, and a second work function layer 245, respectively located on opposite sidewall surfaces of the isolation spacer 223. The height of the isolation structure 260 in a direction perpendicular to the surface of the substrate 200 is less than 100 nanometers.

[0080] In another embodiment, a surface of the third region III is in direct contact with the gate.

[0081] Figures 14 to 18 It is a schematic cross-sectional structural diagram of the formation process of a semiconductor structure according to another embodiment of the present application.

[0082] Please Figure 10 Based on reference Figure 14 After forming the first work function layer 242, the dummy gate 225 on the second region II is removed, and a second gate opening 324 is formed in the dummy gate 225, and the second gate opening 324 exposes the surface of the second initial channel structure 210 and the isolation sidewall 223; the second sacrificial layer 211 is removed, and the second gate opening 324 exposes the surface of the second channel layer 212.

[0083] Please refer to Figure 15 The isolation spacer 223 on the third region III is removed, and the second gate opening 324 exposes the surface of the first gate dielectric layer 241 on the third region III. Removing the isolation spacer 223 frees up space on the third region III, thereby increasing the fill rate during subsequent gate formation and improving the electrical performance of the device.

[0084] Please refer to Figure 16A second gate dielectric layer 344 is formed on the surface of the second channel layer 212; a second work function layer 345 is formed on the surface of the second gate dielectric layer 344. The thickness of the second work function layer 345 is different from that of the first work function layer 242. In this embodiment, the second gate dielectric layer 344 and the second work function layer 345 are also located on the surface of the first gate dielectric layer 241 on the third region III.

[0085] Next, a second capping layer 346 is filled into the second gate opening 324, and an annealing process is performed on the structure on the first region I and the second region II. During the annealing process, the first capping layer 243 and the second capping layer 346 are used to protect the first work function layer 242 and the second work function layer 345 from oxidation.

[0086] Please refer to Figure 17 , the first gate dielectric layer 241 , the first work function layer 242 , the second gate dielectric layer 344 and the second work function layer 345 on the third region III are etched back to form an isolation structure 360 ​​on the third region III.

[0087] In this embodiment, the isolation structure 360 ​​on the third region III includes a first gate dielectric layer 241, a first work function layer 242, and a second gate dielectric layer 344 and a second work function layer 345 located on the surface of the first gate dielectric layer 241. Specifically, the height of the isolation structure 360 ​​in a direction perpendicular to the surface of the substrate 200 is less than 100 nanometers.

[0088] In this embodiment, during the process of back-etching the first gate dielectric layer 241, the first work function layer 242, the second gate dielectric layer 344 and the second work function layer 345 on the third region III, the isolation sidewall 223, the first gate dielectric layer 241, the first work function layer 242, the second gate dielectric layer 344 and the second work function layer 345 on the fifth region V are simultaneously back-etched.

[0089] Please refer to Figure 18 , removing the dummy gate 225 and forming a gate 350 on the substrate 200. In this embodiment, the gate 350 is also located between adjacent first channel layers 204 and adjacent second channel layers 212, thereby forming a full-surround gate transistor on the first region I and the second region II.

[0090] In this embodiment, since the isolation sidewall 223 on the third region III is removed before forming the second work function layer 345, the volume of the isolation structure 360 ​​on the third region III is made smaller, thereby increasing the filling rate during the formation of the gate 350 and improving the electrical performance of the device.

[0091] In another embodiment, the isolation sidewall, the first gate dielectric layer, the first work function layer, the second gate dielectric layer and the second work function layer can be etched back until they are completely removed, so that the surface of the third region III and the surface of the fifth region V are in direct contact with the gate, thereby further freeing up space on the substrate surface, thereby increasing the gate fill rate and improving device performance.

[0092] In another embodiment, after the first gate dielectric layer, the first work function layer, the second gate dielectric layer, and the second work function layer are formed, they may not be etched back, thereby simplifying the process flow.

[0093] Accordingly, the embodiment of the present application also provides a method of Figures 14 to 18 The semiconductor structure formed by the semiconductor structure forming method.

[0094] Please continue to refer to Figure 18 The semiconductor structure includes: a substrate 200, the substrate 200 including a first region I, a second region II, and a third region III located between the first region I and the second region II; a first channel structure (not labeled) located on the first region I and a second channel structure (not labeled) located on the second region II, the first channel structure including a plurality of first channel layers 204 that overlap and are separated from each other in a direction perpendicular to the surface of the substrate 200, the second channel structure including a plurality of second channel layers 212 that overlap and are separated from each other in a direction perpendicular to the surface of the substrate 200; a gate 350 spanning the first channel structure and the second channel structure, the gate 350 also being located between adjacent first channel layers 204 and adjacent second channel layers 212, and the surface of the third region III having an isolation structure 360.

[0095] In this embodiment, the isolation structure 360 ​​on the third region III includes: a first gate dielectric layer 241, a first work function layer 242, and a second gate dielectric layer 344 and a second work function layer 345 located on the surface of the first gate dielectric layer 241. The height of the isolation structure 360 ​​in a direction perpendicular to the surface of the substrate 200 is less than 100 nanometers. In another embodiment, the surface of the third region III is in direct contact with the gate.

[0096] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first region, a second region adjacent to each other, and a third region located between the first region and the second region; a first channel structure located on the first region and a second channel structure located on the second region, wherein the first channel structure includes a plurality of first channel layers that overlap and are separated from each other in a direction perpendicular to the substrate surface, and the second channel structure includes a plurality of second channel layers that overlap and are separated from each other in a direction perpendicular to the substrate surface; A gate spans the first channel structure and the second channel structure, and the gate is also located between adjacent first channel layers and between adjacent second channel layers. The surface of the third region has an isolation structure, or the surface of the third region is in direct contact with the gate.

2. The semiconductor structure according to claim 1, wherein The isolation structure includes an isolation sidewall and a first work function layer and a second work function layer respectively located on the surfaces of two opposite sidewalls of the isolation sidewall.

3. The semiconductor structure according to claim 1, wherein: The isolation structure includes a first work function layer and a second work function layer located on a surface of the first work function layer.

4. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region, a second region adjacent to each other, and a third region located between the first region and the second region; forming a plurality of first initial channel structures on the first region and a plurality of second initial channel structures on the second region, wherein the first initial channel structures include a plurality of first channel layers that overlap and are separated from each other in a direction perpendicular to the substrate surface, and a first sacrificial layer between adjacent first channel layers; and the second initial channel structures include a plurality of second channel layers that overlap and are separated from each other in a direction perpendicular to the substrate surface, and a second sacrificial layer between adjacent second channel layers; forming an initial dummy gate material layer on the substrate, the first initial channel structure, and the second initial channel structure, wherein the initial dummy gate material layer includes an initial isolation layer located on the third region; Patterning the initial dummy gate material layer to form a dummy gate spanning the first initial channel structure and the second initial channel structure on the substrate, wherein the initial isolation layer in the initial dummy gate material layer serves as an isolation spacer; removing the dummy gate on the first region to form a first gate opening in the dummy gate, wherein the first gate opening exposes the first initial channel structure and the surface of the isolation sidewall; removing the first sacrificial layer, so that the first gate opening exposes the surface of the first channel layer; After removing the first sacrificial layer, forming a first work function layer on the surface of the first channel layer; removing the dummy gate on the second region, forming a second gate opening in the dummy gate, wherein the second gate opening exposes the second initial channel structure and the surface of the isolation sidewall; removing the second sacrificial layer, so that the second gate opening exposes the surface of the second channel layer; After removing the second sacrificial layer, a second work function layer is formed on the surface of the second channel layer, and the thickness of the second work function layer is different from that of the first work function layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the initial pseudo gate material layer includes: forming a first material layer on the substrate, the first initial channel structure and the second initial channel structure; performing patterning on the first material layer to form an initial opening in the first material layer, wherein the initial opening exposes the surfaces of the second region and the third region; forming an initial isolation layer located on the third region on the sidewall of the initial opening; and filling the initial opening with a second material layer, wherein the first material layer, the second material layer and the initial isolation layer constitute an initial pseudo gate material layer.

6. The method for forming a semiconductor structure according to claim 4, wherein: The method for patterning the initial pseudo gate material layer includes: forming a mask structure on the initial pseudo gate material layer, the mask structure exposing a portion of the surface of the initial pseudo gate material layer; using the mask structure as a mask, etching the initial pseudo gate material layer to form a pseudo gate on the substrate, and the initial isolation layer within the initial pseudo gate material layer becomes an isolation side wall within the pseudo gate.

7. The method for forming a semiconductor structure according to claim 6, wherein: After patterning the initial dummy gate material layer, the method further includes: planarizing the dummy gate until the surface of the isolation sidewall is exposed.

8. The method for forming a semiconductor structure according to claim 4, wherein: After forming the dummy gate and before forming the first gate opening, the method further includes: forming a gate sidewall on the sidewalls of the first initial channel structure and the second initial channel structure; etching the first initial channel structure and the second initial channel structure on both sides of the dummy gate to form a source and drain region on the substrate on both sides of the dummy gate, and the gate sidewall is located between the source and drain region and the dummy gate.

9. The method for forming a semiconductor structure according to claim 4, wherein: The thickness of the isolation sidewall is in the range of 5 nanometers to 20 nanometers.

10. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the first gate opening includes: forming a first mask layer on the dummy gate, the first mask layer exposing the dummy gate surface on the first region; using the first mask layer as a mask, etching the dummy gate on the first region to form the first gate opening.

11. The method for forming a semiconductor structure according to claim 4, wherein: After forming the first work function layer and before forming the second gate opening, the method further includes: filling the first gate opening with a first covering layer.

12. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the second gate opening includes: forming a second mask layer on the dummy gate, the second mask layer exposing the dummy gate surface on the second region; using the second mask layer as a mask, etching the dummy gate on the second region to form the second gate opening.

13. The method for forming a semiconductor structure according to claim 4, wherein: After removing the first sacrificial layer and before forming the first work function layer, the method further includes: forming a first gate dielectric layer on the surface of the first channel layer; after removing the second sacrificial layer and before forming the second work function layer, the method further includes: forming a second gate dielectric layer on the surface of the second channel layer, and the thickness of the first gate dielectric layer is the same as or different from the thickness of the second gate dielectric layer.

14. The method for forming a semiconductor structure according to claim 4, wherein: After forming the second work function layer, the method further includes: etching back the isolation sidewalls to form an isolation structure on the third region.

15. The method for forming a semiconductor structure according to claim 14, wherein: The height of the isolation structure in a direction perpendicular to the substrate surface is less than 100 nanometers.

16. The method for forming a semiconductor structure according to claim 4, wherein: After forming the second work function layer, the method further includes: removing the isolation sidewalls on the third region.

17. The method for forming a semiconductor structure according to claim 4, wherein: After forming the first work function layer and the second work function layer, the method further includes: removing the dummy gate; and forming a gate on the substrate, wherein the gate is also located between adjacent first channel layers and between adjacent second channel layers.

18. The method for forming a semiconductor structure according to claim 4, wherein: After forming the second gate opening and before forming the second work function layer, the method further includes: removing the isolation sidewalls on the third region.

19. The method for forming a semiconductor structure according to claim 4, wherein: The method for removing the dummy gate on the first region includes an isotropic wet etching process or an isotropic dry etching process; the method for removing the dummy gate on the second region includes an isotropic wet etching process or an isotropic dry etching process.

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