Semiconductor device and forming method thereof

Abstract

Semiconductor devices and methods of forming the same are provided. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, a first electrode, a separation conductive structure, and a source metal layer. The silicon carbide substrate has a first region and a first conductivity type. The epitaxial layer is disposed on the top surface of the silicon carbide substrate. The epitaxial layer has a first conductivity type. The first electrode is arranged in the epitaxial layer of the first region and extends along a first direction. The separated conductive structure is disposed in the epitaxial layer of the first region. The separate conductive structure includes a first conductive feature and a second conductive feature separated from each other on opposite sidewalls of the first electrode. The source metal layer is arranged on the epitaxial layer of the first region. The source metal layer covers and is electrically connected with the first conductive part, the second conductive part and the first electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a power transistor device of a Schottky diode and a method for forming the same. Background Art

[0002] The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the minimum component size, allowing more components to be integrated into a given area. For example, the trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET), widely used in power switch devices, utilizes a vertical structure design to reduce the cell pitch to increase functional density. It uses the back of the chip as the drain, while the source and gate of multiple transistors are fabricated on the front of the chip. As a result, the driving current flows in a vertical direction instead of in-plane, which enables the semiconductor device to achieve high reverse voltage resistance and low on-resistance.

[0003] However, as the functional density requirements for semiconductor devices continue to increase, the complexity of the components integrated into semiconductor devices and their formation methods has also increased, and there are certain electronic characteristics that require trade-offs in performance that need to be considered. Therefore, although existing semiconductor devices are generally suitable and sufficient for their intended purposes, they are not completely satisfactory in all aspects. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, a first electrode, a separated conductive structure, and a source metal layer. The silicon carbide substrate has a first region and has a first conductivity type. The epitaxial layer is arranged on the top surface of the silicon carbide substrate. The epitaxial layer has a first conductivity type. The first electrode is arranged in the epitaxial layer of the first region and extends along a first direction. The separated conductive structure is arranged in the epitaxial layer of the first region. The separated conductive structure includes a first conductive component and a second conductive component separated from each other, located on opposite side walls of the first electrode. The source metal layer is arranged on the epitaxial layer of the first region. The source metal layer covers and electrically connects the first conductive component, the second conductive component, and the first electrode.

[0005] Some embodiments of the present invention provide a method for forming a semiconductor device. The method includes providing a silicon carbide substrate having a first region and a first conductivity type; forming a first trench in an epitaxial layer of the first region along a first direction; forming a first electrode in the first trench, wherein the first electrode extends along the first direction; forming a separated conductive structure on opposite sidewalls of the first electrode, wherein the separated conductive structure includes a first conductive component and a second conductive component separated from each other; forming an interlayer dielectric layer throughout the entirety of the device; removing the interlayer dielectric layer on the top surface of the epitaxial layer of the first region, so that at least one of the first conductive component and the second conductive component and the first electrode are exposed from the remaining interlayer dielectric layer; and forming a source metal layer on the epitaxial layer of the first region, wherein the source metal layer covers and electrically connects the first electrode, the first conductive component, and the second conductive component.

[0006] Some embodiments of the present invention provide semiconductor devices and methods for forming the same, which can improve the switching characteristics of the semiconductor device and further reduce the forward voltage drop (VF) and reverse leakage current of the Schottky diode itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description will provide a better understanding of the present invention when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are provided for illustrative purposes only. Indeed, the dimensions of the elements may be arbitrarily increased or decreased to clearly illustrate the features of the present invention.

[0008] Figure 1A 、 Figure 1B Schematic cross-sectional views of semiconductor devices according to some embodiments of the present invention.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 To form Figure 1A 、 Figure 1B FIG2 is a schematic cross-sectional view of a semiconductor device at an intermediate stage according to some embodiments of the present invention.

[0010] Figure 23 To form Figure 1A 、 Figure 1B FIG2 is a schematic top view of a semiconductor device at an intermediate stage according to some embodiments of the present invention, showing the configuration of a source region and a wiring doping region above a well region.

[0011] Reference numerals:

[0012] 100:Silicon carbide substrate

[0013] 100T,200T,216T,216ART,216BRT,216CRT,220AT,220BT,220CT,220DT,220ART,220BRT,220CRT,220DRT,220F1T,220F2T,220F3T,224BRT,230AG1T,230AG2T,230BG1T,230BG2T,220F3T: Top

[0014] 100B,212A-B,212B-B,212C-B,212D-B,234B: Bottom

[0015] 200: epitaxial layer

[0016] 210: mask layer

[0017] 210P: Mask pattern

[0018] 212A, 212B, 212C, 212D: Grooves

[0019] 212A-S,212B-S,212C-S,212D-S,220F1S,220F2S,220F3S,240AS: Sidewall

[0020] 216, 216AR, 216BR, 216CR, 216DR: shielding dielectric layer

[0021] 220A, 220B, 220C, 220D, 220AR, 220BR, 220CR, 220DR: Conductive materials

[0022] 220AR-1, 220BR-1, 220CR-1: upper part

[0023] 220F1, 220F2, 220F3, 220F4: Electrode

[0024] 220F1-1,220AR-1,220BR-1,220CR-1: Top

[0025] 222,222DR: Oxide layer

[0026] 222T1,222T2: Upper surface

[0027] 224A, 224C, 224A-1, 224A-2, 224C-1, 224C-2, 224AR, 224C: Gate dielectric layer

[0028] 224B, 224B-1, 224B-2, 224BR: Dielectric layer

[0029] 230:Electrode material

[0030] 230AG: Split gate structure

[0031] 230BG: Separated conductive structure

[0032] 230AG1, 230AG2, 230G: Gate

[0033] 230BG1, 230BG2: Conductive parts

[0034] 234: Well region

[0035] 236: Source region

[0036] 238: Wiring doping area

[0037] 240, 240AR, 240BR, 240CR, 240DR: interlayer dielectric layer

[0038] 242A1,242A2,242C,244A1,244A2,244C: Open

[0039] 245: contact doping region

[0040] 246, 246S, 246G: Contact barrier layer

[0041] 248S1, 248S2, 248G: Contact conductive layer

[0042] 250G: Gate contact

[0043] 250S1, 250S2: Source contact

[0044] 254S: Source metal layer

[0045] 254G: Gate metal layer

[0046] 300,310,320: direction

[0047] 400: District 1

[0048] 400M: table area

[0049] 410: District 2

[0050] 420: District 3

[0051] 430: District 4

[0052] 500:Semiconductor devices

[0053] PR1, PR2, PR3, PR4, PR5, PR6: mask pattern

[0054] W1,W2,W3,W4,W5,W6,W7: Width DETAILED DESCRIPTION

[0055] The present invention is more fully described below with reference to the accompanying drawings illustrating embodiments of the present invention. However, the present invention may be implemented in a variety of different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers in the various drawings represent the same or similar elements. It will be understood that additional steps may be provided before, during, or after the method, and that some described steps may be replaced or deleted for other embodiments of the method.

[0056] Various embodiments or examples are provided below for implementing various components of the provided semiconductor structure. Reference to a first component being formed above a second component may include embodiments in which the first and second components are in direct contact, as well as embodiments in which an additional component is formed between the first and second components, preventing direct contact. Furthermore, embodiments of the present invention may use repeated reference numerals across multiple examples. This repetition is for simplicity and clarity purposes only and does not represent a specific relationship between the various embodiments and / or configurations discussed.

[0057] Furthermore, spatially relative terms such as "below," "beneath," "below," "above," "upper," and similar terms may be used in the following description to simplify the description of the relationship of one element or component to other elements or components as shown in the figures. Such spatially relative terms encompass not only the orientation depicted in the figures, but also different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0058] In a shielded gate trench MOSFET (SGTMOSFET) cell array, a Schottky diode can be provided to bypass the reverse current flowing through the SGT MOSFET to the Schottky diode to improve the switching characteristics of the semiconductor device. However, the forward voltage drop (V F Therefore, it is necessary to seek a semiconductor device with an isolated gate trench MOSFET and a method for forming the same, which can solve or improve the above-mentioned problems.

[0059] Figure 1A 、 Figure 1B Schematic cross-sectional view of a semiconductor device 500 according to some embodiments of the present invention. Figure 1A Schematic cross-sectional views of different regions of a semiconductor device 500 according to some embodiments of the present invention. Figure 1B A semiconductor device 500 ( Figure 1A ) is a schematic cross-sectional view of a cell region and a trench MOS barrier Schottky (TMBS) region, which shows the device configuration at the boundary between the cell region and the trench MOS barrier Schottky (TMBS) region. In some embodiments, the semiconductor device 500 includes a power metal oxide semiconductor field effect transistor (power MOSFET) and a Schottky diode, such as an isolation gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) integrated with the trench MOS barrier Schottky diode region and having a split-gate structure. Figure 1A 、 Figure 1B As shown, the semiconductor device 500 includes a silicon carbide (SiC) substrate 100, an epitaxial layer 200, an electrode 220F1, an electrode 220F2, a separation gate structure 230AG, a separation conductive structure 230BG, and a source metal layer 254S. Figure 1A 、 Figure 1BIn the following figures, directions 300 and 310 are substantially parallel to the top surface 100T of the silicon carbide substrate 100 and can also be considered as lateral directions. Direction 320 is substantially perpendicular to the top surface 100T of the silicon carbide substrate 100 and can also be considered as a longitudinal direction (or can be considered as a channel length direction). Furthermore, direction 300 is perpendicular to directions 310 and 320, direction 310 is perpendicular to directions 300 and 320, and direction 320 (can also be considered as a channel width direction) is perpendicular to directions 300 and 310.

[0060] like Figure 1A 、 Figure 1B As shown, the silicon carbide substrate 100 has a top surface 100T and a bottom surface 100B. Furthermore, the silicon carbide substrate 100 has a first region 400, a second region 410, a third region 420, and a fourth region 430. In some embodiments, the first region 400 may be a cell region in which a power metal oxide semiconductor field effect transistor array is formed. The second region 410 may be a trench Schottky diode region (TMBS region), which may be connected in parallel with the isolation gate trench metal oxide semiconductor field effect transistor unit in the cell region to reduce the on-resistance of the semiconductor device and thereby reduce power loss. The third region 420 may be a gate pickup region in which a gate contact is formed. In addition, the fourth region 430 may be a termination region, which is used to surround the cell region to serve as a buffer zone for the doped region in the cell region, thereby preventing a sharp drop in the device breakdown voltage at the cell region boundary. In the following embodiments, the cell region (first region 400) is described using a structure with two isolated-gate trench MOSFET units. The trench Schottky diode region (second region 410), the gate connection region (third region 420), and the terminal region (fourth region 430) are described using a structure with one trench electrode (e.g., a source electrode). However, any number of isolated-gate trench MOSFET units and trench electrodes may be provided in the cell region, the gate connection region, and the terminal region, and are not limited to the embodiments described herein.

[0061] In some embodiments, the conductivity type of the silicon carbide substrate 100 can be P-type or N-type depending on design requirements. In this embodiment, the silicon carbide substrate 100 can be doped with dopants to have a first conductivity type, such as N-type. In applications involving vertical trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), the silicon carbide substrate 100 having the first conductivity type can serve as the drain region of the final semiconductor device 500.

[0062] The epitaxial layer 200 is disposed on the top surface 100T of the silicon carbide substrate 100. In some embodiments, the epitaxial layer 200 may be doped with dopants to have a first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the epitaxial layer 200 is an N-type epitaxial layer 200. Furthermore, the doping concentration of the epitaxial layer 200 (e.g., about 10 15 -10 16 atoms / cm 3 ) is less than the doping concentration of the silicon carbide substrate 100 (10 19 -10 21 atoms / cm 3 For example, when the silicon carbide substrate 100 is an N-type heavily doped (N+) silicon carbide substrate 100, the epitaxial layer 200 is an N-type lightly doped (N-) epitaxial layer 200. In applications of vertical trench-gate metal oxide semiconductor field effect transistors (vertical trench-gate MOSFETs), the epitaxial layer 200 having the first conductivity type can serve as a drift region of the final semiconductor device 500. In some embodiments, the epitaxial layer 200 comprises silicon carbide.

[0063] The well region 234 of the semiconductor device 500 is located in the epitaxial layer 200 in the first region 400, the third region 420, and the fourth region 430, and is close to the top surface 200T of the epitaxial layer 200. In other words, the epitaxial layer 200 in the trench Schottky diode region (the second region 410) does not have a well region 234. In some embodiments, the well region 234 may be doped with dopants to have a second conductivity type opposite to the first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the well region 234 is a P-type well region 234. In addition, the above-mentioned dopants with the second conductivity type may include aluminum (Al), boron (B), or other suitable dopants. In some embodiments, the doping concentration of the well region 234 (for example, about 10 17 -10 18 atoms / cm 3 ) is greater than the doping concentration of the epitaxial layer 200. In some embodiments, the well region 234 may be formed using an ion implantation process. In applications of vertical trench-gate metal-oxide-semiconductor field-effect transistors, the well region 234 having the second conductivity type may serve as a channel region of the final semiconductor device 500.

[0064] The source region 236 of the semiconductor device 500 is located on the well region 234 in the first region 400 and is close to the top surface 200T of the epitaxial layer 200. In addition, the second region 410, the third region 420 and the fourth region 430 may not have the source region 236. Figure 1A 、 Figure 1B As shown, the source region 236 is surrounded by the well region 234. In some embodiments, the source region 236 may be doped with a dopant to have a first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the source region 236 is an N-type source region 236. Furthermore, the doping concentration of the source region 236 is greater than the doping concentration of the epitaxial layer 200. For example, when the epitaxial layer 200 is an N-type lightly doped (N-) epitaxial layer 200, the source region 236 is an N-type heavily doped (N+) source region 236.

[0065] The semiconductor device 500 further includes a wiring doping region 238 (see also FIG. 16 and FIG. 22 ). The wiring doping region 238 is located on the well region 234 in the first region 400 and is close to the top surface 200T of the epitaxial layer 200. Furthermore, the second region 410, the third region 420, and the fourth region 430 may not have the wiring doping region 238. Figure 16 As shown, the wiring doping region 238 is surrounded by the well region 234. The source region 236 and the wiring doping region 238 are adjacent to each other along direction 310. In addition, in some embodiments, multiple source regions 236 and multiple wiring doping regions 238 are staggered along direction 310. The source region 236 and the wiring doping region 238 may have opposite conductivity types. For example, when the source region 236 has a first conductivity type, the wiring doping region 238 has a second conductivity type. The wiring doping region 238 has the same conductivity type as the well region 234, for example, a P-type wiring doping region 238. Furthermore, the doping concentration of the wiring doping region 238 is greater than the doping concentration of the well region 234. For example, when the well region 234 is a P-type well region 234, the wiring doping region 238 is a P-type heavily doped (P+) wiring doping region 238, serving as the wiring doping region of the well region 234.

[0066] The semiconductor device 500 further includes shielding dielectric layers 216AR, 216BR, 216CR, 216DR and electrodes 220F1, 220F2, 220F3, 220F4. Figure 1A 、 Figure 1B As shown, the shielding dielectric layer 216AR and the electrode 220F1 are disposed in the epitaxial layer 200 in the first region 400. The shielding dielectric layer 216AR is located below the top surface 200T of the epitaxial layer 200. The electrode 220F1 is on the shielding dielectric layer 216AR, and the shielding dielectric layer 216AR covers the bottom surface and opposite sidewalls of the electrode 220F1. Figure 1A 、 Figure 1BAs shown, electrode 220F1 extends along direction 320 toward top surface 200T of epitaxial layer 200 and silicon carbide substrate 100. In some embodiments, in direction 300, width W1 of an upper portion of electrode 220F1 (including top portion 220F1-1) is smaller than width W2 of a lower portion of electrode 220F1.

[0067] like Figure 1A As shown, a shielding dielectric layer 216BR and an electrode 220F2 are disposed in the epitaxial layer 200 of the second region 410. The electrode 220F2 extends from a position near the top surface 200T of the epitaxial layer 200 along a direction 320 toward the silicon carbide substrate 100. The electrode 220F2 is located on the shielding dielectric layer 216BR, and the shielding dielectric layer 216BR covers the bottom surface and opposite sidewalls of the electrode 220F2. In some embodiments, in the direction 300, the width W3 of the upper portion of the electrode 220F2 is less than the width W4 of the lower portion of the electrode 220F2. In some embodiments, the width W1 may be equal to the width W3, and the width W2 may be equal to the width W4.

[0068] like Figure 1A As shown, a shielding dielectric layer 216CR and an electrode 220F3 are disposed in the epitaxial layer 200 of the third region 420. The electrode 220F3 extends from a position near the top surface 200T of the epitaxial layer 200 toward the silicon carbide substrate 100 along a direction 320. The electrode 220F3 is located on the shielding dielectric layer 216CR, and the shielding dielectric layer 216CR covers the bottom surface and opposite sidewalls of the electrode 220F3. In some embodiments, in the direction 300, the width W5 of the upper portion of the electrode 220F3 is less than the width W6 of the lower portion of the electrode 220F3. In some embodiments, the width W5 may be equal to the widths W1 and W3, and the width W6 may be equal to the widths W2 and W4.

[0069] like Figure 1A As shown, a shielding dielectric layer 216DR and an electrode 220F4 are disposed in the epitaxial layer 200 in the fourth region 430. The fourth electrode 220F4 extends from a position near the top surface 200T of the epitaxial layer 200 along a direction 320 toward the silicon carbide substrate 100. The electrode 220F4 is located on the shielding dielectric layer 216DR, and the shielding dielectric layer 216DR covers the bottom surface and opposite sidewalls of the electrode 220F4. In some embodiments, in the direction 300, the electrode 220F4 has a uniform width W7. In some embodiments, the width W7 may be equal to the widths W1, W3, and W5.

[0070] In some embodiments, the shielding dielectric layers 216AR, 216BR, 216CR, and 216DR may comprise the same material. For example, the shielding dielectric layers 216AR, 216BR, 216CR, and 216DR may comprise silicon oxide, other suitable semiconductor oxide materials, or combinations thereof. In some embodiments, the shielding dielectric layers 216AR, 216BR, 216CR, and 216DR may be formed using a conformable deposition process, an oxidation process, or other suitable formation process. In some embodiments, the oxidation process may be thermal oxidation or other suitable process. In some embodiments, the deposition process may be physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), other suitable processes, or combinations thereof.

[0071] In some embodiments, the electrodes 220F1, 220F2, 220F3, and 220F4 may optionally include a dopant of the second conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the electrodes 220F1, 220F2, 220F3, and 220F4 are respectively a P-type electrode 220F1, a P-type electrode 220F2, a P-type electrode 220F3, and a P-type electrode 220F4. Furthermore, the dopant of the second conductivity type may include aluminum (Al), boron (B), boron difluoride (BF2), or other suitable dopant. In some embodiments, the electrodes 220F1, 220F2, 220F3, and 220F4 are electrically connected to the source contacts 250S1 and 250S2.

[0072] In some embodiments, the electrode 220F1 of the first region 400 can reduce the gate-to-drain capacitance (C gd ) to improve the switching characteristics of the semiconductor device 500, and it has a field plate function, so that the gate dielectric layer (eg Figure 1A 、 Figure 1B The gate dielectric layer 224A shown (will be described later) has a more uniform electric field distribution and improves the breakdown voltage to improve the reliability of the gate dielectric layer. In some embodiments, the electrode 220F2 of the second region 410 also has a field plate function to make the electric field distribution of the epitaxial layer (drift region) 200 more uniform. By setting the electrodes 220F1 and 220F2, the doping concentration of the epitaxial layer (drift region) 200 can be further increased to reduce the on-resistance (R) of the isolation gate trench MOSFET unit in the first region 400. onsp), and reduce the forward voltage (V F ).

[0073] exist Figure 1A 、 Figure 1B In the embodiment shown, two split gate structures 230AG are disposed in the epitaxial layer 200 in the first region 400 and are located above the lower portion of the electrode 220F1. The two split gate structures 230AG are separated from each other by the epitaxial layer 200 along the direction 300. Furthermore, the region of the epitaxial layer 200 between the two split gate structures 230AG can be considered as a mesa region 400M of the semiconductor device 500. Figure 1A 、 Figure 1B As shown, the split gate structure 230AG extends along direction 320. In some embodiments, the split gate structure 230AG includes a gate dielectric layer 224AR and gates 230AG1 and 230AG2 separated from each other along direction 300. In some embodiments, the split gate structure 230AG can further reduce the overall gate-to-drain capacitance (C gd ) and feedback capacitor (C rss =C gd ) to improve the overall power conversion efficiency of the semiconductor device 500.

[0074] like Figure 1A 、 Figure 1B As shown, gate dielectric layer 224AR is disposed in epitaxial layer 200 in first region 400. Gate dielectric layer 224AR extends from near top surface 200T of epitaxial layer 200 into epitaxial layer 200 along direction 320. A top portion of electrode 220F1 is exposed from gate dielectric layer 224AR of split gate structure 230AG.

[0075] In some embodiments, the gate dielectric layer 224AR may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glass (OSG), a low-k dielectric material, and / or other suitable dielectric materials, or combinations thereof. In this embodiment, the gate dielectric layer 224AR may include silicon oxide. In some embodiments, the shielding dielectric layers 216AR, 216BR, and 216CR and the gate dielectric layer 224AR may be made of the same or different materials depending on actual needs. In some embodiments, the gate dielectric layer 224AR may be formed using an oxidation process and a deposition process. In some embodiments, the oxidation process may include thermal oxidation or other suitable processes. In some embodiments, the deposition process may include spin-on coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), other suitable processes, or combinations thereof.

[0076] Gates 230AG1 and 230AG2 are located on opposite sidewalls 220F1S of electrode 220F1 and extend along direction 320. Top surfaces 230AG1T and 230AG2T of gates 230AG1 and 230AG2 may be aligned with top surface 200T of epitaxial layer 200 (top surfaces 230AG1T, 230AG2T, 200T are coplanar). Furthermore, gate dielectric layer 224AR surrounds gates 230AG1 and 230AG2. Furthermore, electrode 220F1 may extend along direction 320 from below gates 230AG1 and 230AG2 to top surfaces 230AG1T and 230AG2T of gates 230AG1 and 230AG2. Furthermore, electrode 220F1 may be interposed between gates 230AG1 and 230AG2 along direction 300. Opposite sidewalls 220F1S of the electrode 220F1 proximate to the gates 230AG1 and 230AG2 are separated from the gates 230AG1 and 230AG2 by a gate dielectric layer 224AR.

[0077] In some embodiments, the gates 230AG1 and 230AG2 may be a single-layer or multi-layer structure formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. In some embodiments, the metal may include but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), and platinum (Pt). In some embodiments, the metal nitride may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include but is not limited to tungsten silicide (WSi x In some embodiments, gates 230AG1 and 230AG2 may optionally include a dopant of the second conductivity type. For example, when silicon carbide substrate 100 is an N-type silicon carbide substrate 100, gates 230AG1 and 230AG2 are P-type gates 230AG1 and 230AG2. Furthermore, the dopant of the second conductivity type may include aluminum (Al), boron (B), boron difluoride (BF2), or other suitable dopant. In some embodiments, electrodes 220F1, 220F2, 220F3, and 220F4 may include the same or different materials as gates 230AG1 and 230AG2.

[0078] like Figure 1A 、 Figure 1B As shown, a separate conductive structure 230BG is disposed in the epitaxial layer 200 of the second region 410. In some embodiments, the separate gate structure 230AG and the separate conductive structure 230BG may have similar structures. However, at least one difference between the separate conductive structure 230BG and the gates 230AG1 and 230AG2 is that the separate conductive structure 230BG is not surrounded by a well region 234. For example, the well region 234 may only be adjacent to one of the two opposite sides of the separate conductive structure 230BG along the direction 300, or may not be adjacent to the two opposite sides of the separate conductive structure 230BG along the direction 300. In some embodiments, the separate conductive structure 230BG includes conductive components 230BG1 and 230BG2 separated from each other along the direction 300.

[0079] like Figure 1A 、 Figure 1B As shown, semiconductor device 500 further includes a dielectric layer 224BR. Dielectric layer 224BR is disposed in epitaxial layer 200 in second region 410. Dielectric layer 224BR extends from a position proximate to top surface 200T of epitaxial layer 200 into epitaxial layer 200 along direction 320. A top surface 220F2T of electrode 220F2 is exposed from top surface 224BRT of dielectric layer 224BR. Specifically, top surface 220F2T of electrode 220F2 may be aligned with top surface 200T of epitaxial layer 200 (top surfaces 220F2T and 200T are coplanar).

[0080] In some embodiments, the dielectric layer 224BR and the gate dielectric layer 224AR may comprise the same or similar materials and processes. In this embodiment, the dielectric layer 224BR may comprise silicon oxide. In some embodiments, the shielding dielectric layers 216AR, 216BR, 216CR, the gate dielectric layer 224AR, and the dielectric layer 224BR may be made of the same or different materials depending on actual needs. In some embodiments, the dielectric layer 224BR and the gate dielectric layer 224AR may be formed simultaneously.

[0081] Conductive components 230BG1 and 230BG2 are located on opposite sidewalls 220F2S of electrode 220F2 and extend along direction 320. Top surfaces 230BG1T and 230BG2T of conductive components 230BG1 and 230BG2 may be aligned with top surface 200T of epitaxial layer 200 and top surface 220F2T of electrode 220F2 (top surfaces 230BG1T, 230BG2T, 200T, and 220F2T are coplanar). Dielectric layer 224BR surrounds conductive components 230BG1 and 230BG2. Furthermore, top surfaces 230BG1T and 230BG2T of conductive components 230BG1 and 230BG2 are exposed from top surface 224BRT of dielectric layer 224BR. Furthermore, the electrode 220F2 may extend from beneath the conductive components 230BG1 and 230BG2 to the top surfaces 230BG1T and 230BG2T of the conductive components 230BG1 and 230BG2 along a direction 320. Furthermore, the electrode 220F2 may be interposed between the conductive components 230BG1 and 230BG2 along a direction 300. The electrode 220F2 is separated from the conductive components 230BG1 and 230BG2 by the dielectric layer 224BR near opposite sidewalls 220F2S of the conductive components 230BG1 and 230BG2.

[0082] In some embodiments, the conductive components 230BG1 and 230BG2 may be a single-layer or multi-layer structure formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. In some embodiments, the metal may include but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), and platinum (Pt). In some embodiments, the metal nitride may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include but is not limited to tungsten silicide (WSi xIn some embodiments, the conductive components 230BG1 and 230BG2 may optionally include a dopant of the second conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the conductive components 230BG1 and 230BG2 are P-type conductive components 230BG1 and 230BG2. Furthermore, the dopant of the second conductivity type may include aluminum (Al), boron (B), boron difluoride (BF2), or other suitable dopant. In some embodiments, the electrodes 220F1, 220F2, 220F4, and 220F5 may include the same or different material as the conductive components 230BG1 and 230BG2.

[0083] The semiconductor device 500 further includes a gate dielectric layer 224C and a gate 230G disposed in the epitaxial layer 200 in the third region 420. The gate dielectric layer 224C extends from near the top surface 200T of the epitaxial layer 200 into the epitaxial layer 200 along a direction 320. Furthermore, the gate dielectric layer 224C covers the top of the electrode 220F3. The gate 230G is located on the gate dielectric layer 224C and is connected to the separate gate structure 230AG. In some embodiments, the gate 230G extends from opposite sidewalls 220F3S of the electrode 220F3 to cover the top surface 220F3T of the electrode 220F3 and the top surface 200T of the epitaxial layer 200. Portions of the gate 230G located on the opposite sidewalls 220F3S of the electrode 220F3 may extend along the direction 320. Furthermore, a portion of the gate 230G located above the top surface 220F3T of the electrode 220F3 and the top surface 200T of the epitaxial layer 200 may extend along the direction 300 .

[0084] The semiconductor device 500 further includes interlayer dielectric layers 240AR, 240CR, and 240DR. The interlayer dielectric layers 240AR, 240CR, and 240DR are disposed on the epitaxial layer 200 in the first region 400, the third region 420, and the fourth region 430. The interlayer dielectric layer 240AR covers the gate 230AG1, the gate 230AG2, the gate dielectric layer 224AR, the wiring doped region 238, and the gate 230G. The interlayer dielectric layer 240CR covers the gate dielectric layer 224C and the gate 230G. The interlayer dielectric layer 240CR covers the electrode 220F4. Furthermore, the conductive component 230BG1 and / or the conductive component 230BG2 and the electrode 220F2 may be exposed from the interlayer dielectric layers 240AR, 240CR, and 240DR. Figure 1A 、 Figure 1BAs shown, the top surface 200T of the epitaxial layer 200 in the second region 410 may not be completely covered by the interlayer dielectric layer. For example, the interlayer dielectric layer 240AR may extend from the top surface 200T of the epitaxial layer 200 in the first region 400 to cover the conductive component 230BG1 of the isolated conductive structure 230BG close to the first region 400, and expose the electrode 220F2 and the conductive component 230BG2. Figure 1B As shown, the sidewalls 240AS of the interlayer dielectric layer 240AR are located on the dielectric layer 224BR near the electrode 220F2, for example, on the dielectric layer 224BR between the conductive feature 230BG1 and the electrode 220F2. Furthermore, the interlayer dielectric layers 240AR, 240CR, and 240DR do not cover other isolated conductive structures 230BG. In some embodiments, the interlayer dielectric layers 240AR, 240CR, and 240DR may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or a combination thereof. In some embodiments, the interlayer dielectric layers 240AR, 240CR, and 240DR may be formed using a conformable deposition process, an oxidation process, or other suitable formation process, followed by a subsequent patterning process. In some embodiments, the oxidation process may be thermal oxidation or other suitable process. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, other suitable processes, or a combination thereof.

[0085] Source contacts 250S1 and 250S2 are disposed on the epitaxial layer 200 of the first region 400. The source contacts 250S1 and 250S2 penetrate the interlayer dielectric layer 240AR of the first region 400. Furthermore, the source contact 250S1 extends along the direction 320 into a portion of the electrode 220F1, and the source contact 250S2 penetrates the source region 236 (and the wiring doped region 238) and extends along the direction 320 into a portion of the well region 234. The source contact 250S1 is electrically connected to the electrode 220F1, and the source contact 250S2 is electrically connected to the source region 236 and the wiring doped region 238. Figure 1A 、 Figure 1BAs shown, a source contact 250S2 can be disposed in each of the source regions 236 (and the interconnect doped region 238) on both sides of the split gate structure 230AG and in the interconnect doped region 238 (e.g., in the mesa region 400M). Furthermore, a source contact 250S1 can be disposed above the electrode 220F1 used to separate the gates 230AG1 and 230AG2, such that the source contact 250S1 is sandwiched between the two source contacts 250S2. The source contacts 250S1 and 250S2 can be electrically connected to the conductive components 230BG1 and 230BG2 and the electrodes 220F2, 220F3, and 220F4 via other interconnects (not shown). Furthermore, the gates 230AG1 and 230AG2 can be separated from the source contacts 250S1 and 250S2 by a gate dielectric layer 224AR.

[0086] In some embodiments, the source contact 250S1 may include a contact barrier layer 246S and a contact conductive layer 248S1. The source contact 250S2 may include a contact barrier layer 246S and a contact conductive layer 248S2. In some embodiments, the source contacts 250S1 and 250S2 are formed simultaneously. Figure 1B As shown, the contact barrier layer 246S may continuously cover the top surface 200T of the epitaxial layer 200 in the first region 400 and the second region 410 and extend into a portion of the epitaxial layer 200 in the first region 400. The contact barrier layer 246S may cover and physically contact the top surface 220F2T of the electrode 220F2. Furthermore, the contact barrier layer 246S may cover and physically contact at least one of the top surface 230BG1T of the conductive component 230BG1 and the top surface 230BG2T of the conductive component 230BG2. The contact barrier layer 246S may be used to prevent subsequently formed contact conductive layers 248S1 and 248S2 from diffusing into the gates 230AG1 and 230AG2. The material of the contact barrier layer 246S may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), other suitable barrier materials, or combinations thereof. In some embodiments, the contact barrier layer 246S may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or a combination thereof.

[0087] In some embodiments, the contact conductive layers 248S1 and 248S2 of the source contacts 250S1 and 250S2 may have a single-layer or multi-layer structure. The materials of the contact conductive layers 248S1 and 248S2 may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), other suitable metals, or combinations thereof. In some embodiments, the contact conductive layers 248S1 and 248S2 may be formed using chemical vapor deposition, atomic layer deposition, physical vapor deposition, other suitable processes, or combinations thereof.

[0088] The semiconductor device 500 further includes a gate contact 250G. The gate contact 250G is disposed on the epitaxial layer 200 in the third region 420. The gate contact 250G extends from above the interlayer dielectric layer 240CR along the direction 320 through the interlayer dielectric layer 240CR and into a portion of the gate 230G to electrically connect the gate 230G. Similar to the source contacts 250S1 and 250S2, the gate contact 250G may include a contact barrier layer 246G and a contact conductive layer 248G. In some embodiments, the contact barrier layers 246S and 246G may include the same or similar materials and processes and may be formed simultaneously. Furthermore, the contact barrier layer 246S and the contact barrier layer 246G are separated from each other. The contact conductive layers 248S1, 248S2, and 248G may include the same or similar materials and processes and may be formed simultaneously.

[0089] like Figure 1A 、 Figure 1B As shown, the semiconductor device 500 further includes a source metal layer 254S and a gate metal layer 254G, which are separated from each other. The source metal layer 254S extends from the epitaxial layer 200 in the first region 400 to cover the epitaxial layer 200 in the second region 410, and is electrically connected to the electrode 220F2, the source region 236 (and the interconnect doped region 238), and the well region 234 through source contacts 250S1 and 250S2. Furthermore, the source metal layer 254S is electrically connected to the conductive components 230BG1 and 230BG2 through the contact barrier layer 246S. The gate metal layer 254G covers the epitaxial layer 200 in the third region 420 and is electrically connected to the gate 230G through the gate contact 250G. The source metal layer 254S and the gate metal layer 254G can serve as the top metal layer of the final semiconductor device 500. The source metal layer 254S can electrically connect the conductive components 230BG1 and 230BG2 to the electrodes 220F1 and 220F2, the source region 236, and the well region 234. Figure 1BAs shown, the source metal layer 254S and the contact barrier layer 246S thereunder in the second region 410 can form a Schottky junction with the epitaxial layer 200 between two adjacent pairs of separated conductive structures 230BG. Furthermore, the source metal layer 254S can also be electrically connected to the electrodes 220F3 and 220F4 via other interconnects (not shown). The gate metal layer 254G can be electrically connected to the gate 230G via the gate contact 250G.

[0090] like Figure 1B As shown, the source metal layer 254S located in the second region 410 and the contact barrier layer 246S thereunder can form a Schottky diode as a whole with the epitaxial layer (drift region) 200 between the two adjacent pairs of separated conductive structures 230BG. The intrinsic parasitic diode at the interface between the well region 234 of different conductivity types and the epitaxial layer (drift region) 200 is called a body diode. The Schottky diode of the embodiment is connected in parallel with the body diode. Because the energy barrier of the Schottky diode is lower than that of the body diode, that is, the on-resistance (Von) is lower, when the semiconductor device is operated, the carriers will flow through the Schottky diode rather than the body diode. Therefore, the Schottky diode of the embodiment of the present invention can disable the body diode, thereby enabling the semiconductor device to achieve the benefits of reducing on-resistance and reducing power loss.

[0091] In some embodiments, the source metal layer 254S and the gate metal layer 254G may include copper, silver, gold, aluminum, tungsten, other suitable metal materials, or combinations thereof. In some embodiments, the source metal layer 254S, the gate metal layer 254G, the source contacts 250S1, 250S2, and the gate contact 250G may include the same material or different materials. In some embodiments, the source metal layer 254S and the gate metal layer 254G may be formed using a deposition process followed by a patterning process. In some embodiments, the deposition process may include a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or combinations thereof.

[0092] Next, Figures 2 to 22 Methods for forming a semiconductor device 500 according to some embodiments of the present invention are described. Figures 2 to 22 To form Figure 1A 、 Figure 1B FIG. 5 is a cross-sectional view of a semiconductor device 500 at an intermediate stage according to some embodiments of the present invention. Figures 2 to 22 Zhongyu Figure 1A 、 Figure 1B The same or similar reference numerals represent the same or similar elements.

[0093] like Figure 2As shown, a silicon carbide substrate 100 having a first conductivity type is provided, for example, an N-type heavily doped (N+) silicon carbide substrate 100 .

[0094] Next, an epitaxial growth process is performed to grow an epitaxial layer 200 having a first conductivity type, such as an N-type lightly doped (N-) silicon carbide epitaxial layer 200, on the top surface 100T of the silicon carbide substrate 100. In some embodiments, the epitaxial growth process includes metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable epitaxial growth processes, or combinations thereof.

[0095] Then, if Figure 3 As shown, a photolithography process and a subsequent ion implantation process can be performed to form a well region 234 having a second conductivity type, for example, a P-type well region 234, in the epitaxial layer 200 in the first region 400, the third region 420, and the fourth region 430. The well region 234 extends from the top surface 200T of the epitaxial layer 200 in the first region 400, the third region 420, and the fourth region 430 into a portion of the epitaxial layer 200. The epitaxial layer 200 in the second region 410 does not have a well region 234.

[0096] Then, if Figure 4 As shown, a deposition process may be performed to form a mask layer 210 on the epitaxial layer 200. In some embodiments, the mask layer 210 may be a single layer or a multi-layer structure. In some embodiments, the mask layer 210 may include an insulating material such as silicon oxide.

[0097] Then, if Figure 5 As shown, a photolithography process and a subsequent patterning process are performed. Part of the mask layer 210 is removed to form mask patterns 210P on the top surface 200T of the epitaxial layer 200 to define the formation position of the groove. Afterwards, the epitaxial layer 200 is etched using the mask pattern 210P as an etching mask. The above etching process removes the epitaxial layer 200 not covered by the mask pattern 210P to form trenches 212A, 212B, 212C, and 212D in the epitaxial layer 200 in the first area 400, the second area 410, the third area 420, and the fourth area 430 along the direction 320. Figure 5In the illustrated embodiment, the etching process forms two trenches 212A in the epitaxial layer 200 in the first region 400, one trench 212B in the epitaxial layer 200 in the second region 410, one trench 212C in the epitaxial layer 200 in the third region 420, and one trench 212D in the epitaxial layer 200 in the fourth region 430. Two adjacent trenches 212A are spaced apart from each other along a direction 300 and define a mesa region 400M of the epitaxial layer 200. In some embodiments, the etching process includes dry etching. Dry etching can include plasma etching, plasma-free gas etching, sputter etching, ion milling, reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma etching, or other suitable processes.

[0098] Then, if Figure 6 As shown, a selective etching process may be performed to remove the mask pattern 210P. Thereafter, an oxidation process and subsequent etching processes may be performed to form a sacrificial oxide layer (SAC oxide layer) (not shown) on the sidewalls 212A-S, 212B-S, 212C-S, 212D-S and bottom surfaces 212A-B, 212B-B, 212C-B, 212D-B of the trenches 212A, 212B, 212C, 212D. An etching process may then be performed to remove the sacrificial oxide layer, exposing the sidewalls 212A-S, 212B-S, 212C-S, 212D-S and bottom surfaces 212A-B, 212B-B, 212C-B, 212D-B of the trenches 212A, 212B, 212C, 212D. Figure 6 The oxidation process and etching process shown can remove the etching process ( Figure 5 ) surface damage caused by.

[0099] Then, if Figure 7 As shown, an oxidation process and a subsequent deposition process may be performed to fully form a shielding dielectric layer 216. The shielding dielectric layer 216 covers the top surface 200T of the epitaxial layer 200 and extends into the trenches 212A, 212B, 212C, and 212D, conformally covering the sidewalls 212A-S, 212B-S, 212C-S, and 212D-S and bottom surfaces 212A-B, 212B-B, 212C-B, and 212D-B of the trenches 212A, 212B, 212C, and 212D. Figure 6 ).

[0100] In some embodiments, a thermal process may be optionally performed on the shielding dielectric layer 216 to increase the density of the shielding dielectric layer 216 and improve the interface properties between the shielding dielectric layer 216 and the epitaxial layer 200. In some embodiments, the thermal process may be a rapid thermal annealing (RTA) process.

[0101] Then, if Figure 8 As shown, a deposition process and a subsequent planarization process may be performed on the trenches 212A, 212B, 212C, and 212D ( Figure 7 ) are formed in the shielding dielectric layer 216. In some embodiments, the conductive materials 220A, 220B, 220C, and 220D are formed simultaneously. The top surface 220AT of the conductive material 220A, the top surface 220BT of the conductive material 220B, the top surface 220CT of the conductive material 220C, and the top surface 220DT of the conductive material 220D are all higher than the top surface 200T of the epitaxial layer 200 and are aligned with one another. For example, the top surface 220AT of the conductive material 220A, the top surface 220BT of the conductive material 220B, the top surface 220CT of the conductive material 220C, and the top surface 220DT of the conductive material 220D are all aligned with the top surface 216T of the shielding dielectric layer 216. Furthermore, the conductive materials 220A, 220B, 220C, and 220D comprise the same material. In some embodiments, the conductive materials 220A, 220B, 220C, and 220D may be formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. In some embodiments, the metal may include, but is not limited to, tungsten (W), titanium (Ti), tantalum (Ta), and platinum (Pt). In some embodiments, the metal nitride may include, but is not limited to, titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include, but is not limited to, tungsten silicide (WSi x In some embodiments, the deposition process may include metal organic chemical vapor deposition (MOCVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition processes. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

[0102] Then, if Figure 9As shown, an etch-back process may be performed to remove portions of the conductive materials 220A, 220B, 220C, and 220D from the top surfaces 220AT, 220BT, 220CT, and 220DT of the conductive materials 220A, 220B, 220C, and 220D. After the etch-back process, the remaining conductive materials 220A, 220B, 220C, and 220D are labeled as conductive materials 220AR, 220BR, 220CR, and 220DR. Top surfaces 220ART, 220BRT, 220CRT, and 220DRT of the conductive materials 220AR, 220BR, 220CR, and 220DR may be located above the top surface 200T of the epitaxial layer 200. For example, top surfaces 220ART, 220BRT, 220CRT, 220DRT of conductive materials 220AR, 220BR, 220CR, 220DR may be higher than top surface 200T of epitaxial layer 200 and lower than top surface 216T of shielding dielectric layer 216. In some embodiments, the etch-back process may be a selective etching process, such as dry etching.

[0103] Then, if Figure 10 As shown, a deposition process can be performed to fully form an oxide layer 222. The oxide layer 222 covers the shielding dielectric layer 216 and the conductive materials 220AR, 220BR, 220CR, and 220DR. When both the oxide layer 222 and the shielding dielectric layer 216 comprise silicon oxide, the interface between the oxide layer 222 and the shielding dielectric layer 216 is not distinct. In some embodiments, the oxide layer 222 comprises tetraethyl orthosilicate (TEOS) oxide formed using low-pressure chemical vapor deposition (LPCVD). Since the top surfaces 220ART, 220BRT, 220CRT, 220DRT of the conductive materials 220AR, 220BR, 220CR, 220DR are lower than the top surface 216T of the shielding dielectric layer 216, the upper surface 222T1 of the portion of the oxide layer 222 directly above the conductive materials 220AR, 220BR, 220CR, 220DR will be lower than the upper surface 222T2 of the portion of the oxide layer 222 directly above the shielding dielectric layer 216.

[0104] Then, if Figure 11 As shown, a photolithography process can be performed to form a mask pattern PR1 such as a photoresist pattern on the epitaxial layer 200 of the fourth region 430. The mask pattern PR1 covers the conductive material 220DR and a portion of the shielding dielectric layer 216 and the oxide layer 222 of the fourth region 430, and makes the first region 400, the second region 410, and the third region 420 partially oxide layer 222 ( Figure 10) is exposed from the mask pattern PR1. Then, a selective etching process may be performed to remove the oxide layer 222 and a portion of the shielding dielectric layer 216 from the top surface 200T of the epitaxial layer 200 and the upper portion of the trenches 212A, 212B, and 212C close to the top surface 200T of the epitaxial layer 200 ( Figure 10 ), exposing the upper portions 220AR-1, 220BR-1, and 220CR-1 of the conductive materials 220AR, 220BR, and 220CR. After the selective etching process, the shielding dielectric layer 216 remaining in the trenches 212A, 212B, and 212C in the first region 400, the second region 410, and the third region 420 is labeled as shielding dielectric layers 216AR, 216BR, and 216CR. The shielding dielectric layer 216 and the oxide layer 222 remaining in the fourth region 430 are labeled as shielding dielectric layer 216DR and oxide layer 222DR. Shielding dielectric layers 216AR, 216BR, and 216CR surround the lower portions of conductive materials 220AR, 220BR, and 220CR, exposing sidewalls 212A-S, 212B-S, and 212C-S at the upper portions of trenches 212A, 212B, and 212C. Top surfaces 216ART, 216BRT, and 216CRT of shielding dielectric layers 216AR, 216BR, and 216CR may be below the bottom surface 234B of well region 234. Shielding dielectric layer 216DR and oxide layer 222DR surround conductive material 220DR. In some embodiments, the selective etching process includes wet etching. After forming shielding dielectric layers 216AR, 216BR, 216CR, and 216DR, mask pattern PR1 is removed.

[0105] Then, if Figure 12 As shown, an oxidation process may be performed to form gate dielectric layers 224A and 224C in the trenches 212A and 212C, and simultaneously form a dielectric layer 224B in the trench 212B. The oxidation process includes oxidizing the sidewalls 212A-S of the upper portion of the trench 212A and the upper portion 220AR-1 ( Figure 11 ) to form a gate dielectric layer 224A and an electrode 220F1 in the trench 212A. A top surface 220F1T of the electrode 220F1 can be aligned with a top surface 200T of the epitaxial layer 200 (the top surfaces 220F1T and 200T are coplanar).

[0106] The oxidation process further includes oxidizing the sidewall 212B-S of the upper portion of the trench 212B and the upper portion 220BR-1 ( Figure 11 ) to form a dielectric layer 224B and an electrode 220F2 in the trench 212B. The oxidation process further includes oxidizing the sidewall 212C-S of the upper portion of the trench 212C and the upper portion 220CR-1 ( Figure 11) to form a gate dielectric layer 224C and an electrode 220F3 in the trench 212C. The shielding dielectric layers 216AR, 216BR, and 216CR surround the lower portions of the conductive materials 220AR, 220BR, and 220CR, thereby preventing the lower portions of the conductive materials 220AR, 220BR, and 220CR from being oxidized. When the gate dielectric layers 224A, 224B, and 224C, as well as the shielding dielectric layers 216AR, 216BR, and 216CR, all comprise silicon oxide, the interfaces between the gate dielectric layers 224A, 224C and the shielding dielectric layers 216AR, 216CR (or between the dielectric layer 224B and the shielding dielectric layer 216BR) are not distinct. Furthermore, the gate dielectric layers 224A, 224B, and 224C extend to cover the top surface 200T of the epitaxial layer 200 in the first, second, and third regions 400, 410, and 420. The oxidation process further includes forming an oxide layer (not shown) on the oxide layer 222DR in the fourth region 430.

[0107] In some embodiments of the present invention, the gate dielectric layer 224A does not completely fill the trench 212A. In addition, the gate dielectric layer 224A includes sidewalls 212A-S ( Figure 11 ) and a gate dielectric layer 224A-1 on the upper portion of the electrode 220F1, and a gate dielectric layer 224A-2 surrounding the upper portion of the electrode 220F1. Similarly, the dielectric layer 224B does not fill the trench 212B. In addition, the dielectric layer 224B includes a sidewall 212B-S ( Figure 11 ) and a dielectric layer 224B-1 on the upper portion of the electrode 220F2, and a dielectric layer 224B-2 surrounding the upper portion of the electrode 220F2. Similarly, the gate dielectric layer 224C does not fill the trench 212C. In addition, the gate dielectric layer 224C includes a sidewall 212C-S ( Figure 11 ) and a gate dielectric layer 224C-2 surrounding the upper portion of the electrode 220F3. In some embodiments, the thickness of the gate dielectric layer 224A-1, the dielectric layer 224B-1, and the gate dielectric layer 224C-1 is less than the thickness of the shielding dielectric layers 216AR, 216BR, and 216CR. Compared to the gate dielectric layer 224A-1, the dielectric layer 224B-1, and the gate dielectric layer 224C-1 formed by oxidation of the epitaxial layer 200 of silicon carbide, the gate dielectric layer 224A-2, the dielectric layer 224B-2, and the gate dielectric layer 224C-2 are made of a conductive material 220AR, 220BR, and 220CR (such as polysilicon) Figure 11 ) is oxidized, so it has a thicker thickness.

[0108] After the oxidation process, the unoxidized conductive materials 220AR, 220BR, and 220CR in trenches 212A, 212B, and 212C respectively form electrodes 220F1, 220F2, and 220F3. The unoxidized conductive material 220DR in trench 212D forms electrode 220F4. In some embodiments of the present invention, electrodes 220F1, 220F2, 220F3, and 220F4 extend along direction 320. In direction 300, since the gate dielectric layer 224A-2, the dielectric layer 224B-2, and the gate dielectric layer 224C-2 are thicker than the gate dielectric layer 224A-1, the dielectric layer 224B-1, and the gate dielectric layer 224C-1, the width W1 of the upper portion of the electrode 220F1 (the upper portion 220AR-1 of the unoxidized conductive material 220A) may be smaller than the width W2 of the lower portion of the electrode 220F1 (the portion surrounded by the shielding dielectric layer 216AR). Similarly, in direction 300, the width W3 of the upper portion of electrode 220F2 (the upper portion 220BR-1 of the unoxidized conductive material 220B) may be smaller than the width W4 of the lower portion of electrode 220F2 (the portion surrounded by shielding dielectric layer 216BR), and the width W5 of the upper portion of electrode 220F3 (the upper portion 220CR-1 of the unoxidized conductive material 220C) may be smaller than the width W6 of the lower portion of electrode 220F3 (the portion surrounded by shielding dielectric layer 216CR). In some embodiments, widths W1, W3, and W5 may be equal to each other, and widths W2, W4, and W6 may be equal to each other. Furthermore, in direction 300, electrode 220F4 has a uniform width W7. In some embodiments, width W7 may be equal to widths W1, W3, and W5.

[0109] In some embodiments, the oxidation process may be thermal oxidation or other suitable processes. In some embodiments, the gate dielectric layer 224A, the dielectric layer 224B, and the gate dielectric layer 224C may be formed using an oxidation process and a subsequent deposition process. In some embodiments, the deposition process may be low-pressure chemical vapor deposition (LPCVD) or other suitable processes.

[0110] Then, if Figure 13 As shown, a deposition process and a subsequent planarization process may be performed to form an electrode material 230 on the entire epitaxial layer 200. The electrode material 230 covers the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C in the first region 400, the second region 410, and the third region 420, and the oxide layer 222DR in the fourth region 430. In addition, the electrode material 230 fills the trenches 212A, 212B, and 212C ( Figure 12In some embodiments, the electrode material 230 and the electrodes 220F1, 220F2, 220F3, and 220F4 may comprise the same material, such as polysilicon. In some embodiments, the deposition process may include metal organic chemical vapor deposition (MOCVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition processes. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process.

[0111] Then, if Figure 14 As shown, a patterning process may be performed to remove portions of the electrode material 230 above the epitaxial layer 200 in the first region 400, the second region 410, and the fourth region 430 ( Figure 13 ). The above-mentioned patterning process includes a photolithography process and a subsequent selective etching process. The above-mentioned photolithography process can form a mask pattern PR2, such as a photoresist pattern, above the epitaxial layer 200 in the third region 420. The mask pattern PR2 covers the electrode material 230 in the third region 420 and exposes the electrode material 230 in the first region 400, the second region 410 and the fourth region 430. Thereafter, a selective etching process can be performed to remove the electrode material 230 located on the top surface 200T of the epitaxial layer 200 in the first region 400 and the upper portion of the trench 212A close to the top surface 200T of the epitaxial layer 200, so as to form gates 230AG1 and 230AG2 separated from each other along the direction 300 and extending along the direction 320 on the opposite sidewalls 220F1S of the electrode 220F1 in the trench 212A. Furthermore, the selective etching process simultaneously removes the electrode material 230 located on the top surface 200T of the epitaxial layer 200 in the second region 410 and the upper portion of the trench 212B close to the top surface 200T of the epitaxial layer 200, thereby forming conductive components 230BG1 and 230BG2 separated from each other along the direction 300 and extending along the direction 320 on opposite sidewalls 220F2S of the electrode 220F2 in the trench 212B. The conductive components 230BG1 and 230BG2 may constitute a separate conductive structure 230BG. Figure 14As shown, gates 230AG1, 230AG2, conductive features 230BG1, and 230BG2 may extend along direction 320 to below bottom surface 234B of well region 234. In some embodiments, gates 230AG1 and 230AG2 may completely fill trench 212A, and conductive features 230BG1 and 230BG2 may completely fill trench 212B. In some embodiments, top surfaces 230AG1T, 230AG2T, 230BG1T, 230BG2T, and 220F1T of electrode 220F1 may be aligned with top surface 200T of epitaxial layer 200.

[0112] like Figure 14 As shown, the selective etching process can also remove the electrode material 230 on the oxide layer 222DR in the fourth region 430. After the selective etching process, the electrode material 230 can be removed from the epitaxial layer 200 in the third region 420 and the trench 212C ( Figure 12 ) is formed in the trench 212B. In some embodiments, the gate 230G fills the remaining space in the trench 212B and extends to cover the electrode 220F3 and the epitaxial layer 200 outside the trench 212C. Because the electrode material 230 and the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C, and the oxide layer 222DR can be made of different materials, the selective etching process described above does not remove the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C, and the oxide layer 222DR. In some embodiments, the selective etching process includes dry etching. After forming the gate 230AG1, the gate 230AG2, the conductive component 230BG1, the conductive component 230BG2, and the gate 230G, the mask pattern PR2 is removed.

[0113] Then, Figure 15 、 Figure 16 The formation methods of the source region 236 and the wiring doping region 238 are described separately. Figure 23 The formation positions of the source region 236 and the wiring doping region 238 in the first region 400 are described. In order to describe the configuration of the source region 236 and the wiring doping region 238, Figure 23 The gate dielectric layer 224A- 1 covering the top surface 200T of the epitaxial layer 200 is not shown. Figure 15 、 Figure 16 Cross-sectional views of intermediate structures of a semiconductor device 500 at different positions along direction 310 are shown according to some embodiments of the present invention. Figure 20 To form Figure 1A 、 Figure 1BFIG. 5 is a top view schematically illustrating an intermediate stage of a semiconductor device 500 according to some embodiments of the present invention, showing the configuration of the source region 236 and the interconnect doping region 238 above the well region 234 . Figure 15 、 Figure 16 The first area 400 shown may correspond to Figure 20 The cross-sectional positions of the AA′ and BB′ lines are used to illustrate the formation of the source regions 236 and the wiring doping regions 238 that are staggered along the direction 310 in the epitaxial layer 200 of the first region 400 .

[0114] like Figure 15 As shown, a photolithography process can be performed to form a mask pattern PR3 such as a photoresist pattern above the epitaxial layer 200 in the second region 410, the third region 420, and the fourth region 430, exposing a predetermined formation area of ​​the source region 236 in the first region 400 (corresponding to Figure 23 Then, an ion implantation process is performed to form a source region 236 of the first conductivity type (eg, an N-type source region 236) on the well region 234 of the first region 400. After forming the source region 236, the mask pattern PR3 is removed.

[0115] like Figure 16 As shown, a photolithography process can be performed to form a mask pattern PR4 such as a photoresist pattern on the epitaxial layer 200 of the second region 410, the third region 420, and the fourth region 430, exposing a predetermined formation area of ​​the wiring doping region 238 in the first region 400 (corresponding to Figure 23 It is worth noting that the predetermined formation regions of the source region 236 and the wiring doping region 238 are respectively located in different regions of the epitaxial layer 200 that are staggered along the direction 310 ( Figure 20 ). Then, an ion implantation process is performed to form a wiring doping region 238 having a second conductivity type (eg, a P-type wiring doping region 238) on the well region 234 of the first region 400. After forming the wiring doping region 238, the mask pattern PR4 is removed.

[0116] In some embodiments, the source region 236 and the wiring doped region 238 are disposed in the epitaxial layer 200 adjacent to the trench 212A. Furthermore, the source region 236 and the wiring doped region 238 are each disposed in the epitaxial layer 200 between two adjacent pairs of gates 230AG1 and 230AG2 along direction 300. In other words, the source region 236 and the wiring doped region 238 are each disposed in the mesa region 400M. In direction 300, no other doped regions exist between the opposing sidewalls of each source region 236 and wiring doped region 238 and the adjacent two gates 230AG1 and 230AG2 of the two pairs of gates 230AG1 and 230AG2.

[0117] In some embodiments, Figure 15 、 Figure 16 The process sequence shown can be interchanged, that is, the wiring doping region 238 can be formed first and then the source region 236 can be formed.

[0118] Then, if Figure 17 As shown, a deposition process and a subsequent planarization process can be performed to form an interlayer dielectric layer 240 completely on the epitaxial layer 200. The interlayer dielectric layer 240 covers the gate 230AG1, the gate 230AG2, the conductive component 230BG1, the conductive component 230BG2, the gate 230G, the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C, and the oxide layer 222DR. When the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C, the oxide layer 222DR, and the interlayer dielectric layer 240 all comprise silicon oxide, the interfaces between the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C, the oxide layer 222DR, and the interlayer dielectric layer 240 are not obvious. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

[0119] Then, if Figure 18 As shown, a photolithography process may be performed to form a mask pattern PR5, such as a photoresist pattern, on the epitaxial layer 200. The mask pattern PR5 includes an opening 242A1 located directly above the electrode 220F1, an opening 242A2 located directly above the source region 236 and the wiring doped region 238, and an opening 242C located directly above the gate 230G. Furthermore, the mask pattern PR5 completely covers the epitaxial layer 200 and the interlayer dielectric layer 240 in the second region 410 and the fourth region 430.

[0120] Then, if Figure 19 As shown, an etching process may be performed to remove the openings 242A1 and 242A2 ( Figure 18 ) is formed in the interlayer dielectric layer 240 of the first region 400, and the gate dielectric layer 224A, the electrode 220F1 and a portion of the epitaxial layer 200 exposed thereunder, thereby forming an opening (contact hole) 244A1 exposing the electrode 220F1 and an opening (contact hole) 244A2 exposing the well region 234, the source region 236 and the wiring doping region 238. The above etching process simultaneously removes the opening (contact hole) 242C ( Figure 18) is performed to expose the interlayer dielectric layer 240 and the portion of the gate 230G thereunder, thereby forming an opening (contact hole) 244C in the portion of the interlayer dielectric layer 240 directly above the gate 230G in the third region 420, exposing the gate 230G. In some embodiments, the above-mentioned etching process includes dry etching. After the above-mentioned etching process, the interlayer dielectric layer 240 remaining in the first region 400 is labeled as the interlayer dielectric layer 240AR, and the remaining gate dielectric layer 224A is labeled as the gate dielectric layer 224AR. The gate dielectric layer 224AR, together with the gates 230AG1 and 230AG2, forms a separated gate structure 230AG. In addition, the interlayer dielectric layer 240 remaining in the second region 410, the third region 420, and the fourth region 430 are labeled as the interlayer dielectric layer 240BR, the interlayer dielectric layer 240CR, and the interlayer dielectric layer 240DR, respectively. After forming the interlayer dielectric layer 240AR, the gate dielectric layer 224AR, the interlayer dielectric layer 240BR, the interlayer dielectric layer 240CR, and the interlayer dielectric layer 240DR, the mask pattern PR5 is removed.

[0121] Then, if Figure 20 As shown, an ion implantation process may be performed to form a contact doped region 245 in the epitaxial layer 200 below the opening (contact hole) 244A2. The contact doped region 245 has the same conductivity type as the well region 234, for example, a P-type contact doped region 245. Furthermore, the doping concentration of the contact doped region 245 is greater than the doping concentration of the well region 234. For example, when the well region 234 is a P-type well region 234, the contact doped region 245 is a heavily P-type (P+) doped contact doped region 245 to serve as a wiring doped region for the well region 234. After the aforementioned ion implantation process, an annealing process may be performed to activate dopants in the well region 234, the source region 236, the wiring doped region 238, and the contact doped region 245. In some embodiments, the annealing process includes laser annealing, rapid thermal annealing (RTA), other suitable annealing processes, or a combination thereof.

[0122] Then, if Figure 21 As shown, a photolithography process can be performed to form a mask pattern PR6 such as a photoresist pattern on the epitaxial layer 200 in the first region 400, the third region 420, and the fourth region 430. The mask pattern PR6 fills the openings (contact holes) 244A1, 244A2, and 244C, and makes the interlayer dielectric layer 240BR ( Figure 20 ) is exposed. Then, an etching process is performed to remove the interlayer dielectric layer 240BR and the dielectric layer 224B ( Figure 20). The dielectric layer 224B after the above process is marked as a dielectric layer 224BR. After the above process, at least one of the conductive component 230BG1 and the conductive component 230BG2 and the electrode 220F2 are exposed from the remaining interlayer dielectric layers 240AR, 240CR, and 240DR. Figure 21 In the illustrated embodiment, the top surface 220F2T of the electrode 220F2, the top surface 230BG1T of the conductive feature 230BG1, and the top surface 230BG2T of the conductive feature 230BG2 are exposed from the remaining interlayer dielectric layers 240AR, 240CR, 240DR. Figure 1B In the embodiment shown, the top surface 220F2T of the electrode 220F2 and the top surface 230BG2T of the conductive feature 230BG2 closest to the first region 400 are exposed from the remaining interlayer dielectric layers 240AR, 240CR, 240DR. The interlayer dielectric layer 240BR on the top surface 200T of the epitaxial layer 200 of the second region 410 is removed. Figure 20 ) Thereafter, the mask pattern PR6 is removed.

[0123] Then, if Figure 22 As shown, a deposition process may be performed to form a contact barrier layer 246 on the interlayer dielectric layers 240AR, 240CR, and 240DR and on the top surface 200T of the epitaxial layer 200 in the second region 410, and the contact barrier layer 246 is conformably deposited in the openings (contact holes) 244A1, 244A2, and 244C ( Figure 20 ). The contact barrier layer 246 of the second region 410 directly contacts the separated conductive structure 230BG and the electrode 220F2 that are not covered by the interlayer dielectric layer 240AR. Figure 22 In the illustrated embodiment, the contact barrier layer 246 of the second region 410 directly contacts the top surface 220F2T of the electrode 220F2, the top surface 230BG1T of the conductive feature 230BG1, and the top surface 230BG2T of the conductive feature 230BG2. Figure 1B In the illustrated embodiment, the contact barrier layer 246 of the second region 410 directly contacts the top surface 220F2T of the electrode 220F2 and the top surface 230BG2T of the conductive feature 230BG2 closest to the first region 400 .

[0124] Afterwards, if Figure 22As shown, a contact conductive layer (not shown) is deposited over the contact barrier layer 246. The contact conductive layer fills the remaining space in the openings (contact holes) 244A1, 244A2, and 244C. Next, a removal process (e.g., an etching process or a planarization process) is performed to remove excess portions of the contact conductive layer on the interlayer dielectric layers 240AR, 240CR, and 240DR and above the top surface 200T of the epitaxial layer 200 in the second region 410, thereby forming contact conductive layers 248S1, 248S2, and 248G in the openings (contact holes) 244A1, 244A2, and 244C. The contact conductive layers 248S1, 248S2, and 248G fill the remaining space in the openings (contact holes) 244A1, 244A2, and 244C. The contact barrier layer 246 in the second region 410 is not covered by the contact conductive layer. Furthermore, the removal process does not remove the contact barrier layer 246 .

[0125] Then, if Figure 1A 、 Figure 1B As shown, a deposition process and subsequent patterning process can be performed to form a source metal layer 254S on the epitaxial layer 200 in the first and second regions 400 and 410, and a gate metal layer 254G on the epitaxial layer 200 in the third region 420. The deposition process fully forms a metal layer (not shown), which covers and physically connects the contact conductive layer 248S1, the contact conductive layer 248S2, and the contact conductive layer 248G. The patterning process not only removes the metal layer in the fourth region 430, but also removes the contact barrier layer 246 in the fourth region 430 to form a contact barrier layer 246S on the epitaxial layer 200 in the first and second regions 400 and 410, and a contact barrier layer 246G on the epitaxial layer 200 in the third region 420. The contact barrier layer 246S and the contact barrier layer 246G are separated from each other. The source metal layer 254S directly contacts the contact barrier layer 246S in the first region 400 and the second region 410 . The gate metal layer 254G directly contacts the contact barrier layer 246G in the third region 420 .

[0126] During the formation of the source metal layer 254S, the gate metal layer 254G, the contact barrier layer 246S and the contact barrier layer 246G, a source contact 250S1 (including the contact barrier layer 246S and the contact conductive layer 248S1) is formed on the electrode 220F1 of the first region 400, and a source contact 250S2 (including the contact barrier layer 246S and the contact conductive layer 248S2) is formed on the well region 234, the source region 236 and the wiring doped region 238 of the first region 400, and at the same time, a gate contact 250G (including the contact barrier layer 246G and the contact conductive layer 248G) is formed on the gate 230G of the third region 420.

[0127] like Figure 1A 、 Figure 1B As shown, the source metal layer 254S is continuously distributed on the epitaxial layer 200 in the first region 400 and the second region 410. The source metal layer 254S covers and is electrically connected to the source contacts 250S1 and 250S2. In addition, the source metal layer 254S covers and is electrically connected to the isolated conductive structure 230BG and the electrode 220F2 that are not covered by the interlayer dielectric layer 240AR. Figure 1A 、 Figure 1B In the embodiment shown, the source metal layer 254S of the second region 410 covers and electrically connects the top surface 220F2T of the electrode 220F2 and the top surface 230BG2T of the conductive component 230BG2 closest to the first region 400, as well as the separated conductive structure 230BG (including the conductive components 230BG1 and 230BG2) and the electrode 220F2 away from the first region 400. In addition, the source metal layer 254S directly contacts the contact barrier layer 246S of the first region 400 and the second region 410. Figure 1B As shown, the source metal layer 254S located in the second region 410 and the contact barrier layer 246S thereunder can form a Schottky diode together with the epitaxial layer (drift region) 200 between two adjacent pairs of separated conductive structures 230BG.

[0128] like Figure 1A 、 Figure 1B As shown, the gate metal layer 254G covers and is electrically connected to the gate contact 250G. Furthermore, the gate metal layer 254G directly contacts the contact barrier layer 246G in the third region.

[0129] In some embodiments, the deposition process for forming the source metal layer 254S and the gate metal layer 254G may include a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or a combination thereof.

[0130] Subsequent processes may be further performed to form a drain contact (not shown) on the bottom surface 100B of the silicon carbide substrate 100. The drain contact may be electrically connected to the silicon carbide substrate 100. After the above processes, the semiconductor device 500 is formed.

[0131] Some embodiments of the present invention provide semiconductor devices and methods for forming the same. The semiconductor device includes an isolated gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) unit formed in a cell region (e.g., the first region 400) of an epitaxial layer. The above-mentioned isolated gate trench metal oxide semiconductor field effect transistor unit has a split gate structure. The two gates of the split gate structure (e.g., gates 230AG1 and 230AG2) are formed on opposite side walls of an electrode having a field plate function (also referred to as a source electrode, such as electrode 220F1). The split gate structure can further reduce the overall gate-to-drain capacitance (Cgd ) and feedback capacitor (C rss =C gd ) to improve the overall power conversion efficiency of the isolated gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) unit. In addition to reducing the gate-to-drain capacitance (C gd ) to improve the switching characteristics of the semiconductor device, and can make the electric field distribution of the gate dielectric layer near the bottom of the separated gate structure more uniform and increase the breakdown voltage to improve the reliability of the gate dielectric layer. It can also further increase the doping concentration of the epitaxial layer (drift region) to reduce the on-resistance (R) of the isolated gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) unit. onsp ).

[0132] The semiconductor device of an embodiment of the present invention further includes a Schottky diode formed in the trench Schottky diode region (e.g., second region 410). The Schottky diode is composed of an epitaxial layer (e.g., epitaxial layer 200), a contact barrier layer (e.g., contact barrier layer 246S), and a source metal layer (e.g., source metal layer 254S). The Schottky diode can be connected in parallel with the isolation gate trench MOSFET unit to disable the body diode, thereby reducing on-resistance and power loss, thereby improving the switching characteristics of the semiconductor device.

[0133] In some embodiments, the above-mentioned Schottky diode is clamped between two adjacent pairs of trench-type separated conductive structures (such as separated conductive structure 230BG), and can therefore be called a trench Schottky diode (TMBS). Therefore, the reverse leakage current of the Schottky diode of the present invention can be clamped by the trench-type separated conductive structure, and will have a lower leakage current. In some embodiments, the two conductive components of the trench-type separated conductive structure (such as conductive components 230BG1, 230BG2) are formed on the opposite side walls of another electrode (also referred to as a source electrode, such as electrode 220F2) having a field plate function. In some embodiments, the other source electrode inserted into the above-mentioned two conductive components also has a field plate function, so that the electric field distribution of the epitaxial layer (drift region) of the Schottky diode is more uniform. Therefore, the doping concentration of the epitaxial layer (drift region) can be further increased to further reduce the forward voltage drop (V F Therefore, the Schottky diode of the present invention can not only improve the switching characteristics of the semiconductor device, but also further reduce the forward voltage drop (V F ) and reverse leakage current.

[0134] While the present invention has been described above with reference to the aforementioned embodiments, these are not intended to limit the present invention. Persons skilled in the art will readily appreciate that modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A silicon carbide substrate having a first region and a first conductivity type; an epitaxial layer disposed on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; a first electrode disposed in the epitaxial layer of the first region and extending along a first direction; a separate conductive structure disposed in the epitaxial layer of the first region, wherein the separate conductive structure comprises: A first conductive component and a second conductive component separated from each other are located on opposite side walls of the first electrode; as well as A source metal layer is disposed on the epitaxial layer in the first region, wherein the source metal layer covers and electrically connects the first conductive component, the second conductive component and the first electrode.

2. The semiconductor device according to claim 1, wherein Also includes: A contact barrier layer is disposed on the epitaxial layer in the first region, wherein the contact barrier layer is in direct contact with at least one of the first electrode, the first conductive component, and the second conductive component, and the source barrier layer.

3. The semiconductor device according to claim 1, wherein The silicon carbide substrate has a second region, and the semiconductor device further includes: a well region located in the epitaxial layer of the second region, and the well region has a second conductivity type; a second electrode disposed in the epitaxial layer of the second region and extending along the first direction; a split gate structure disposed in the epitaxial layer of the second region, wherein the split gate structure comprises: A first gate and a second gate separated from each other are located on opposite side walls of the second electrode; an interlayer dielectric layer disposed on the epitaxial layer in the second region; and A plurality of source contacts penetrate the interlayer dielectric layer in the second region and extend into the second electrode and the well region, wherein the source metal layer covers and electrically connects the source contacts.

4. The semiconductor device according to claim 3, wherein The first electrode is exposed from the interlayer dielectric layer.

5. The semiconductor device according to claim 3, wherein At least one of the first conductive component and the second conductive component is exposed from the interlayer dielectric layer.

6. The semiconductor device according to claim 3, wherein Also includes: a first dielectric layer disposed in the epitaxial layer of the first region and surrounding the first conductive component and the second conductive component, wherein the first electrode, the first conductive component, and the second conductive component are exposed from a top surface of the first dielectric layer; The split gate structure further comprises: A first gate dielectric layer is disposed in the epitaxial layer in the second region and surrounds the first gate and the second gate, wherein the interlayer dielectric layer covers the first gate dielectric layer.

7. The semiconductor device according to claim 6, wherein A sidewall of the interlayer dielectric layer is located on the first dielectric layer close to the first electrode.

8. The semiconductor device according to claim 3, wherein Also includes: A plurality of source regions and a plurality of wiring doping regions are located on the well region in the second region and close to a top surface of the epitaxial layer, wherein the source regions and the wiring doping regions are staggered along a third direction and have opposite conductivity types. The source contact is connected to the source region and the wiring doping region.

9. The semiconductor device according to claim 8, wherein The interlayer dielectric layer covers the source region and the wiring doping region.

10. The semiconductor device according to claim 3, wherein The silicon carbide substrate has a third region and a fourth region, and the semiconductor device further includes: a third electrode disposed in the epitaxial layer in the third region and extending along the first direction, wherein the third electrode is electrically connected to the source contact; a third gate disposed in the epitaxial layer of the third region and connected to the split-gate structure, wherein the third gate extends from opposite sidewalls of the third electrode to cover a third electrode top surface of the third electrode and a top surface of the epitaxial layer; a gate contact extending from above the epitaxial layer in the third region into the third gate and electrically connected to the third gate; a gate metal layer disposed on the epitaxial layer in the third region, wherein the gate metal layer covers and is electrically connected to the gate contact; and a fourth electrode disposed in the epitaxial layer of the fourth region and extending along the first direction, wherein the fourth electrode is electrically connected to the source contact, The well region is located in the epitaxial layer of the third region and the fourth region, and the interlayer dielectric layer covers the third electrode and the fourth electrode.

11. A method for forming a semiconductor device, characterized in that: include: Providing a silicon carbide substrate having a first region and a first conductivity type; growing an epitaxial layer on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; forming a first trench in the epitaxial layer of the first region along a first direction; forming a first electrode in the first trench, wherein the first electrode extends along the first direction; forming a separate conductive structure on opposite sidewalls of the first electrode, wherein the separate conductive structure includes a first conductive component and a second conductive component separated from each other; Comprehensively forming an interlayer dielectric layer; removing the interlayer dielectric layer on a top surface of the epitaxial layer in the first region, so that at least one of the first conductive component and the second conductive component and the first electrode are exposed from the remaining interlayer dielectric layer; and A source metal layer is formed on the epitaxial layer in the first region, wherein the source metal layer covers and is electrically connected to the first electrode, the first conductive component, and the second conductive component.

12. The method for forming a semiconductor device according to claim 11, wherein: Also includes: Before forming the first trench, a well region is formed in the epitaxial layer in a second region of the silicon carbide substrate, wherein the well region has a second conductivity type; During the formation of the first trench, a second trench is formed in the epitaxial layer of the second region along the first direction; During the formation of the first electrode, a second electrode is formed in the second trench; During the formation of the separated conductive structure, a first gate and a second gate are formed on opposite sidewalls of the second electrode; and forming a plurality of source regions and a plurality of wiring doping regions on the well region of the second region, wherein the source regions and the wiring doping regions are staggered along a third direction and have opposite conductivity types; Performing a patterning process on the interlayer dielectric layer to form a plurality of first openings in the interlayer dielectric layer in the second region to expose the second electrode, the source region, and the wiring doping region respectively; and During the formation of the source metal layer, a plurality of source contacts are formed in the first opening.

13. The method for forming a semiconductor device according to claim 12, wherein: The patterning process is performed before removing the interlayer dielectric layer on the top surface of the epitaxial layer in the first region.

14. The method for forming a semiconductor device according to claim 13, wherein: Also includes: During the formation of the first trench, a third trench and a fourth trench are formed in the epitaxial layer in a third region and a fourth region of the silicon carbide substrate along the first direction, respectively; During the formation of the first electrode, a third electrode and a fourth electrode are formed in the third trench and the fourth trench respectively; During the formation of the separated conductive structure, a third gate is formed in the third trench; During the patterning process, a second opening is formed in the interlayer dielectric layer in the third region to expose the third gate; and Before forming the source metal layer, a gate contact is formed in the second opening.

15. The method for forming a semiconductor device according to claim 14, wherein: Also includes: After forming the first opening and the second opening, forming a mask pattern on the epitaxial layer in the second region, the third region, and the fourth region, wherein the mask pattern fills the first opening and the second opening; and After removing the interlayer dielectric layer on the top surface of the epitaxial layer in the first region, the mask pattern is removed.

16. The method for forming a semiconductor device according to claim 14, wherein: Forming the source contact and the gate contact includes: Conformally forming a contact barrier layer on the epitaxial layer and in the first opening and the second opening, wherein the contact barrier layer directly contacts at least one of the first conductive component and the second conductive component, the first electrode, the second electrode, and the third gate; filling a contact conductive layer in the first opening and the second opening; and The contact barrier layer in the fourth region is removed, wherein the source metal layer directly contacts the contact barrier layer in the first region and the second region.

17. The method for forming a semiconductor device according to claim 16, wherein: Forming the source metal layer includes: forming a metal layer throughout the entire surface of the conductive contact layer, the metal layer covering and physically connecting the conductive contact layer; and The metal layer in the fourth region is removed to form the source metal layer on the epitaxial layer in the first region and the second region, and a gate metal layer is formed on the epitaxial layer in the third region, wherein the source metal layer is continuously distributed on the epitaxial layer in the first region and the second region.

18. The method for forming a semiconductor device according to claim 14, wherein: Forming the first electrode, the second electrode, the third electrode, and the fourth electrode includes: forming a first conductive material, a second conductive material, a third conductive material, and a fourth conductive material in the first trench, the second trench, the third trench, and the fourth trench, wherein the first conductive material, the second conductive material, the third conductive material, and the fourth conductive material comprise the same material; forming an oxide layer on the fourth conductive material; and An oxidation process is performed to form a first dielectric layer, a first gate dielectric layer, and a second gate dielectric layer in the first trench, the second trench, and the third trench, wherein forming the first dielectric layer, the first gate dielectric layer, and the second gate dielectric layer includes partially oxidizing a first upper portion of the first conductive material, a second upper portion of the second conductive material, and a third upper portion of the third conductive material, and the unoxidized first conductive material, the second conductive material, the third conductive material, and the fourth conductive material form the first electrode, the second electrode, the third electrode, and the fourth electrode, respectively.

19. The method for forming a semiconductor device according to claim 18, wherein: Also includes: After forming the first electrode, the second electrode, the third electrode, and the fourth electrode, an electrode material is formed on the entire surface of the epitaxial layer, wherein the electrode material fills the first trench, the second trench, and the third trench; and A patterning process is performed to remove a portion of the electrode material above the epitaxial layer in the first region, the second region, and the fourth region to form the first conductive component and the second conductive component in the first trench, the first gate and the second gate in the second trench, and the third gate in the third trench.

20. The method for forming a semiconductor device according to claim 18, wherein: After the patterning process is performed, a sidewall of the interlayer dielectric layer is located on the first dielectric layer close to the first electrode.

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