GaN vertical groove power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device on SiC substrate and manufacturing method thereof

Abstract

The invention discloses a gallium nitride (GaN) vertical groove power metal oxide semiconductor field effect transistor (MOSFET) device on a silicon carbide (SiC) substrate. The GaN vertical groove power metal oxide semiconductor field effect transistor (MOSFET) device comprises an n-SiC substrate, an n < + >-AlxGaN conductive buffer layer, an n <->-GaN drift layer, a p-GaN channel layer and an n < + >-GaN source contact layer from bottom to top in sequence. The gate dielectric layer and the gate form a vertical trench extending into the drift layer over the source contact layer. Sources are arranged on the two sides of the grid, and a drain is arranged below the substrate. The ohmic contacts of the gate and the source are separately exposed on the upper surface of the device. In particular, the aluminum content of the conductive buffer layer is gradually reduced from bottom to top. The invention further discloses a manufacturing method of the device.

Description

Technical Field

[0001] The present invention relates to the field of power devices, and in particular to a gallium nitride (GaN) vertical trench power metal oxide semiconductor field effect transistor (MOSFET) device on a silicon carbide (SiC) substrate and a manufacturing method thereof.

[0002] List of abbreviations and symbols

[0003] Al Aluminum

[0004] Al2O3 aluminum oxide

[0005] ALD Atomic Layer Deposition

[0006] AlxGaN Aluminum Gallium Nitride

[0007] Au gold

[0008] B Boron

[0009] Beryllium

[0010] Ca Calcium

[0011] Cu Copper

[0012] FET Field Effect Transistor

[0013] GaAs Gallium Arsenide

[0014] GaN Gallium Nitride

[0015] GaN-on-Si Gallium Nitride on Silicon Substrate

[0016] GaN-on-SiC Gallium Nitride on Silicon Carbide Substrate

[0017] Germanium

[0018] HEMT High Electron Mobility Transistor

[0019] HfO2 Hafnium Dioxide

[0020] HVPE Halide Vapor Phase Epitaxy

[0021] ICP Inductively Coupled Plasma

[0022] LPCVD Low Pressure Chemical Vapor Deposition

[0023] MBE Molecular Beam Epitaxy

[0024] Mg

[0025] MgO magnesium oxide

[0026] MOCVD Metal Organic Chemical Vapor Deposition

[0027] MOSFET Metal Oxide Semiconductor Field Effect Transistor

[0028] N Nitrogen

[0029] N2 nitrogen

[0030] NH3 ammonia

[0031] Nickel

[0032] Oxygen

[0033] Phosphorus

[0034] PECVD Plasma Enhanced Chemical Vapor Deposition

[0035] Pt platinum

[0036] RIE Reactive Ion Etching

[0037] RTA Rapid Thermal Annealing

[0038] SBD Schottky Barrier Diode

[0039] Sc2O3 scandium oxide

[0040] Si

[0041] SiC Silicon Carbide

[0042] SiO2 silicon dioxide

[0043] SixNy silicon nitride

[0044] Ti Titanium

[0045] TMAH Tetramethylammonium hydroxide

[0046] TMG Trimethyl Gallium

[0047] Zn

[0048] ZrO2 Zirconium Dioxide Background Art

[0049] GaN is a III-nitride compound semiconductor with a large band gap of approximately 3.4 eV. The indirect transition conduction band is located at an energy level 1.5 eV higher than the band gap. The saturation velocity of GaN is approximately 2.5×10 7 cm / s, which is higher than other types of semiconductors, such as Si, GaAs, and SiC. In addition, the breakdown electric field of GaN is about 5×10 6 V / cm, which is greater than SiC and more than an order of magnitude greater than Si and GaAs. Therefore, GaN has physical properties suitable for use in high-frequency, high-temperature, and high-power semiconductor devices.

[0050] In this specification, n indicates that electrons are the majority carriers, and p indicates that holes are the majority carriers. Elements such as O, Si, or Ge can be used as n-type dopants for GaN. The p-type dopant for GaN can be an element such as Mg, Be, Ca, or Zn. The n-dopant for SiC can be an element such as N or P. The p-type dopant for SiC can be an element such as B or Al. A “+” written to the upper right of “n” and “p” indicates that the carrier concentration is higher than when the “+” is not written, and a “-” written to the upper right of “n” and “p” indicates that the carrier concentration is lower than when the “-” sign is not written.

[0051] Over the past two decades, research has focused on the development of normally-off AlGaN / GaN heterojunction-based high-power transistor devices and fabrication processes, resulting in commercially viable, reliable transistors. However, existing commercial lateral GaN power transistors based on AlGaN / GaN heterojunctions still suffer from several issues, including: low threshold voltage (typically 1V-2V) leading to false turn-on; limited packaging density due to lateral device design; and high gate leakage and a lack of avalanche blocking capability due to the use of Schottky gate contacts.

[0052] For lateral GaN power devices, GaN-on-Si technology has been widely adopted. Panasonic is the patent holder for GaN-on-Si HEMTs with p-GaN gates and has extensive experience developing power p-GaN gate HEMTs. However, this technology has several limitations: a low threshold voltage (typically 1V-2V), which can lead to false turn-on; high gate leakage current and limited gate voltage swing due to the Schottky gate contact; limited packaging density due to the lateral device design; and a complex buffer layer structure to prevent wafer warping and cracking. Infineon also uses p-GaN HEMT technology for power applications, but its products have similar limitations. Innoscience is the first company in China to establish an 8-inch GaN-on-Si platform. Its products include single GaN FETs and half-bridge GaN FETs. Some of these products have been used in fast-charging applications. However, the company's technology is licensed from IMEC, and they also employ p-GaN gate HEMT transistors on Si. Transphorm's products use cascode technology, but the switching speed of the devices is limited.

[0053] To improve the rated voltage and current handling capabilities of GaN transistors, device structures with vertical current conduction paths have attracted extensive research interest. NexGen Power Systems designs, develops and manufactures the NexGen Vertical Semiconductors with vertical structure designs can be used in high-power applications and power conversion systems.

[0054] Figure 1 The xyz coordinate system is shown. For convenience, in the present invention, the positive direction roughly along the z-axis is referred to as "up", "upward" or "above", etc., and the negative direction roughly along the z-axis is referred to as "down", "downward" or "below", etc. The direction roughly along the x-axis is referred to as the "lateral" direction, and the direction roughly along the z-axis is referred to as the "vertical" direction. The vertical trench MOSFET adopts a vertical topology, and a high-voltage chip can be realized by increasing the thickness of the drift region without sacrificing the device size. The advantage of the vertical MOSFET is that the breakdown voltage from the drain to the source can be very high because the drift region of the vertical MOSFET is the entire thickness of the substrate. The drift region provides support for the electric field generated by the voltage gradient between the source or gate and the drain. The GaN vertical trench MOSFET process is simple, does not require regrowth, and is suitable for large-scale production and application in the industry. The GaN vertical trench MOSFET can provide a high threshold voltage to protect conduction and avalanche blocking capability.

[0055] R. Zhu et al. [1] studied the effect of p-GaN bulk doping concentration on the on-state performance of a quasi-vertical GaN trench MOSFET on a sapphire substrate (where the drain is located on the top surface of the device). The sapphire substrate is primarily composed of Al2O3. Lower p-GaN doping can increase the maximum drain current and reduce the on-resistance, but at the expense of a lower threshold voltage. Furthermore, its quasi-vertical design also limits its packaging density.

[0056] C.Liu et al. [2] first realized GaN vertical trench MOSFET on a cost-effective Si substrate. The device has a high breakdown voltage of 645V, a high threshold voltage of 6.3V, and a 8 The on-off ratio and the higher on-resistance are 6.8mΩ·cm 2 .

[0057] Y. Zhang et al. [3] fabricated and characterized a large-area GaN vertical power FinFET (a FET with a thin vertical fin rather than a flat top surface) using GaN as the substrate. The device has a high current of more than 5A and a high breakdown voltage of 1.2kV. The device also exhibits good high-frequency switching capability.

[0058] Y.Li et al. [4] demonstrated a low on-resistance fully vertical GaN-on-SiC SBD with a highly conductive buffer structure between the GaN drift layer and the SiC substrate.

[0059] US20180061934A1[5] provides a vertical MOSFET having a compound semiconductor GaN layer, which mainly includes a gate, a gate insulating film arranged between the gate and the compound semiconductor layer, a drift region arranged to be in direct contact with at least a portion of the gate insulating film and serving as a portion of the compound semiconductor layer, and a high-resistance region at least arranged in the drift region and located below at least a portion of the gate insulating film, wherein the resistance value per unit length of the high-resistance region is higher than that of the drift region.

[0060] US10903352B2[6] provides a method for manufacturing a vertical GaN-based semiconductor device, comprising: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region, wherein the doping concentration of n-type impurities in the drift region is lower than the doping concentration of the GaN-based semiconductor substrate, and the GaN-based semiconductor layer is disposed on the GaN-based semiconductor substrate; and a MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film. The method comprises: implanting an n-type dopant into the lower surface of the GaN-based semiconductor substrate to form the MIS structure, and annealing the GaN-based semiconductor substrate after implanting the n-type dopant.

[0061] GaN-on-GaN technology has been widely used in existing research and inventions for vertical GaN power devices. However, the high cost of GaN substrates limits its application. Compared with GaN-on-GaN technology, GaN-on-SiC technology is a more cost-effective method for manufacturing vertical power devices. This paper proposes a design and manufacturing method for a GaN-on-SiC vertical trench power MOSFET device. Summary of the Invention

[0062] The present invention discloses a GaN vertical trench power MOSFET device on a SiC substrate, comprising: a SiC substrate having a first n-type doping concentration; an AlxGaN conductive buffer layer having a second n-type doping concentration and located above the substrate; a GaN drift layer having a third n-type doping concentration and located above the conductive buffer layer; a GaN channel layer having a p-type doping concentration and located above the drift layer; a GaN source contact layer having a fourth n-type doping concentration and located above the channel layer; a gate dielectric layer having a lateral epitaxial portion located above the source contact layer and a longitudinal trench portion passing through the source contact layer and the channel layer and entering the drift layer, the lateral epitaxial portion and the longitudinal trench portion of the gate dielectric layer forming an uninterrupted trench-shaped surface; and a gate, wherein an ohmic contact layer of the gate covers the trench-shaped surface of the gate dielectric layer, thereby forming a trench shape, and the gate has a substantially uniform distribution of doping potentials. The lateral width of the lateral epitaxial portion is smaller than the lateral width of the lateral epitaxial portion of the gate dielectric layer; a source electrode, the source electrodes are arranged on both sides of the gate and are spaced apart from the gate dielectric layer, each of the sources includes a source ohmic contact and a body metal, the upper surface of the body metal is flush with the upper surface of the source contact layer and passes through the source contact layer into the channel layer, the source ohmic contact is arranged above the body metal, the lateral width of the source ohmic contact is greater than the lateral width of the body metal, so that the source ohmic contact is at least partially in contact with the upper surface of the source contact layer; and a drain electrode, the ohmic contact of the drain electrode is located below the substrate and covers the entire lower surface of the substrate, wherein the ohmic contacts of the gate and the source electrode are separately exposed above the upper surface of the device, wherein the aluminum content of the conductive buffer layer gradually decreases from bottom to top.

[0063] In some embodiments, the second and fourth n-type doping concentrations are greater than the first n-type doping concentration, and the first n-type doping concentration is greater than the third n-type doping concentration.

[0064] In some embodiments, the dopant having the first to fourth n-type doping concentrations is Si, and the p-type dopant is Mg.

[0065] In some embodiments, the first n-type doping concentration is about 1×10 18 cm -3 , the second n-type doping concentration is about 1x10 19 cm -3 , the third n-type doping concentration is about 1x10 16 cm -3 , the fourth n-type doping concentration is about 5x10 18 cm -3 , and the concentration of p-type doping is about 1x10 19 cm -3 .

[0066] In some embodiments, the substrate thickness is about 350 μm, the conductive buffer layer thickness is about 160 nm, the drift layer thickness is about 5 μm, the channel layer thickness is about 400 nm, and the source contact layer thickness is about 200 nm.

[0067] In some embodiments, the gate dielectric layer is composed of one or more layers, and the material constituting each layer is selected from one or more of the following dielectrics: SiO2, Al2O3, SixNy, ZrO2, HfO2, MgO or Sc2O3; the ohmic contact of the gate is selected from one or more of the following materials: a metal film formed by Ti, Al, Au, Pt, Ni or an alloy of these metals; the body metal is selected from one or more of the following materials: Ni or Au; the source ohmic contact is selected from one or more of the following materials: Ti, Al, Ni or Cu; and the material of the drain ohmic contact is Ni.

[0068] In some embodiments, the gate dielectric layer is Al2O3 with a thickness of approximately 45 nm.

[0069] In some embodiments, the conductive buffer layer includes at least a first conductive buffer layer in which the Al content is uniformly distributed and a second conductive buffer layer in which the Al content gradually decreases from bottom to top.

[0070] In some embodiments, the first conductive buffer layer is Al2O3 having a thickness of about 70 nm. 0.145 GaN layer.

[0071] In some embodiments, the second conductive buffer layer is Al2O3 having a thickness of about 90 nm. 0.145→0 GaN layer, wherein the Al doping decreases linearly from 0.145 to 0 from bottom to top.

[0072] In some embodiments, the lattice structure of the substrate is 4H-SiC, 6H-SiC, or 3C-SiC.

[0073] In some embodiments, the device further includes an edge terminal for separating the device, the edge terminal being located on a lateral side of each source away from the gate and spaced apart from the source ohmic contact, the edge terminal passing through the source contact layer and the channel layer and entering the drift layer.

[0074] The present invention also discloses a method for manufacturing a GaN vertical trench power MOSFET device on a SiC substrate, comprising: epitaxially growing, at least partially from a SiC substrate having a first n-type doping concentration, an AlxGaN conductive buffer layer having a second n-type doping concentration, a GaN drift layer having a third n-type doping concentration, a GaN channel layer having a p-type doping, and a GaN source contact layer having a fourth n-type doping concentration; dry etching or wet etching from the upper surface of the source contact layer to form a gate trench and a p-body contact of the channel layer; forming an edge terminal for separating the device by mesa dry etching and / or ion implantation; dry etching the p-body contact to activate the channel layer; depositing a drain metal on the lower surface of the substrate and annealing to form an ohmic contact of the drain; depositing a gate dielectric on the upper surface of the device and patterning the gate dielectric into a gate dielectric layer; and depositing body metal, a source ohmic contact, and a gate.

[0075] In some embodiments, the epitaxial growth method is selected from at least one of the following methods: HVPE, MBE, or MOCVD.

[0076] In some embodiments, the dry etching is selected from at least one of the following methods: ICP etching or RIE.

[0077] In some embodiments, the deposition is selected from at least one of the following methods: ALD, PECVD, LPCVD, or sputtering.

[0078] In some embodiments, the second and fourth n-type doping concentrations are greater than the first n-type doping concentration, and the first n-type doping concentration is greater than the third n-type doping concentration.

[0079] In some embodiments, the dopant having the first to fourth n-type doping concentrations is Si, and the p-type dopant is Mg.

[0080] In some embodiments, the first n-type doping concentration is about 1×10 18 cm -3 , the second n-type doping concentration is about 1x10 19 cm -3 , the third n-type doping concentration is about 1x10 16 cm -3 , the fourth n-type doping concentration is about 5x10 18 cm -3 , and the p-type doping concentration is about 1x10 19 cm -3 .

[0081] In some embodiments, the substrate thickness is about 350 μm, the conductive buffer layer thickness is about 160 nm, the drift layer thickness is about 5 μm, the channel layer thickness is about 400 nm, and the source contact layer thickness is about 200 nm.

[0082] In some embodiments, the gate dielectric layer is composed of one or more layers, and the material constituting each layer is selected from one or more of the following dielectrics: SiO2, Al2O3, SixNy, ZrO2, HfO2, MgO or Sc2O3; the ohmic contact of the gate is selected from one or more of the following materials: a metal film formed by Ti, Al, Au, Pt, Ni or an alloy of these metals; the body metal is selected from one or more of the following materials: Ni or Au; the source ohmic contact is selected from one or more of the following materials: Ti, Al, Ni or Cu; and the material of the drain ohmic contact is Ni.

[0083] In some embodiments, the gate dielectric layer is Al2O3 with a thickness of about 45 nm.

[0084] In some embodiments, the conductive buffer layer includes at least a first conductive buffer layer in which the Al content is uniformly distributed and a second conductive buffer layer in which the Al content gradually decreases from bottom to top.

[0085] In some embodiments, the first conductive buffer layer is Al2O3 having a thickness of about 70 nm. 0.145 GaN layer.

[0086] In some embodiments, the second conductive buffer layer is Al2O3 having a thickness of about 90 nm. 0.145→0 GaN layer, wherein the Al doping decreases linearly from 0.145 to 0 from bottom to top.

[0087] In some embodiments, the lattice structure of the substrate is 4H-SiC, 6H-SiC, or 3C-SiC.

[0088] Other features and advantages will become apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] The foregoing and further features of the present invention will become apparent from the following description of preferred embodiments provided by way of example only and taken in conjunction with the accompanying drawings, in which:

[0090] Figure 1 Schematic diagram of a GaN-on-SiC vertical trench power MOSFET device according to an embodiment of the present invention is shown;

[0091] Figure 2 Schematic diagram of a GaN-on-SiC vertical trench power MOSFET device according to an embodiment of the present invention is shown;

[0092] Figure 3 A flow chart showing a method for manufacturing a GaN-on-SiC vertical trench power MOSFET according to an embodiment of the present invention is shown;

[0093] Figure 4A A schematic diagram showing a transfer curve of a GaN-on-SiC vertical trench power MOSFET according to an embodiment of the present invention is shown;

[0094] Figure 4B FIG. 1 is a schematic diagram showing an output curve of a GaN-on-SiC vertical trench power MOSFET according to an embodiment of the present invention. DETAILED DESCRIPTION

[0095] As used herein, the terms "first," "second," and "third" are used interchangeably to distinguish one component from another, rather than to indicate the position or importance of a single component. The singular expressions "a," "an," and "the" also include the plural, unless the context clearly dictates otherwise. Terms such as "coupled," "fixed," and "connected to" refer to direct coupling, fixing, or connection, as well as indirect coupling, fixing, or connection through one or more intermediate components or features, unless the context clearly dictates otherwise. The terms "comprise," "include," "compose," "have," or any other variations thereof herein are intended to encompass non-exclusive inclusion. For example, a process, method, article, or device that includes a set of features is not necessarily limited to those features, but may include features not explicitly listed or other features inherent to such a process, method, article, or device. In addition, unless expressly stated to the contrary, "or" is inclusive rather than exclusive. For example, any of the following satisfies condition A or B: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), and both A and B are true (or exist).

[0096] Terms indicating approximation, such as "about," "approximately," "substantially," or "substantially," are understood to include values ​​within 10% greater or less than the value being described, unless a range is explicitly stated in the specification. When used in the context of an angle or direction, these terms include values ​​within 10 degrees greater or less than the angle or direction being described. For example, "substantially perpendicular" includes directions within 10 degrees of perpendicular in any direction (e.g., clockwise or counterclockwise).

[0097] It should be understood that, if any prior art publication is cited herein, such reference does not constitute an admission that the publication forms part of the common general knowledge in the art in any country.

[0098] The present invention describes the design and manufacturing method of GaN-on-SiC vertical trench power MOSFET for high power applications. In the present invention, GaN-on-SiC technology is used. GaN-on-SiC has a high thermal conductivity. The thermal conductivity of GaN-on-SiC is three times that of GaN-on-Si, enabling the device to operate at higher voltages and higher power densities. SiC can have different stacking forms, resulting in different lattice structures, such as 2H-SiC, 3C-SiC, 4H-SiC, 6H-SiC, 15R-SiC, etc. An appropriate SiC lattice structure (for example, the present invention preferably uses 4H-SiC, 6H-SiC or 3C-SiC) is selected to lattice match GaN, so that higher crystal quality can be achieved without a thicker buffer layer, reducing the cost of epitaxial manufacturing. High crystal quality ensures low leakage and high stability of the device. In addition, GaN-on-SiC can easily achieve a fully vertical (as opposed to lateral or quasi-vertical) design.

[0099] Figure 1 FIG2 shows a schematic diagram of a GaN-on-SiC vertical trench power MOSFET device according to an embodiment of the present invention. Figure 1 As shown, the SiC substrate 101 has a first n-type doping concentration, which can be recorded as "n-SiC substrate". The present invention uses N or P as the n-type dopant of the SiC substrate 101. The doping concentration range can be 1x10 17 cm -3 ~1x10 20 cm -3 , preferably about 1x10 18 cm -3 The thickness of the SiC substrate 101 ranges from 100 μm to 1000 μm. To lattice-match the GaN buffer layer located above it, the lattice structure of the SiC substrate can be 4H-SiC, 6H-SiC, or 3C-SiC. This allows the GaN buffer layer to be sufficiently thin. Preferably, the SiC substrate 101 is 4H-SiC with a thickness of approximately 350 μm.

[0100] The conductive buffer layer 102 is located above the SiC substrate 101. The conductive buffer layer 102 is an Al-doped GaN layer with Si as an n-type dopant, which can be recorded as “n + -AlxGaN layer", with a second n-type doping concentration. The doping concentration of Si can range from 1x10 17 cm -3 ~1x10 20 cm -3 , the preferred doping concentration is about 1×10 19 cm -3In the present application, the conductive buffer layer 102 can be as thin as about 20 nm. This is because the SiC substrate and the AlGaN layer are designed to be lattice-matched. The thickness of the conductive buffer layer 102 can range from 20 nm to 400 nm. For example, the thickness of the conductive buffer layer can be about 160 nm.

[0101] The drift layer 103 is located above the conductive buffer layer 102. The drift layer 103 is n - -GaN layer, with a third n-type doping concentration. The present invention preferably uses Si as the n-type dopant of the drift layer 103. The doping concentration of Si can range from 5x10 15 cm -3 ~1x10 17 cm -3 , the preferred doping concentration is about 1×10 16 cm -3 The drift layer 103 may have a thickness ranging from 1 μm to 20 μm, preferably about 5 μm.

[0102] The channel layer 104 is located above the drift layer 103. The channel layer 104 is a p-GaN layer with p-type doping. In the present invention, Mg is preferably used as the p-type dopant of the channel layer 104. The doping concentration of Mg can be in the range of 1×10 17 cm -3 ~1×10 20 cm -3 , the preferred doping concentration is about 1×10 19 cm -3 The thickness of the channel layer 104 may be in the range of 100 nm to 2000 nm, and preferably is about 400 nm.

[0103] The source contact layer 105 is located above the channel layer 104. The source contact layer 105 is n + -GaN layer, having a fourth n-type doping concentration. The present invention preferably uses Si as the n-type dopant of the source contact layer 105. The doping concentration of Si can be in the range of 1×10 17 cm -3 ~1×10 20 cm -3 , the preferred doping concentration is about 5×10 18 cm -3 The thickness of the source contact layer 105 may be in the range of 100 nm to 500 nm, and preferably is about 200 nm.

[0104] A trench-type gate dielectric layer 107 is located above the source contact layer 105. The gate dielectric layer 107 has a lateral epitaxial portion 107a located above the source contact layer 105 and a vertical trench portion 107b extending through the source contact layer 105 and the channel layer 104 and into the drift layer 103. The lateral epitaxial portion 107a and the vertical trench portion 107b of the gate dielectric layer 107 form a continuous trench-type surface. The lateral epitaxial portion 107a only covers a portion of the upper surface 105a of the source contact layer 105. The gate dielectric layer 107 is composed of one or more layers, each of which is made of one or more of the following materials: SiO2, Al2O3, Si6Ny, ZrO2, HfO2, MgO, or Sc2O3. The use of a high-k oxide layer allows for the use of a thinner oxide layer. This arrangement can provide higher drain current and transconductance. Preferably, the gate dielectric layer 107 is Al 2 O 3 with a thickness of about 45 nm.

[0105] The ohmic contact layer of gate 110 overlies the trenched surface of gate dielectric layer 107, thereby forming an appearance having a lateral epitaxial portion 110a and a vertical trench portion 110b. The lateral width of lateral epitaxial portion 110a of gate 110 is smaller than the lateral width of lateral epitaxial portion 107a of gate dielectric layer 117. The ohmic contact of gate 110 is selected from one or more of the following materials: a metal film formed of Ti, Al, Au, Pt, Ni, or alloys of these metals.

[0106] The source electrodes are disposed on either side of the gate 110, spaced apart from the gate dielectric layer 107. Each source electrode includes a source ohmic contact 109 and a bulk metal 108. The upper surface of the bulk metal 108 is flush with the upper surface 105a of the source contact layer 105 and extends through the source contact layer 105 into the channel layer 104. The bulk metal 108 is selected from one or more of the following materials: Ni or Au. The source ohmic contact 109 is disposed above the bulk metal 108. The lateral width of the source ohmic contact 109 is greater than the lateral width of the bulk metal 108, such that the source ohmic contact 109 at least partially contacts the upper surface 105a of the source contact layer 105. The source ohmic contact 109 is selected from one or more of the following materials: Ti, Al, Ni, or Cu. For example, the source ohmic contact 109 may be a stack of Ti and Al. These stacks can be formed by known methods such as sputtering and evaporation, or patterned by known methods, such as deposition with lift-off and / or subsequent etching. GaN etching can include, for example, ICP etching and / or other suitable GaN dry / wet etching processes.

[0107] The ohmic contact of the drain electrode 106 is located below the SiC substrate 101 and covers the entire lower surface of the SiC substrate 101. Placing the drain electrode 106 on the lower surface of the substrate can achieve a higher packaging density. Preferably, the ohmic contact material of the drain electrode 106 is Ni.

[0108] An edge terminal 111 for isolating the device is located on a lateral side of each source away from the gate. The edge terminal 111 is laterally spaced apart from the source ohmic contact 109. The edge terminal 111 passes through the source contact layer 105 and the channel layer 104 and enters the drift layer 103.

[0109] Figure 2 Schematic diagram of a GaN-on-SiC vertical trench power MOSFET device according to an embodiment of the present invention is shown. Figure 1 The difference is, Figure 2 The edge terminal 111 is not shown. Those skilled in the art will appreciate that the edge terminal 111 can be provided as needed. Figure 2 The Al content of the conductive buffer layer 102 gradually decreases from bottom to top. For the convenience of description herein, the "gradually decreasing" also includes the case where part of it is constant. For example, the conductive buffer layer 102 can be divided into at least a first buffer layer 102a (denoted as "n + -Al 0.145 GaN layer”) and the second buffer layer 102b (denoted as “n + -Al 0.145→0 GaN layer"). The thickness of the first buffer layer 102a is in the range of 10nm to 200nm, preferably with a thickness of about 70nm. The Al content in the first buffer layer 102a can be uniformly distributed with a doping ratio of about 0.145. The thickness of the second buffer layer 102b is in the range of 10nm to 200nm, preferably with a thickness of about 90nm. It is noted that the Al content of the second buffer layer 102b gradually decreases from bottom to top, preferably linearly decreases from (about) 0.145 to 0. The inventors of the present invention have found that such an Al distribution can achieve the technical effect of reducing the contact resistance of the buffer layer. The reason is that the use of a buffer layer with a gradient Al composition can significantly reduce the conduction band step between the buffer layer and the drift layer.

[0110] Figure 3 A flow chart of a method for manufacturing a GaN-on-SiC vertical trench power MOSFET according to an embodiment of the present invention is shown.

[0111] In step S100, n is epitaxially grown at least partially from above the SiC substrate 101. + -AlxGaN conductive buffer layer 102, n - -GaN drift layer 103, p-GaN channel layer 104, n +-GaN source contact layer 105. In some embodiments, the n + During the formation of the AlxGaN conductive buffer layer 102, n + -Al 0.145 GaN first conductive buffer layer 102a and n + -Al 0.145→0 The GaN second conductive buffer layer 102b can be grown by at least one of the following methods: HVPE, MBE, or MOCVD. For example, an n-type doped GaN layer can be formed by MOCVD using TMG, NH3, and a suitable carrier gas.

[0112] In step S101, from n + The upper surface of the p-GaN source contact layer 105 is dry-etched to form a gate trench 120 and a p-body contact 130 for the p-GaN channel layer 104. The p-body contact 130 is located within the channel layer 104 and adjacent to the gate trench 120. Dry etching is performed using a hard mask to form a vertical gate trench structure in the device, extending from top to bottom through the source contact layer 105 and the channel layer 104 until it reaches at least a portion of the drift layer 103. Alternatively, wet etching can be performed using a TMAH solution. TMAH wet etching can effectively remove damage to the GaN sidewalls caused by dry etching.

[0113] In step S102, edge terminals 111 for separating devices are formed by mesa dry etching. The edge terminals 111 can also be formed by mesa etching, ion implantation, or a combination of these two methods.

[0114] In step S103, the p-body contact 130 is dry-etched to activate the channel layer 104. For example, after the p-body contact 130 is opened, RTA is performed in an N2 environment at 700-900°C for 5-30 minutes to activate the buried p-GaN channel layer 104.

[0115] In step S104 , a drain metal is deposited on the lower surface of the SiC substrate 101 and annealed to form an ohmic contact of the drain 106 .

[0116] In step S105, a gate dielectric is deposited on the upper surface of the device and patterned into a gate dielectric layer 107. A 45 nm thick Al3O2 gate dielectric for vertical trenches is deposited on the upper surface 105a and the surface of the gate trench 120 by ALD. The gate dielectric is patterned into Figure 1 and 2 The gate dielectric layer 107 in FIG. 1 is formed, and the opened portion of the gate dielectric is used for the ohmic contact of the source.

[0117] In steps S106 , S107 and S108 , a bulk metal 108 , a source ohmic contact 109 and a gate 110 are deposited respectively.

[0118] The dry etching method in the above steps may be ICP or RIE, and the deposition method may be ALD, PECVD, LPCVD or sputtering.

[0119] Figure 4A A schematic diagram of the transfer curve of a GaN-on-SiC vertical trench power MOSFET according to an embodiment of the present invention is shown. When the GaN-on-SiC vertical trench power MOSFET device is in operation, a predetermined voltage is applied between the source ohmic contact 109 and the drain ohmic contact 106, and a voltage equal to or greater than the threshold voltage is applied to the gate 110. At this time, an inversion layer is formed in the channel layer 104, and the inversion layer forms a channel, so that current can flow from the drain to the source, and the MOSFET is in the on state. On the contrary, when a voltage lower than the threshold voltage is applied to the gate 110, the inversion layer in the channel layer 104 disappears, so that the current from the drain to the source is interrupted, and the MOSFET is in the off state. Figure 4A It can be seen that the fabricated GaN-on-SiC vertical trench MOSFET has a high threshold voltage (V th ).

[0120] Figure 4B Schematic diagram showing the output curve of GaN-on-SiC vertical trench power MOSFET according to an embodiment of the present invention. Figure 4B The fabricated GaN-on-SiC vertical trench MOSFET achieved a low specific on-resistance of 1.98mΩ·cm 2 and a higher maximum current density of 3.8kA / cm 2 .

[0121] These results demonstrate that the GaN-on-SiC vertical trench power MOSFET of the present invention exhibits superior performance in threshold voltage, specific on-resistance, and maximum current density, demonstrating its significant potential for high-efficiency applications. The GaN-on-SiC vertical trench power MOSFET of the present invention can be applied in power management for consumer electronics, intelligent power modules for household appliances, solar inverters, and transformers for electric vehicles.

[0122] The present invention has been shown and described in detail above with reference to the accompanying drawings, but the above embodiments should be considered as illustrative rather than restrictive. Different embodiments may be combined with each other without contradiction. The present invention also includes various combinations, modifications and variations of the exemplary embodiments without departing from the spirit and scope of the present invention.

[0123] References

[0124] The following is a list of references occasionally cited in this specification. The disclosures of each of these references are incorporated herein by reference in their entirety.

[0125] [1] R.Zhu, H.Jiang, CWTang and KMLau, "Effects of p-GaN Body DopingConcentration on the ON-State Performance of Vertical GaN Trench MOSFETs," accepted by IEEE Electron Device Letters, 2021in IEEE Electron Device Letters,Vol.42,no.7,pp.970-973,2021,doi:10.1109 / LED.2021.3080260.

[0126] [2] C. Liu, R. Abdul Khadar, and E. Matioli, "GaN-on-Si Quasi-Vertical PowerMOSFETs," in IEEE Electron Device Letters, vol.39, no.1, pp.71-74, Jan.2018, doi:10.1109 / LED.2017.2779445.

[0127] [3] Y. Zhang, M. Sun, J. Perozek, Z. Liu, A. Zubair, D. Piedra, N. Chowdhury, X. Gao, K. Shepard, and T. Palacios, "Large-Area 1.2-kV GaN Vertical Power FinFETs With a Record Switching Figure of Merit," in IEEE Electron Device Letters, vol.40, no.1, pp.75-78, Jan.2019, doi:10.1109 / LED.2018.2880306.

[0128] [4]Y.Li,S.Yang,K.Liu,K.Cheng,K.Sheng and B.Shen,"Fully-Vertical GaN-on-SiC Schottky Barrier Diode:Role of Conductive Buffer Structure,"in IEEETransactions on Electron Devices,vol.70,no.2,pp.619-626,Feb.2023,doi:10.1109 / TED.2022.3227227.

[0129] [5]US20180061934A1(2018),Katsunori Ueno(JP),"Vertical mosfet"

[0130] [6]US10903352B2(2021),Takashima Shinya(JP),Katsunori Ueno(JP),andMasaharu Edo(JP)."Manufacturing method of vertical GaN-based semiconductordevice and vertical GaN-based semiconductor device".

Claims

1. A gallium nitride (GaN) vertical trench power metal oxide semiconductor (MOSFET) device on a silicon carbide (SiC) substrate, comprising: A SiC substrate having a first n-type doping concentration; an aluminum gallium nitride AlxGaN conductive buffer layer, the conductive buffer layer having a second n-type doping concentration and located above the substrate; a GaN drift layer having a third n-type doping concentration and located above the conductive buffer layer; A GaN channel layer, wherein the channel layer has p-type doping and is located above the drift layer; a GaN source contact layer, the source contact layer having a fourth n-type doping concentration and being located above the channel layer; a gate dielectric layer, the gate dielectric layer having a lateral epitaxial portion located above the source contact layer and a longitudinal trench portion passing through the source contact layer and the channel layer and entering the drift layer, wherein the lateral epitaxial portion and the longitudinal trench portion of the gate dielectric layer form an uninterrupted trench surface; a gate, wherein the ohmic contact layer of the gate is overlying the grooved surface of the gate dielectric layer to form a groove shape, and the lateral width of the lateral epitaxial portion of the gate is smaller than the lateral width of the lateral epitaxial portion of the gate dielectric layer; Source electrodes are provided on both sides of the gate and spaced apart from the gate dielectric layer, each of the source electrodes comprising a source ohmic contact and a body metal, an upper surface of the body metal being flush with an upper surface of the source contact layer and penetrating the source contact layer into the channel layer, the source ohmic contact being arranged above the body metal, a lateral width of the source ohmic contact being greater than a lateral width of the body metal, such that the source ohmic contact is at least partially in contact with the upper surface of the source contact layer; and A drain electrode, wherein the ohmic contact of the drain electrode is located below the substrate and covers the entire lower surface of the substrate. wherein the ohmic contacts of the gate and the source are separately exposed above the upper surface of the device, Wherein, the aluminum content of the conductive buffer layer gradually decreases from bottom to top.

2. The device according to claim 1, wherein The second and fourth n-type doping concentrations are greater than the first n-type doping concentration, and the first n-type doping concentration is greater than the third n-type doping concentration.

3. The device according to claim 2, wherein The dopant having the first to fourth n-type doping concentrations is silicon Si, and the dopant for the p-type doping is magnesium Mg.

4. The device according to claim 3, wherein The first n-type doping concentration is about 1x10 18 cm -3 , the second n-type doping concentration is about 1x10 19 cm -3 , the third n-type doping concentration is about 1x10 16 cm -3 , the fourth n-type doping concentration is about 5x10 18 cm -3 , and the concentration of the p-type doping is about 1x10 19 cm -3 .

5. The device according to claim 1, wherein The substrate thickness is about 350 μm, the conductive buffer layer thickness is about 160 nm, the drift layer thickness is about 5 μm, the channel layer thickness is about 400 nm, and the source contact layer thickness is about 200 nm.

6. The device according to claim 1, wherein The gate dielectric layer is composed of one or more layers, and the material constituting each layer is selected from one or more of the following dielectrics: silicon dioxide SiO2, aluminum oxide Al2O3, silicon nitride SixNy, zirconium dioxide ZrO2, hafnium dioxide HfO2, magnesium oxide MgO or scandium oxide Sc2O3; The ohmic contact of the gate is selected from one or more of the following materials: a metal film formed by titanium Ti, aluminum Al, gold Au, platinum Pt, nickel Ni or an alloy of these metals; The body metal is selected from one or more of the following materials: Ni or copper Au; The source ohmic contact is selected from one or more of the following materials: Ti, Al, Ni or Cu; and The material of the ohmic contact of the drain electrode is Ni.

7. The device according to claim 1, wherein The gate dielectric layer is aluminum oxide Al2O3 with a thickness of about 45 nm.

8. The device according to claim 1, wherein The conductive buffer layer at least includes a first conductive buffer layer in which the Al content is uniformly distributed and a second conductive buffer layer in which the Al content gradually decreases from bottom to top.

9. The device according to claim 8, wherein The first conductive buffer layer is an Al2O3 layer with a thickness of about 70 nm. 0.145 GaN layer.

10. The device according to claim 8, wherein The second conductive buffer layer is Al with a thickness of about 90 nm. 0.145→ 0GaN layer, in which the Al doping decreases linearly from 0.145 to 0 from bottom to top.

11. The device according to claim 1, wherein The lattice structure of the substrate is 4H-SiC, 6H-SiC or 3C-SiC.

12. The device according to claim 1, further comprising an edge terminal for separating the device, wherein the edge terminal is located on a lateral side of each source away from the gate and is spaced apart from the source ohmic contact, and the edge terminal passes through the source contact layer and the channel layer and enters the drift layer.

13. A method for manufacturing a gallium nitride (GaN) vertical trench power metal oxide semiconductor (MOSFET) device on a silicon carbide (SiC) substrate, comprising: Epitaxially growing, at least partially from a SiC substrate having a first n-type doping concentration, an aluminum gallium nitride AlxGaN conductive buffer layer having a second n-type doping concentration, a GaN drift layer having a third n-type doping concentration, a GaN channel layer having a p-type doping concentration, and a GaN source contact layer having a fourth n-type doping concentration; Performing dry etching or wet etching from the upper surface of the source contact layer to form a gate trench and a p-body contact of the channel layer; forming edge terminals for separating the devices by mesa dry etching and / or ion implantation; performing dry etching on the p-body contact to activate the channel layer; Depositing a drain metal on the lower surface of the substrate and annealing to form an ohmic contact of the drain; depositing a gate dielectric on the upper surface of the device and patterning the gate dielectric into the gate dielectric layer; and Deposit bulk metal, source ohmic contact, and gate.

14. The method according to claim 13, wherein: The epitaxial growth method is selected from at least one of the following methods: halide vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD).

15. The method according to claim 13, wherein The dry etching is selected from at least one of the following methods: inductively coupled plasma (ICP) etching or reactive ion etching (RIE).

16. The method according to claim 13, wherein: The deposition is selected from at least one of the following methods: atomic layer deposition ALD, plasma enhanced chemical vapor deposition PECVD, low pressure chemical vapor deposition LPCVD or sputtering.

17. The method according to claim 13, wherein: The second and fourth n-type doping concentrations are greater than the first n-type doping concentration, and the first n-type doping concentration is greater than the third n-type doping concentration.

18. The method according to claim 17, wherein The dopant having the first to fourth n-type doping concentrations is silicon Si, and the dopant for the p-type doping is magnesium Mg.

19. The method according to claim 18, wherein The first n-type doping concentration is about 1x10 18 cm -3 , the second n-type doping concentration is about 1x10 19 cm -3 , the third n-type doping concentration is about 1x10 16 cm -3 , the fourth n-type doping concentration is about 5x10 18 cm -3 , and the p-type doping concentration is about 1x10 19 cm -3 .

20. The method according to claim 13, wherein The substrate thickness is about 350 μm, the conductive buffer layer thickness is about 160 nm, the drift layer thickness is about 5 μm, the channel layer thickness is about 400 nm, and the source contact layer thickness is about 200 nm.

21. The method according to claim 13, wherein The gate dielectric layer is composed of one or more layers, and the material constituting each layer is selected from one or more of the following dielectrics: silicon dioxide SiO2, aluminum oxide Al2O3, silicon nitride SixNy, zirconium dioxide ZrO2, hafnium dioxide HfO2, magnesium oxide MgO or scandium oxide Sc2O3; The ohmic contact of the gate is selected from one or more of the following materials: a metal film formed by titanium Ti, aluminum Al, gold Au, platinum Pt, nickel Ni or an alloy of these metals; The body metal is selected from one or more of the following materials: Ni or copper Au; The source ohmic contact is selected from one or more of the following materials: Ti, Al, Ni or Cu; and The material of the ohmic contact of the drain electrode is Ni.

22. The method according to claim 13, wherein The gate dielectric layer is aluminum oxide Al2O3 with a thickness of about 45 nm.

23. The method according to claim 13, wherein The conductive buffer layer at least includes a first conductive buffer layer in which the Al content is uniformly distributed and a second conductive buffer layer in which the Al content gradually decreases from bottom to top.

24. The device according to claim 23, wherein The first conductive buffer layer is an Al2O3 layer with a thickness of about 70 nm. 0.145 GaN layer.

25. The method according to claim 23, wherein The second conductive buffer layer is Al with a thickness of about 90 nm. 0.145→0 GaN layer, wherein the Al doping decreases linearly from 0.145 to 0 from bottom to top.

26. The method according to claim 13, wherein The lattice structure of the substrate is 4H-SiC, 6H-SiC or 3C-SiC.

Images