Silicon carbide super junction structure, manufacturing method and semiconductor device

Abstract

The invention discloses a silicon carbide super-junction structure, a manufacturing method and a semiconductor device, and belongs to the technical field of semiconductors. The epitaxial layer is arranged on the upper surface of the substrate; the semiconductor column extends into the epitaxial layer; the semiconductor column comprises more than two stacked semiconductor structures; wherein the sectional area of the semiconductor structure is gradually reduced along the axial direction; the semiconductor column is of a first doping type; the substrate and the epitaxial layer are of a second doping type; therefore, the longitudinal electric field of the silicon carbide super-junction structure forms the maximum value at the central point of each semiconductor structure, the integral area of the overall electric field is increased, the charge balance point of the super-junction structure is optimized, the electric field distribution of charge balance is improved, and the improvement of charge balance improves the reverse breakdown voltage and the reliability of the device.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a silicon carbide superjunction structure, a manufacturing method, and a semiconductor device. Background Art

[0002] Related silicon carbide superjunction structures, such as Figure 1A and Figure 1B As shown, the structure comprises a substrate, an epitaxial layer, and semiconductor pillars. The semiconductor pillars have equal cross-sectional areas along the axial direction. The semiconductor pillars are of the first type, while the substrate and epitaxial layer are of the second type. The first type is either P-type or N-type, while the second type is the other of these two types, thus forming a superjunction structure. The longitudinal electric field distribution of this silicon carbide superjunction structure is shown in Figure 1. Because the electric field intensity has only one peak point, the integrated electric field area is small, resulting in a low reverse breakdown voltage and poor reliability.

[0003] Therefore, the related silicon carbide super junction structure has the problems of small reverse breakdown voltage and poor reliability. Summary of the Invention

[0004] The purpose of this application is to provide a silicon carbide super junction structure, a manufacturing method and a semiconductor device, aiming to solve the problems of low reverse breakdown voltage and poor reliability of related silicon carbide super junction structures.

[0005] An embodiment of the present application provides a silicon carbide super junction structure, comprising:

[0006] substrate;

[0007] an epitaxial layer disposed on the upper surface of the substrate;

[0008] a semiconductor pillar extending into the interior of the epitaxial layer;

[0009] The semiconductor column comprises two or more superimposed semiconductor structures; the cross-sectional area of ​​the semiconductor structure gradually decreases along the axial direction;

[0010] The semiconductor pillar is of a first doping type; the substrate and the epitaxial layer are of a second doping type.

[0011] In one embodiment, the semiconductor column includes n stacked semiconductor structures; wherein n is 2 or 3.

[0012] In one embodiment, the height of the semiconductor structure is between 2 microns and 9 microns.

[0013] In one embodiment, the cross-section of the semiconductor structure comprises a polygon, and the width of the polygon gradually decreases along the axial direction;

[0014] The cross section of the semiconductor structure is parallel to the axial direction;

[0015] The axial direction is perpendicular to the upper surface of the substrate.

[0016] In one embodiment, the silicon carbide super junction structure further includes:

[0017] a charge storage layer disposed on the upper surface of the epitaxial layer;

[0018] a first well region extending downward from the charge storage layer to the semiconductor pillar;

[0019] two active layers extending downward from the upper surface of the first well region to the interior of the first well region and spaced apart from each other;

[0020] Two gate structures each cover a portion of the charge storage layer, the active layer and a portion of the first well region.

[0021] In one embodiment, the substrate, the epitaxial layer, and the semiconductor pillar are made of silicon carbide.

[0022] The present invention also provides a method for manufacturing a silicon carbide superjunction structure, the method comprising:

[0023] forming a sub-epitaxial layer on the upper surface of the substrate;

[0024] forming a sub-groove; wherein the sub-groove penetrates the sub-epitaxial layer and has a cross-sectional area gradually decreasing along the axial direction;

[0025] forming a semiconductor structure in the sub-trench;

[0026] Wherein, the base material is a substrate, or the base material is a composite structure including the sub-epitaxial layer and the semiconductor structure;

[0027] Wherein, two or more sub-epitaxial layers are stacked to form an epitaxial layer; and two or more semiconductor structures are stacked to form a semiconductor pillar.

[0028] In one embodiment, the steps in the manufacturing method are cyclically repeated more than twice.

[0029] In one embodiment, forming the sub-grooves includes:

[0030] forming a first mask layer on the upper surface of the sub-epitaxial layer;

[0031] removing a portion of the first mask layer to form a second mask layer on the upper surface of the sub-epitaxial layer;

[0032] removing a portion of the sub-epitaxial layer to form the sub-trench;

[0033] The second mask layer is removed.

[0034] In one embodiment, after the steps in the manufacturing method are cyclically repeated for more than two times, the manufacturing method further comprises:

[0035] forming a charge storage layer on the upper surface of the epitaxial layer;

[0036] forming a first well region covering the semiconductor pillar through the charge storage layer;

[0037] forming two active layers on the upper surface of the first well region and extending downward to the interior of the first well region; wherein the two active layers are spaced apart;

[0038] Two gate structures are formed, each covering a portion of the charge storage layer, the active layer and a portion of the first well region.

[0039] An embodiment of the present application further provides a semiconductor device, which includes the above-mentioned silicon carbide super junction structure.

[0040] An embodiment of the present application further provides an electronic device, which includes the above-mentioned semiconductor device.

[0041] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the semiconductor pillar includes two or more superimposed semiconductor structures, wherein the cross-sectional area of ​​the semiconductor structure gradually decreases along the axial direction, the longitudinal electric field of the silicon carbide superjunction structure forms a maximum value at the center point of each semiconductor structure, the overall electric field integrated area is increased, the charge balance point of the superjunction structure is optimized, and the charge balanced electric field distribution is improved. The improvement in charge balance increases the reverse breakdown voltage and improves the device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical inventions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1A and Figure 1B Schematic diagram of the first structure of the related silicon carbide super junction structure;

[0044] Figure 2 Schematic diagram of the longitudinal electric field distribution of the related silicon carbide superjunction structure;

[0045] Figure 3A and Figure 3B A schematic structural diagram of a silicon carbide superjunction structure provided in one embodiment of the present application;

[0046] Figure 4 A schematic diagram of the longitudinal electric field distribution of a silicon carbide superjunction structure provided in one embodiment of the present application;

[0047] Figure 5A and Figure 5B Another structural schematic diagram of a silicon carbide superjunction structure provided in one embodiment of the present application;

[0048] Figure 6A and Figure 6B A schematic diagram of forming a sub-epitaxial layer in the method for manufacturing a silicon carbide superjunction structure provided in an embodiment of the present application;

[0049] Figure 7A and Figure 7B A schematic diagram of forming a sub-trench in the method for manufacturing a silicon carbide super junction structure provided in an embodiment of the present application;

[0050] Figure 8A and Figure 8B A schematic diagram of forming a semiconductor structure in the method for manufacturing a silicon carbide superjunction structure provided in an embodiment of the present application;

[0051] Figure 9A and Figure 9B A schematic diagram of forming a semiconductor pillar in the method for manufacturing a silicon carbide super junction structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0053] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0054] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0056] Figure 3A and Figure 3B The silicon carbide super junction structure provided by an embodiment of the present invention is shown. For ease of illustration, only the portion related to the embodiment of the present invention is shown, which is described in detail as follows:

[0057] The silicon carbide super junction structure includes a substrate 100 , an epitaxial layer 90 and a semiconductor pillar 80 .

[0058] The epitaxial layer 90 is disposed on the upper surface of the substrate 100 .

[0059] The semiconductor pillar 80 extends into the epitaxial layer 90 . In one embodiment, the semiconductor pillar 80 extends from the upper surface of the epitaxial layer 90 to the inside of the epitaxial layer 90 .

[0060] It should be emphasized that the semiconductor column 80 includes two or more stacked semiconductor structures 81 ; wherein the cross-sectional area of ​​the semiconductor structure 81 gradually decreases along the axial direction.

[0061] The semiconductor pillar 80 is of a first doping type; the substrate 100 and the epitaxial layer 90 are of a second doping type; the first type is one of P-type and N-type, and the second type is the other of P-type and N-type.

[0062] In a specific implementation, a semiconductor column 80 of the first doping type and an epitaxial layer 90 of the second doping type constitute a "super junction unit". When turned on, the current flows vertically through the low-impedance N-type semiconductor column 80 or the N-type epitaxial layer 90; when turned off, the depletion layer formed by the semiconductor column 80 of the first doping type and the epitaxial layer 90 of the second doping type share the electric field together to achieve high-voltage bearing capacity. The total amount of doping of the semiconductor column 80 of the first doping type and the epitaxial layer 90 of the second doping type must be strictly equal to ensure that the electric field is uniformly distributed when fully depleted to avoid local breakdown. At the same time, the semiconductor column 80 includes two or more superimposed semiconductor structures 81; wherein the cross-sectional area of ​​the semiconductor structure 81 gradually decreases along the axial direction, and the longitudinal electric field distribution of the silicon carbide super junction structure is as follows: Figure 4As shown, since the side surfaces of the semiconductor structure 81 are inclined at a certain angle, according to the charge balance principle, the longitudinal electric field of the silicon carbide super junction structure forms a maximum value at the center point of each semiconductor structure 81, and the overall electric field integral area is increased, thereby optimizing the charge balance point of the super junction structure and improving the charge balanced electric field distribution. The improvement in charge balance increases the reverse breakdown voltage and improves the device reliability.

[0063] It should be noted that the first doping type is P-type and the second doping type is N-type; or

[0064] The first doping type is N-type, and the second doping type is P-type.

[0065] In one embodiment, the semiconductor pillar 80 includes n stacked semiconductor structures 81 , where n is 2 or 3. It is understood that the thickness of the semiconductor structure 81 is K, which is less than the thickness of the epitaxial layer 90 divided by n.

[0066] Since one etching and two epitaxial processes are added each time a semiconductor structure 81 is manufactured, by providing two or three stacked semiconductor structures 81 , the electric field distribution is improved while simplifying the manufacturing process and saving costs.

[0067] In one embodiment, the heights h, h of the semiconductor structure 81 are between 2 μm and 9 μm.

[0068] It can be understood that, at this time, the number of the semiconductor structures 81 is m, where m is the integer of the quotient of the thickness of the epitaxial layer 90 divided by h.

[0069] Due to lattice and orientation limitations, SiC's current deep trench etching technology is still immature. When developing trenches deeper than 10µm, the difference between the top and bottom is significant, easily disrupting the charge balance at the bottom. The creation of micro-trenching also makes it more likely to disrupt the equilibrium state of the superjunction structure. Furthermore, filling SiC epitaxy with high aspect ratios remains challenging, and voids are prone to forming within the trenches, leading to device performance degradation or charge imbalance.

[0070] By setting a reasonable height of the semiconductor structure 81, the sidewall interface state and roughness of the trench are optimized, and the angle and bottom morphology of the trench are improved, thereby improving the bottom charge balance of the super junction structure in the trench and improving the reliability of the silicon carbide super junction structure.

[0071] As an example and not a limitation, the shape of the cross section of the semiconductor structure 81 includes a polygon, the width of the polygon gradually decreases along the axial direction; wherein the polygon includes a trapezoid; the cross section of the semiconductor structure 81 is parallel to the axial direction; the axial direction is perpendicular to the upper surface of the substrate 100.

[0072] By setting the cross-sectional shapes of various semiconductor structures 81 , the flexibility of the silicon carbide super junction structure design is improved.

[0073] It should be noted that the materials of the substrate 100 , the epitaxial layer 90 and the semiconductor pillar 80 include silicon carbide.

[0074] As a wide-bandgap material, silicon carbide (SiC) boasts higher breakdown field strength, higher intrinsic temperature, higher thermal conductivity, and higher carrier saturation drift velocity. Due to its material performance advantages, SiC-based MOSFETs can achieve the same withstand voltage as silicon-based IGBTs, while offering faster switching speeds and a smaller chip area. Therefore, IGBTs made from SiC possess performance advantages far exceeding those of silicon-based IGBTs. Applications include power systems, high-speed railways, and other applications, with withstand voltages exceeding 6kV. Consequently, SiC IGBT devices demonstrate greater competitiveness in high-voltage, high-temperature, and high-power applications.

[0075] like Figure 5A and Figure 5B As shown, the silicon carbide super junction structure further includes a charge storage layer 10 , a first well region 20 , two active layers 30 and two gate structures 40 .

[0076] The charge storage layer 10 is disposed on the upper surface of the epitaxial layer 90 ; wherein the charge storage layer 10 is of the lightly doped second type.

[0077] The first well region 20 extends downward from the charge storage layer 10 to the semiconductor pillar 80 ; wherein the first well region 20 is of the first type.

[0078] The two active layers 30 extend downward from the upper surface of the first well region 20 to the interior of the first well region 20 and are spaced apart from each other; wherein the two active layers 30 are heavily doped of the second type.

[0079] The two gate structures 40 each cover a portion of the charge storage layer 10 , the active layer 30 and a portion of the first well region 20 .

[0080] It can be understood that each gate structure 40 forms an inversion layer on the upper surface of the first well region 20 between the charge storage layer 10 and the active layer 30 to constitute a gate channel of the field effect transistor.

[0081] It should be noted that the gate structure 40 is connected to the gate electrode, the upper surface of the first well region 20 between the two active layers 30 is connected to the source electrode 99, and the substrate 100 is connected to the drain electrode, thereby forming a silicon carbide field effect transistor.

[0082] Corresponding to an embodiment of a silicon carbide super junction structure, the present invention also provides an embodiment of a method for manufacturing a silicon carbide super junction structure.

[0083] A method for manufacturing a silicon carbide super junction structure includes multiple cyclic steps, each of which includes steps A to C.

[0084] In step A, if Figure 6A and Figure 6B As shown, a sub-epitaxial layer 91 is formed on the upper surface of the substrate.

[0085] It can be understood that step A can be specifically to grow a SiC N-type sub-epitaxial layer 91 on the N-type substrate 100 (or the upper surface of the sub-epitaxial layer 91 and the upper surface of the semiconductor structure 81), the sub-epitaxial layer 91 is 2um to 9um, the specific thickness depends on the actual design size of the device, and the doping concentration is between 1e15 and 1e18.

[0086] In step B, if Figure 7A and Figure 7B As shown, a sub-trench 71 is formed, wherein the sub-trench 71 penetrates the sub-epitaxial layer 91. It is understood that the angle of the side surface of the sub-trench can be adjusted by setting etching parameters.

[0087] In step C, if Figure 8A and Figure 8B As shown, a semiconductor structure 81 is formed in the sub-trench 71;

[0088] It can be understood that the trench is filled with P-type epitaxial filling, and the epitaxial filling can be one or more times. The deposition thickness can be different, and the doping concentration can be different. The thickness of the epitaxial filling depends on the filling morphology in the trench. The thickness is between 0.2um and 2um, and the doping concentration is in the range of 1e15 to 1e18, forming a charge balance with the N-type column of the epitaxial layer 90, and then chemical mechanical planarization is performed to flatten its surface.

[0089] The base material is the substrate 100 , or the base material is a composite structure including the sub-epitaxial layer 91 and the semiconductor structure 81 .

[0090] Two or more sub-epitaxial layers 91 are stacked to form an epitaxial layer 90 ; and two or more semiconductor structures 81 are stacked to form a semiconductor pillar 80 .

[0091] like Figure 9A and Figure 9B As shown, in one embodiment, the steps in the above manufacturing method are cyclically repeated more than twice, that is, the above steps A to C are repeated more than twice.

[0092] By fabricating the semiconductor structure 81 more than twice to form the semiconductor pillar 80, a superior sub-trench aspect ratio is achieved, which facilitates trench etching stability and epitaxial fill uniformity, reducing device failures caused by deep trench etching instability and epitaxial fill anomalies. Maintaining the same aspect ratio effectively reduces lateral dimensions and cell pitch, enabling the fabrication of a finer cell structure and increasing the number of cells. This reduces the device's on-state resistance between the drain and source, the saturation voltage drop of the SiC IGBT, and the forward voltage drop of the SiC fast recovery diode, thereby improving device performance. Furthermore, compared to the Multi-EPI process, this significantly reduces manufacturing costs and tapeout cycles.

[0093] In a specific implementation, step B includes steps B1 to B4.

[0094] In step B1 , a first mask layer is formed on the upper surface of the sub-epitaxial layer 91 .

[0095] It can be understood that step B1 can be specifically to deposit the first mask layer required for etching the groove on the N-type SiC sub-epitaxial layer 91. The film composition of the first mask layer can be one or a combination of oxide, nitride, carbon film, etc., and the thickness is selected according to its etching and groove depth, and can be between 0.1um and 4um.

[0096] In step B2, a portion of the first mask layer is removed to form a second mask layer on the upper surface of the sub-epitaxial layer 91;

[0097] In a specific implementation, a trench mask may be used for photolithography, specifically, dry etching may be used for etching.

[0098] In step B3, a portion of the sub-epitaxial layer 91 is removed to form a sub-trench 71;

[0099] It can be understood that step B3 can be to use a second mask layer to perform dry etching and edge chamfering of the sub-groove 71, with the diameter of the groove being 0.8um to 2um, the depth being 2um to 9um, and the angle being 86° to 90°, and is not limited to gases such as O2, H2, AR, or chemically induced etching.

[0100] In step B4, the second mask layer is removed.

[0101] In a specific implementation, the second mask layer may be removed by wet etching.

[0102] It is worth emphasizing that after the steps in the above manufacturing method are cyclically repeated for more than two times, the manufacturing method further includes steps D to G.

[0103] In step D, a charge storage layer is formed on the upper surface of the epitaxial layer;

[0104] A charge storage layer is formed on the upper surface of the epitaxial layer by ion implantation. Specifically, N elements are implanted using a charge storage layer mask to form a charge storage layer on the upper surface of the epitaxial layer, thereby reducing the JFET resistance.

[0105] In step E, a first well region is formed through the charge storage layer and covers the semiconductor pillar;

[0106] Ion implantation is performed through the charge storage layer to form a first well region covering the semiconductor pillar. Specifically, AL elements are implanted through a well region mask to penetrate the charge storage layer to form the first well region covering the semiconductor pillar.

[0107] In step F, two active layers extending downward to the interior of the first well region are formed on the upper surface of the first well region; wherein the two active layers are spaced apart;

[0108] Two active layers extending downward into the first well region are formed on the upper surface of the first well region by ion implantation. Specifically, N elements are implanted through an active layer mask to form two active layers extending downward into the first well region.

[0109] In step G, two gate structures are formed, each covering a portion of the charge storage layer, the active layer, and a portion of the first well region. Specifically, the gate structure includes an oxide layer, a polysilicon layer, and an insulating layer. The oxide layer can be deposited first, with a thickness of 30 nm to 120 nm, followed by a polysilicon layer to form the gate wiring, and finally, the insulating layer.

[0110] After step G, the insulating layer above the first well region between the two active layers may be removed by etching, metal Ni may be deposited to form an ohmic contact, and finally metal Al may be deposited to lead out a source electrode.

[0111] An embodiment of the present application further provides a semiconductor device, which includes the above-mentioned silicon carbide super junction structure.

[0112] An embodiment of the present application further provides an electronic device, which includes the above-mentioned semiconductor device.

[0113] An embodiment of the present invention includes a substrate, an epitaxial layer and a semiconductor pillar; the epitaxial layer is arranged on the upper surface of the substrate; the semiconductor pillar extends into the interior of the epitaxial layer; the semiconductor pillar includes two or more superimposed semiconductor structures; wherein the cross-sectional area of ​​the semiconductor structure gradually decreases along the axial direction; the semiconductor pillar is of a first doping type; the substrate and the epitaxial layer are of a second doping type; thereby, the longitudinal electric field of the silicon carbide superjunction structure forms a maximum value at the center point of each semiconductor structure, the overall electric field integrated area is increased, the charge balance point of the superjunction structure is optimized, the charge balanced electric field distribution is improved, the improvement in charge balance increases the reverse breakdown voltage, and the device reliability is improved.

[0114] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0115] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A silicon carbide superjunction structure, characterized in that: The silicon carbide super junction structure comprises: substrate; an epitaxial layer disposed on the upper surface of the substrate; a semiconductor pillar extending into the interior of the epitaxial layer; The semiconductor column comprises two or more superimposed semiconductor structures; the cross-sectional area of ​​the semiconductor structure gradually decreases along the axial direction; The semiconductor pillar is of a first doping type; the substrate and the epitaxial layer are of a second doping type.

2. The silicon carbide superjunction structure according to claim 1, wherein: The semiconductor column includes n stacked semiconductor structures; wherein n is 2 or 3.

3. The silicon carbide superjunction structure according to claim 1, wherein: The height of the semiconductor structure is between 2 micrometers and 9 micrometers.

4. The silicon carbide superjunction structure according to claim 1, wherein: The cross section of the semiconductor structure is a polygon, and the width of the polygon gradually decreases along the axial direction; The cross section of the semiconductor structure is parallel to the axial direction; The axial direction is perpendicular to the upper surface of the substrate.

5. The silicon carbide superjunction structure according to any one of claims 1 to 4, wherein: The substrate, the epitaxial layer and the semiconductor pillar are made of silicon carbide.

6. The silicon carbide super junction structure according to any one of claims 1 to 4, wherein: The silicon carbide super junction structure further includes: a charge storage layer disposed on the upper surface of the epitaxial layer; a first well region extending downward from the charge storage layer to the semiconductor pillar; two active layers extending downward from the upper surface of the first well region to the interior of the first well region and spaced apart from each other; Two gate structures each cover a portion of the charge storage layer, the active layer and a portion of the first well region.

7. A method for manufacturing a silicon carbide superjunction structure, characterized in that: The manufacturing method comprises: forming a sub-epitaxial layer on the upper surface of the substrate; forming a sub-groove, wherein the sub-groove penetrates the sub-epitaxial layer and has a cross-sectional area gradually decreasing along the axial direction; forming a semiconductor structure in the sub-trench; Wherein, the base material is a substrate, or the base material is a composite structure including the sub-epitaxial layer and the semiconductor structure; Two or more sub-epitaxial layers are stacked to form an epitaxial layer; two or more semiconductor structures are stacked to form a semiconductor pillar.

8. The method for manufacturing a silicon carbide super junction structure according to claim 7, wherein: The steps in the manufacturing method are cyclically repeated twice or more.

9. The method for manufacturing a silicon carbide super junction structure according to claim 8, wherein: After the steps in the manufacturing method are cyclically repeated for more than two times, the manufacturing method further includes: forming a charge storage layer on the upper surface of the epitaxial layer; forming a first well region covering the semiconductor pillar through the charge storage layer; forming two active layers on the upper surface of the first well region and extending downward to the interior of the first well region; wherein the two active layers are spaced apart; Two gate structures are formed, each covering a portion of the charge storage layer, the active layer and a portion of the first well region.

10. A semiconductor device, characterized in that: The semiconductor device comprises the silicon carbide super junction structure according to any one of claims 1 to 6.

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