MOSFET device and preparation method thereof

Abstract

The invention relates to an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and the preparation method comprises the steps: providing a silicon carbide substrate which is internally provided with a drift region; forming a silicon carbide epitaxial layer on the silicon carbide substrate; forming a first well region and a second well region which are not in contact in the silicon carbide epitaxial layer; forming a shallow doping region in the first well region and the second well region, wherein the doping type of the shallow doping region is opposite to that of the first well region; forming a source region in the first well region, wherein the source region is overlapped with a part, far away from the second well region, of the lightly doped region in the first well region; forming a gate structure on the silicon carbide epitaxial layer, wherein the gate structure crosses and covers a part of the first well region, a part of the second well region and a part of the shallow doped region in the first well region and the second well region; and forming a drain region on the back surface of the silicon carbide substrate. The short-circuit tolerance time of the MOSFET device is prolonged, and the leakage current is reduced.

Description

Technical Field

[0001] The present application relates to the field of half-power device preparation, and in particular to a MOSFET device and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC), a third-generation wide-bandgap semiconductor material, boasts advantages such as a wide bandgap, high critical breakdown electric field, high electron saturation mobility, and high thermal conductivity, making it a hot topic in current power device research. Among SiC switching devices, SiC MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) offer significant performance advantages over Si MOSFETs, including lower on-resistance, higher switching voltages, higher operating frequencies, and improved temperature performance. These advantages hold broad promise in new energy, rail transit, power electronics, electric vehicles, photovoltaic inverters, and industrial power supplies.

[0003] However, existing SiC MOSFETs have problems with short-circuit withstand time and high leakage current. Summary of the Invention

[0004] Based on this, the present application provides a MOSFET device of a semiconductor structure and a preparation method thereof, so as to improve the short-circuit withstand time of the MOSFET device and reduce the leakage current.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a MOSFET device, comprising:

[0006] Providing a silicon carbide substrate, wherein the silicon carbide substrate has a drift region;

[0007] forming a silicon carbide epitaxial layer on a silicon carbide substrate;

[0008] forming a first well region and a second well region that are not in contact with each other in the silicon carbide epitaxial layer, wherein the doping types of the first well region and the second well region are opposite to the doping type of the drift region;

[0009] forming a shallow doped region in the first well region and the second well region, wherein the doping type of the shallow doped region is opposite to the doping type of the first well region;

[0010] forming a source region in the first well region, the source region overlapping with a portion of the shallow doped region in the first well region away from the second well region, the source region having the same doping type as the shallow doped region, the source region having a depth and a doping ion concentration greater than the depth and the doping ion concentration of the shallow doped region, and the source region having a depth less than the depth of the first well region;

[0011] forming a gate structure on the silicon carbide epitaxial layer, wherein the gate structure spans and covers a portion of the first well region, a portion of the second well region, and a portion of the shallowly doped region within the first well region and the second well region;

[0012] A drain region is formed on the back surface of the silicon carbide substrate.

[0013] In some embodiments of the present application, an end of the shallowly doped region in the first well region close to the second well region does not contact the first well region;

[0014] An end of the shallowly doped region in the second well region close to the first well region does not contact the second well region.

[0015] In some embodiments of the present application, the source region includes a first part, a second part, and a third part connected in sequence, the first part overlaps with the source region, the third part is covered by the gate structure, and the second part is located between the source region and the gate structure.

[0016] In some embodiments of the present application, the method further includes: forming a heavily doped region in the second well region, the heavily doped region overlapping with a portion of the shallowly doped region in the second well region that is away from the first well region, the heavily doped region having the same doping type as the second well region, the heavily doped region having a greater depth than the shallowly doped region, and the heavily doped region having a greater doping concentration than the second well region;

[0017] A junction doping region is formed in the silicon carbide epitaxial layer between the first well region and the second well region. The doping type of the junction doping region is opposite to the doping type of the first well region.

[0018] In some embodiments of the present application, the doping type of the drift region is N-type, the doping type of the first well region and the second well region is P-type, the doping type of the shallow doping region is N-type, the doping type of the source region is N-type, the doping type of the heavily doped region is P-type, and the doping type of the junction doping region is N-type.

[0019] In some embodiments of the present application, the doping type of the drift region is P type, the doping type of the first well region and the second well region is N type, the doping type of the shallow doping region is P type, the doping type of the source region is P type, the doping type of the heavily doped region is N type, and the doping type of the junction doping region is P type.

[0020] In some embodiments of the present application, after forming a junction doping region in the silicon carbide epitaxial layer, a first well region and a second well region are formed in the silicon carbide epitaxial layer; after forming the first well region and the second well region, a shallow doping region is formed; after forming the shallow doping region, a source region and a heavily doped region are formed.

[0021] In some embodiments of the present application, the formation process of the junction doped region, the shallow doped region and the source region includes:

[0022] When forming the silicon carbide epitaxial layer, forming a junction doping region in the silicon carbide epitaxial layer by an in-situ doping process;

[0023] forming a first patterned mask layer on a portion of the silicon carbide epitaxial layer, wherein the first patterned mask layer exposes areas on both sides that need to be implanted;

[0024] Using the first patterned mask layer as a mask, a first ion implantation process is used to implant impurity ions into the silicon carbide epitaxial layer on both sides of the first patterned mask layer to form a first well region and a second well region;

[0025] forming sidewall spacers on both sidewalls of the first patterned mask layer;

[0026] Using the first patterned mask layer and the sidewalls as masks, a second ion implantation process is used to implant impurity ions into the silicon carbide epitaxial layer on both sides of the first patterned mask layer and the sidewalls to form a shallow doped region;

[0027] The first patterned mask layer and the sidewall spacer are removed.

[0028] In a second aspect, an embodiment of the present application further provides a MOSFET device, comprising:

[0029] A silicon carbide substrate having a drift region therein;

[0030] a silicon carbide epitaxial layer on a silicon carbide substrate;

[0031] A first well region and a second well region that are not in contact with each other and are located in the silicon carbide epitaxial layer, wherein the doping type of the first well region and the second well region is opposite to the doping type of the drift region;

[0032] a shallowly doped region located within the first well region and the second well region, wherein the doping type of the shallowly doped region is opposite to the doping type of the first well region;

[0033] a source region located in the first well region, the source region overlapping with a portion of the shallowly doped region in the first well region that is away from the second well region, the source region having the same doping type as the shallowly doped region, the source region having a depth and a doping ion concentration that are correspondingly greater than the depth and doping ion concentration of the shallowly doped region, and the source region having a depth that is less than the depth of the first well region;

[0034] A gate structure located on the silicon carbide epitaxial layer, the gate structure spanning and covering a portion of the first well region, a portion of the second well region, and a portion of the shallowly doped region within the first well region and the second well region;

[0035] The drain region is located on the back side of the silicon carbide substrate.

[0036] In some embodiments of the present application, an end of the shallowly doped region in the first well region close to the second well region does not contact the first well region;

[0037] An end of the shallowly doped region in the second well region close to the first well region does not contact the second well region;

[0038] The source region includes a first part, a second part and a third part which are connected in sequence. The first part overlaps with the source region, the third part is covered by the gate structure, and the second part is located between the source region and the gate structure.

[0039] The embodiments of the present application may or at least have the following advantages:

[0040] In an embodiment of the present application, a MOSFET device and a preparation method thereof are provided. The preparation method comprises providing a silicon carbide substrate having a drift region therein; forming a silicon carbide epitaxial layer on the silicon carbide substrate; forming a non-contact first well region and a second well region in the silicon carbide epitaxial layer, wherein the doping type of the first well region and the second well region is opposite to the doping type of the drift region; forming a shallowly doped region in the first well region and the second well region, wherein the doping type of the shallowly doped region is opposite to the doping type of the first well region; forming a source region in the first well region, wherein the source region overlaps with a portion of the shallowly doped region in the first well region away from the second well region, and the doping type of the source region is the same as the doping type of the shallowly doped region, the depth and doping ion concentration of the source region are correspondingly greater than the depth and doping ion concentration of the shallowly doped region, and the depth of the source region is less than the depth of the first well region; forming a gate structure on the silicon carbide epitaxial layer, wherein the gate structure spans and covers a portion of the first well region, a portion of the second well region, and a portion of the shallowly doped region in the first well region and the second well region; and forming a drain region on the back side of the silicon carbide substrate. By forming a shallow doped region between the source region and the gate structure, it is equivalent to setting a low doping region with low doping concentration and low depth near the channel. The low doping region can withstand part of the voltage to relieve the pressure resistance at the channel and achieve short-circuit resistance, thereby increasing the short-circuit withstand time (SCWT) of the MOSFET device, that is, the maximum time that the device can withstand under short-circuit conditions, thereby improving the reliability of the MOSFET device. In addition, by forming the shallow doped region 109, the expansion of the depletion region can also be limited, reducing the interference of the drain electric field on the channel, thereby maintaining a high threshold voltage and driving voltage, increasing the barrier height at both ends of the channel, and ultimately effectively suppressing the short channel effect and reducing leakage current.

[0041] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 A schematic diagram of a cross-sectional structure after providing a silicon carbide substrate in a method for preparing a MOSFET device provided in some embodiments of the present application;

[0044] Figure 2 A schematic diagram of a cross-sectional structure after forming a first well region and a second well region in a method for manufacturing a MOSFET device provided in some embodiments of the present application;

[0045] Figure 3 A schematic diagram of a cross-sectional structure after forming a shallowly doped region in a method for preparing a MOSFET device provided in some embodiments of the present application;

[0046] Figure 4 A schematic diagram of a cross-sectional structure after forming a source region in a method for preparing a MOSFET device provided in some embodiments of the present application;

[0047] Figure 5 A schematic diagram of a cross-sectional structure after forming a heavily doped region in a method for preparing a MOSFET device provided in some embodiments of the present application;

[0048] Figure 6 A schematic cross-sectional view of a method for preparing a MOSFET device according to some embodiments of the present application after forming a gate structure;

[0049] Figure 7 A schematic diagram of a cross-sectional structure after forming a dielectric layer in a method for preparing a MOSFET device provided in some embodiments of the present application;

[0050] Figure 8 A schematic diagram of a cross-sectional structure after forming a source electrode in a method for preparing a MOSFET device provided in some embodiments of the present application;

[0051] Figure 9 A schematic cross-sectional structure diagram of forming a drain electrode in a method for preparing a MOSFET device provided in some embodiments of the present application.

[0052] Description of reference numerals:

[0053] Silicon carbide substrate 101; drift region 102; silicon carbide epitaxial layer 103; junction doping region 104; first patterned mask layer 105; first well region 106; second well region 107; sidewalls 108; shallowly doped region 109; second patterned mask layer 110; source region 111; third patterned mask layer 112; heavily doped region 113; gate structure 114; interlayer dielectric layer 115; metal silicide layer 116; source electrode 117; second metal silicide layer 118; drain electrode 119. DETAILED DESCRIPTION

[0054] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0056] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0057] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0058] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of the stated features, integers, steps, operations, components, parts, or several, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or several. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] The structures of the embodiments of the present application should not be limited to the specific shapes shown in the drawings, but include shape deviations due to, for example, manufacturing technology.

[0060] It can be understood that in the drawings of the present application, some adjacent film layers made of the same processing film material are drawn as being connected to make them close to the actual structure.

[0061] Planar SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) is a power device based on silicon carbide (SiC) material. Planar SiC MOSFET generally includes: a silicon carbide substrate, which includes opposite top and back surfaces; a drift region located in the silicon carbide substrate; a first well region located in the drift region and a second well region located on one side of the first well region, the first well region and the second well region not in contact; a source region located in the first well region and the second well region; a gate structure located on the top surface of the silicon carbide substrate, spanning and covering part of the first well region, part of the second well region, and part of the source region of the first well region and the second well region; and a drain region located on the back side of the silicon carbide substrate.

[0062] Currently, the short-circuit withstand time (SCWT) of the aforementioned planar SiC MOSFET, the maximum time the device can withstand short-circuit conditions, is typically between a few microseconds and more than ten microseconds. This short short-circuit withstand time can withstand extremely high current density, causing the internal temperature of the device to rise rapidly, affecting device reliability. Furthermore, during device iteration, the feature size gradually shrinks, and the channel length becomes shorter and shorter, resulting in a lower threshold voltage (Vth). This triggers the short-channel effect, causing the leakage current of the planar SiC MOSFET to increase.

[0063] To this end, an embodiment of the present application first provides a method for preparing a MOSFET device. Figures 1-9 Schematic diagram of the cross-sectional structure of each stage in a method for preparing a MOSFET device provided in some embodiments of the present application.

[0064] First, refer to Figure 1 A silicon carbide substrate 101 is provided, wherein the silicon carbide substrate 101 has a drift region 102 therein; and a silicon carbide epitaxial layer 103 is formed on the silicon carbide substrate 101.

[0065] The silicon carbide substrate 101 serves as the substrate structure for the subsequent formation of MOSFET devices. Silicon carbide (SiC) material, as a third-generation wide-bandgap semiconductor material, has the advantages of wide bandgap width, high critical breakdown electric field, high electron saturation mobility and high thermal conductivity. The MOSFET formed on the silicon carbide substrate 101 has significant performance advantages over the MOSFET formed on the silicon substrate, such as smaller on-resistance, higher switching voltage, higher application frequency and better temperature performance.

[0066] The silicon carbide substrate 101 includes opposing back and front surfaces, with a silicon carbide epitaxial layer 103 formed on the front surface of the silicon carbide substrate 101. The back surface of the silicon carbide substrate 101 can be doped with impurity ions to form the drain region of the MOSFET device (not shown in the figure), and the front surface of the silicon carbide substrate 101 can also be doped with impurity ions to form the drift region 102 of the MOSFET device. The doping type of the drain region is the same as the doping type of the drift region, or the impurity ions doped in the drain region are the same as the impurity ions doped in the drift region. In one example, the impurity ions doped in the drain region are N-type, and the impurity ions doped in the drift region 102 are N-type. The concentration of the impurity ions doped in the drain region is greater than that in the drift region 102. The N-type impurity ions include nitrogen ions, or may also include one or more of phosphorus ions, arsenic ions, or antimony ions. In another example, the impurity ions doped in the drain region are of P-type, the impurity ions doped in the drift region 102 are of P-type, and the concentration of the impurity ions doped in the drain region is greater than the concentration of the impurity ions doped in the drift region 102. The P-type impurity ions include aluminum ions, or may include one or more of boron ions, aluminum ions, gallium ions, or indium ions. In one embodiment, the drain region and the drift region 102 may be formed by an ion implantation process.

[0067] The silicon carbide epitaxial layer 103 is subsequently used to form junction doping regions, source regions, lightly doped regions, and heavily doped regions. Forming the silicon carbide epitaxial layer 103 can reduce the on-resistance from the source region to the drain region. The silicon carbide epitaxial layer 103 can be formed by an epitaxial process. Depending on the performance of the MOSFET device to be formed, the thickness of the silicon carbide epitaxial layer 103 can be different. For example, in one example, the thickness of the silicon carbide epitaxial layer 103 can be 1 micron to 14 microns, specifically 1 micron, 2 microns, 5 microns, 8 microns, 10 microns, 12 microns, and 14 microns. For example, in another example, when the withstand voltage of the MOSFET device is 1000V to 1400V, the thickness of the silicon carbide epitaxial layer 103 can be 10 microns to 14 microns.

[0068] The silicon carbide epitaxial layer 103 is formed by an epitaxial process. Impurity ions can be self-doped in the silicon carbide epitaxial layer 103, or impurity ions can be doped in the silicon carbide epitaxial layer 103 by an ion implantation process. The portion of the silicon carbide epitaxial layer 103 doped with impurity ions is subsequently used as a junction doping region. The type of impurity ions doped in the silicon carbide epitaxial layer 103 is the same as the type of impurity ions doped in the drift region 102. In some embodiments, when the type of impurity ions doped in the drift region 102 is N-type, the type of impurity ions doped in the silicon carbide epitaxial layer 103 is N-type. The N-type impurity ions include nitrogen ions, or may include one or more of phosphorus ions, arsenic ions, or antimony ions. In a specific example, the impurity ions doped in the silicon carbide epitaxial layer 103 are nitrogen ions, and the concentration of the impurity ions is 8E11atom / cm 3 -5E12atom / cm 3 , with a depth of 1 micron to 2 microns. In other embodiments, when the impurity ions doped in the drift region 102 are of P-type, the impurity ions doped in the silicon carbide epitaxial layer 103 are of P-type, and the P-type impurity ions include aluminum ions, or may also include one or more of boron ions, aluminum ions, gallium ions, or indium ions.

[0069] Next, refer to Figure 2 , in the silicon carbide epitaxial layer 103 (reference Figure 1 ), and the doping types of the first well region 106 and the second well region 107 are opposite to the doping type of the drift region 102.

[0070] A shallow doped region and a source region are subsequently formed in the first well region 106 , and a shallow doped region and a heavily doped region are subsequently formed in the second well region 107 .

[0071] The first well region 106 and the second well region 107 are not in contact. In one example, the first well region 106 is located on one side of the second well region 107, and the remaining silicon carbide epitaxial layer 103 between the first well region 106 and the second well region 107 serves as a junction doping region (JFET) 104. Since the type of impurity ions doped in the junction doping region (JFET) 104 is opposite to the type of impurity ions doped in the first well region 106 and the second well region 107, the electric field distribution in the silicon carbide epitaxial layer 103 is optimized, thereby reducing the on-resistance of the super junction MOSFET while maintaining a large breakdown voltage.

[0072] The depth of the first well region 106 and the second well region 107 may be less than the depth of the junction doping region 104. The type of impurity ions doped in the first well region 106 and the second well region 107 (or doping type) is opposite to the type of impurity ions doped in the junction doping region 104 and the drift region 102 (or doping type). In some embodiments, when the type of impurity ions doped in the junction doping region 104 and the drift region 102 is N-type, the type of impurity ions doped in the first well region 106 and the second well region 107 is P-type. The P-type impurity ions include aluminum ions, or may also include one or more of boron ions, aluminum ions, gallium ions, or indium ions. In a specific example, the impurity ions doped in the first well region 106 and the second well region 107 are aluminum ions, and the concentration of the impurity ions is 1E12 atom / cm 3 -1E13atom / cm 3 , with a depth of 0.4 μm to 0.6 μm. In other embodiments, when the impurity ions doped in the junction doping region 104 and the drift region 102 are of P-type, the impurity ions doped in the first well region 106 and the second well region 107 are of N-type, and the N-type impurity ions include nitrogen ions, or may also include one or more of phosphorus ions, arsenic ions, or antimony ions.

[0073] In some embodiments, after the junction doping region 104 is formed in the silicon carbide epitaxial layer 103 , a first well region 106 and a second well region 107 are formed in the silicon carbide epitaxial layer 103 .

[0074] In some embodiments, the formation process of the junction doped region 104, the shallow doped region 109 and the source region 111 includes:

[0075] forming a junction doping region 104 in the silicon carbide epitaxial layer 103 by an in-situ doping process or an ion implantation process;

[0076] A first patterned mask layer 105 is formed on a portion of the silicon carbide epitaxial layer 103 (refer to Figure 2 ), the first patterned mask layer 105 exposes the areas on both sides that need to be implanted. In some embodiments, the formation process of the first patterned mask layer 105 includes: forming a first mask material layer on the silicon carbide epitaxial layer 103, the material of the first mask material layer is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, polycrystalline silicon, amorphous silicon, amorphous carbon, or a combination thereof. In a specific example, the material of the first mask material layer is polycrystalline silicon; forming a photoresist layer on the first mask material layer; exposing and developing the photoresist layer to expose the areas of the first mask material layer that need to be etched; etching the first mask material layer using the photoresist layer as a mask, and using the remaining first mask material layer under the photoresist layer as the first patterned mask layer 105;

[0077] Using the first patterned mask layer 105 as a mask, a first ion implantation process is used to implant impurity ions into the silicon carbide epitaxial layer 103 on both sides of the first patterned mask layer 105, thereby forming a first well region 106 and a second well region 107. After forming the first well region 106 and the second well region 107, the first patterned mask layer 105 is not removed, and spacers 108 are subsequently formed on both sidewalls of the first patterned mask layer 105 (refer to FIG. Figure 3 ), using the first patterned mask layer 105 and the sidewall 108 as masks, a second ion implantation process is used to implant impurity ions into the silicon carbide epitaxial layer 103 on both sides of the first patterned mask layer 105 and the sidewall 108 to form a shallow doped region 109 (refer to Figure 3 ), thus only one mask process is required to form the first well region 106 and the second well region 107, as well as the subsequent shallow doping region 109, thereby simplifying the process steps.

[0078] Next, refer to Figure 3 A shallow doped region 109 is formed in the first well region 106 and the second well region 107 , and the doping type of the shallow doped region 109 is opposite to the doping type of the first well region 106 .

[0079] The purpose of forming the shallow doped region 109 is that after the source region 111 and the gate structure 114 are subsequently formed, part of the shallow doped region 109 is located between the gate structure 114 and the source region 111. By providing the shallow doped region 109 between the source region 111 and the gate structure 114, it is equivalent to providing a low-doping region with a low doping concentration and a low depth near the channel. This low-doping region can withstand a portion of the voltage to relieve the pressure resistance at the channel and achieve a short-circuit resistance effect, thereby increasing the short-circuit withstand time (SCWT) of the MOSFET device, that is, the maximum time that the device can withstand under short-circuit conditions, thereby improving the reliability of the MOSFET device. In addition, by forming the shallow doped region 109, the expansion of the depletion region can be limited, reducing the interference of the drain electric field on the channel, thereby maintaining a high threshold voltage and driving voltage, and increasing the barrier height at both ends of the channel, ultimately effectively suppressing the short channel effect and reducing leakage current.

[0080] The depth of the shallow doped region 109 is smaller than the depth of the first well region 106 and the second well region 107. The depth of the shallow doped region 109 is also smaller than the source region 111 formed subsequently (refer to Figure 4 or Figure 6), and the doping type of the shallow doped region 109 (or the type of impurity ions doped in the shallow doped region 109) is opposite to the doping type of the first well region 106 (or the type of impurity ions doped in the first well region 106), and is the same as the doping type of the subsequently formed source region 111. The concentration of impurity ions doped in the shallow doped region 109 is lower than the concentration of impurity ions doped in the subsequently formed source region 111. In some embodiments, the depth of the shallow doped region 109 is 1 / 6 to 1 / 4 of the depth of the first well region 106. Specifically, the depth of the shallow doped region 109 is 1 / 6, 1 / 5, or 1 / 4 of the depth of the first well region 106.

[0081] In some embodiments, the doping type of the first well region 106 (or the type of impurity ions doped in the first well region 106) is P-type, and the doping type of the corresponding shallow doped region 109 (or the type of impurity ions doped in the shallow doped region 109) is N-type. The N-type impurity ions include nitrogen ions, or may also include one or more of phosphorus ions, arsenic ions, or antimony ions. In a specific example, the impurity ions doped in the shallow doped region 109 are nitrogen ions, and the concentration of the impurity ions is 3E13 atoms / cm 3 -7E13atom / cm 3 , specifically 3E13atom / cm 3 、4E13atom / cm 3 、5E13atom / cm 3 、6E13atom / cm 3 、7E13atom / cm 3 , with a depth of 0.08 μm to 0.12 μm, specifically 0.08 μm, 0.09 μm, 0.10 μm, 0.11 μm, or 0.12 μm. In other embodiments, the doping type of the first well region 106 (or the type of impurity ions doped in the first well region 106 ) is N-type, and the corresponding doping type of the shallow doped region 109 (or the type of impurity ions doped in the shallow doped region 109 ) is P-type. The P-type impurity ions include aluminum ions, or may include one or more of boron ions, aluminum ions, gallium ions, or indium ions.

[0082] The end of the shallow doped region 109 in the first well region 106 close to the second well region 107 does not contact the first well region 106; the end of the shallow doped region 109 in the second well region 107 close to the first well region 106 does not contact the second well region 107. Figure 6 ), so that a channel can be formed in the portion of the first well region 106 below the gate structure when the MOSFET device is in operation.

[0083] In some embodiments, continue to refer to Figure 3The process of forming the shallow doped region 109 includes:

[0084] A spacer 108 is formed on the sidewall of the first patterned mask layer 105. The position of the subsequently formed source region can be controlled by adjusting the width of the formed spacer 108. The material of the spacer 108 is different from the material of the first patterned mask layer 105. The material of the spacer 108 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. In one example, the formation process of the spacer 108 includes: forming a spacer material layer covering the silicon carbide epitaxial layer and the first patterned mask layer 105; removing the surface of the silicon carbide epitaxial layer and the spacer material layer of the first patterned mask layer 105 by a maskless etching process, and retaining the spacer material layer of the first patterned mask layer 105 as the spacer 108;

[0085] Using the first patterned mask layer 105 and the sidewall spacer 108 as masks, a second ion implantation process is used to implant impurity ions into the silicon carbide epitaxial layer 103 on both sides of the first patterned mask layer 105 and the sidewall spacer 108 to form a shallow doped region 109;

[0086] The first patterned mask layer 105 and the spacer 108 are removed.

[0087] When forming the shallow doped region 109 by this method, there is no need to remove the first patterned mask layer 105 formed previously. It is only necessary to form the sidewall 108 on the sidewall of the first patterned mask layer 105, thereby saving one mask process step, simplifying the process, and saving costs. In addition, since the sidewall 108 is self-aligned and formed on the sidewall of the first patterned mask layer 105, the position and width of the formed sidewall 108 are highly accurate. Therefore, with the first patterned mask layer 105 and the sidewall 108 as masks, a second ion implantation process is adopted to implant impurity ions into the silicon carbide epitaxial layer 103 on both sides of the first patterned mask layer 105 and the sidewall 108. The position of the formed shallow doped region 109 is also highly accurate, which is conducive to accurate control of the short-circuit withstand time and the threshold voltage (preventing the influence of position offset when forming the shallow doped region 109 on the short-circuit withstand time and the threshold voltage).

[0088] In some embodiments, after forming the first well region 106 and the second well region 107 , a shallow doped region 109 is formed.

[0089] In some embodiments, the shallow doped region 109 includes a first portion, a second portion, and a third portion that are sequentially connected, and the first portion is connected to the subsequently formed source region 111 (refer to Figure 6 ) overlaps, and the third portion is formed by the subsequently formed gate structure 114 (reference Figure 6 ), and the second portion is located between the source region 111 and the gate structure 114.

[0090] Next, refer to Figure 4 A source region 111 is formed in the first well region 106. The source region 111 overlaps with a portion of the shallow doped region 109 in the first well region 106 that is away from the second well region 107. The doping type of the source region 111 is the same as the doping type of the shallow doped region 109. The depth and doping ion concentration of the source region 111 are correspondingly greater than the depth and doping ion concentration of the shallow doped region 109. The depth of the source region 111 is less than the depth of the first well region 106.

[0091] In some embodiments, the depth of the source region 111 is 1 / 3 to 2 / 3 of the depth of the first well region 106 , and the depth of the source region 111 is 1.5 to 2.5 times the depth of the shallowly doped region 109 .

[0092] In some embodiments, the doping type of the shallow doped region 109 (or the type of impurity ions doped in the shallow doped region 109) is N-type, and the corresponding doping type of the source region 111 (or the type of impurity ions doped in the source region 111) is N-type. The N-type impurity ions include nitrogen ions, or may also include one or more of phosphorus ions, arsenic ions, or antimony ions. In a specific example, the impurity ions doped in the source region 111 are nitrogen ions, and the concentration of the impurity ions is 1E14 atom / cm 3 -4E14atom / cm 3 , specifically 1E14atom / cm 3 、2E14atom / cm 3 、3E14atom / cm 3 、4E14atom / cm 3 , with a depth of 0.18 μm to 0.22 μm, specifically 0.18 μm, 0.19 μm, 0.20 μm, 0.21 μm, or 0.22 μm. In other embodiments, the doping type of the shallow doped region 109 (or the type of impurity ions doped in the shallow doped region 109) is P-type, and the corresponding doping type of the source region 111 (or the type of impurity ions doped in the source region 111) is P-type. The P-type impurity ions include aluminum ions, or may include one or more of boron ions, aluminum ions, gallium ions, or indium ions.

[0093] In some embodiments, continuing with reference to step 4, the process of forming the source region 111 includes: forming a second patterned mask layer 110 on the silicon carbide epitaxial layer, the second patterned mask layer 110 exposing a portion of the surface of the shallowly doped region 109 in the first well region 106 away from the second well region 107; using the second patterned mask layer 110 as a mask, employing a third ion implantation to implant impurity ions into the exposed silicon carbide epitaxial layer to form the source region 111.

[0094] In some embodiments, reference Figure 5, also including: forming a heavily doped region 113 in the second well region 107, the heavily doped region 113 overlaps with a portion of the shallowly doped region 109 in the second well region 107 away from the first well region 106, and the doping type of the heavily doped region 113 is the same as the doping type of the second well region 107, the depth of the heavily doped region 113 is greater than the depth of the shallowly doped region 109, and the doping concentration of the heavily doped region 113 is greater than the doping concentration of the second well region 107.

[0095] By forming the heavily doped region 113, the gate structure 114 is formed later (refer to Figure 6 ), the structure in the silicon carbide epitaxial layer on both sides of the gate structure 114 is an asymmetric structure. The existence of the heavily doped region 113 can prevent the formation of parasitic transistors and reduce the on-resistance of the MOSFET device.

[0096] In some embodiments, the doping type of the second well region 107 (or the type of impurity ions doped in the second well region 107) is P-type, and the doping type of the corresponding heavily doped region 113 (or the type of impurity ions doped in the heavily doped region 113) is P-type. The P-type impurity ions include aluminum ions, or may also include one or more of boron ions, aluminum ions, gallium ions, or indium ions. In a specific example, the impurity ions doped in the heavily doped region 113 are aluminum ions, and the concentration of the impurity ions is 2E14 atoms / cm 3 -6E14atom / cm 3 , specifically 2E14atom / cm 3 、3E14atom / cm 3 、4E14atom / cm 3 、5E14atom / cm 3 、6E14atom / cm 3 , with a depth of 0.38 μm to 0.42 μm, specifically 0.38 μm, 0.39 μm, 0.40 μm, 0.41 μm, or 0.42 μm. In other embodiments, the doping type of the second well region 107 (or the type of impurity ions doped in the second well region 107 ) is P-type, and the corresponding doping type of the heavily doped region 113 (or the type of impurity ions doped in the heavily doped region 113 ) is N-type. The N-type impurity ions include nitrogen ions, or may include one or more of phosphorus ions, arsenic ions, or antimony ions.

[0097] In some embodiments, continuing with reference to step 5, the formation process of the heavily doped region 113 includes: forming a third patterned mask layer 112 on the silicon carbide epitaxial layer, the third patterned mask layer 112 exposing a portion of the surface of the shallowly doped region 109 in the second well region 107 away from the first well region 106; using the third patterned mask layer 112 as a mask, employing a fourth ion implantation to implant impurity ions into the exposed silicon carbide epitaxial layer to form the heavily doped region 113.

[0098] In some embodiments, after the shallow doped region 109 is formed, the source region 111 and the heavily doped region 113 are formed.

[0099] Next, refer to Figure 6 A gate structure 114 is formed on the silicon carbide epitaxial layer 103 , and the gate structure 114 spans and covers a portion of the first well region 106 , a portion of the second well region 107 , and a portion of the shallowly doped region 109 within the first well region 106 and the second well region 107 .

[0100] The gate structure 114 includes a gate dielectric layer and a gate electrode on the gate dielectric layer. In one example, the gate dielectric layer is made of silicon oxide, the gate electrode is made of polysilicon, the gate dielectric layer has a thickness of 300-500 angstroms, and the gate electrode has a thickness of 3000-4800 angstroms.

[0101] In some embodiments, reference Figure 7 , further comprising: forming an interlayer dielectric layer 115 covering the gate structure 114 and the shallowly doped regions 109 on both sides of the gate structure 114, a portion of the source region 111, and a portion of the heavily doped region 113; and forming a metal silicide layer 116 on the surfaces of the source region 111 and the heavily doped region 113 not covered by the interlayer dielectric layer 115.

[0102] Interlayer dielectric layer 115 comprises a single layer structure formed from one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), BPSG (boron-phosphorus-doped silicon dioxide), or a low-k material (K less than 2.5), or a stacked layer structure formed from two or more of the foregoing materials. In one example, interlayer dielectric layer 115 comprises a silicon oxide layer and a BPSG layer disposed on the silicon oxide layer. The silicon oxide layer can be formed using TEOS (tetraethoxysilane) as a silicon source during a deposition process. The silicon oxide layer has a thickness of 2800 to 3200 angstroms, and the BPSG layer has a thickness of 6500 to 7500 angstroms.

[0103] The material of the metal silicide layer 116 includes one or more of nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide, and titanium silicide.

[0104] In some embodiments, the formation process of the metal silicide layer 116 includes: forming a metal layer, such as a nickel metal layer or a cobalt metal layer, on the surfaces of the interlayer dielectric layer 115, the source region 111, and the heavily doped region 113; annealing the metal layer so that the metal in the metal layer reacts with the exposed silicon carbide to form the metal silicide layer 116; and removing the unreacted metal layer. The annealing process includes a first annealing and a second annealing. The first annealing is performed at a temperature of 700°C to 800°C for a time of 180 seconds to 220 seconds to form a high-resistance silicide. The second annealing is performed at a temperature of 850°C to 950°C for a time of 170 seconds to 190 seconds to convert the high-resistance silicide into a low-resistance silicide, thereby further reducing the contact resistance of the metal silicide.

[0105] In some embodiments, reference Figure 8 , further comprising: forming a source electrode 117 electrically connected to the source region 111 and the metal silicide on the heavily doped region 116. The material of the source electrode 117 may include one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. In one example, the source electrode 117 includes a first titanium metal layer, an aluminum metal layer located on the first titanium metal layer, and a second titanium metal layer located on the aluminum metal layer. The thickness of the first titanium metal layer is 40 nanometers to 60 nanometers, the thickness of the aluminum metal layer is 3 micrometers to 4 micrometers, and the thickness of the second titanium metal layer is 25 nanometers to 35 nanometers.

[0106] In some embodiments, reference Figure 9 , further comprising: forming a drain electrode 119 on the back side of the silicon carbide substrate 101.

[0107] Before forming the drain electrode 119 , a second metal silicide layer 118 may be formed on the back surface of the silicon carbide substrate 101 . After forming the second metal silicide layer 118 , the drain electrode 119 may be formed on the surface of the second metal silicide layer 118 .

[0108] In some embodiments, the second metal silicide layer 118 includes one or more of nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide, and titanium silicide. The material of the drain electrode 119 includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0109] The present application also provides a MOSFET device, referring to Figure 5 ,include:

[0110] A silicon carbide substrate 101 having a drift region 102 therein;

[0111] A silicon carbide epitaxial layer 103 located on a silicon carbide substrate 101;

[0112] A first well region 106 and a second well region 107 that are not in contact with each other and are located in the silicon carbide epitaxial layer 103 , wherein the doping types of the first well region 106 and the second well region 107 are opposite to the doping type of the drift region 102 ;

[0113] A shallowly doped region 109 located within the first well region 106 and the second well region 107 , wherein the doping type of the shallowly doped region 109 is opposite to the doping type of the first well region 106 ;

[0114] A source region 111 is located in the first well region 106. The source region 111 overlaps with a portion of the shallowly doped region 109 in the first well region 106 that is away from the second well region 107. The doping type of the source region 111 is the same as the doping type of the shallowly doped region 109. The depth and dopant ion concentration of the source region 111 are correspondingly greater than the depth and dopant ion concentration of the shallowly doped region 109. The depth of the source region 111 is less than the depth of the first well region 106.

[0115] A gate structure 114 located on the silicon carbide epitaxial layer 103 , the gate structure 114 spanning and covering a portion of the first well region 106 , a portion of the second well region 107 , and a portion of the shallowly doped region 109 within the first well region 106 and the second well region 107 ;

[0116] A drain region (not shown) is located on the back side of the silicon carbide substrate 101 .

[0117] In some embodiments, an end of the shallowly doped region 109 in the first well region 106 that is close to the second well region 107 does not contact the first well region 106 ;

[0118] An end of the shallowly doped region 109 in the second well region 107 , which is close to the first well region 106 , does not contact the second well region 107 ;

[0119] The source region 111 includes a first portion, a second portion, and a third portion connected in sequence. The first portion overlaps with the source region 111 , the third portion is covered by the gate structure 114 , and the second portion is located between the source region 111 and the gate structure 114 .

[0120] It should be noted that the limitations or descriptions of the same or similar parts in this embodiment (MOSFET device) and the aforementioned embodiment (method for preparing a MOSFET device) are not repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the aforementioned embodiment for details.

[0121] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0122] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a MOSFET device, characterized in that: include: Providing a silicon carbide substrate, wherein the silicon carbide substrate has a drift region; forming a silicon carbide epitaxial layer on the silicon carbide substrate; forming a first well region and a second well region that are not in contact with each other in the silicon carbide epitaxial layer, wherein the doping type of the first well region and the second well region is opposite to the doping type of the drift region; forming a shallow doped region in the first well region and the second well region, wherein the doping type of the shallow doped region is opposite to the doping type of the first well region; forming a source region in the first well region, the source region overlapping with a portion of the shallowly doped region in the first well region away from the second well region, the source region having the same doping type as the shallowly doped region, the source region having a depth and a doping ion concentration greater than the depth and doping ion concentration of the shallowly doped region, and a depth less than the depth of the first well region; forming a gate structure on the silicon carbide epitaxial layer, wherein the gate structure spans and covers a portion of the first well region, a portion of the second well region, and a portion of the shallowly doped region within the first well region and the second well region; A drain region is formed on the back side of the silicon carbide substrate.

2. The method for preparing a MOSFET device according to claim 1, wherein: An end of the shallowly doped region in the first well region close to the second well region does not contact the first well region; An end of the shallowly doped region in the second well region close to the first well region does not contact the second well region; The depth of the shallow doped region is 1 / 6-1 / 4 of the depth of the first well region; The depth of the source region is 1 / 3-2 / 3 of the depth of the first well region.

3. The method for preparing a MOSFET device according to claim 1 or 2, wherein: The shallow doped region includes a first portion, a second portion, and a third portion that are sequentially connected, the first portion overlaps with the source region, the third portion is covered by the gate structure, and the second portion is located between the source region and the gate structure.

4. The method for preparing a MOSFET device according to claim 1, wherein: Also includes: forming a heavily doped region in the second well region, wherein the heavily doped region overlaps with a portion of the lightly doped region in the second well region that is away from the first well region, and the doping type of the heavily doped region is the same as that of the second well region, the depth of the heavily doped region is greater than the depth of the lightly doped region, and the doping concentration of the heavily doped region is greater than the doping concentration of the second well region; A junction doping region is formed in the silicon carbide epitaxial layer between the first well region and the second well region. The doping type of the junction doping region is opposite to the doping type of the first well region.

5. The method for preparing a MOSFET device according to claim 4, wherein: The doping type of the drift region is N-type, the doping type of the first well region and the second well region is P-type, the doping type of the shallow doping region is N-type, the doping type of the source region is N-type, the doping type of the heavily doped region is P-type, and the doping type of the junction doping region is N-type.

6. The method for preparing a MOSFET device according to claim 4, wherein: The doping type of the drift region is P type, the doping type of the first well region and the second well region is N type, the doping type of the shallow doping region is P type, the doping type of the source region is P type, the doping type of the heavily doped region is N type, and the doping type of the junction doping region is P type.

7. The method for preparing a MOSFET device according to claim 4, wherein: After forming a junction doping region in the silicon carbide epitaxial layer, the first well region and the second well region are formed in the silicon carbide epitaxial layer; after forming the first well region and the second well region, the shallow doping region is formed; after forming the shallow doping region, the source region and the heavily doped region are formed.

8. The method for preparing a MOSFET device according to claim 7, wherein: The formation process of the junction doped region, the shallow doped region and the source region includes: forming the junction doping region in the silicon carbide epitaxial layer by an in-situ doping process or an ion implantation process; forming a first patterned mask layer on a portion of the silicon carbide epitaxial layer, wherein the first patterned mask layer exposes areas on both sides that need to be implanted; Using the first patterned mask layer as a mask, a first ion implantation process is used to implant impurity ions into the silicon carbide epitaxial layer on both sides of the first patterned mask layer to form the first well region and the second well region; forming sidewall spacers on sidewalls of the first patterned mask layer; Using the first patterned mask layer and the sidewalls as masks, a second ion implantation process is used to implant impurity ions into the silicon carbide epitaxial layer on both sides of the first patterned mask layer and the sidewalls to form the shallow doped region; The first patterned mask layer and the sidewall spacer are removed.

9. A MOSFET device, characterized in that: include: A silicon carbide substrate having a drift region therein; a silicon carbide epitaxial layer located on the silicon carbide substrate; a first well region and a second well region that are not in contact with each other and are located in the silicon carbide epitaxial layer, wherein the doping type of the first well region and the second well region is opposite to the doping type of the drift region; a shallowly doped region located within the first well region and the second well region, wherein the doping type of the shallowly doped region is opposite to the doping type of the first well region; a source region located in the first well region, the source region overlapping with a portion of a shallowly doped region in the first well region away from the second well region, the doping type of the source region being the same as that of the shallowly doped region, the depth and dopant ion concentration of the source region being respectively greater than the depth and dopant ion concentration of the shallowly doped region, and the depth of the source region being less than the depth of the first well region; a gate structure located on the silicon carbide epitaxial layer, the gate structure spanning and covering a portion of the first well region, a portion of the second well region, and a portion of the shallowly doped region within the first well region and the second well region; A drain region is located on the back side of the silicon carbide substrate.

10. The MOSFET device according to claim 9, wherein: An end of the shallowly doped region in the first well region close to the second well region does not contact the first well region; An end of the shallowly doped region in the second well region close to the first well region does not contact the second well region; The source region includes a first portion, a second portion, and a third portion that are sequentially connected, the first portion overlaps with the source region, the third portion is covered by the gate structure, and the second portion is located between the source region and the gate structure.

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