Method of fabricating vertically stacked semiconductor devices and semiconductor devices

Abstract

The application provides a vertical stacked semiconductor device manufacturing method and a semiconductor device, and relates to the technical field of semiconductors, which solves the problem that the contact leads of the upper layer source / drain and the lower layer source / drain of the existing CFET cannot be simultaneously led out by the upper layer. The manufacturing method comprises the following steps: providing a substrate; forming a lower layer stack structure on the substrate; forming an intermediate sacrificial layer on the lower layer stack structure; forming an upper layer stack structure on the intermediate sacrificial layer; patterning the upper layer stack structure so that the size of the upper layer stack structure along a first direction is smaller than the size of the lower layer stack structure along the first direction; removing the intermediate sacrificial layer and forming an insulating layer in the position of the intermediate sacrificial layer; forming lower layer source / drain at both ends of the lower layer stack structure; forming upper layer source / drain at both ends of the upper layer stack structure; and forming a first contact hole in communication with the lower layer source / drain and a second contact hole in communication with the upper layer source / drain. The application enables the contact leads of the upper layer source / drain and the lower layer source / drain to be simultaneously led out by the upper layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a method for fabricating a vertically stacked semiconductor device and the semiconductor device itself. Background Technology

[0002] With the continuous development of semiconductor technology, the number of transistors that can be accommodated per unit area of ​​a chip is constantly increasing. In the 1.8nm and above technology generations, CFET (Complementary Field Effect Transistor) is commonly used to reduce the area of ​​transistors, thereby increasing the number of transistors per unit area.

[0003] Typically, a CFET consists of vertically stacked N-type and P-type transistors. However, in existing CFETs, the contact leads for the upper and lower source / drain layers cannot be simultaneously led out from the upper layer, making circuit design impossible. Summary of the Invention

[0004] The first objective of this invention is to provide a method for fabricating a vertically stacked semiconductor device to solve the technical problem that the contact leads of the upper and lower source / drain electrodes of the existing CFET cannot be simultaneously led out from the upper layer.

[0005] The method for fabricating a vertically stacked semiconductor device provided by the present invention includes:

[0006] A substrate is provided; a lower layer stacked structure of a lower layer gate-around transistor is formed on top of the substrate; an intermediate sacrificial layer is formed on top of the lower layer stacked structure; and an upper layer stacked structure of an upper layer gate-around transistor is formed on top of the intermediate sacrificial layer.

[0007] The upper stack structure is graphically represented such that the dimension of the upper stack structure along the first direction is smaller than the dimension of the lower stack structure along the first direction, wherein the first direction is perpendicular to the thickness direction of the substrate;

[0008] Remove the intermediate sacrificial layer and form an insulating layer in the space occupied by the intermediate sacrificial layer;

[0009] Lower layer source / drain electrodes are formed at both ends of the lower layer stacked structure along the first direction;

[0010] Upper source / drain electrodes are formed at both ends of the upper stacked structure along the first direction, and the lower source / drain electrodes extend out of the upper source / drain electrodes along the first direction;

[0011] A first contact hole is formed downwards to communicate with the lower layer source / drain, and a second contact hole is formed downwards to communicate with the upper layer source / drain.

[0012] Furthermore, after the step of forming the upper layer stacked structure, the method further includes:

[0013] The upper stacked structure, the intermediate sacrificial layer, the lower stacked structure, and a portion of the substrate are etched to form fins, wherein trench isolation regions are formed at both ends of the fins along a second direction; the second direction is perpendicular to the first direction and perpendicular to the thickness direction of the substrate.

[0014] A trench isolation structure is formed in the trench isolation area, and the upper surface of the trench isolation structure is not higher than the lower surface of the lower layer of the stacked structure; the portion of the fin exposed outside the trench isolation structure is a fin-shaped structure;

[0015] A dummy gate layer is formed across the fin structure, and a hard mask layer is located on top of the dummy gate layer;

[0016] Remove the portion of the fin structure exposed outside the dummy gate layer; form a protective layer at both ends of the fin structure along the first direction, the protective layer not exceeding the upper surface of the intermediate sacrificial layer.

[0017] Furthermore, after the step of graphically representing the upper-layer stacked structure, the method further includes:

[0018] A first sidewall is deposited, which covers the upper surfaces of both the protective layer and the hard mask layer, as well as both ends of the upper stacked structure, the dummy gate layer, and the hard mask layer along the first direction;

[0019] Remove the first sidewall covering the upper surfaces of both the protective layer and the hard mask layer;

[0020] Remove a portion of the protective layer downwards to expose the insulating layer at both ends in the first direction.

[0021] Further, the step of forming an insulating layer in the space occupied by the intermediate sacrificial layer includes:

[0022] An insulating material is deposited, which covers the upper surfaces of the protective layer, the first sidewall, and the hard mask layer, as well as both ends of the first sidewall along the first direction; wherein the thickness of the insulating material covering the protective layer is a, and the occupancy thickness of the intermediate sacrificial layer is b, where a > 0.5b + 2 nm;

[0023] Remove the insulating material covering the upper surfaces of the protective layer, the first sidewall, and the hard mask layer, as well as the end of the first sidewall along the first direction.

[0024] Further, the step of forming the lower layer source / drain at both ends of the lower layer stacked structure along the first direction includes:

[0025] Remove the protective layer;

[0026] The lower layer source / drain is formed by extending the lower layer stacked structure outwards at both ends along the first direction.

[0027] Further, the step of forming upper source / drain electrodes at both ends of the upper stacked structure along the first direction includes:

[0028] A first dielectric layer is formed at both ends of the insulating layer along the first direction;

[0029] Remove a portion of the first medium layer so that the first medium layer is not higher than the lower surface of the first sidewall;

[0030] Remove the first sidewall and the hard mask layer to expose the upper stacked structure and the dummy gate layer;

[0031] The upper source / drain electrodes are formed by extending the upper layer stacked structure outwards at both ends along the first direction.

[0032] Further, after the step of forming the upper source / drain electrodes at both ends of the upper stacked structure along the first direction, the method includes:

[0033] A second dielectric layer is formed on the first dielectric layer, the second dielectric layer being located at both ends of the upper source / drain electrode along the first direction and covering the upper source / drain electrode above;

[0034] Remove the dummy gate layer at the top of the upper stacked structure to form a groove located inside the second dielectric layer at the top of the upper stacked structure;

[0035] A second sidewall is formed on the sidewall of the groove;

[0036] Remove the first sacrificial layer of the lower stacked structure and the second sacrificial layer of the upper stacked structure;

[0037] The groove is filled with a high-dielectric metal material, the space occupied by the first sacrificial layer is filled with a first gate material, and the space occupied by the second sacrificial layer is filled with a second gate material.

[0038] Furthermore, the first contact hole is formed at the top of the second dielectric layer and extends downward, penetrating the first dielectric layer; the second contact hole is formed at the top of the second dielectric layer and extends downward.

[0039] Furthermore, the lower stacked structure includes a first sacrificial layer and a first channel layer stacked alternately in sequence along the direction away from the substrate, and the thickness of the stack formed by one layer of the first sacrificial layer and one layer of the first channel layer is between 5 and 15 nm; the upper stacked structure includes a second channel layer and a second sacrificial layer stacked alternately in sequence along the direction away from the intermediate sacrificial layer, and the thickness of the stack formed by one layer of the second sacrificial layer and one layer of the second channel layer is between 5 and 15 nm; the thickness of the intermediate sacrificial layer is between 10 and 30 nm.

[0040] The beneficial effects of the fabrication method for vertically stacked semiconductor devices of the present invention are:

[0041] When fabricating vertically stacked semiconductor devices using this method, by patterning the upper stack structure, the dimension of the upper stack structure along the first direction can be made smaller than the dimension of the lower stack structure along the first direction. This allows the lower stack structure to extend beyond the upper stack structure in the first direction, creating a spatially staggered arrangement between the upper and lower stack structures. Furthermore, by forming lower source / drain electrodes at both ends of the lower stack structure along the first direction and upper source / drain electrodes at both ends of the upper stack structure along the first direction, the upper and lower source / drain electrodes are also staggered. This allows the contact leads of the upper and lower source / drain electrodes to be simultaneously led out from the upper layer without interfering with each other.

[0042] In addition, in the fabrication method of this vertically stacked semiconductor device, the lower source / drain and the upper source / drain are isolated by the insulating layer, so that the lower source / drain and the upper source / drain of the vertically stacked semiconductor device can be fabricated separately, effectively avoiding the connection between the upper and lower circuits and ensuring the effectiveness of the circuit.

[0043] The second objective of this invention is to provide a vertically stacked semiconductor device to solve the technical problem that the contact leads of the upper and lower source / drain electrodes of existing CFETs cannot be simultaneously led out from the upper layer.

[0044] The vertically stacked semiconductor device provided by the present invention includes:

[0045] Substrate;

[0046] Along the thickness direction of the substrate, a lower-layer gate-around transistor and an upper-layer gate-around transistor are disposed at intervals above the substrate. The lower-layer gate-around transistor includes a lower-layer source / drain, and the upper-layer gate-around transistor includes an upper-layer source / drain.

[0047] An insulating layer disposed between the lower-level gate-around transistor and the upper-level gate-around transistor; and

[0048] A first contact hole is connected downward to the lower source / drain electrode, and a second contact hole is connected downward to the upper source / drain electrode, wherein the first contact hole and the second contact hole are arranged at least at a distance from each other in the first direction.

[0049] Furthermore, the first contact hole and the second contact hole are also arranged at intervals in the second direction, which is perpendicular to the first direction and perpendicular to the thickness direction of the substrate.

[0050] The beneficial effects of the vertically stacked semiconductor device of this invention are:

[0051] In this vertically stacked semiconductor device, by setting the upper source / drain of the upper ring gate transistor and the lower source / drain of the lower ring gate transistor to be staggered in a first direction, the lower source / drain can extend beyond the upper source / drain in the first direction, so that the upper source / drain and the lower source / drain are spatially misaligned. This ensures that the first contact hole connecting downward to the lower source / drain will not interfere with the upper source / drain, and the second contact hole connecting downward to the upper source / drain will not interfere with the lower source / drain. The contact lead of the lower source / drain can be led out from the upper layer through the first contact hole, and the contact lead of the upper source / drain can be led out from the upper layer through the second contact hole. This solves the problem in related technologies where the contact leads of the upper and lower source / drain of the CFET cannot be led out from the upper layer at the same time. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0053] Figure 1 A schematic flowchart illustrating a method for fabricating a vertically stacked semiconductor device according to an embodiment of the present invention;

[0054] Figure 2 The following are schematic diagrams showing the fabrication method of a vertically stacked semiconductor device according to an embodiment of the present invention, in which a lower stacked structure, an intermediate sacrificial layer and an upper stacked structure are sequentially formed on a substrate, wherein (a) is a top view and (b) is a cross-sectional view of (a) AA.

[0055] Figure 3 The diagrams provided are schematic diagrams related to the fabrication method of a vertically stacked semiconductor device according to an embodiment of the present invention, which form a fin and a trench isolation structure on both sides of the fin, wherein (a) is a top view and (b) is a cross-sectional view of (a) AA.

[0056] Figure 4 The following are schematic diagrams related to the formation of a dummy gate layer and a hard mask layer across a portion of the fin in the fabrication method of the vertically stacked semiconductor device provided in the embodiments of the present invention, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0057] Figure 5 The diagrams provided are schematic representations of the lower stacked structure, the intermediate sacrificial layer, and the upper stacked structure, as well as the formation of a protective layer, in order to illustrate the fabrication method of the vertically stacked semiconductor device provided in the embodiments of the present invention. In the diagrams, (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0058] Figure 6 The above diagram illustrates the upper stacked structure, dummy gate layer, and hard mask layer, as well as the related schematic diagrams for forming the first sidewall, in order to fabricate a vertically stacked semiconductor device according to an embodiment of the present invention. (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0059] Figure 7 The following are schematic diagrams showing the removal of the top and bottom of the first sidewall in the method for fabricating a vertically stacked semiconductor device according to an embodiment of the present invention, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0060] Figure 8 The following are schematic diagrams related to the method of fabricating a vertically stacked semiconductor device according to an embodiment of the present invention, in which a portion of the protective layer is removed to expose the intermediate sacrificial layer, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0061] Figure 9 The following are schematic diagrams related to the method for fabricating a vertically stacked semiconductor device according to an embodiment of the present invention, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0062] Figure 10 The diagrams provided are schematic diagrams related to the deposition of insulating material in the fabrication method of vertically stacked semiconductor devices according to embodiments of the present invention, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0063] Figure 11The following are schematic diagrams related to the method for fabricating a vertically stacked semiconductor device according to an embodiment of the present invention, which removes excess insulating material to form an insulating layer in the space occupied by the intermediate sacrificial layer, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0064] Figure 12 The following are schematic diagrams related to the method for fabricating a vertically stacked semiconductor device according to an embodiment of the present invention, in which a lower layer notch is formed in the lower layer stacked structure, wherein (a) is a top view and (b) is a cross-sectional view of BB in (a);

[0065] Figure 13 The following are schematic diagrams related to the filling of the lower inner wall of the lower recess in the fabrication method of the vertically stacked semiconductor device provided in the embodiment of the present invention, wherein (a) is a top view and (b) is a BB cross-sectional view in (a);

[0066] Figure 14 The diagrams provided are schematic diagrams related to the fabrication method of vertically stacked semiconductor devices according to embodiments of the present invention, wherein (a) is a top view and (b) is a cross-sectional view of BB in (a);

[0067] Figure 15 The diagrams provided are schematic diagrams related to the fabrication method of a vertically stacked semiconductor device according to an embodiment of the present invention, wherein (a) is a top view and (b) is a cross-sectional view of BB in (a);

[0068] Figure 16 The following are schematic diagrams related to the method for fabricating a vertically stacked semiconductor device according to an embodiment of the present invention, wherein the lower surface of the first sidewall is used as the stop surface for etching the first dielectric layer, wherein (a) is a top view and (b) is a BB cross-sectional view in (a);

[0069] Figure 17 The following are schematic diagrams showing the fabrication method of a vertically stacked semiconductor device according to an embodiment of the present invention, with the first sidewall removed. In these diagrams, (a) is a top view and (b) is a cross-sectional view of (a) by BB.

[0070] Figure 18 The diagrams provided in the embodiments of the present invention illustrate the formation of the upper inner wall and the upper source / drain of the vertically stacked semiconductor device, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0071] Figure 19The diagrams provided are schematic diagrams related to the fabrication method of a vertically stacked semiconductor device according to an embodiment of the present invention, wherein (a) is a top view and (b) is a cross-sectional view of BB in (a);

[0072] Figure 20 The following are schematic diagrams related to the method of fabricating a vertically stacked semiconductor device according to an embodiment of the present invention, which removes the dummy gate layer at the top of the upper stacked structure to form a groove located inside the second dielectric layer, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0073] Figure 21 The following are schematic diagrams related to the method of fabricating a vertically stacked semiconductor device according to an embodiment of the present invention, in which (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0074] Figure 22 The following are schematic diagrams showing the fabrication method of a vertically stacked semiconductor device according to an embodiment of the present invention, with a portion of the second sidewall removed. In these diagrams, (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0075] Figure 23 The following are schematic diagrams related to the removal of the first sacrificial layer and the second sacrificial layer in the fabrication method of the vertically stacked semiconductor device provided in the embodiments of the present invention, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0076] Figure 24 The following are schematic diagrams related to filling high-dielectric metal material, first gate material and second gate material in the fabrication method of vertically stacked semiconductor device provided in the embodiments of the present invention, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0077] Figure 25 The following are schematic diagrams related to the fabrication method of a vertically stacked semiconductor device according to an embodiment of the present invention, wherein a first contact hole and a second contact hole are formed on the top of a second dielectric layer, wherein (a) is a top view, (b) is a cross-sectional view of AA in (a), and (c) is a cross-sectional view of BB in (a).

[0078] Figure 26 This is a top view schematic diagram of another form of the method for fabricating a vertically stacked semiconductor device according to an embodiment of the present invention, wherein a first contact hole and a second contact hole are formed on the top of a second dielectric layer.

[0079] Explanation of reference numerals in the attached figures:

[0080] 100 - Substrate; 200 - Lower gate-around transistor; 300 - Upper gate-around transistor; 400 - Insulating material; 410 - Insulating layer; 420 - Intermediate sacrificial layer; 500 - Dielectric material; 510 - First dielectric layer; 520 - Second dielectric layer; 521 - Groove; 610 - First contact hole; 620 - Second contact hole; 700 - Trench isolation structure;

[0081] 101-Fin structure; 102-Dummy gate layer; 103-Hard mask layer; 104-Protective layer; 105-First sidewall; 106-Second sidewall; 107-High dielectric metal material; 108-First gate material; 109-Second gate material;

[0082] 210 - Lower layer source / drain; 220 - Lower layer stacked structure; 221 - First channel layer; 222 - First sacrificial layer; 223 - Lower layer notch; 224 - Lower layer inner wall;

[0083] 310 - Upper source / drain electrode; 320 - Upper stacked structure; 321 - Second channel layer; 322 - Second sacrificial layer; 323 - Upper inner wall. Detailed Implementation

[0084] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0085] like Figure 1 As shown, the method for fabricating a vertically stacked semiconductor device provided in this embodiment is used to fabricate the aforementioned vertically stacked semiconductor device, including:

[0086] Step S100: As Figure 2 As shown in (a) and (b), a substrate 100 is provided; a lower stacked structure 220 of a lower gate ring transistor 200 is formed on top of the substrate 100; an intermediate sacrificial layer 420 is formed on top of the lower stacked structure 220; and an upper stacked structure 320 of an upper gate ring transistor 300 is formed on top of the intermediate sacrificial layer 420.

[0087] Please continue to refer to Figure 2 In (a), specifically, the lower stacked structure 220 includes a first sacrificial layer 222 and a first channel layer 221 stacked alternately in sequence along the direction away from the substrate 100, and the upper stacked structure 320 includes a second channel layer 321 and a second sacrificial layer 322 stacked alternately in sequence along the direction away from the intermediate sacrificial layer 420.

[0088] In this step, the substrate 100 can be made of silicon; the first sacrificial layer 222 and the second sacrificial layer 322 can be made of germanium-silicon; and the first channel layer 221 and the second channel layer 321 can be made of silicon. The intermediate sacrificial layer 420 can be made of germanium-silicon.

[0089] The thickness of the stack formed by the first sacrificial layer 222 and the first channel layer 221 is between 5 and 15 nm, the thickness of the stack formed by the second sacrificial layer 322 and the second channel layer 321 is between 5 and 15 nm, and the thickness of the intermediate sacrificial layer 420 is between 10 and 30 nm.

[0090] Both the upper layer stacked structure 320 and the lower layer stacked structure 220 are multi-layered, preferably stacked alternately three times.

[0091] By limiting the thickness of the stack formed by the first sacrificial layer 222 and the first channel layer 221, as well as the thickness of the stack formed by the second sacrificial layer 322 and the second channel layer 321, within the aforementioned range, on the one hand, it is possible to avoid the semiconductor device being too large due to excessive thickness of the lower stack structure 220 and the upper stack structure 320, and on the other hand, it is also possible to avoid the gate control capability of the semiconductor device being reduced due to insufficient gate material filling caused by excessively small thickness of the lower stack structure 220 and the lower stack structure 220.

[0092] By setting the thickness of the intermediate sacrificial layer 420 between 10 and 30 nm, the insulating layer 410 subsequently formed on the space occupied by the intermediate sacrificial layer 420 has a larger thickness. This setting can increase the insulation distance between the upper stacked structure 320 and the lower stacked structure 220, thereby enhancing the electrical isolation effect between the upper gate ring transistor 300 and the lower gate ring transistor 200.

[0093] Step S200: Pattern the upper stacked structure 320 such that the dimension of the upper stacked structure 320 along the first direction is smaller than the dimension of the lower stacked structure 220 along the first direction, wherein the first direction is perpendicular to the thickness direction of the substrate 100.

[0094] In this embodiment, "first direction" and "second direction" can be referred to as Figure 2 As indicated by the corresponding arrow in (a) of the diagram, the "thickness direction of substrate 100" can be referenced. Figure 2 As shown by the corresponding arrow in (b) of the diagram, both the first and second directions are perpendicular to the thickness direction of the substrate 100, and they are mutually perpendicular. During the manufacturing process, the thickness direction of the substrate 100 can also be considered as the vertical direction, while both the first and second directions are parallel to the horizontal direction.

[0095] When patterning the upper stacked structure 320, dry etching or wet etching can be used to remove the upper stacked structure 320 at both ends along the first direction. The etching stop layer is the upper surface of the intermediate sacrificial layer 420. This step allows the lower stacked structure 220 to extend beyond the upper stacked structure 320 at both ends in the first direction, so that the subsequently formed lower source / drain 210 can extend beyond the upper source / drain 310 in the first direction. This allows the contact leads connected to the lower source / drain 210 and the contact leads connected to the upper source / drain 310 to be led out from the upper layer.

[0096] After the step of forming the upper layer stacked structure 320, the method further includes: Figure 3 As shown in (a) and (b), the upper stacked structure 320, the intermediate sacrificial layer 420, the lower stacked structure 220 and a portion of the substrate 100 are etched to form a fin, wherein trench isolation regions are formed at both ends of the fin along the second direction; a trench isolation structure 700 is formed in the trench isolation region, the upper surface of the trench isolation structure 700 is not higher than the lower surface of the lower stacked structure 220, and the portion of the fin exposed outside the trench isolation structure 700 is a fin-shaped structure 101.

[0097] The trench isolation structure 700 described above can form an insulating barrier to reduce leakage current. The trench isolation structure 700 can be made of silicon nitride and can be obtained by deposition. The fin structure 101 has a dimension between 20 and 50 nm along the second direction.

[0098] After obtaining the fin-like structure 101, as Figure 4 As shown in (a), (b) and (c), it also includes: forming a dummy gate layer 102 across the fin structure 101, and a hard mask layer 103 located on top of the dummy gate layer 102.

[0099] Specifically, the dummy gate layer 102 can be made of polysilicon and can be formed by deposition. By patterning the dummy gate layer 102 and the hard mask layer 103, the dimensions of the fin structure 101 along the first direction can be positioned, thereby achieving the dimensional positioning of the gate structure subsequently formed by the high-dielectric metal material 107. The dimensions of the gate structure formed by the high-dielectric metal material 107 in the first direction can be between 20 and 40 nm.

[0100] After the patterned dummy gate layer 102 and the hard mask layer 103, as Figure 5 As shown in (a), (b) and (c), it also includes: removing the portion of the fin structure 101 exposed outside the dummy gate layer 102; forming a protective layer 104 at both ends of the fin structure 101 along the first direction, the protective layer 104 not exceeding the upper surface of the intermediate sacrificial layer 420.

[0101] In the above process, the removal of the fin structure 101 can be completed by dry etching or wet etching, with the etching stop layer being the upper surface of the substrate 100. Afterwards, a spin-coating material can be applied and etched back to the upper surface of the intermediate sacrificial layer 420 to form a protective layer 104, thus protecting the bottom material. The spin-coating material can be SOC (spin on carbon, spin-coated hard mask) or SOG (spin on glass coating).

[0102] By setting the protective layer 104 to be no higher than the upper surface of the intermediate sacrificial layer 420, it is possible to avoid the formation of shielding of the upper layer stack 320 at both ends along the first direction. Furthermore, while ensuring effective protection of the bottom material, it is also possible to reduce the waste of spin coating material.

[0103] After the protective layer 104 is formed, the upper layer stacked structure 320 can be patterned to make the upper layer stacked structure 320 spatially misaligned with the lower layer stacked structure 220.

[0104] like Figure 6 As shown in (a), (b) and (c), after the step of graphically representing the upper stacked structure 320, the method further includes: depositing a first sidewall 105, which covers the upper surfaces of both the protective layer 104 and the hard mask layer 103, and covers both ends of the upper stacked structure 320, the dummy gate layer 102 and the hard mask layer 103 along a first direction.

[0105] like Figure 7 As shown in (a), (b) and (c), the first sidewall 105 covering the upper surfaces of both the protective layer 104 and the hard mask layer 103 is removed.

[0106] The removal of the aforementioned first sidewall 105 can be achieved by anisotropic etching. This step can remove the top and bottom first sidewalls 105, while only retaining the vertical first sidewalls 105.

[0107] The formation of the first sidewall 105 is often achieved through atomic layer deposition. In this process, the sidewall material is basically uniformly covered on the device surface. Only the vertical first sidewall 105 can reduce parasitic capacitance. Therefore, the first sidewall 105 at the top and bottom needs to be removed.

[0108] Figure 8 As shown in (a), (b) and (c), a portion of the protective layer 104 is removed downwards to expose the intermediate sacrificial layer 420 in the first direction.

[0109] After the removal of the bottom first sidewall 105 is completed, the upper surface of the protective layer 104 is exposed. By changing the etching gas method, the protective layer 104 is etched back to the lower surface of the intermediate sacrificial layer 420, so that the two ends of the intermediate sacrificial layer 420 in the first direction are exposed.

[0110] Please continue to refer to Figure 1 After graphically representing the upper stacked structure 320 so that its dimension along the first direction is smaller than that of the lower stacked structure 220 along the first direction, the method further includes step S300: removing the intermediate sacrificial layer 420, such as... Figure 9 As shown in (a), (b), and (c); and an insulating layer 410 is formed in the space occupied by the intermediate sacrificial layer 420, as shown in (a), (b), and (c). Figure 11 As shown in (a), (b) and (c) in the figure.

[0111] In step S300 above, a high-selectivity isotropic etching process can be used to remove the intermediate sacrificial layer 420, wherein the selectivity is greater than 100:1. Specifically, a fluorine-containing gas can be used for etching to remove the intermediate sacrificial layer 420.

[0112] Please continue to refer to Figure 10 In (a), (b), and (c), the step of forming an insulating layer 410 in the space occupied by the intermediate sacrificial layer 420 may include: depositing an insulating material 400, specifically, the insulating material 400 covering the upper surfaces of the protective layer 104, the first sidewall 105, and the hard mask layer 103, and covering both sides of the first sidewall 105 along the first direction; wherein, as Figure 10 As shown in (b), the thickness of the insulating material 400 covering the protective layer 104 is a, and the occupancy thickness of the intermediate sacrificial layer 420 is b, where a > 0.5b + 2 nm.

[0113] Specifically, the insulating material 400 can be a dielectric material, such as silicon nitride. By controlling the thickness of the insulating material 400 covering the protective layer 104 to be greater than half the thickness of the intermediate sacrificial layer 420 plus 2 nm, it can be ensured that the insulating material 400 completely fills the space occupied by the intermediate sacrificial layer 420.

[0114] Please continue to refer to Figure 11 In (a), (b), and (c), after the insulating material 400 has been completely filled into the space occupied by the intermediate sacrificial layer 420, the insulating material 400 covering the upper surfaces of the protective layer 104, the first sidewall 105, and the hard mask layer 103, as well as covering the end of the first sidewall 105 along the first direction, can be removed.

[0115] The removal of the excess insulating material 400 can be achieved by dry etching or wet etching.

[0116] The insulating material 400 can be formed by atomic layer deposition. In this process, the insulating material 400 not only fills the space between the upper stacked structure 320 and the lower stacked structure 220 to form the insulating layer 410, but also covers the upper surfaces of the protective layer 104, the first sidewall 105 and the hard mask layer 103, as well as the two ends of the first sidewall 105 along the first direction. Only the insulating layer 410 between the upper stacked structure 320 and the lower stacked structure 220 can play an insulating role. Therefore, the first sidewall 105 at the top and bottom needs to be removed.

[0117] Please continue to refer to Figure 1 After forming the insulating layer 410, the method further includes step S400: forming lower layer source / drain electrodes 210 at both ends of the lower layer stacked structure 220 along the first direction.

[0118] The step of forming the lower layer source / drain 210 at both ends of the lower layer stack 220 along the first direction includes: removing the protective layer 104; and forming the lower layer source / drain 210 by extension at both ends of the lower layer stack 220 along the first direction.

[0119] Specifically, such as Figure 12 As shown in (a) and (b), the protective layer 104 can be removed by dry etching or wet etching to expose both ends of the lower stacked structure 220 in the first direction; then, both ends of the first sacrificial layer 222 can be removed by dry etching or wet etching to form the lower layer notch 223; subsequently, as... Figure 13 As shown in (a) and (b), a lower inner sidewall 224 is formed in the lower notch 223 to prevent leakage between the subsequent lower source / drain 210 and the gate structure, thus preventing performance degradation. After the lower inner sidewall 224 is formed, the lower source / drain 210 is epitaxially grown using an epitaxial process, as shown in (a) and (b). Figure 14 As shown in (a) and (b) in the figure. The material of the lower inner wall 224 can be silicon nitride or silicon oxynitride, etc.

[0120] Please continue to refer to Figure 1 After forming the lower layer source / drain 210, the method further includes step S500: forming the upper layer source / drain 310 at both ends of the upper layer stacked structure 320 along the first direction.

[0121] In other words, in the fabrication method of this vertically stacked semiconductor device, the lower source / drain 210 is fabricated first, and then the lower source / drain 210 is shielded by the insulating layer 410 to isolate the lower source / drain 210 from the upper source / drain 310. This allows the lower source / drain 210 and the upper source / drain 310 of the vertically stacked semiconductor device to be fabricated separately, effectively avoiding the connection between the upper and lower circuits and ensuring the effectiveness of the circuit.

[0122] The above-described step of forming upper source / drain electrodes 310 at both ends of the upper stacked structure 320 along the first direction includes: as follows Figure 15 As shown in (b), a first dielectric layer 510 is formed at both ends of the insulating layer 410 along the first direction, and a portion of the first dielectric layer 510 is removed so that the first dielectric layer 510 is not higher than the lower surface of the first sidewall 105.

[0123] By forming the first dielectric layer 510, further isolation of the lower source / drain 210 can be formed above, reducing the adverse effects on the lower source / drain 210; at the same time, by ensuring that the first dielectric layer 510 is not higher than the lower surface of the first sidewall 105, it is also possible to avoid lateral obstruction of the upper ring gate transistor 300.

[0124] Specifically, the formation process of the first dielectric layer 510 can be as follows: Figure 15 As shown in (a) and (b), a first dielectric layer 510 is first formed by means of fluid chemical vapor deposition or sub-atmospheric pressure vapor deposition, covering the top of the lower source / drain electrode 210, the insulating layer 410 at both ends in the first direction, and the first sidewall 105 at both ends in the first direction; then, as shown in (a) and (b), a first dielectric layer 510 is formed covering the top of the lower source / drain electrode 210, the insulating layer 410 at both ends in the first direction, and the first sidewall 105 at both ends in the first direction; then, as shown in (b) and (c), a first dielectric layer 510 is formed by means of fluid chemical vapor deposition or sub-atmospheric pressure vapor deposition, covering the top of the lower source / drain electrode 210, the insulating layer 410 at both ends in the first direction, and the first sidewall 105 at both ends in the first direction. Figure 16 As shown in (a) and (b), the first dielectric layer 510 is etched to the lower surface of the first sidewall 105 using either dry etching or wet etching.

[0125] The above-described step of forming upper source / drain electrodes 310 at both ends of the upper stacked structure 320 along the first direction further includes: as follows Figure 17 As shown in (a) and (b), the first sidewall 105 and the hard mask layer 103 are removed to expose the upper stacked structure 320 and the dummy gate layer 102. The removal of the first sidewall 105 and the hard mask layer 103 can be achieved by dry etching or wet etching. After the two ends of the upper stacked structure 320 are fully exposed along the first direction, the upper inner sidewall 323 can be formed using the same process as the lower inner sidewall 224 to prevent device performance loss due to leakage between the upper source / drain 310 and the second gate material 109.

[0126] like Figure 18 As shown in (a), (b) and (c), after the upper inner wall 323 is formed, the upper source / drain 310 is formed by extending the upper layer stacked structure 320 outward along the first direction at both ends, thereby realizing the fabrication of the upper source / drain 310.

[0127] Please continue to refer to Figure 1 After the step of forming the upper source / drain 310 at both ends of the upper stacked structure 320 along the first direction, the method includes: Figure 19As shown in (a) and (b), a second dielectric layer 520 is formed on the first dielectric layer 510. The second dielectric layer 520 is located at both ends of the upper source / drain 310 along the first direction and covers the upper source / drain 310 on top.

[0128] By forming the second dielectric layer 520, the upper source / drain electrode 310 can be protected to reduce adverse effects from external factors. Specifically, the second dielectric layer 520 can be formed by flowable chemical vapor deposition or sub-atmospheric pressure vapor deposition, and the material of the second dielectric layer 520 can be the same as or different from the material of the first dielectric layer 510.

[0129] After the step of forming the second dielectric layer 520 in the first dielectric layer 510, the following steps are included: Figure 20 As shown in (a), (b) and (c), the dummy gate layer 102 at the top of the upper stacked structure 320 is removed to form a groove 521 located inside the second dielectric layer 520 at the top of the upper stacked structure 320.

[0130] In this step, the etching degree can be controlled by controlling the etching time, so that the dummy gate layer 102 is etched to the upper surface of the upper stacked structure 320 and then stopped, so that the edge of the dummy gate layer 102 is flush with the upper stacked structure 320 or slightly lower than the upper surface of the upper stacked structure 320, to ensure that the dummy gate layer 102 at the top of the upper stacked structure 320 is completely removed, so that when the second sidewall 106 is filled in the subsequent process, the sidewall of the groove 521 can be completely covered to prevent the generation of excessive parasitic capacitance.

[0131] After forming the aforementioned groove 521, as Figure 22 As shown in (a), (b), and (c), a second sidewall 106 is formed on the sidewall of the groove 521. Specifically, the second sidewall 106 can be formed using atomic layer deposition technology to completely cover the sidewall of the groove 521, preventing interference between the metal grid and the contact lines on the side. The material of the second sidewall 106 can be the same as or different from the material of the upper inner sidewall 323, as long as it can provide insulation.

[0132] Specifically, during the deposition process, the second sidewall 106 will not only cover the sidewall of the groove 521, but also the bottom wall of the groove 521, such as... Figure 21 As shown in (a), (b) and (c), the material covering the bottom wall of the groove 521 can be removed by dry etching or wet etching to obtain the second sidewall 106 formed on the sidewall of the groove 521.

[0133] After completing the construction of the second side wall 106, as follows Figure 23As shown in (a), (b), and (c), the first sacrificial layer 222 of the lower stacked structure 220 and the second sacrificial layer 322 of the upper stacked structure 320 are removed. This step enables the release of the channels in the upper stacked structure 320 and the lower stacked structure 220. The removal of the first sacrificial layer 222 and the second sacrificial layer 322 can be achieved using fluorine-containing gas etching, with an etching selectivity greater than 100:1.

[0134] After the channel release of the upper stacked structure 320 and the lower stacked structure 220 is completed, as Figure 24 As shown in (a), (b) and (c), the groove 521 is filled with high-k metal material 107, the space in the first sacrificial layer 222 is filled with first gate material 108, and the space in the second sacrificial layer 322 is filled with second gate material 109.

[0135] Specifically, the high-dielectric metal material 107 can be filled in the groove 521 by atomic layer deposition; the first gate material 108 and the second gate material 109 can be filled by spin coating. The above filling method and the resulting structure are beneficial to reducing gate leakage current and enhancing gate control capability.

[0136] Please continue to refer to Figure 1 The fabrication method of the vertically stacked semiconductor device further includes step S600: as follows Figure 25 As shown in (a), (b) and (c) in the figure, a first contact hole 610 is opened downward to communicate with the lower source / drain 210, and a second contact hole 620 is opened downward to communicate with the upper source / drain 310.

[0137] Through the above steps, the lower source / drain 210 extends out of the upper source / drain 310 in the first direction, thereby creating a staggered arrangement between the lower source / drain 210 and the upper source / drain 310 in space. Therefore, when positioning the contact holes, the first contact hole 610 connected to the lower source / drain 210 and the second contact hole 620 connected to the upper source / drain 310 can be simultaneously led out from the upper layer without interfering with each other.

[0138] Specifically, the first contact hole 610 is formed at the top of the second dielectric layer 520 and extends downward, penetrating the first dielectric layer 510; the second contact hole 620 is formed at the top of the second dielectric layer 520 and extends downward.

[0139] Please continue to refer to Figure 25In addition to (a) and (c) in the above embodiments, this embodiment also provides a vertically stacked semiconductor device, including: a substrate 100, a lower gate ring transistor 200, an upper gate ring transistor 300, an insulating layer 410, a first contact hole 610, and a second contact hole 620. Specifically, the lower gate ring transistor 200 and the upper gate ring transistor 300 are spaced apart above the substrate 100 along the thickness direction of the substrate 100. The lower gate ring transistor 200 includes a lower source / drain 210, and the upper gate ring transistor 300 includes a lower source / drain 210. The gate-around transistor 300 includes an upper source / drain 310; along a first direction, the upper source / drain 310 extends beyond the lower source / drain 210; an insulating layer 410 is disposed between the lower gate-around transistor 200 and the upper gate-around transistor 300; a first contact hole 610 communicates downward to the lower source / drain 210, and a second contact hole 620 communicates downward to the upper source / drain, wherein the first contact hole 610 and the second contact hole 620 are arranged at least at a distance from each other in the first direction.

[0140] In this vertically stacked semiconductor device, by setting the upper source / drain 310 of the upper ring gate transistor 300 and the lower source / drain 210 of the lower ring gate transistor 200 to be offset in a first direction, the lower source / drain 210 can extend beyond the upper source / drain 310 in the first direction, so that the upper source / drain 310 and the lower source / drain 210 are spatially misaligned, thereby ensuring that the first contact hole 610 communicating downward to the lower source / drain 210 will not interfere with the upper source / drain. The first contact hole 620, which connects downward to the upper source / drain 310, does not cause interference to the lower source / drain 210. The contact leads of the lower source / drain 210 can be led out from the upper layer through the first contact hole 610, and the contact leads of the upper source / drain 310 can be led out from the upper layer through the second contact hole 620. This solves the problem in related technologies that the contact leads of the upper source / drain 310 and the lower source / drain 210 of the CFET cannot be led out from the upper layer at the same time.

[0141] Please continue to refer to Figure 25 In embodiments (a) and (c), two first contact holes 610 are provided, and the two first contact holes 610 serve as lower electrode contact holes; two second contact holes 620 are also provided, and the two second contact holes 620 serve as upper electrode contact holes, wherein each first contact hole 610 and each second contact hole 620 are arranged in a straight line.

[0142] In other embodiments, such as Figure 26As shown, based on the above arrangement of the first contact hole 610 and the second contact hole 620 at intervals in the first direction, the first contact hole 610 and the second contact hole 620 can be further arranged at intervals in the second direction. That is, the first contact hole 610 and the second contact hole 620 are not only staggered in the first direction, but also staggered in the second direction.

[0143] This setting increases the distance between the first contact hole 610 and the second contact hole 620, thereby minimizing signal interference caused by the small distance between them.

[0144] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

[0145] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0146] In the above embodiments, descriptions of directions such as "up", "down", and "side" are based on the accompanying drawings.

[0147] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating a vertically stacked semiconductor device, characterized in that, include: A substrate (100) is provided; a lower layer stack structure (220) of a lower layer gate ring transistor (200) is formed on top of the substrate (100); an intermediate sacrificial layer (420) is formed on top of the lower layer stack structure (220); and an upper layer stack structure (320) of an upper layer gate ring transistor (300) is formed on top of the intermediate sacrificial layer (420). The upper stacked structure (320) is graphically represented such that the dimension of the upper stacked structure (320) along a first direction is smaller than the dimension of the lower stacked structure (220) along the first direction, the first direction being perpendicular to the thickness direction of the substrate (100); Remove the intermediate sacrificial layer (420) and form an insulating layer (410) in the space occupied by the intermediate sacrificial layer (420). Lower layer source / drain electrodes (210) are formed at both ends of the lower layer stacked structure (220) along the first direction. Upper source / drain electrodes (310) are formed at both ends of the upper stacked structure (320) along the first direction. A first contact hole (610) communicating with the lower source / drain (210) is opened downwards, and a second contact hole (620) communicating with the upper source / drain (310) is opened downwards. After the step of forming the upper layer stacked structure (320), the method further includes: The upper stacked structure (320), the intermediate sacrificial layer (420), the lower stacked structure (220), and a portion of the substrate (100) are etched to form fins, wherein trench isolation regions are formed at both ends of the fins along a second direction; the second direction is perpendicular to the first direction and perpendicular to the thickness direction of the substrate (100); A trench isolation structure (700) is formed in the trench isolation area, and the upper surface of the trench isolation structure (700) is not higher than the lower surface of the lower layer stacked structure (220); the portion of the fin exposed outside the trench isolation structure (700) is a fin-shaped structure (101). A dummy gate layer (102) is formed across the fin structure (101), and a hard mask layer (103) is located on top of the dummy gate layer (102). Remove the portion of the fin structure (101) exposed outside the dummy gate layer (102); form a protective layer (104) at both ends of the fin structure (101) along the first direction, the protective layer (104) not exceeding the upper surface of the intermediate sacrificial layer (420); After the step of graphically representing the upper stacked structure (320), the method further includes: depositing a first sidewall (105) that covers the upper surfaces of both the protective layer (104) and the hard mask layer (103), and covers both ends of the upper stacked structure (320), the dummy gate layer (102), and the hard mask layer (103) along the first direction; removing the first sidewall (105) that covers the upper surfaces of both the protective layer (104) and the hard mask layer (103); and removing a portion of the protective layer (104) downwards to expose the insulating layer (410) at both ends of the first direction.

2. The method for fabricating a vertically stacked semiconductor device according to claim 1, characterized in that, The step of forming an insulating layer (410) in the space occupied by the intermediate sacrificial layer (420) includes: An insulating material (400) is deposited, which covers the upper surfaces of the protective layer (104), the first sidewall (105), and the hard mask layer (103), and covers both ends of the first sidewall (105) along the first direction; wherein the thickness of the insulating material (400) covering the protective layer (104) is a, and the occupancy thickness of the intermediate sacrificial layer (420) is b, where a > 0.5b + 2 nm; Remove the insulating material (400) covering the upper surfaces of the protective layer (104), the first sidewall (105), and the hard mask layer (103), as well as the end of the first sidewall (105) along the first direction.

3. The method for fabricating a vertically stacked semiconductor device according to claim 1, characterized in that, The step of forming the lower layer source / drain (210) at both ends of the lower layer stacked structure (220) along the first direction includes: Remove the protective layer (104); The lower layer source / drain (210) is formed by extending the lower layer stack (220) outward at both ends along the first direction.

4. The method for fabricating a vertically stacked semiconductor device according to claim 1, characterized in that, The step of forming upper source / drain electrodes (310) at both ends of the upper stacked structure (320) along the first direction includes: A first dielectric layer (510) is formed at both ends of the insulating layer (410) along the first direction. Remove a portion of the first medium layer (510) so that the first medium layer (510) is not higher than the lower surface of the first sidewall (105); Remove the first sidewall (105) and the hard mask layer (103) to expose the upper stacked structure (320) and the dummy gate layer (102). The upper source / drain (310) is formed by extending the upper layer stacked structure (320) outward at both ends along the first direction.

5. The method for fabricating a vertically stacked semiconductor device according to claim 4, characterized in that, After the step of forming upper source / drain electrodes (310) at both ends of the upper stacked structure (320) along the first direction, the method includes: A second dielectric layer (520) is formed on the first dielectric layer (510). The second dielectric layer (520) is located at both ends of the upper source / drain (310) along the first direction and covers the upper source / drain (310) above. Remove the dummy gate layer (102) on top of the upper stacked structure (320) to form a groove (521) located inside the second dielectric layer (520) on top of the upper stacked structure (320). A second sidewall (106) is formed on the sidewall of the groove (521). Remove the first sacrificial layer (222) of the lower stacked structure (220) and the second sacrificial layer (322) of the upper stacked structure (320). The groove (521) is filled with a high-dielectric metal material (107), the first gate material (108) is filled in the occupancy of the first sacrificial layer (222), and the second gate material (109) is filled in the occupancy of the second sacrificial layer (322).

6. The method for fabricating a vertically stacked semiconductor device according to claim 5, characterized in that, The first contact hole (610) is formed on the top of the second dielectric layer (520) and extends downward, penetrating the first dielectric layer (510); the second contact hole (620) is formed on the top of the second dielectric layer (520) and extends downward.

7. The method for fabricating a vertically stacked semiconductor device according to claim 1, characterized in that, The lower stacked structure (220) includes a first sacrificial layer (222) and a first channel layer (221) stacked alternately in a direction away from the substrate (100), and the thickness of the stack formed by one layer of the first sacrificial layer (222) and one layer of the first channel layer (221) is between 5 and 15 nm; the upper stacked structure (320) includes a second channel layer (321) and a second sacrificial layer (322) stacked alternately in a direction away from the intermediate sacrificial layer (420), and the thickness of the stack formed by one layer of the second sacrificial layer (322) and one layer of the second channel layer (321) is between 5 and 15 nm; the thickness of the intermediate sacrificial layer (420) is between 10 and 30 nm.

8. A vertically stacked semiconductor device, characterized in that, The method of fabricating a vertically stacked semiconductor device according to any one of claims 1-7 comprises: Substrate (100); Along the thickness direction of the substrate (100), a lower ring gate transistor (200) and an upper ring gate transistor (300) are disposed at intervals above the substrate (100). The lower ring gate transistor (200) includes a lower source / drain (210), and the upper ring gate transistor (300) includes an upper source / drain (310). An insulating layer (410) is disposed between the lower gate ring transistor (200) and the upper gate ring transistor (300); and A first contact hole (610) is connected downward to the lower source / drain (210), and a second contact hole (620) is connected downward to the upper source / drain (310), the first contact hole (610) and the second contact hole (620) being arranged at least at a distance in the first direction.

9. The vertically stacked semiconductor device according to claim 8, characterized in that, The first contact hole (610) and the second contact hole (620) are also arranged at intervals in the second direction.

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