Ge-Si curved surface junction single photon avalanche diode and preparation method thereof, electronic component and detector
By optimizing the electric field and conduction band distribution through the Ge-Si curved junction structure, the problems of low absorption rate and time jitter of silicon-based single-photon avalanche diodes in the near-infrared band are solved, and efficient detection of photons in the range of 800-1550nm is achieved, thereby improving the detection performance.
Patent Information
- Application Number
- CN202510876029.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-27
- Publication Date
- 2025-09-12
AI Technical Summary
Existing silicon-based single-photon avalanche diodes have low absorption in the near-infrared band, the thick depletion layer design leads to high operating voltage and integration difficulties, the timing jitter is obvious, and the detection spectrum is limited to below 1000nm.
The Ge-Si curved junction structure is adopted. By optimizing the Ge-Si interface electric field and conduction band distribution, combined with the light trapping layer, microlens, FTI structure and metal reflective surface, the photon absorption efficiency is improved and the timing jitter is reduced.
The detection efficiency in the short-wave near-infrared band is improved, the time jitter is reduced, the detection spectrum is expanded to 1000nm-1550nm, and the comprehensive detection performance is improved.
Smart Images
Figure CN120640790A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of avalanche diodes, and specifically relates to a Ge-Si curved junction single-photon avalanche diode and its preparation method, electronic components, and detectors. Background Art
[0002] A single-photon avalanche diode (SPAD), also known as a single-photon avalanche diode (SPAD), is an avalanche photodiode operating in Geiger mode (where the operating voltage is greater than the breakdown voltage). Due to its high detection efficiency, low power consumption, and fast response speed, it has been widely used in spectroscopy, quantum communications, and 3D imaging. The SPAD operates under the Geiger mode. When the SPAD absorbs a photon, electron-hole pairs are generated in the avalanche region. A strong electric field generates an avalanche multiplication effect, generating an avalanche current, enabling photon detection.
[0003] Silicon manufacturing technology provides a mature processing platform for SPAD integration. However, silicon has a low absorption rate in the near-infrared band. To optimize the photon detection efficiency (PDE), near-infrared enhanced silicon SPADs use a variety of techniques to obtain a thicker absorption region to improve the PDE. The carriers generated in the absorption region then move toward the electric field peak, triggering avalanche breakdown. However, this, to a certain extent, leads to high operating voltages, high over-bias voltages, and increased sensitivity to defects generated during the manufacturing process. At the same time, this thick depletion layer SPAD requires a large guard ring, making it difficult to integrate into dense arrays. In addition, the technical design that allows electrons to reach the central avalanche region through drift motion in traditional technologies, while improving the near-infrared photon detection efficiency (PDE), will cause significant timing jitter in the avalanche diode.
[0004] Moreover, the detectable spectrum of the above-mentioned avalanche diode is limited to below 1000nm. Therefore, in order to detect photons above 1000nm, it is necessary to develop a new type of single-photon avalanche diode to solve the various existing problems.
[0005] Application Contents The purpose of this application is to address the deficiencies of the prior art and provide a Ge-Si curved junction single-photon avalanche diode and its preparation method, electronic components, and detectors, specifically adopting the following technical solutions: First, the present application provides a Ge-Si curved junction single-photon avalanche diode, comprising: an N+ layer, a P buried layer, an N GR layer, a P+ layer, a P layer, a Si P-epi layer, and a Ge P-epi layer; wherein the N+ layer, the P buried layer, the N GR layer, the P+ layer, the P layer, the Si P-epi layer, and the Ge P-epi layer are all prepared from a wafer comprising Si and Ge elements; The light incident side of the Ge-Si curved junction single-photon avalanche diode is the first surface, and the surface farthest from the first surface along the light propagation direction is the second surface. On the light-emitting side of the first surface, along the light propagation direction, a Ge P-epi layer and a Si P-epi layer are sequentially arranged, a P buried layer is arranged on the Si P-epi layer away from the light incident direction, and an N+ layer is wrapped inside the Pburied layer; the N+ layer and the P buried layer extend to the second surface, an N GR layer is arranged around the outside of the P buried layer, a P+ layer is arranged around the outside of the N GR layer, the P+ layer is provided with a P layer along the light incident direction, and the P layer is located between the P+ layer and the Ge P-epi layer; The electric field strength of Ge-Si curved junction single-photon avalanche diode is in the range of 2.446e-02 V*cm -1 to 1.310e+06V*cm -1 .
[0006] In some specific implementations, the Ge-Si curved junction single-photon avalanche diode further includes a light-trapping layer, and the light-trapping layer is located on the light-incident side of the first surface.
[0007] In some specific implementations, the Ge-Si curved junction single-photon avalanche diode further includes a microlens, which is located on the light-incident side of the light-trapping layer.
[0008] In some specific implementations, the Ge-Si curved junction single-photon avalanche diode further includes an FTI structure, which surrounds the outer side of the P+ and extends from the first surface to the second surface.
[0009] In some specific implementations, the Ge-Si curved junction single-photon avalanche diode further includes a cathode and an anode, wherein the cathode and the anode are located on the second surface, the cathode contacts the N+ layer, and the anode contacts the P+ layer.
[0010] In some specific implementations, a metal reflective surface is further provided on the light-emitting side of the second surface, and the metal reflective surface is used to reflect light.
[0011] Secondly, the present application also provides a method for preparing the above-mentioned Ge-Si curved junction single-photon avalanche diode, which includes a light trapping layer, a microlens, an FTI structure, a cathode, an anode, and a metal reflective surface. The specific preparation method includes the following steps: A wafer F having a structure consisting of a Si P-epi layer, a Ge epi layer, a Ge layer and a Si Base layer from top to bottom is prepared for a CIS process. The Si P-epi layer is etched using the layout FTI as a photolithography mask to prepare a deep groove penetrating the Si P-epi layer, and P-type doping is performed on the inner side of the deep groove, followed by metal filling to form an FTI structure. Subsequently, an ion implantation process is performed using the layout N GR as a photolithography mask to perform n-type doping to form an N GR layer. Subsequently, n+ type doping is performed using the layout N1 as a photolithography mask, and an N+ layer is formed after annealing. Subsequently, p+ type and p-type doping are performed using the layout P+ as a photolithography mask to form an anode contact area. Subsequently, p-type doping is performed using the layout P buried as a photolithography mask to form a P buried layer. Subsequently, a contact electrode and a metal reflective layer are formed on the second surface. Subsequently, the Si Base layer is stripped off, the Ge layer is thinned, and a light trapping layer is deposited. After the deposition of the light trapping layer is completed, a microlens is prepared on the outside of the light trapping layer.
[0012] In some specific implementations, the method for preparing the wafer F includes the following steps: Wafer A1 is prepared, which has a structure consisting of a Si P+ Base layer and a Si P- epi layer from bottom to top. Ge epitaxial growth is performed on wafer A to obtain wafer B with a Ge epi layer grown on the surface. Wafer B is annealed to obtain wafer C1 with a Ge epi layer grown on the annealed surface. A wafer A2 having a Si Base layer is prepared, and Ge bonding is performed on wafer A2 to obtain a wafer C2 having a structure consisting of a Si Base layer and a Ge layer from bottom to top; the Ge layer of wafer C2 and the Ge epi layer of wafer C1 are docked to bond wafers C2 and C1, followed by an annealing process to obtain a wafer D having a structure consisting of a Si P+ Base layer, a Si P-epi layer, a Geepi layer, a Ge layer, and a Si Base layer from bottom to top; the Si P+ Base layer is then thinned to obtain a thinned wafer E; wafer E is polished to obtain a wafer F; the structure of wafer F consists of a Si P-epi layer, a Ge epi layer, a Ge layer, and a Si Base layer from top to bottom.
[0013] Subsequently, the present application also provides an electronic component including the above-mentioned Ge-Si curved junction single-photon avalanche diode.
[0014] Finally, the present application also provides a detector comprising the above electronic component.
[0015] The beneficial effects of the present application are as follows: the Ge-Si curved junction single-photon avalanche diode provided by the present application is combined with the curved junction technology to optimize the electric field distribution and conduction band distribution of the Ge-Si interface, thereby overcoming the problem of interface defects existing in traditional technical means, improving the detection efficiency in the short-wave near-infrared band, and at the same time ensuring low time jitter, thereby improving the overall detection performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 The figure shows a schematic structural diagram of a Ge-Si curved junction single-photon avalanche diode provided in a specific embodiment; Figure 2 FIG2 is a schematic diagram showing a curve of the probability of electrons in Ge moving to the avalanche region of a Ge-Si curved junction single-photon avalanche diode provided in a specific embodiment as a function of the distance from the device center axis; Figure 3 FIG2 is a schematic diagram of a wafer processing flow used in the preparation of a Ge-Si curved junction single-photon avalanche diode structure provided in a specific embodiment; Figure 4 FIG2 is a schematic diagram of a photolithography layout used in the preparation process of a Ge-Si curved junction single-photon avalanche diode structure provided in a specific embodiment; Figure 5 Shown is an electric field intensity distribution and electron motion diagram of a Ge-Si curved junction single photon avalanche diode structure provided in a specific embodiment; Figure 6 The figure shows the electric field intensity at the edge of a Ge-Si curved junction single photon avalanche diode structure provided in a specific embodiment; Figure 7 Shown is a detection efficiency diagram within the range of 800-1550nm of a Ge-Si curved junction single-photon avalanche diode structure provided in a specific embodiment; Figure 8 The figure shows a time jitter diagram of a Ge-Si curved junction single photon avalanche diode structure within the range of 800-1550nm provided in a specific embodiment; Figure 9 Shown is an energy band diagram at the Ge-Si interface of a Ge-Si curved junction single-photon avalanche diode structure provided in a specific embodiment. DETAILED DESCRIPTION
[0017] The following will be combined with the embodiments and drawings to clearly and completely describe the concept, specific structure and technical effects of this application so as to fully understand the purpose, scheme and effect of this application. It should be noted that the embodiments and features in the embodiments of this application can be combined with each other unless there is a conflict. The same reference numerals used throughout the drawings indicate the same or similar parts.
[0018] Combined with attachment Figure 1-9 First, the present application provides a Ge-Si curved junction single-photon avalanche diode, comprising: an N+ layer, a P buried layer, an NGR layer, a P+ layer, a P layer, a Si P- epi layer, and a Ge P- epi layer; wherein the N+ layer, the P buried layer, the NGR layer, the P+ layer, the P layer, the Si P- epi layer, and the Ge P- epi layer are all prepared from a wafer comprising Si and Ge elements; like Figure 1 As shown, the light incident side of the Ge-Si curved junction single-photon avalanche diode is the first surface, and the surface farthest from the first surface along the light propagation direction is the second surface. On the light-emitting side of the first surface, along the light propagation direction, a Ge P-epi layer and a Si P-epi layer are sequentially arranged, and the Si P-epi layer is provided with a Pburied layer in the direction away from the light incident, and the interior of the P buried layer is wrapped with an N+ layer; the N+ layer and the P buried layer extend to the second surface, the outside of the P buried layer is surrounded by an N GR layer, the outside of the N GR layer is surrounded by a P+ layer, the P+ layer is provided with a P layer along the light incident direction, and the P layer is located between the P+ layer and the Ge P-epi layer; The electric field strength of Ge-Si curved junction single-photon avalanche diode is in the range of 2.446e-02 V*cm -1 to 1.310e+06V*cm -1 .
[0019] Specifically, the structure of the traditional avalanche diode is optimized in this application so that a strong electric field of a specific intensity is generated within the structure of a specific curved junction, so that the electrons generated after the photons of incident light are absorbed in the Ge P-epi layer (also known as the Ge epitaxial layer) enter the subsequent structure and drift toward the avalanche area under the action of the specific strong electric field of the curved junction, eventually causing avalanche breakdown.
[0020] like Figure 5 As shown in the figure, since the conduction band of Ge is higher than that of Si, electrons move into Si and gather in the avalanche region under the action of the electric field, triggering avalanche breakdown. The electric field strength of the Ge-Si curved junction single-photon avalanche diode is in the range of 2.446e-02 V*cm -1to 1.310e+06 V*cm -1 .
[0021] like Figure 6 As shown, the Ge-Si curved junction single-photon avalanche diode provided by the present application greatly reduces the dark counts caused by the Ge-Si lattice mismatch. At the same time, the strong electric field area is only concentrated in a small area at the edge of Ge. That is, at a depth of 5μm, the electric field strength reaches 1E+5 V*cm -1 .
[0022] like Figure 9 As shown, the energy band of the Ge-Si curved junction single-photon avalanche diode provided by the present application at the interface of the curved junction changes with the distance from the center axis of the device. The specific changes are as follows: Figure 9 shown.
[0023] like Figure 2 As shown in the figure, the conduction band energy level of Ge at the edge of the device is lower than the conduction band energy level of Si, which makes it difficult for electrons in Ge at the edge to reach Si, thereby weakening the influence of electrons generated by Ge sidewall defects on the device, thereby reducing the dark count.
[0024] like Figure 7 As shown, since the Ge-Si curved junction single-photon avalanche diode provided by the present application adopts a variety of structures to cooperate with each other, its detection efficiency in the range of 800nm-1550nm is significantly improved; compared with the problem that the detectable spectrum of traditional avalanche diodes is limited to 1000nm, the detection efficiency of the Ge-Si curved junction single-photon avalanche diode provided by the present application remains stable in the wavelength range of 1000nm-1400nm. Although the detection efficiency decreases significantly in the range of 1400nm-1500nm, the detection capability is still maintained; until 1500nm-1550nm, the detection efficiency gradually decreases to zero.
[0025] like Figure 8 As shown, the Ge-Si curved junction single-photon avalanche diode provided by the present application has relatively stable time jitter of each wavelength within the detection range under an over-bias voltage of 3.3V. Although the time jitter increases after the wavelength exceeds 1000nm, it is still within an acceptable range.
[0026] In some specific implementations, the Ge-Si curved junction single-photon avalanche diode further includes a light-trapping layer, and the light-trapping layer is located on the light-incident side of the first surface.
[0027] In some specific implementations, the Ge-Si curved junction single-photon avalanche diode further includes a microlens, which is located on the light-incident side of the light-trapping layer.
[0028] In some specific implementations, the Ge-Si curved junction single-photon avalanche diode further includes an FTI structure, which surrounds the outer side of the P+ and extends from the first surface to the second surface.
[0029] In some specific implementations, the Ge-Si curved junction single-photon avalanche diode further includes a cathode and an anode, wherein the cathode and the anode are located on the second surface, the cathode contacts the N+ layer, and the anode contacts the P+ layer.
[0030] In some specific implementations, a metal reflective surface is further provided on the light-emitting side of the second surface, and the metal reflective surface is used to reflect light.
[0031] Secondly, the present application also provides a method for preparing the above-mentioned Ge-Si curved junction single-photon avalanche diode, which includes a light trapping layer, a microlens, an FTI structure, a cathode, an anode, and a metal reflective surface. The specific preparation method includes the following steps: A wafer F having a structure consisting of a Si P-epi layer, a Ge epi layer, a Ge layer and a Si Base layer from top to bottom is prepared for a CIS process. The Si P-epi layer is etched using the layout FTI as a photolithography mask to prepare a deep groove penetrating the Si P-epi layer, and P-type doping is performed on the inner side of the deep groove, followed by metal filling to form an FTI structure. Subsequently, an ion implantation process is performed using the layout N GR as a photolithography mask to perform n-type doping to form an N GR layer. Subsequently, the layout N1 is used as a photolithography mask to perform n+ type doping, and an N+ layer is formed after annealing. Subsequently, the layout P+ is used as a photolithography mask to perform p+ type doping and p-type doping to form an anode contact area. Subsequently, the layout P buried is used as a photolithography mask to perform p-type doping to form a P buried layer. Subsequently, a contact electrode and a metal reflective layer are formed on the second surface. Subsequently, the Si Base layer is stripped off, the Ge layer is thinned, and a light trapping layer is deposited. After the deposition of the light trapping layer is completed, a microlens is prepared on the outer side of the light trapping layer. Among them, when using the layout P+ as a photolithography mask to perform p+ type doping and p- type doping, what is formed is the P+ layer, and the contact surface between the P+ layer and the anode is the anode contact area; In the above preparation process, the Ge epi layer is doped with P type to form a Ge P-epi layer.
[0032] like Figure 3 As shown, in some specific implementations, the method for preparing the wafer F includes the following steps: Prepare wafer A1, which has a structure consisting of a Si P+ base layer and a Si P- epi layer from bottom to top. Perform Ge epitaxial growth on wafer A, specifically using UHV-CVD and dual-temperature epitaxial growth, to obtain wafer B with a Ge epi layer grown on the surface. Perform an annealing process on wafer B to obtain wafer C1 with a Ge epi layer grown on the annealed surface. A wafer A2 having a Si Base layer is prepared, and Ge bonding is performed on wafer A2 to obtain a wafer C2 having a structure consisting of a Si Base layer and a Ge layer from bottom to top; the Ge layer of wafer C2 and the Ge epi layer of wafer C1 are docked to bond wafers C2 and C1, followed by an annealing process to obtain a wafer D having a structure consisting of a Si P+ Base layer, a Si P-epi layer, a Geepi layer, a Ge layer, and a Si Base layer from bottom to top; the Si P+ Base layer is then thinned to obtain a thinned wafer E; wafer E is polished to obtain a wafer F; the structure of wafer F consists of a Si P-epi layer, a Ge epi layer, a Ge layer, and a Si Base layer from top to bottom.
[0033] Subsequently, the present application also provides an electronic component including the above-mentioned Ge-Si curved junction single-photon avalanche diode.
[0034] Finally, the present application also provides a detector comprising the above electronic component.
[0035] The Ge-Si curved junction single-photon avalanche diode provided in this application combines curved junction technology to optimize the electric field distribution and conduction band distribution at the Ge-Si interface, thereby overcoming the interface defect problems existing in traditional technical means, improving the detection efficiency in the short-wave near-infrared band, and at the same time ensuring low time jitter, thereby improving the overall detection performance.
[0036] Although the description of the present application has been quite detailed and specifically describes several embodiments, it is not intended to be limited to any of these details or embodiments or any particular embodiment, but should be regarded as providing a broad possible interpretation of these claims by reference to the appended claims in view of the prior art, thereby effectively covering the intended scope of the present application. In addition, the above description of the present application is based on the embodiments foreseeable by the applicant, which is intended to provide a useful description, and those non-substantial changes to the present application that have not yet been foreseen may still represent equivalent changes to the present application.
Claims
1. A Ge-Si curved junction single-photon avalanche diode, characterized in that: include: N+ layer, P buried layer, N GR layer, P+ layer, P layer, Si P- epi layer and Ge P- epi layer; The light incident side of the Ge-Si curved junction single-photon avalanche diode is the first surface, and the surface farthest from the first surface along the light propagation direction is the second surface. On the light-emitting side of the first surface, along the light propagation direction, the Ge P-epi layer and the Si P-epi layer are sequentially arranged, the Si P-epi layer is provided with the P buried layer in the direction away from the light incident, and the interior of the P buried layer is wrapped with the N+ layer; the N+ layer and the P buried layer extend to the second surface, the outer side of the P buried layer is surrounded by the N GR layer, the outer side of the N GR layer is surrounded by the P+ layer, the P+ layer is provided with the P layer along the light incident direction, and the P layer is located between the P+ layer and the Ge P-epi layer; The electric field strength of the Ge-Si curved junction single-photon avalanche diode is in the range of 2.446e-02 V*cm -1 to 1.310e+06V*cm -1 .
2. The Ge-Si curved junction single-photon avalanche diode according to claim 1, characterized in that: It also includes a light trapping layer, which is located on the light incident side of the first surface.
3. The Ge-Si curved junction single-photon avalanche diode according to claim 2, characterized in that: It also includes a micro lens, which is located on the light incident side of the light trapping layer.
4. The Ge-Si curved junction single-photon avalanche diode according to claim 1, characterized in that: The invention also includes an FTI structure, wherein the FTI structure surrounds the outside of the P+ layer and extends from the first surface to the second surface.
5. The Ge-Si curved junction single-photon avalanche diode according to claim 1, characterized in that: The device further includes a cathode and an anode, wherein the cathode and the anode are located on the second surface, the cathode is in contact with the N+ layer, and the anode is in contact with the P+ layer.
6. The Ge-Si curved junction single-photon avalanche diode according to claim 1, characterized in that: A metal reflective surface is further provided on the light-emitting side of the second surface, and the metal reflective surface is used to reflect light.
7. A method for preparing a Ge-Si curved junction single-photon avalanche diode according to any one of claims 1 to 6, characterized in that: The Ge-Si curved junction single-photon avalanche diode comprises a light trapping layer, a microlens, an FTI structure, a cathode, an anode and a metal reflective surface; and the specific preparation method comprises the following steps: Prepare a wafer F with a structure consisting of a Si P-epi layer, a Ge epi layer, a Ge layer and a Si Base layer from top to bottom for a CIS process, use the layout FTI as a photolithography mask, etch the Si P-epi layer to prepare a deep groove penetrating the Si P-epi layer, and perform P-type doping on the inner side of the deep groove, and then deposit metal filling to form the FTI structure; then use the layout N GR as a photolithography mask to perform an ion implantation process to perform n-type doping to form the N GR layer; then use the layout N1 as a photolithography mask to perform n+ type doping, and form the N+ layer after annealing; then use the layout P+ as a photolithography mask to perform p+ type doping and p-type doping to form an anode contact area; then use the layout P buried as a photolithography mask to perform p-type doping to form the P buried layer; then form a contact electrode and a metal reflective layer on the second surface; then strip Si The base layer is formed, the Ge layer is thinned, a light trapping layer is deposited, and after the deposition of the light trapping layer is completed, the micro lens is prepared on the outer side of the light trapping layer.
8. The method for preparing a Ge-Si curved junction single-photon avalanche diode according to claim 7, characterized in that: The method for preparing the wafer F comprises the following steps: Prepare a wafer A1 having a structure consisting of a Si P+ Base layer and the Si P- epi layer from bottom to top, perform Ge epitaxial growth on the wafer A1 to obtain a wafer B having the Ge epi layer grown on the surface; perform an annealing process on the wafer B to obtain an annealed wafer C1 having the Ge epi layer grown on the surface; A wafer A2 having a Si Base layer is prepared, and Ge bonding is performed on the wafer A2 to obtain a wafer C2 whose structure from bottom to top consists of a Si Base layer and a Ge layer; the Ge layer of the wafer C2 and the Ge epi layer of the wafer C1 are docked, so that the wafers C2 and C1 are bonded, and then an annealing process is performed to obtain a wafer D whose structure from bottom to top consists of the Si P+ Base layer, the Si P- epi, the Ge epi layer, the Ge layer and the Si Base layer; the Si P+ Base layer is then thinned to obtain a thinned wafer E; the wafer E is polished to obtain a wafer F; the structure of the wafer F consists of the Si P- epi layer, the Ge epi layer, the Ge layer and the Si Base layer from top to bottom.
9. An electronic component, characterized in that: The invention comprises the Ge-Si curved junction single-photon avalanche diode according to any one of claims 1 to 6.
10. A detector, characterized in that: The electronic component according to claim 9 is included.