Back contact battery and preparation method of back contact battery

Abstract

The invention relates to a back contact battery and a preparation method of the back contact battery. The back contact battery comprises a substrate, a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, a second doped semiconductor layer, a first electrode and a second electrode. In the thickness direction of the substrate, the substrate is provided with a front face and a back face which are oppositely arranged, and the back face comprises first areas and second areas which are alternately arranged. And the first tunneling layer, the first doped semiconductor layer, the second tunneling layer and the second doped semiconductor layer are stacked on the first region of the back surface along the direction far away from the substrate. The first electrode is electrically connected with the second doped semiconductor layer, and the second electrode is arranged in the second area and electrically connected with the substrate. Therefore, the probability of short circuit can be reduced while an additional grooving process for separating the first region from the second region can be omitted, so that the manufacturing efficiency and reliability of the back contact battery can be improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a method for preparing the back-contact cell. Background Art

[0002] The electrodes of the back contact cell are arranged on the back side of the back contact cell, so that the front side of the back contact cell is not blocked by the electrodes, thereby increasing the area of ​​the back contact cell that absorbs sunlight, thereby improving the conversion efficiency of the back contact cell.

[0003] In the related art, the preparation process of the back-contact battery generally includes: separating the P region and the N region on the back side of the back-contact battery through a grooving process (the P region refers to the area on the back side of the back-contact battery for setting the P-type doping layer, and the N region refers to the area on the back side of the back-contact battery for setting the N-type doping layer) to reduce the probability of short circuit. Summary of the Invention

[0004] Based on this, it is necessary to provide a back-contact battery and a method for preparing the back-contact battery to address the above technical problems, which can improve the manufacturing efficiency of the back-contact battery.

[0005] According to a first aspect of the present application, there is provided a back-contact battery, comprising:

[0006] A substrate, wherein along a thickness direction of the substrate, the substrate has a front surface and a back surface disposed opposite to each other, the back surface including first regions and second regions disposed alternately;

[0007] A first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer are stacked on the first region of the back surface in a direction away from the substrate; wherein the first doped semiconductor layer and the second doped semiconductor layer have the same conductivity type and are opposite to the conductivity type of the substrate;

[0008] a first electrode electrically connected to the second doped semiconductor layer; and

[0009] The second electrode is disposed in the second region and electrically connected to the substrate; a height difference is formed between the first electrode and the second electrode.

[0010] In one embodiment, the second area of ​​the back surface has a first velvet structure, and the first velvet structure includes a plurality of first pyramid structures;

[0011] Along the direction from the front surface to the back surface, the height of the first pyramid structure is 2 μm-5 μm;

[0012] Along a direction perpendicular to the front surface and pointing toward the back surface, a size of the first pyramid structure is 1 μm-5 μm.

[0013] In one embodiment, the front surface has a second velvet structure, and the second velvet structure includes a plurality of second pyramid structures;

[0014] Along the direction from the front surface to the back surface, the height of the second pyramid structure is 1 μm-3 μm;

[0015] Along a direction perpendicular to the front surface and pointing toward the back surface, a size of the second pyramid structure is 1 μm-5 μm.

[0016] In one embodiment, the sheet resistance of the second doped semiconductor layer is 100Ω / □-300Ω / □; and / or

[0017] The sheet resistance of the first doped semiconductor layer is 100Ω / □-300Ω / □; and / or

[0018] The thickness of the first doped semiconductor layer is 20 nm-100 nm; and / or

[0019] The thickness of the second doped semiconductor layer is 100 nm-250 nm; and / or

[0020] The thickness of the first tunneling layer is 1 nm to 4 nm; and / or

[0021] The thickness of the second tunneling layer is 1 nm-4 nm.

[0022] In one embodiment, the first region is flatter than the second region; and / or

[0023] The second area of ​​the back surface has a first velvet structure, the first velvet structure includes a plurality of first pyramid structures; the first area of ​​the back surface has a polished structure, the polished structure includes a plurality of tower base structures, and the height of the first pyramid structure is greater than the height of the tower base structure in the direction from the front surface to the back surface; and / or

[0024] The area of ​​the first region is S1, and the area of ​​the second region is S2, wherein S1 and S2 have the same unit, and S2 satisfies the following condition: S2 / (S1+S2)=a, where a is 30%-70%.

[0025] According to a second aspect of the present application, a method for preparing a back-contact battery is provided, comprising:

[0026] Providing a substrate, wherein along a thickness direction of the substrate, the substrate has a front surface and a back surface disposed opposite to each other, the back surface including first regions and second regions disposed alternately;

[0027] forming a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer in a stacked manner on the first region of the back side of the substrate in a direction away from the substrate; wherein the first doped semiconductor layer and the second doped semiconductor layer have the same conductivity type and are opposite to the conductivity type of the substrate;

[0028] forming a first electrode electrically connected to the second doped semiconductor layer, and a second electrode disposed on the second region and electrically connected to the substrate;

[0029] Wherein, a height difference is formed between the first electrode and the second electrode.

[0030] In one embodiment, forming a stacked first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer on the first region of the back side of the substrate in a direction away from the substrate specifically includes:

[0031] forming a first initial tunneling layer, a first initial semiconductor layer, a second initial tunneling layer, and a second initial semiconductor layer stacked on the first region of the back side of the substrate in a direction away from the substrate;

[0032] forming a doping source layer on a side of the second initial semiconductor layer away from the second initial tunneling layer;

[0033] diffusing the doping element in the doping source layer into the first initial semiconductor layer and the second initial semiconductor layer, so that the first initial semiconductor layer is transformed into a first initial doped semiconductor layer, and the second initial semiconductor layer is transformed into a second initial doped semiconductor layer;

[0034] patterning the doping source layer using a laser in a first preset pattern to remove a portion of the doping source layer corresponding to the second region;

[0035] removing the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer, and a portion of the second initial doped semiconductor layer corresponding to the second region to form a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer stacked on the first region of the back side of the substrate;

[0036] The doping source layer is removed.

[0037] In one embodiment, in the step of patterning the doping source layer with a first preset pattern using a laser to remove the portion of the doping source layer corresponding to the second region, the process parameters of the laser treatment include: a laser wavelength of 300nm-1000nm; a laser energy density of 103W / cm 2 -106W / cm 2 , laser line width is 80μm-1500μm; and / or

[0038] The removing of the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer and the portion of the second initial doped semiconductor layer corresponding to the second region specifically includes: using a first etching solution to remove the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer and the portion of the second initial doped semiconductor layer corresponding to the second region; wherein the first etching solution includes an alkali and a polishing additive; the volume of the alkali is 20L-40L, and the volume of the polishing additive is 2L-5L; the temperature of the first etching solution is 60°C-80°C; and the processing time of the first etching solution is 100s-300s.

[0039] In one embodiment, before patterning the doping source layer with a laser using a first preset pattern to remove the portion of the doping source layer corresponding to the second region, the method further includes: forming a protective layer on a side of the doping source layer away from the second initially doped semiconductor layer;

[0040] The method of patterning the doping source layer with a first preset pattern using a laser to remove a portion of the doping source layer corresponding to the second region specifically includes: patterning the doping source layer and the protective layer with a first preset pattern using a laser to remove a portion of the doping source layer corresponding to the second region, and a portion of the protective layer corresponding to the second region.

[0041] In one embodiment, before forming the first electrode electrically connected to the second doped semiconductor layer and the second electrode provided on the second region and electrically connected to the substrate, after forming the first tunneling layer, the first doped semiconductor layer, the second tunneling layer, and the second doped semiconductor layer in a stacked arrangement on the first region on the back side of the substrate in a direction away from the substrate, the method further includes:

[0042] Performing a texturing process on the second region and the front surface to form a first velvet structure on the second region and a second velvet structure on the front surface; wherein the first velvet structure includes a plurality of first pyramid structures; and the second velvet structure includes a plurality of second pyramid structures;

[0043] Along the direction away from the substrate, a first passivation layer and a first anti-reflection layer are stacked on the side of the second doped semiconductor layer facing away from the second tunneling layer and on the first velvet structure, and a second passivation layer and a second anti-reflection layer are stacked on the second velvet structure.

[0044] In the technical solution of the present application, a first tunneling layer, a first doped semiconductor layer, a second tunneling layer and a second doped semiconductor layer are stacked on a first region on the back side of a substrate. On the one hand, compared with a thicker tunneling layer, in the present application, the thickness of the first tunneling layer or the second tunneling layer in the two tunneling layers can be designed to be thinner, so that the first tunneling layer and the second tunneling layer can jointly play an anti-tunneling role and a passivation role at the same time, thereby enhancing the passivation performance and carrier transport of the back contact battery, thereby improving the electrical performance of the back contact battery such as open circuit voltage and fill factor; on the other hand, compared with a thicker doped semiconductor layer, the present application Two thinner doped semiconductor layers can be designed in the application, which is beneficial to increasing the doping concentration of the first doped semiconductor layer and the second doped semiconductor layer, thereby improving the electrical performance of the back contact battery; in addition, the first tunneling layer, the first doped semiconductor layer, the second tunneling layer and the second doped semiconductor layer are stacked on the first area on the back side of the substrate, which can also form a height difference between the first electrode and the second electrode, and the first electrode and the second electrode can be electrically isolated by the first tunneling layer, eliminating the need to separate the first area and the second area through an additional grooving process, and can also reduce the probability of short circuit, thereby improving the manufacturing efficiency and reliability of the back contact battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic structural diagram of a back-contact battery in one embodiment of the present application is shown.

[0046] Figure 2 A schematic diagram (partial structural diagram) of the process of manufacturing a back-contact battery in one embodiment of the present application is shown.

[0047] Figure 3 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 2 process diagram that follows the process diagram shown).

[0048] Figure 4 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 3 process diagram that follows the process diagram shown).

[0049] Figure 5 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 4process diagram that follows the process diagram shown).

[0050] Figure 6 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 5 process diagram that follows the process diagram shown).

[0051] Figure 7 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 6 process diagram that follows the process diagram shown).

[0052] Figure 8 A schematic diagram of the process of manufacturing a back-contact battery in an embodiment of the present application (overall structural schematic diagram) is shown.

[0053] Figure 9 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 8 process diagram that follows the process diagram shown).

[0054] Figure 10 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 9 process diagram that follows the process diagram shown).

[0055] Figure 11 A schematic diagram showing a process of manufacturing a back contact battery in an embodiment of the present application (located at Figure 10 process diagram that follows the process diagram shown).

[0056] Figure numerals: 100, substrate; 101, front side; 102, back side; 1021, first region; 1022, second region; 103, first pyramid structure; 104, second pyramid structure; 105, side; 210, first tunneling layer; 310, first doped semiconductor layer; 220, second tunneling layer; 320, second doped semiconductor layer; 211, first initial tunneling layer; 311, first initial semiconductor layer; 312, first initial doped semiconductor layer; 221, second initial tunneling layer; 321, second initial semiconductor layer; 322, second initial doped semiconductor layer; 400, doping source layer; 500, protective layer; 610, first passivation layer; 620, second passivation layer; 710, first anti-reflection layer; 720, second anti-reflection layer; 810, first electrode; 820, second electrode. DETAILED DESCRIPTION

[0057] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0058] In the description of this application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0059] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, if the term "plurality" appears, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0060] In this application, unless otherwise specified or limited, the terms "mounted," "connected," "connected," "fixed," etc., should be interpreted broadly. For example, these terms may refer to fixed connections, removable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; and internal communication between two components or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0061] In this application, unless otherwise expressly specified or limited, if a first feature is described as being "above" or "below" a second feature, or similar descriptions, this may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is described as being "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is described as being "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0062] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only embodiment.

[0063] Figure 1 A schematic structural diagram of a back-contact battery in one embodiment of the present application is shown.

[0064] See also Figure 1 An embodiment of the present application provides a back-contact battery, including a substrate 100, a first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220, a second doped semiconductor layer 320, a first electrode 810 and a second electrode 820.

[0065] Along the thickness direction of the substrate 100, the substrate 100 has a front side 101 and a back side 102, which are arranged opposite to each other. The back side 102 includes a first region 1021 and a second region 1022, which are arranged alternately. The first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220, and the second doped semiconductor layer 320 are stacked on the first region 1021 of the back side 102, away from the substrate 100. The first doped semiconductor layer 310 and the second doped semiconductor layer 320 have the same conductivity type, which is opposite to the conductivity type of the substrate 100. The first electrode 810 is electrically connected to the second doped semiconductor layer 320, and the second electrode 820 is provided in the second region 1022 and is electrically connected to the substrate 100.

[0066] The substrate 100 is used to receive incident light and generate photogenerated carriers.

[0067] Alternatively, the substrate 100 may have a conductivity type of either P-type or N-type, and the first doped semiconductor layer 310 and the second doped semiconductor layer 320 may have a conductivity type of the other of P-type and N-type. For example, the substrate 100 may have an N-type conductivity, and the first doped semiconductor layer 310 and the second doped semiconductor layer 320 may have a P-type conductivity.

[0068] Alternatively, the front surface 101 of the substrate 100 may be configured as a pyramid-shaped suede surface, so that the reflectivity of the front surface 101 of the substrate 100 to incident light is low, thereby increasing the light absorption and utilization rate. Alternatively, the front surface 101 of the substrate 100 may be configured as a non-pyramid-shaped suede surface, such as a stacked step morphology. This is not specifically limited here.

[0069] Alternatively, at least a portion of the back surface 102 of the substrate 100 may be provided as a pyramid-shaped suede surface. Alternatively, the back surface 102 of the substrate 100 may be provided as a non-pyramid-shaped suede surface. This is not particularly limited.

[0070] The materials of the first tunneling layer 210 and the second tunneling layer 220 may be dielectric materials, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or magnesium fluoride.

[0071] The material of the first doped semiconductor layer 310 and the second doped semiconductor layer 320 may be at least one of amorphous silicon, silicon carbide, microcrystalline silicon, or polycrystalline silicon.

[0072] The materials of the first electrode 810 and the second electrode 820 may be silver, copper, nickel or aluminum.

[0073] In the technical solution of the present application, a first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220 and a second doped semiconductor layer 320 are stacked on the first region 1021 of the back side 102 of the substrate 100. On the one hand, compared with a thicker tunneling layer, in the present application, the thickness of the first tunneling layer 210 or the second tunneling layer 220 in the two tunneling layers can be designed to be thinner, so that the first tunneling layer 210 and the second tunneling layer 220 can play an anti-tunneling role together and play a passivation role at the same time, thereby enhancing the passivation performance and carrier transport of the back contact battery, thereby improving the electrical performance of the back contact battery such as open circuit voltage and fill factor; on the other hand, compared with a thicker doped semiconductor layer, two layers can be designed in the present application. A thinner doped semiconductor layer is beneficial to increasing the doping concentration of the first doped semiconductor layer 310 and the second doped semiconductor layer 320, thereby helping to improve the electrical performance of the back contact battery; in addition, the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220 and the second doped semiconductor layer 320 are stacked on the first region 1021 of the back side 102 of the substrate 100, and a height difference can be formed between the first electrode 810 and the second electrode 820, and the first electrode 810 and the second electrode 820 can be electrically isolated by the first tunneling layer 210, eliminating the need to separate the first region 1021 and the second region 1022 through an additional grooving process, and can also reduce the probability of short circuit, thereby improving the manufacturing efficiency and reliability of the back contact battery.

[0074] It should be noted that the second electrode 820 is in contact with the substrate 100, that is, the second electrode 820 is directly electrically connected to the substrate 100, and no conductive layer is provided between the second electrode 820 and the substrate 100. This eliminates the need for forming an additional conductive layer of a conductivity type opposite to that of the first doped semiconductor layer 310, and also eliminates the need for removing the portion of the conductive layer on the first region 1021. This eliminates the need for the high-temperature doping process and masking process associated with the conductive layer, thereby improving the reliability and manufacturing efficiency of back-contact cells. This also facilitates the subsequent formation of a suede structure on the second region 1022 of the back surface 102, thereby increasing the light absorption efficiency of the back surface 102 of the substrate 100 and improving the contact effect of the electrode slurry to a certain extent, thereby enabling the second electrode 820 to form a better ohmic contact.

[0075] In some embodiments, the second region 1022 of the back surface 102 has a first textured structure including a plurality of first pyramid structures 103 .

[0076] Thus, by utilizing the plurality of first pyramid structures 103, the second region 1022 of the back surface 102 of the substrate 100 can have a lower reflectivity to incident light, thereby maximizing the light absorption efficiency. Furthermore, the suede structure can also improve the contact effect of the electrode paste to a certain extent, thereby enabling the second electrode 820 to form a better ohmic contact.

[0077] In some embodiments, the height of the first pyramid structure 103 along the direction from the front surface 101 to the back surface 102 is 2 μm-5 μm, and the size of the first pyramid structure 103 along the direction perpendicular to the front surface 101 and toward the back surface 102 is 1 μm-5 μm.

[0078] For example, the height of the first pyramid structure 103 is 2 μm, 3 μm, 4 μm or 5 μm along the direction from the front surface 101 to the back surface 102. The size of the first pyramid structure 103 is 1 μm, 2 μm, 3 μm, 4 μm or 5 μm along the direction perpendicular to the front surface 101 and toward the back surface 102.

[0079] Setting the height of the first pyramid structure 103 within an appropriate range and the size of the first pyramid structure 103 in a direction perpendicular to the front surface 101 and pointing toward the back surface 102 within an appropriate range is beneficial to improving the absorption and utilization rate of light in the second area 1022 of the back surface 102 of the substrate 100, and also enables the second electrode 820 to form a better ohmic contact.

[0080] In some embodiments, the front surface 101 has a second textured structure including a plurality of second pyramid structures 104 .

[0081] In this way, by utilizing the plurality of second pyramid structures 104 , the reflectivity of the front surface 101 of the substrate 100 to the incident light can be reduced, thereby increasing the light absorption efficiency.

[0082] In some embodiments, the height of the second pyramid structure 104 along the direction from the front surface 101 to the back surface 102 is 1 μm-3 μm, and the size of the second pyramid structure 104 along the direction perpendicular to the front surface 101 and toward the back surface 102 is 1 μm-5 μm.

[0083] For example, the height of the second pyramid structure 104 is 1 μm, 2 μm or 3 μm along the direction from the front surface 101 to the back surface 102 , and the size of the second pyramid structure 104 is 1 μm, 2 μm, 3 μm, 4 μm or 5 μm along the direction perpendicular to the front surface 101 and toward the back surface 102 .

[0084] Setting the height of the second pyramid structure 104 within an appropriate range and the size of the second pyramid structure 104 in a direction perpendicular to the front surface 101 and pointing toward the back surface 102 within an appropriate range is beneficial to improving the light absorption utilization rate of the front surface 101 of the substrate 100.

[0085] In some embodiments, the second doped semiconductor layer 320 has a sheet resistance of 100Ω / □ to 300Ω / □.

[0086] For example, the sheet resistance of the second doped semiconductor layer 320 is 100Ω / □, 200Ω / □, or 300Ω / □.

[0087] In some embodiments, the sheet resistance of the first doped semiconductor layer 310 is 100Ω / □-300Ω / □.

[0088] For example, the sheet resistance of the first doped semiconductor layer 310 is 100Ω / □, 200Ω / □, or 300Ω / □.

[0089] The square resistance of the doped region is related to the doping concentration. The greater the doping concentration, the smaller the square resistance, and the smaller the doping concentration, the larger the square resistance. If the square resistance of the first doped semiconductor layer 310 is too large or the square resistance of the second doped semiconductor layer 320 is too large, then the doping concentration of the second doped semiconductor layer 320 is too small or the doping concentration of the second doped semiconductor layer 320 is too small, which will lead to greater overall recombination of the back contact battery and a lower open circuit voltage of the back contact battery; if the square resistance of the first doped semiconductor layer 310 is too small or the square resistance of the second doped semiconductor layer 320 is too small, then the recombination generated by the first doped semiconductor layer 310 or the second doped semiconductor layer 320 is greater, resulting in greater recombination of the back contact battery and a lower open circuit voltage of the back contact battery. Therefore, the square resistance of the first doped semiconductor layer 310 and the square resistance of the second doped semiconductor layer 320 both need to be selected within a suitable range. For example, when the square resistance of the first doped semiconductor layer 310 is 100Ω / □-300Ω / □ and the square resistance of the second doped semiconductor layer 320 is 100Ω / □-300Ω / □, the overall recombination of the back contact battery can be effectively reduced, thereby increasing the open circuit voltage of the back contact battery and further improving the performance of the back contact battery.

[0090] In some embodiments, the thickness of the first doped semiconductor layer 310 is 20 nm-100 nm.

[0091] In some embodiments, the second doped semiconductor layer 320 has a thickness of 100 nm-250 nm.

[0092] The thickness of the first doped semiconductor layer 310 is set within an appropriate range, and the thickness of the second doped semiconductor layer 320 is set within an appropriate range, for example, the thickness of the first doped semiconductor layer 310 is 20nm-100nm, and the thickness of the second doped semiconductor layer 320 is 100nm-250nm, which is conducive to the corresponding doping elements being incorporated into the first doped semiconductor layer 310 and the second doped semiconductor layer 320, and is conducive to increasing the doping concentration of the first doped semiconductor layer 310 and the second doped semiconductor layer 320, and further conducive to improving the electrical performance of the back contact battery.

[0093] In some embodiments, the thickness of the first tunneling layer 210 is 1 nm-4 nm.

[0094] In some embodiments, the second tunneling layer 220 has a thickness of 1 nm-4 nm.

[0095] The thickness of the first tunneling layer 210 is set within an appropriate range, and the thickness of the second tunneling layer 220 is set within an appropriate range, for example, the thickness of the first tunneling layer 210 is 1nm-4nm, and the thickness of the second tunneling layer 220 is 1nm-4nm, so that the first tunneling layer 210 and the second tunneling layer 220 can jointly play an anti-tunneling role and a passivation role at the same time, thereby enhancing the passivation performance and carrier transport of the back contact battery, thereby improving the electrical performance of the back contact battery such as open circuit voltage and fill factor.

[0096] In some embodiments, the first region 1021 is flatter than the second region 1022 .

[0097] In some embodiments, the second area 1022 of the back side 102 has a first velvet structure, the first velvet structure includes multiple first pyramid structures 103, and the first area 1021 of the back side 102 has a polishing structure, the polishing structure includes multiple tower base structures (not shown in the figure), and the height of the first pyramid structure 103 is greater than the height of the tower base structure along the direction from the front side 101 to the back side 102.

[0098] For example, the height of the tower base structure is less than or equal to one quarter of the height of the first pyramid structure 103 .

[0099] It can be understood that compared to the first velvet structure including the plurality of first pyramid structures 103, the polished structure is smoother. Thus, the first tunneling layer 210 located in the first region 1021 of the back surface 102 of the substrate 100 can have a higher density and uniformity, so that the first tunneling layer 210 has a good passivation effect on the back surface 102 of the substrate 100. Furthermore, the first pyramid structures 103 can also reduce the reflectivity of the second region 1022 of the back surface 102 of the substrate 100 to incident light, thereby increasing the light absorption and utilization rate.

[0100] In some embodiments, the area of ​​the first region 1021 is S1, and the area of ​​the second region 1022 is S2, wherein S1 and S2 have the same unit, and S2 satisfies the following condition: S2 / (S1+S2)=a, where a is 30%-70%.

[0101] Setting a to 30%-70% can make the back contact battery have lower reflectivity, reduce current loss, improve bifaciality, and balance the negative effects such as passivation loss and PN junction area loss caused by the suede structure.

[0102] Please refer to Figure 2-Figure 7 , an embodiment of the present application provides a method for preparing a back-contact battery, comprising:

[0103] S10 , providing a substrate 100 , wherein the substrate 100 has a front surface 101 and a back surface 102 disposed opposite to each other along a thickness direction of the substrate 100 , and the back surface 102 includes first regions 1021 and second regions 1022 disposed alternately.

[0104] S20: Forming a stacked first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220, and a second doped semiconductor layer 320 on the first region 1021 of the back surface 102 of the substrate 100 in a direction away from the substrate 100. The first doped semiconductor layer 310 and the second doped semiconductor layer 320 have the same conductivity type, which is opposite to the conductivity type of the substrate 100.

[0105] Optionally, step S20 of forming a stacked first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220, and a second doped semiconductor layer 320 on the first region 1021 of the back side 102 of the substrate 100 in a direction away from the substrate 100 specifically includes:

[0106] S21 , forming a first initial tunneling layer 211 , a first initial semiconductor layer 311 , a second initial tunneling layer 221 , and a second initial semiconductor layer 321 in a stacked manner on the first region 1021 of the back surface 102 of the substrate 100 in a direction away from the substrate 100 .

[0107] S22, such as Figure 2 As shown, a doping source layer 400 is formed on a side of the second preliminary semiconductor layer 321 away from the second preliminary tunneling layer 221 .

[0108] The doping source layer 400 may include a P-type or N-type doping element. For example, the doping source layer 400 includes a P-type doping element.

[0109] S23 , diffusing the doping elements in the doping source layer 400 into the first initial semiconductor layer 311 and the second initial semiconductor layer 321 , so that the first initial semiconductor layer 311 is transformed into the first initial doped semiconductor layer 312 , and the second initial semiconductor layer 321 is transformed into the second initial doped semiconductor layer 322 .

[0110] It should be noted that due to process reasons, some doping elements diffuse into the substrate 100 , but this does not affect the conductivity type of the substrate 100 .

[0111] S24, such as Figure 4 As shown, the doping source layer 400 is patterned with a laser using a first preset pattern to remove the portion of the doping source layer 400 corresponding to the second region 1022 , ie, the portion of the doping source layer 400 corresponding to the first region 1021 is retained.

[0112] S25, such as Figure 5 As shown, the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221 and the second initial doped semiconductor layer 322 corresponding to the second region 1022 are removed to form a stacked first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220 and a second doped semiconductor layer 320 on the first region 1021 of the back side 102 of the substrate 100.

[0113] S26 , removing the doping source layer 400 .

[0114] In the present application, laser grooving technology is used to remove the portion of the doping source layer 400 corresponding to the second region 1022, and the portion of the doping source layer 400 corresponding to the first region 1021 can be used to protect the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220 and the second doped semiconductor layer 320 stacked in layers, thereby abandoning the complicated mask process and achieving a better film opening effect.

[0115] S30, such as Figure 1 As shown, a first electrode 810 electrically connected to the second doped semiconductor layer 320 and a second electrode 820 disposed in the second region 1022 and electrically connected to the substrate 100 are formed.

[0116] In some embodiments, in step S24, laser processing is performed to pattern the doping source layer 400 in a first predetermined pattern to remove the portion of the doping source layer 400 corresponding to the second region 1022. The process parameters of the laser processing include: a laser wavelength of 300 nm to 1000 nm; an energy density of 103 W / cm 2 -106W / cm 2 , the laser line width is 80μm-1500μm.

[0117] For example, the wavelength of the laser is 300 nm, 500 nm, 700 nm, 900 nm or 1000 nm, and the energy density of the laser is 103 W / cm 2 、104W / cm 2 , 105W / cm 2 or 106W / cm 2 , the laser line width is 80μm, 100μm, 200μm, 400μm, 600μm, 1000μm, 1200μm, 1400μm or 1500μm.

[0118] The process parameters of the laser treatment are set to include: the wavelength of the laser is 300nm-1000nm; the energy density of the laser is 103W / cm 2 -106W / cm 2 , the laser line width is 80μm-1500μm, which is conducive to improving the accuracy of laser grooving technology and thus achieving better film opening effect.

[0119] In some embodiments, step S25 of removing the portions of the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221, and the second initial doped semiconductor layer 322 corresponding to the second region 1022 specifically includes: using a first etchant to remove the portions of the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221, and the second initial doped semiconductor layer 322 corresponding to the second region 1022. The first etchant includes an alkali and a polishing additive; the volume of the alkali in the first etchant is 20 L to 40 L, the volume of the polishing additive in the first etchant is 2 L to 5 L, the temperature of the first etchant is 60° C. to 80° C., and the processing time of the first etchant is 100 s to 300 s.

[0120] For example, the volume of the alkali in the first etching solution is 20L, 30L or 40L, the volume of the polishing additive in the first etching solution is 2L, 3L, 4L or 5L, the temperature of the first etching solution is 60°C, 70°C or 80°C, and the processing time of the first etching solution is 100s, 200s or 300s.

[0121] Laser grooving technology combined with wet etching technology is used to remove the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221 and the second initial doped semiconductor layer 322 corresponding to the second region 1022, thereby abandoning the complicated mask process, thereby improving the manufacturing efficiency of the back contact battery preparation method and achieving a better film opening effect.

[0122] In some embodiments, as Figure 3As shown, before step S24 of patterning the doping source layer 400 with a first preset pattern using a laser to remove the portion of the doping source layer 400 corresponding to the second region 1022, the method for preparing a back-contact battery also includes: forming a protective layer 500 on the side of the doping source layer 400 away from the second initial doped semiconductor layer 322.

[0123] The step S24 of patterning the doping source layer 400 with a first preset pattern using a laser to remove the portion of the doping source layer 400 corresponding to the second region 1022 specifically includes: patterning the doping source layer 400 and the protective layer 500 with a first preset pattern using a laser to remove the portion of the doping source layer 400 corresponding to the second region 1022 and the portion of the protective layer 500 corresponding to the second region 1022 (such as Figure 4 shown).

[0124] The portion of the doping source layer 400 corresponding to the first region 1021 and the portion of the protective layer 500 corresponding to the first region 1021 can be used to protect the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220 and the second doped semiconductor layer 320 stacked in layers, thereby abandoning the complicated mask process, improving the manufacturing efficiency of the back-contact battery preparation method, and achieving a better film opening effect.

[0125] It should be noted that, before step S26 of removing the doping source layer 400 , the method for preparing the back contact battery further includes: removing the protective layer 500 .

[0126] In some embodiments, before step S30 of forming the first electrode 810 electrically connected to the second doped semiconductor layer 320 and the second electrode 820 provided on the second region 1022 and electrically connected to the substrate 100, after step S20 of forming the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220, and the second doped semiconductor layer 320 stacked on the first region 1021 of the back side 102 of the substrate 100 in a direction away from the substrate 100, the method for preparing a back contact cell further includes:

[0127] like Figure 6 As shown, the second area 1022 and the front surface 101 are subjected to a velvet treatment to form a first velvet structure on the second area 1022 and a second velvet structure on the front surface 101; wherein the first velvet structure includes a plurality of first pyramid structures 103, and the second velvet structure includes a plurality of second pyramid structures 104.

[0128] Optionally, the texturing treatment of the second area 1022 and the front surface 101 specifically includes: using a second etching solution to perform texturing treatment on the second area 1022 and the front surface 101, wherein the second etching solution includes alkali and additives, the volume of the alkali of the second etching solution is 20L-40L, the volume of the additive of the second etching solution is 2L-5L, the temperature of the second etching solution is 60℃-80℃, and the processing time of the second etching solution is 300s-800s.

[0129] For example, the volume of the alkali in the second etching solution is 20L, 30L or 40L, the volume of the additive in the second etching solution is 2L, 3L, 4L or 5L, the temperature of the second etching solution is 60°C, 70°C or 80°C, and the processing time of the second etching solution is 300s, 400s, 500s, 600s, 700s or 800s.

[0130] In this way, the height of the first pyramid structure 103 along the direction pointing from the front face 101 to the back face 102 can be 2 μm-5 μm, and the height of the second pyramid structure 104 can be 1 μm-3 μm. The size of the first pyramid structure 103 and the second pyramid structure 104 along the direction perpendicular to the front face 101 pointing to the back face 102 can also be 1 μm-5 μm, so that the reflectivity of the second region 1022 can reach 8%-10%.

[0131] like Figure 7 As shown, in a direction away from the substrate 100, a first passivation layer 610 and a first anti-reflection layer 710 are stacked on the side of the second doped semiconductor layer 320 away from the second tunneling layer 220 and on the first velvet structure, and a second passivation layer 620 and a second anti-reflection layer 720 are stacked on the second velvet structure.

[0132] The first anti-reflection layer 710 and the second anti-reflection layer 720 can be formed by physical vapor deposition or plasma enhanced chemical vapor deposition (PECVD). The material of the first anti-reflection layer 710 and the second anti-reflection layer 720 can be silicon nitride (SiN x ), silicon oxynitride (SiON x ) and silicon oxide (SiO x ) layer, the first anti-reflection layer 710 and the second anti-reflection layer 720 can be used to improve the light absorption efficiency of the substrate 100, enhance the light utilization rate, and help to improve the short-circuit current of the back contact battery, thereby improving the photoelectric conversion efficiency of the back contact battery, and also help to improve the isolation effect between the back contact battery and the outside world.

[0133] The first passivation layer 610 may be formed on the side of the second doped semiconductor layer 320 facing away from the second tunneling layer 220 and on the first texture structure by atomic layer deposition, or the second passivation layer 620 may be formed on the second texture structure by atomic layer deposition.

[0134] The material of the first passivation layer 610 and the second passivation layer 620 can be aluminum oxide (AlO x ).

[0135] By using the first passivation layer 610 and the second passivation layer 620 , the passivation performance of the back contact cell can be improved.

[0136] In some embodiments, please refer to Figures 8-11 , the preparation method of the back contact battery comprises:

[0137] S110 , providing a substrate 100 , where the substrate 100 is an N-type silicon substrate.

[0138] S120 , performing double-side polishing on the substrate 100 , and using an existing polishing liquid (a combination of alkali and additives) to perform double-side polishing on the substrate 100 .

[0139] S210 , forming a first initial tunneling layer 211 , a first initial semiconductor layer 311 , a second initial tunneling layer 221 , and a second initial semiconductor layer 321 in a stacked manner on the substrate 100 in a direction away from the substrate 100 .

[0140] S220, such as Figure 8 As shown, a doping source layer 400 is formed on a side of the second preliminary semiconductor layer 321 away from the second preliminary tunneling layer 221. The doping source layer 400 may be a borosilicate glass layer.

[0141] S230 , diffusing the doping elements in the doping source layer 400 into the first initial semiconductor layer 311 and the second initial semiconductor layer 321 , so that the first initial semiconductor layer 311 is transformed into the first initial doped semiconductor layer 312 , and the second initial semiconductor layer 321 is transformed into the second initial doped semiconductor layer 322 .

[0142] S240, such as Figure 9 As shown, a protective layer 500 is formed on a side of the doping source layer 400 away from the second initially doped semiconductor layer 322. Alternatively, a tubular or chain oxidation process may be used to form the protective layer 500 on a side of the doping source layer 400 away from the second initially doped semiconductor layer 322. The protective layer 500 may have a thickness of 100 nm to 200 nm and may be made of silicon oxide.

[0143] S250, such as Figure 10 As shown, the doping source layer 400 and the protective layer 500 are patterned with a laser using a first preset pattern to remove a portion of the doping source layer 400 corresponding to the second region 1022 and a portion of the protective layer 500 corresponding to the second region 1022 .

[0144] S260 , using hydrofluoric acid (HF) to remove the doping source layer 400 and the protective layer 500 extending around the front surface 101 and the side surface 105 . The side surface 105 refers to the surface of the substrate 100 that connects the front surface 101 and the back surface 102 .

[0145] S270, such as Figure 11 As shown, a first etching solution is used to remove the first initial tunneling layer 211, the first initial doped semiconductor layer 312, the second initial tunneling layer 221 and the second initial doped semiconductor layer 322 corresponding to the second region 1022 to form a stacked first tunneling layer 210, a first doped semiconductor layer 310, a second tunneling layer 220 and a second doped semiconductor layer 320 on the first region 1021 of the back side 102 of the substrate 100.

[0146] S310, using a second etching solution to perform texturing treatment on the second area 1022 and the front surface 101 to form a first texturing structure on the second area 1022 and a second texturing structure on the front surface 101; wherein the first texturing structure includes a plurality of first pyramid structures 103, and the second texturing structure includes a plurality of second pyramid structures 104.

[0147] S320: Using hydrofluoric acid (HF) to remove the doping source layer 400 and the protective layer 500. In this process, the hydrofluoric acid (HF) will not remove the substrate 100 and the first tunneling layer 210, the first doped semiconductor layer 310, the second tunneling layer 220, and the second doped semiconductor layer 320 stacked on the substrate 100.

[0148] S330. Along the direction away from the substrate 100, a first passivation layer 610 and a first anti-reflection layer 710 are formed in a stacked manner on the side of the second doped semiconductor layer 320 facing away from the second tunneling layer 220 and on the first velvet structure, and a second passivation layer 620 and a second anti-reflection layer 720 are formed in a stacked manner on the second velvet structure.

[0149] S400 , forming a first electrode 810 electrically connected to the second doped semiconductor layer 320 , and a second electrode 820 disposed in the second region 1022 and electrically connected to the substrate 100 .

[0150] The first electrode 810 and the second electrode 820 may be formed by screen printing, and then sintered at a high temperature of 700° C. to 800° C. to form a good ohmic contact.

[0151] The back contact cell of the present application is compatible with the advantages of Topcon and BC cells. At the same time, the second area 1022 of the back side 102 and the front side 101 are designed as a velvet structure, which can reduce the reflectivity of the back side 102, thereby improving the double-sidedness of the back contact cell. The velvet structure is more conducive to the contact of the metal paste than the polished structure, and can enable the second electrode 820 to form a better ohmic contact, thereby improving the contact and increasing the fill factor.

[0152] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A back contact battery, characterized in that: include: A substrate, wherein along a thickness direction of the substrate, the substrate has a front surface and a back surface disposed opposite to each other, the back surface including first regions and second regions disposed alternately; A first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer are stacked on the first region of the back surface in a direction away from the substrate; wherein the first doped semiconductor layer and the second doped semiconductor layer have the same conductivity type and are opposite to the conductivity type of the substrate; a first electrode electrically connected to the second doped semiconductor layer; and The second electrode is disposed in the second region and electrically connected to the substrate; a height difference is formed between the first electrode and the second electrode.

2. The back contact battery according to claim 1, characterized in that The second area of ​​the back surface has a first velvet structure, and the first velvet structure includes a plurality of first pyramid structures; Along the direction from the front surface to the back surface, the height of the first pyramid structure is 2 μm-5 μm; Along a direction perpendicular to the front surface and pointing toward the back surface, a size of the first pyramid structure is 1 μm-5 μm.

3. The back contact battery according to claim 1, characterized in that The front surface has a second velvet structure, and the second velvet structure includes a plurality of second pyramid structures; Along the direction from the front surface to the back surface, the height of the second pyramid structure is 1 μm-3 μm; Along a direction perpendicular to the front surface and pointing toward the back surface, a size of the second pyramid structure is 1 μm-5 μm.

4. The back contact battery according to claim 1, characterized in that The sheet resistance of the second doped semiconductor layer is 100Ω / □-300Ω / □; and / or The sheet resistance of the first doped semiconductor layer is 100Ω / □-300Ω / □; and / or The thickness of the first doped semiconductor layer is 20 nm-100 nm; and / or The thickness of the second doped semiconductor layer is 100 nm-250 nm; and / or The thickness of the first tunneling layer is 1 nm to 4 nm; and / or The thickness of the second tunneling layer is 1 nm-4 nm.

5. The back contact battery according to claim 1, characterized in that The first region is flatter than the second region; and / or The second area of ​​the back surface has a first velvet structure, the first velvet structure includes a plurality of first pyramid structures; the first area of ​​the back surface has a polished structure, the polished structure includes a plurality of tower base structures, and the height of the first pyramid structure is greater than the height of the tower base structure in a direction from the front surface to the back surface; and / or The area of ​​the first region is S1, and the area of ​​the second region is S2, wherein S1 and S2 have the same unit, and S2 satisfies the following condition: S2 / (S1+S2)=a, where a is 30%-70%.

6. A method for preparing a back contact battery, characterized in that: include: Providing a substrate, wherein along a thickness direction of the substrate, the substrate has a front surface and a back surface disposed opposite to each other, the back surface including first regions and second regions disposed alternately; forming a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer in a stacked manner on the first region of the back side of the substrate in a direction away from the substrate; wherein the first doped semiconductor layer and the second doped semiconductor layer have the same conductivity type and are opposite to the conductivity type of the substrate; forming a first electrode electrically connected to the second doped semiconductor layer, and a second electrode disposed on the second region and electrically connected to the substrate; Wherein, a height difference is formed between the first electrode and the second electrode.

7. The method for preparing a back contact battery according to claim 6, characterized in that: The step of forming a stacked first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer on the first region of the back side of the substrate in a direction away from the substrate specifically includes: forming a first initial tunneling layer, a first initial semiconductor layer, a second initial tunneling layer, and a second initial semiconductor layer stacked on the first region of the back side of the substrate in a direction away from the substrate; forming a doping source layer on a side of the second initial semiconductor layer away from the second initial tunneling layer; diffusing the doping element in the doping source layer into the first initial semiconductor layer and the second initial semiconductor layer, so that the first initial semiconductor layer is transformed into a first initial doped semiconductor layer, and the second initial semiconductor layer is transformed into a second initial doped semiconductor layer; patterning the doping source layer using a laser in a first preset pattern to remove a portion of the doping source layer corresponding to the second region; removing the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer, and a portion of the second initial doped semiconductor layer corresponding to the second region to form a first tunneling layer, a first doped semiconductor layer, a second tunneling layer, and a second doped semiconductor layer stacked on the first region of the back side of the substrate; The doping source layer is removed.

8. The method for preparing a back contact battery according to claim 7, characterized in that: In the step of patterning the doping source layer with a laser in a first preset pattern to remove the portion of the doping source layer corresponding to the second region, the process parameters of the laser treatment include: a laser wavelength of 300nm-1000nm; a laser energy density of 103W / cm 2 -106W / cm 2 , laser line width is 80μm-1500μm; and / or The removing of the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer and the portion of the second initial doped semiconductor layer corresponding to the second region specifically includes: using a first etching solution to remove the first initial tunneling layer, the first initial doped semiconductor layer, the second initial tunneling layer and the portion of the second initial doped semiconductor layer corresponding to the second region; wherein the first etching solution includes an alkali and a polishing additive; the volume of the alkali is 20L-40L, and the volume of the polishing additive is 2L-5L; the temperature of the first etching solution is 60°C-80°C; and the processing time of the first etching solution is 100s-300s.

9. The method for preparing a back contact battery according to claim 7, wherein: Before patterning the doping source layer with a first preset pattern using a laser to remove the portion of the doping source layer corresponding to the second region, the method further includes: forming a protective layer on a side of the doping source layer away from the second initial doped semiconductor layer; The method of patterning the doping source layer with a first preset pattern using a laser to remove a portion of the doping source layer corresponding to the second region specifically includes: patterning the doping source layer and the protective layer with a first preset pattern using a laser to remove a portion of the doping source layer corresponding to the second region, and a portion of the protective layer corresponding to the second region.

10. The method for preparing a back contact battery according to claim 6, characterized in that: Before forming the first electrode electrically connected to the second doped semiconductor layer and the second electrode provided on the second region and electrically connected to the substrate, after forming the first tunneling layer, the first doped semiconductor layer, the second tunneling layer, and the second doped semiconductor layer stacked on the first region on the back side of the substrate in a direction away from the substrate, the method further comprises: Performing a texturing process on the second region and the front surface to form a first velvet structure on the second region and a second velvet structure on the front surface; wherein the first velvet structure includes a plurality of first pyramid structures; and the second velvet structure includes a plurality of second pyramid structures; Along the direction away from the substrate, a first passivation layer and a first anti-reflection layer are stacked on the side of the second doped semiconductor layer facing away from the second tunneling layer and on the first velvet structure, and a second passivation layer and a second anti-reflection layer are stacked on the second velvet structure.

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