Passivation structure, preparation method of passivation structure and solar cell

Abstract

The invention relates to a passivation structure, a preparation method of the passivation structure and a solar cell, and the passivation structure is suitable for the back surface of a silicon substrate with a first conduction type, and comprises a tunneling silicon oxide layer and a first doped crystalline silicon layer which are arranged on the whole back surface of the silicon substrate; a first intermediate layer and a second doped crystalline silicon layer are sequentially stacked in a metal contact area of the first doped crystalline silicon layer, a non-metal contact area of the first doped crystalline silicon layer is provided with a light trapping structure, or / and a second intermediate layer and a third doped crystalline silicon layer are sequentially stacked in the non-metal contact area, a light trapping structure is arranged on the surface of the third doped crystalline silicon layer, and a light trapping structure is arranged on the surface of the third doped crystalline silicon layer. And the thickness of the third doped crystal silicon layer is smaller than that of the second doped crystal silicon layer. According to the invention, the optical performance of the solar cell passivation structure and the electrical performance of the photovoltaic cell with the passivation structure are improved.

Description

Technical Field

[0001] The present invention belongs to the field of solar cells, and in particular relates to a passivation structure, a method for preparing the passivation structure, and a solar cell. Background Art

[0002] At present, in order to further improve the efficiency of TOPCon cells, a double-layer tunneling polysilicon passivation structure has been introduced on the back of the TOPCon cell. That is, a thin silicon oxide layer is added as a barrier layer inside the original single-layer polysilicon, thereby separating the original single-layer doped polysilicon into a double layer. By adding the silicon oxide barrier layer, on the one hand, the phosphorus diffusion space can be effectively controlled, the doping concentration near the interface between the silicon substrate and the tunneling silicon oxide layer can be reduced, and the passivation quality can be improved. On the other hand, the high phosphorus doping concentration in the polysilicon layer can be guaranteed, and the passivation and contact effects required for the high phosphorus doping concentration are maintained, thereby improving the fill factor of the TOPCon cell.

[0003] However, the narrow band gap and high absorption coefficient of polysilicon cause it to absorb long-wavelength light. These photons cannot be effectively converted into electron-hole pairs, resulting in current loss and serious light loss. As a result, the parasitic absorption of light by polysilicon has become one of the key bottlenecks restricting efficiency improvement. Summary of the Invention

[0004] The purpose of the present invention is to further reduce the light loss of the TOCon cell and improve the photoelectric conversion efficiency of the cell.

[0005] To achieve the above objectives, a first aspect of the present invention provides a passivation structure, which is applicable to the back side of a silicon substrate having a first conductivity type, and includes a tunneling silicon oxide layer and a first doped crystalline silicon layer disposed on the entire back side of the silicon substrate; a surface of the first doped crystalline silicon layer remote from the tunneling silicon oxide layer includes a non-metallic contact region and a metal contact region, wherein the non-metallic contact region is adjacent to the metal contact region and is spaced apart from the metal contact region; The metal contact region is sequentially stacked with a first intermediate layer and a second doped crystalline silicon layer; The non-metallic contact area has a light trapping structure, or / and the non-metallic contact area is sequentially stacked with a second intermediate layer and a third doped crystalline silicon layer, the first doped crystalline silicon layer, the second doped crystalline silicon layer and the third doped crystalline silicon layer have the same conductivity type, the surface of the third doped crystalline silicon layer has a light trapping structure, and the thickness of the third doped crystalline silicon layer is less than the thickness of the second doped crystalline silicon layer.

[0006] Optionally, the thickness of the first intermediate layer and the second intermediate layer are each independently 0.5-3 nm; and / or, the materials of the first intermediate layer and the second intermediate layer are each independently selected from one or more of aluminum oxide, silicon oxide and a transparent conductive layer.

[0007] Optionally, the back surface of the silicon substrate is a smooth surface; and the thickness of the tunneling silicon oxide layer is 0.5-2 nm.

[0008] Optionally, the first doped crystalline silicon layer includes a first doping element; the thickness of the first doped crystalline silicon layer is 20-80 nm, and the doping concentration is 1×10 18 -1×10 20 atoms / cm 3 ; The first doping element is phosphorus or boron.

[0009] Optionally, the second doped crystalline silicon layer and the third doped crystalline silicon layer include a second doping element; the doping concentration in the first doped crystalline silicon layer is less than the doping concentration in the second doped crystalline silicon layer and the third doped crystalline silicon layer; the thickness of the second doped crystalline silicon layer is 40-300 nm, and the doping concentration is 1×10 19 -1×10 21 atoms / cm 3 , and / or, the thickness of the third doped crystalline silicon layer is 0-100 nm; the doping concentration of the third doped crystalline silicon layer is 1×10 19 -1×10 21 atoms / cm 3 ; The ratio of the thickness of the third doped crystalline silicon layer to the thickness of the second doped crystalline silicon layer is (0-0.33):1; the second doping element is phosphorus or boron.

[0010] Optionally, a passivation anti-reflection layer is provided on the second doped crystalline silicon layer, and the passivation anti-reflection layer extends to the non-metallic region of the first doped crystalline silicon layer or the surface of the third doped crystalline silicon layer; the passivation anti-reflection layer is selected from a composite film layer of one or more of a silicon oxide layer, a silicon oxynitride layer and a silicon nitride layer; the thickness of the passivation anti-reflection layer is 60-100 nm.

[0011] In a second aspect, the present invention relates to a method for preparing a passivation structure, the method comprising the following steps: providing a silicon substrate having a first conductivity type; forming a tunneling silicon oxide layer and a first doped crystalline silicon layer in sequence on the back side of the silicon substrate; Depositing an intermediate layer on the surface of the first doped crystalline silicon layer; forming a second doped crystalline silicon layer and a doped silicon glass layer on the surface of the intermediate layer; wherein the second doped crystalline silicon layer and the first doped crystalline silicon layer have the same conductivity type; Patterning the doped silicon glass layer in the non-metal contact area and removing a portion of the second doped crystalline silicon layer in the patterned area, or removing the second doped crystalline silicon layer and the intermediate layer in the patterned area to obtain a patterned silicon wafer; Placing the patterned silicon wafer in an alkaline texturing solution for texturing, so as to form a light trapping structure in the non-metallic contact area on the back side; The doped silicon glass layer covering the surface of the metal contact area is removed to obtain the passivation structure.

[0012] Optionally, the back side of the silicon substrate is a smooth surface; the intermediate layer is formed by plasma-enhanced atomic layer deposition; the thickness of the intermediate layer is 0.5-3 nm; the material of the intermediate layer is selected from one or more of aluminum oxide, silicon oxide and a transparent conductive layer; optionally, the thickness of the tunneling silicon oxide layer is 0.5-2 nm; the method for forming the tunneling silicon oxide layer is selected from at least one of plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition.

[0013] Optionally, the first doped crystalline silicon layer is deposited by plasma enhanced chemical vapor deposition, comprising: depositing a silicon thin film by plasma enhanced chemical vapor deposition while introducing a gas containing a first doping element to obtain a first initial doped crystalline silicon layer; the first doping element is boron or phosphorus; the thickness of the first initial doped crystalline silicon layer is 20-80 nm; the doping concentration in the first initial doped crystalline silicon layer is 1×10 18 -1×10 20 atoms / cm 3 .

[0014] Optionally, the second doped crystalline silicon layer is deposited by plasma enhanced chemical vapor deposition, comprising: depositing a silicon thin film by plasma enhanced chemical vapor deposition while introducing a gas containing a second doping element to obtain a second initial doped crystalline silicon layer; annealing the first initial doped crystalline silicon layer and the second initial doped crystalline silicon layer to obtain the second doped crystalline silicon layer and the doped silicon glass layer; the doping concentration in the first doped crystalline silicon layer is less than the doping concentration in the second doped crystalline silicon layer; the second doping element is boron or phosphorus; the thickness of the second initial doped crystalline silicon layer is 40-300 nm; the doping concentration in the second initial doped crystalline silicon layer is 1×10 19 -1×10 21 atoms / cm 3 ; The temperature of the annealing treatment is 800-1050℃.

[0015] Optionally, the thickness of the second doped crystalline silicon layer retained in the patterned processing area is 0-100 nm.

[0016] Optionally, the method further includes: using plasma enhanced chemical vapor deposition to deposit a passivation anti-reflection layer on the surface of the passivation structure; the passivation anti-reflection layer is selected from a composite film layer of one or more of a silicon oxide layer, a silicon oxynitride layer and a silicon nitride layer; the thickness of the passivation anti-reflection layer is 60-100 nm.

[0017] In another aspect, the present invention provides a solar cell prepared by the method according to the second aspect of the present invention.

[0018] In another aspect, the present invention relates to a solar cell comprising the passivation structure described in the first aspect of the present invention; optionally, the solar cell is selected from one of a TOPCon cell and a bifacial TOPCon cell.

[0019] Through the above technical solution, the present invention optimizes the anisotropy of the passivation of the doped crystalline silicon layer by subdividing the backside of the silicon substrate into a non-metallic contact passivation region and a metal contact passivation region, and retaining the full thickness of the second doped crystalline silicon layer only in the metal contact passivation region, effectively reducing light loss. Furthermore, a textured surface is applied to the doped polysilicon layer in the non-metallic region, increasing light absorption efficiency, while the metal contact region is polished to ensure good electrical contact. Overall, this passivation structure improves both the optical performance and the electrical performance of the photovoltaic cell containing it.

[0020] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1 This is one of the structural schematic diagrams of the passivation structure in some embodiments of the present invention.

[0022] Figure 2 This is the second structural diagram of the passivation structure in some embodiments of the present invention.

[0023] Figure 3 This is the third structural diagram of the passivation structure in some embodiments of the present invention.

[0024] Description of reference numerals: 100. Silicon substrate; 101. Tunneling silicon oxide layer; 102. First doped crystalline silicon layer; 103. First intermediate layer; 104. Second doped crystalline silicon layer; 105. Second intermediate layer; 106. Third doped crystalline silicon layer; 107. Passivation anti-reflection layer. DETAILED DESCRIPTION

[0025] The following is a detailed description of the specific embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention.

[0026] A first aspect of the present invention provides a passivation structure, applicable to the back side of a silicon substrate having a first conductivity type, comprising a tunneling silicon oxide layer and a first doped crystalline silicon layer disposed on the entire back side of the silicon substrate; a surface of the first doped crystalline silicon layer remote from the tunneling silicon oxide layer comprising a non-metallic contact region and a metal contact region, the non-metallic contact region being adjacent to and spaced apart from the metal contact region; The metal contact region is sequentially stacked with a first intermediate layer and a second doped crystalline silicon layer; The non-metallic contact area has a light trapping structure, or / and the non-metallic contact area is sequentially stacked with a second intermediate layer and a third doped crystalline silicon layer, the first doped crystalline silicon layer, the second doped crystalline silicon layer and the third doped crystalline silicon layer have the same conductivity type, the surface of the third doped crystalline silicon layer has a light trapping structure, and the thickness of the third doped crystalline silicon layer is less than the thickness of the second doped crystalline silicon layer.

[0027] By subdividing the backside of the silicon substrate into a non-metallic contact passivation region and a metal contact passivation region, and retaining the full thickness of the second doped crystalline silicon layer only in the metal contact passivation region, the present invention optimizes the anisotropy of the passivation of the doped crystalline silicon layer, effectively reducing light loss. Furthermore, a textured surface is applied to the doped polysilicon layer in the non-metallic region, increasing light absorption efficiency. The metal contact region is polished to ensure good electrical contact, thereby improving the overall optical performance and electrical performance of the photovoltaic cell with this passivation structure.

[0028] Figure 1 A passivation structure of the present invention is schematically shown, referring to Figure 1 The entire back surface of silicon substrate 100 is provided with a tunneling silicon oxide layer 101 and a first doped crystalline silicon layer 102. The surface of first doped crystalline silicon layer 102, away from tunneling silicon oxide layer 101, includes a non-metallic contact region and a metal contact region. The non-metallic contact region and the metal contact region are adjacent and spaced apart. The metal contact region refers to an area suitable for forming a metal electrode.

[0029] like Figure 1As shown, in the direction away from the silicon substrate 100, the metal contact area of ​​the first doped crystalline silicon layer 102 is sequentially stacked with a first intermediate layer 103 and a second doped crystalline silicon layer 104; the non-metallic contact area has a light-trapping structure. The first doped crystalline silicon layer 102 and the second doped crystalline silicon layer 104 have the same conductivity type. The doped crystalline silicon layer outside the non-metallic area is completely removed, which can significantly reduce the parasitic absorption of light by the third doped crystalline silicon layer. At the same time, the outer surface of the third doped crystalline silicon layer is velvet, which can increase the cell's light absorption efficiency, thereby improving the cell's overall conversion efficiency.

[0030] In the present invention, light-trapping structures include, but are not limited to, pyramid structures, inverted pyramid structures, nanopillars, or nanowires. For example, in some embodiments, a pyramid light-trapping structure is formed on the surface of the non-metallic contact region of the first doped crystalline silicon layer 102. Furthermore, the textured surface of the non-metallic contact region can be a complete pyramid structure, or the pyramid top can be modified to improve the uniformity of subsequent anti-reflection film deposition and further optimize the photovoltaic conversion efficiency of the cell.

[0031] In another embodiment, Figure 2 As shown, in a direction away from the silicon substrate 100, the non-metallic contact region of the first doped crystalline silicon layer 102 is sequentially stacked with a second intermediate layer 105 and a third doped crystalline silicon layer 106. The first doped crystalline silicon layer 102, the second doped crystalline silicon layer 104, and the third doped crystalline silicon layer 106 have the same conductivity type. The surface of the third doped crystalline silicon layer 106 has a light-trapping structure, and the thickness of the third doped crystalline silicon layer 106 is less than that of the second doped crystalline silicon layer 104. Thinning the doped crystalline silicon layer outside the non-metallic contact region can further reduce parasitic absorption of light by the doped crystalline silicon layer, thereby improving the conversion efficiency of the solar cell.

[0032] In some embodiments of the passivation structure of the present invention, the second intermediate layer may or may not be provided on the non-metallic area; when the second intermediate layer is provided on the non-metallic area, the thicknesses of the first intermediate layer and the second intermediate layer may be the same or different.

[0033] In some embodiments of the passivation structure of the present invention, the thickness of the first intermediate layer and the second intermediate layer are each independently 0.5-3 nm, so as to prevent the dopant elements in the outer doped crystalline silicon layer from diffusing into the inner doped crystalline silicon layer or the inner silicon wafer, thereby increasing the overall concentration of the dopant elements in the polysilicon layer. For example, the thickness of the first intermediate layer and the second intermediate layer can be 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2.0 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3.0 nm, or any value within the foregoing ranges, or a range consisting of any two of the foregoing ranges. In order to further enhance the barrier effect of the intermediate layer and reduce the influence of the intermediate layer on the battery performance, the thickness of the first intermediate layer and the second intermediate layer are independently 1-2 nm.

[0034] In some embodiments of the passivation structure of the present invention, the materials of the first intermediate layer and the second intermediate layer are independently selected from one or more of aluminum oxide, silicon oxide, and a transparent conductive layer. The materials of the first intermediate layer and the second intermediate layer are not limited to silicon oxide, and can block the high-doping concentration elements in the second doped crystalline silicon layer and the third doped crystalline silicon layer from diffusing into the first doped crystalline silicon layer. This provides more options and can be adapted to different process and performance optimization requirements. The material of the transparent conductive layer can be a common material in the art, for example, selected from aluminum-doped zinc oxide transparent conductive film, indium tin oxide transparent conductive film, tungsten-doped indium oxide transparent conductive film, fluorine-doped tin oxide transparent conductive film, and indium hydroxide transparent conductive film.

[0035] In some embodiments of the passivation structure of the present invention, the back surface of the silicon substrate is a smooth surface to facilitate providing good electrical contact.

[0036] In some embodiments of the passivation structure of the present invention, the thickness of the tunneling silicon oxide layer is 0.5-2 nm to ensure that holes tunnel to the metal electrode, improve the interface passivation effect, and reduce recombination. For example, the thickness of the tunneling silicon oxide layer can be 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2.0 nm, or any value within the aforementioned range, or a range consisting of any two values ​​within the aforementioned range. In order to further improve the interface passivation effect and enhance the light conversion efficiency of the cell, the preferred thickness of the tunneling silicon oxide layer is 0.9-1.2 nm.

[0037] In some embodiments of the passivation structure of the present invention, the first doped crystalline silicon layer, the second doped crystalline silicon layer and the third doped crystalline silicon layer can be a composite structure of one or more layers selected from amorphous silicon layer, nanocrystalline silicon layer, microcrystalline silicon layer and polycrystalline silicon layer.

[0038] In some embodiments of the passivation structure of the present invention, the first doped crystalline silicon layer includes a first doping element; the thickness of the first doped crystalline silicon layer is 20-80 nm, and the doping concentration is 1×10 18 -1×10 20 atoms / cm 3 Specifically, the thickness of the first doped crystalline silicon layer can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, or any value within the aforementioned range, or a range consisting of any two values ​​within the aforementioned range. Specifically, the doping concentration of the first doped crystalline silicon layer can be 1×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 4×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 , 6×10 18 atoms / cm 3 , 7×10 18 atoms / cm 3 , 8×10 18 atoms / cm 3 , 9×1018 atoms / cm 3 , 1×10 19 atoms / cm 3 , 2×10 19 atoms / cm 3 , 3×10 19 atoms / cm 3 , 4×10 19 atoms / cm 3 , 5×10 19 atoms / cm 3 , 6×10 19 atoms / cm 3 , 7×10 19 atoms / cm 3 , 8×10 19 atoms / cm 3 , 9×10 19 atoms / cm 3 , 1×10 20 atoms / cm 3 , or any value within the aforementioned range, or a range consisting of any two values ​​within the aforementioned range.

[0039] In some embodiments of the passivation structure of the present invention, the first doping element is phosphorus or boron.

[0040] In some embodiments of the passivation structure of the present invention, the second doped crystalline silicon layer and the third doped crystalline silicon layer include a second doping element; the thickness of the second doped crystalline silicon layer is 40-300 nm, and the doping concentration is 1×10 19 -1×10 21 atoms / cm 3 Specifically, the thickness of the second doped crystalline silicon layer can be 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, or 300 nm, or any value within the foregoing range, or a range consisting of any two values ​​within the foregoing range. To further increase the overall doping concentration in the polysilicon and enhance the field passivation effect, the thickness of the second doped crystalline silicon layer is 40-200 nm.

[0041] Specifically, the doping concentration of the first doped crystalline silicon layer may be 1×10 19 atoms / cm 3 , 2×10 19 atoms / cm3 , 3×10 19 atoms / cm 3 , 4×10 19 atoms / cm 3 , 5×10 19 atoms / cm 3 , 6×10 19 atoms / cm 3 , 7×10 19 atoms / cm 3 , 8×10 19 atoms / cm 3 , 9×10 19 atoms / cm 3 , 1×10 20 atoms / cm 3 , 2×10 20 atoms / cm 3 , 3×10 20 atoms / cm 3 , 4×10 20 atoms / cm 3 , 5×10 20 atoms / cm 3 , 6×10 20 atoms / cm 3 , 7×10 20 atoms / cm 3 , 8×10 20 atoms / cm 3 , 9×10 20 atoms / cm 3 , 1×10 21 atoms / cm 3 , or any value within the aforementioned range, or a range consisting of any two values ​​within the aforementioned range.

[0042] In some embodiments of the passivation structure of the present invention, the thickness of the third doped crystalline silicon layer is 0-100 nm; the doping concentration of the third doped crystalline silicon layer is 1×10 19 -1×10 21 atoms / cm 3 .

[0043] In some embodiments of the passivation structure of the present invention, the ratio of the thickness of the third doped crystalline silicon layer to the thickness of the second doped crystalline silicon layer is (0-0.33):1, so as to further reduce the light loss caused by parasitic absorption of light by polysilicon.

[0044] In some embodiments of the passivation structure of the present invention, the second doping element is phosphorus or boron. Specifically, the second doping element and the first doping element are both phosphorus. In some other embodiments, the second doping element and the first doping element are both boron.

[0045] In some embodiments of the passivation structure of the present invention, the silicon substrate has a first conductivity type, which may be N-type or P-type. In some embodiments of the present invention, the doping elements in the first doped crystalline silicon layer, the second doped crystalline silicon layer, and the third doped crystalline silicon layer have the same conductivity type, preferably the first conductivity type. Alternatively, in some other embodiments, the doping elements in the first doped crystalline silicon layer, the second doped crystalline silicon layer, and the third doped crystalline silicon layer have a conductivity type opposite to the first conductivity type, denoted as the second conductivity type.

[0046] In some specific embodiments of the passivation structure of the present invention, the passivation structure is applied to the back side of an N-type silicon substrate. The metal contact region on the back side of the silicon substrate is sequentially provided with a tunneling silicon oxide layer, a first N-type doped polysilicon layer, a first intermediate layer, and a second N-type doped polysilicon layer. The non-metal contact region on the back side of the silicon substrate is sequentially provided with a tunneling silicon oxide layer and a first N-type doped polysilicon layer. The back side of the silicon substrate is a polished surface, the surface of the outer doped polysilicon layer in the non-metallic region is a velvet surface, and the interfaces between the tunneling silicon oxide layer, the first N-type doped polysilicon layer, the first intermediate layer, and the second N-type doped polysilicon layer in the metal contact region are all polished surfaces.

[0047] In some embodiments of the passivation structure of the present invention, the doping element in the first doped crystalline silicon layer, the second doped crystalline silicon layer, and the third doped crystalline silicon layer is phosphorus. Due to the barrier effect of the first intermediate layer and / or the second intermediate layer, the doping concentration in the second doped crystalline silicon layer and the third doped crystalline silicon layer can be higher than the doping concentration in the first doped crystalline silicon layer.

[0048] In some embodiments of the passivation structure of the present invention, a passivation anti-reflection layer is provided on the second doped crystalline silicon layer, and the passivation anti-reflection layer extends to the non-metallic region of the first doped crystalline silicon layer or the surface of the third doped crystalline silicon layer.

[0049] like Figure 3 As shown, in Figure 1 On the basis of the passivation structure shown, a passivation anti-reflection layer 107 is deposited on the surface of the second doped crystalline silicon layer 104 and the surface of the first doped crystalline silicon layer 102 .

[0050] In some embodiments of the passivation structure of the present invention, the passivation anti-reflection layer is selected from silicon oxide (SiO x ) layer, silicon oxynitride (SiO xN y ) layer and nitride (SiN x ) A composite film layer of one or more silicon layers.

[0051] In some embodiments of the passivation structure of the present invention, the thickness of the passivation anti-reflection layer may be 60-100 nm, so as to further improve the utilization rate of light by the cell and reduce light loss.

[0052] A second aspect of the present invention provides a method for preparing a passivation structure, the method comprising the following steps: providing a silicon substrate having a first conductivity type; forming a tunneling silicon oxide layer and a first doped crystalline silicon layer in sequence on the back side of the silicon substrate; Depositing an intermediate layer on the surface of the first doped crystalline silicon layer; forming a second doped crystalline silicon layer and a doped silicon glass layer on the surface of the intermediate layer; wherein the second doped crystalline silicon layer and the first doped crystalline silicon layer have the same conductivity type; Patterning and removing the doped silicon glass layer in the non-metal contact area, and removing a portion of the second doped crystalline silicon layer in the patterned area, or removing the second doped crystalline silicon layer and the intermediate layer in the patterned area, to obtain a patterned silicon wafer; Placing the patterned silicon wafer in an alkaline texturing solution for texturing, so as to form a light trapping structure in the non-metallic contact area on the back side; The doped silicon glass layer covering the surface of the metal contact area is removed to obtain the passivation structure.

[0053] The passivation structure fabricated using the method of the present invention optimizes the anisotropy of the passivation of the doped crystalline silicon layer, effectively reducing light loss. Furthermore, a textured surface is created on the non-metallic surface of the doped polysilicon layer, increasing light absorption efficiency. The polished surface in the metal contact area ensures good electrical contact, ultimately improving the optical performance and electrical performance of the photovoltaic cell with this passivation structure.

[0054] In some embodiments of the present invention, the back side of the silicon substrate is polished. Specifically, wet polishing can be used to polish the back side of the silicon substrate to a reflectivity range of 40%-60%. This polishing method not only ensures the surface flatness and smoothness of the back side of the silicon substrate, but also optimizes the reflective properties, laying the foundation for subsequent passivation structure and battery performance optimization. By precisely controlling the polishing parameters, the surface quality of the back side of the silicon substrate can be further improved, ensuring the smooth execution of subsequent process steps.

[0055] In some embodiments of the present invention, the intermediate layer may be formed by chemical vapor deposition, high-temperature thermal oxidation, nitric acid oxidation, or ozone oxidation.

[0056] In some preferred embodiments of the present invention, the intermediate layer is formed by plasma enhanced atomic layer deposition. In some specific embodiments, the material of the intermediate layer is selected from one or more of aluminum oxide, silicon oxide and a transparent conductive layer.

[0057] In some embodiments of the present invention, the tunneling silicon oxide layer is formed by a method selected from one or more of chemical vapor deposition, high-temperature thermal oxidation, nitric acid oxidation, and ozone oxidation.

[0058] In some preferred embodiments of the present invention, the tunneling silicon oxide layer is formed by at least one method selected from plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), and low-pressure chemical vapor deposition (LPCVD). These methods can ensure that the tunneling silicon oxide layer has excellent uniformity and density, thereby improving the passivation effect and electrical performance of the battery.

[0059] In some embodiments of the present invention, the first doped crystalline silicon layer and the second doped crystalline silicon layer may be formed using plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition. When forming the first doped crystalline silicon layer and the second doped crystalline silicon layer using plasma-enhanced chemical vapor deposition, the initially doped silicon film needs to be annealed to induce crystallization of the amorphous silicon to form conductive polycrystalline silicon, activate the first doping element, alleviate stress mismatch at the interface between the tunneling silicon oxide layer or the intermediate layer and the polycrystalline silicon layer, reduce interface defects, and ensure the overall performance and efficiency of the battery.

[0060] In some embodiments of the present invention, the first doped crystalline silicon layer may be deposited by plasma enhanced chemical vapor deposition, including: A first initial doped crystalline silicon layer is obtained by plasma enhanced chemical vapor deposition of a silicon film while introducing a gas containing a first doping element.

[0061] It is understood that the first initially doped crystalline silicon layer can be transformed into a first doped polycrystalline silicon layer after annealing. If the first doped crystalline silicon layer and the second doped crystalline silicon layer are formed by plasma-enhanced chemical vapor deposition, the first and second initially doped crystalline silicon layers can be annealed simultaneously when the second doped crystalline silicon layer is formed to form the first doped crystalline silicon layer, and the second doped crystalline silicon layer can be formed on the intermediate layer at the same time.

[0062] In some embodiments of the present invention, the first doping element is boron or phosphorus.

[0063] In some embodiments of the present invention, the thickness of the first initial doped crystalline silicon layer may be 20-80 nm; the doping concentration in the first initial doped crystalline silicon layer may be 1×10 18 -1×10 20 atoms / cm 3 .

[0064] In some embodiments of the present invention, the second doped crystalline silicon layer may be deposited by plasma enhanced chemical vapor deposition, including: A second initial doped crystalline silicon layer is obtained by depositing a silicon thin film using plasma enhanced chemical vapor deposition while introducing a gas containing a second doping element; Annealing is performed on the first initial doped crystalline silicon layer and the second initial doped crystalline silicon layer to obtain the second doped crystalline silicon layer and the doped silicon glass layer.

[0065] By precisely controlling the deposition process parameters, the second doped polysilicon layer can provide sufficient passivation effect while maintaining good electrical contact performance.

[0066] In some embodiments of the present invention, the second doping element is boron or phosphorus.

[0067] In some embodiments of the present invention, the thickness of the second initial doped crystalline silicon layer may be 40-300 nm; the doping concentration in the second initial doped crystalline silicon layer may be 1×10 19 -1×10 21 atoms / cm 3 .

[0068] In some embodiments of the present invention, the temperature of the annealing treatment can be 800-1050°C to achieve annealing treatment of the first initial doped crystalline silicon layer and the second initial doped crystalline silicon layer. For example, it can be 800°C, 820°C, 840°C, 850°C, 860°C, 880°C, 900°C, 920°C, 940°C, 950°C, 960°C, 980°C, 1000°C, 1050°C, or any value within the aforementioned range, or a range consisting of any two values ​​within the aforementioned range.

[0069] In some embodiments of the present invention, laser patterning can be used to pattern the non-metallic contact area on the back of the cell to remove the BSG (borosilicate glass) or PSG (phosphorus silicate glass) layer in that area. Laser processing can precisely remove the BSG or PSG layer from the non-metallic area, ensuring that the silicon substrate is not damaged during the removal process. It should be understood that the method for removing at least a portion of the second doped crystalline silicon layer is not limited to laser processing. For example, in other embodiments, the second doped crystalline silicon layer in the non-metallic contact area can also be partially or completely removed by using a mask or etching.

[0070] In some embodiments of the present invention, the thickness of the second doped crystalline silicon layer retained in the patterned processing area is 0-100 nm, so as to reduce parasitic absorption loss of polysilicon light.

[0071] In some embodiments of the present invention, the alkaline solution used for wet removal of the second doped crystalline silicon layer in the laser processed area may include a first alkaline agent and a first additive, and the first alkaline agent may be selected from at least one of sodium hydroxide and potassium hydroxide.

[0072] In some embodiments of the present invention, the alkaline texturing solution includes a second alkaline reagent and an additive. The second alkaline reagent can be one or more of sodium hydroxide, potassium hydroxide, sodium carbonate, and sodium bicarbonate. In some preferred embodiments, the concentration of the second alkaline reagent in the alkaline texturing solution can be 0.5-5 wt%, so as to form a textured surface on the first doped crystalline silicon layer or the second doped crystalline silicon layer, reduce the reflectivity of the non-metallic contact area, and help improve the short-circuit current.

[0073] In some embodiments of the present invention, the texturing process causes the reflectivity of the back surface to be between 8% and 15%.

[0074] In the present invention, the metal contact area is protected by BSG or PSG on the surface, and the contact interface of the outermost polysilicon layer (poly) is still a polished surface, which can increase the contact area and adhesion with the electrode.

[0075] In some embodiments of the present invention, a chain pickling method may be used to remove BSG or PSG used for protection in the metal contact area.

[0076] In some embodiments of the present invention, the method further comprises: depositing a passivation anti-reflection layer on the surface of the passivation structure using plasma enhanced chemical vapor deposition to improve the density and anti-reflection effect of the passivation anti-reflection layer.

[0077] In some embodiments of the present invention, the passivation anti-reflection layer may be a composite film layer selected from one or more of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0078] In some embodiments of the present invention, the thickness of the passivation anti-reflection layer may be 60-100 nm.

[0079] The present invention also relates to a passivation structure prepared by the method described in the second aspect of the present invention.

[0080] The present invention also provides a solar cell, which comprises the passivation structure described in the first aspect of the present invention or the passivation structure prepared by the method described in the second aspect of the present invention, so as to improve the conversion efficiency of the solar cell.

[0081] In some embodiments of the solar cell of the present invention, the solar cell may be selected from one of a TOPCon cell and a bifacial TOPCon cell.

[0082] In some embodiments of the solar cell of the present invention, the solar cell is a TOPCon cell, and a first semiconductor layer, a front passivation layer, and a front anti-reflection layer are sequentially stacked on the front surface of the silicon substrate. The first semiconductor layer has a conductivity type opposite to that of the first doped crystalline silicon layer.

[0083] In some embodiments of the solar cell of the present invention, the front passivation layer may be an aluminum oxide passivation layer.

[0084] In some embodiments of the solar cell of the present invention, the front anti-reflection layer may be a composite film layer selected from one or more of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0085] In some embodiments of the present invention, the metallization treatment of the solar cell includes: printing grid lines and electrodes on the light-receiving side and the back side of the silicon wafer after the surface passivation and anti-reflection treatment, respectively, and sintering.

[0086] Specifically, the metallization treatment includes: forming a first metal electrode on the passivation anti-reflection layer, forming a second metal electrode on the front anti-reflection layer, and making the second metal electrode pass through the front anti-reflection layer and the front passivation layer to form an ohmic contact with the first semiconductor layer.

[0087] Specifically, the back side electrodes and grid lines are printed first, and then low temperature curing or pre-curing is performed, and then the light-receiving side electrodes and grid lines are printed, and high temperature sintering is performed. The sintering temperature can be 750-900°C.

[0088] The present invention is further illustrated below by way of examples, but the present invention is not limited thereto.

[0089] The resistivity of the N-type silicon wafer used in the following examples and comparative examples is 1 Ω·cm, and the minority carrier lifetime is >10 ms.

[0090] Example 1 This embodiment is used to illustrate the preparation method of the tunneling passivated contact (TOPCon) solar cell of the present invention, which includes the following steps: S1. Texturing an N-type silicon wafer to remove damage and forming a pyramid structure for surface light trapping on both the light-receiving side and the back side of the N-type silicon wafer to obtain a pre-treated silicon wafer. S2. Boron diffusion is performed on the light-receiving surface of the pretreated silicon wafer using BCl3 and oxygen to form a boron diffusion layer on the textured surface of the light-receiving side of the silicon wafer. Then, chain HF cleaning is performed to remove the BSG that has spread around the back side and the edge. Then, trough alkali polishing is performed to remove the boron spread and the back side of the silicon wafer is polished. Then, trough HF cleaning is performed to remove the BSG on the front side to obtain a back-polished silicon substrate. During the boron diffusion process, the peak doping concentration is 6.5×10 18 atom / cm 3 , junction depth is 0.6 μm, and square resistance is 300 Ω / sq; S3, under the condition of vacuum and nitrous oxide, forming a tunneling silicon oxide layer (SiO x ); SiH4, PH3 mixed with H2 is used to in-situ dope phosphorus on the surface of the tunneling silicon oxide layer by plate-type plasma-enhanced chemical vapor deposition to form a first initial phosphorus-doped amorphous silicon layer; wherein the thickness of the tunneling silicon oxide layer is 1.2 nm; the thickness of the first phosphorus-doped amorphous silicon layer is 30 nm, and the peak phosphorus doping concentration is 1×10 20 atoms / cm 3 ; S4, in a vacuum and with nitrous oxide introduced, using plate-type plasma enhanced chemical vapor deposition to form silicon oxide (SiO x ) middle layer, the thickness of the silicon oxide middle layer is 1.2 nm; S5. In situ phosphorus is doped on the surface of the intermediate layer by plate-type plasma-enhanced chemical vapor deposition using SiH4, PH3 mixed with H2 to obtain a second initial phosphorus-doped amorphous silicon layer. The formed double-layer initial phosphorus-doped amorphous silicon layer is annealed to convert the first initial phosphorus-doped amorphous silicon layer into a first phosphorus-doped polycrystalline silicon layer. A second phosphorus-doped polycrystalline silicon layer and a phosphorus-silicate glass (PSG) layer are formed on the surface of the intermediate layer. The thickness of the second phosphorus-doped polycrystalline silicon layer is 80 nm, and the peak phosphorus doping concentration is 4×10 20 atoms / cm 3 ; The annealing temperature is 880℃; S6. Patterning the phosphosilicate glass layer using a laser, controlling the laser power to remove the phosphosilicate glass layer in the non-metal contact area, and then subjecting the laser-treated silicon wafer to wet alkaline etching to remove the second phosphorus-doped polysilicon and the intermediate layer in the laser-treated area, thereby obtaining a patterned silicon wafer; the laser-treated width is 100 μm; S7, placing the patterned silicon wafer in an alkaline texturing solution for texturing, so as to form a pyramid light trapping structure on the surface of the first phosphorus-doped polysilicon layer exposed in the laser processed area, wherein the reflectivity of the pyramid light trapping structure is 11%; S8, using chain pickling to remove the phosphorus-silicon glass layer covering the surface of the metal contact area; S9. Under vacuum conditions in the ALD chamber, TMA, N2, and H2O are periodically introduced to deposit aluminum oxide on the light-receiving surface of the cell; after the aluminum oxide is deposited, a silicon nitride passivation anti-reflection layer is deposited on the light-receiving surface and back of the cell by plasma-enhanced chemical vapor deposition (PECVD); wherein the thickness of the aluminum oxide passivation layer is 3 nm; the thickness of the silicon nitride passivation anti-reflection layer on the light-receiving surface is 85 nm, and the thickness of the silicon nitride passivation anti-reflection layer on the back is 80 nm; S10, forming main and auxiliary grid lines on the light-receiving surface and back surface of the cell obtained in S9 respectively by screen printing, and sintering at high temperature to form ohmic contact to obtain a tunnel passivation contact solar cell.

[0091] Example 2 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The thickness of the tunneling silicon oxide layer is 0.5 nm; The thickness of the first phosphorus-doped polysilicon layer is 20 nm.

[0092] Example 3 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The thickness of the tunneling silicon oxide layer is 2.0 nm; The thickness of the first phosphorus-doped polysilicon layer is 80 nm.

[0093] Example 4 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The thickness of the tunneling silicon oxide layer is 0.9 nm.

[0094] Example 5 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The thickness of the intermediate layer is 0.5 nm.

[0095] Example 6 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The thickness of the intermediate layer is 2.0 nm.

[0096] Example 7 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The thickness of the intermediate layer is 3.0 nm.

[0097] Example 8 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The thickness of the second phosphorus-doped polysilicon layer is 40 nm.

[0098] Example 9 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The thickness of the second phosphorus-doped polysilicon layer is 200 nm.

[0099] Example 10 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The thickness of the second phosphorus-doped polysilicon layer is 300 nm.

[0100] Example 11 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The material of the middle layer is aluminum oxide.

[0101] Example 12 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: The material of the middle layer is ITO.

[0102] Example 13 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: In step S6, a portion of the second phosphorus-doped polysilicon layer in the laser-processed area is removed by wet alkaline etching, and the thickness of the remaining second phosphorus-doped polysilicon layer is 30 nm. Then, in step S7 , a pyramid light trapping structure is formed on the retained second phosphorus-doped polysilicon layer, and the reflectivity of the pyramid light trapping structure is 11%.

[0103] Example 14 The method for preparing a tunneling passivated contact solar cell in this embodiment refers to that in Example 1, except that: In step S6, the second phosphorus-doped polysilicon in the laser-processed area is removed by wet alkaline etching until the surface of the intermediate layer in the non-metallic contact area is exposed; Then, in step S7 , a pyramid light trapping structure is formed on the intermediate layer in the retained non-metallic contact area, and the reflectivity of the pyramid light trapping structure is 11%.

[0104] Comparative Example 1 The method for preparing a tunnel passivated contact solar cell in this comparative example refers to that in Example 1, except that: Steps S6 to S7 are not performed; In S8, the back side of the silicon wafer and the expanded phosphosilicate glass layer are removed by pickling, and then S9 and S10 are performed.

[0105] Comparative Example 2 The method for preparing a tunnel passivated contact solar cell in this comparative example refers to that in Example 1, except that: Step S7 is not performed, that is, no texture is formed on the surface of the first phosphorus-doped polysilicon layer in the non-metallic region.

[0106] The solar cells obtained in Examples 1-14 and Comparative Examples 1-2 were connected to an external circuit to test power, and the results are shown in Table 1. sc 、V oc , FF, and Eta are the short-circuit current, open-circuit voltage, fill factor, and conversion efficiency of the solar cell, respectively.

[0107] Table 1

[0108] According to the data in Table 1, by comparing Examples 1-14 with the data in Comparative Examples 1 and 2, it can be seen that the method of the present invention can improve the photocurrent loss caused by parasitic absorption of polysilicon and improve the photoelectric conversion efficiency of the battery. By comparing the data in Examples 1-4, it can be seen that the method of the present invention can effectively improve the interface passivation contact effect on the back side by using the tunneling silicon oxide layer in combination with the first phosphorus-doped polysilicon layer. When the thickness of the tunneling silicon oxide layer is within the preferred range of 0.9-1.2 nm of the present invention, it can effectively block the elements in the double-layer doped polysilicon layer from diffusing to the internal silicon wafer during the preparation process, and at the same time can reduce and improve the interface passivation effect, reduce the recombination loss, and thus improve the overall conversion efficiency of the battery.

[0109] The data from Examples 5-7 and 14 demonstrate that the intermediate layer can prevent phosphorus from the second doped polysilicon layer from diffusing into the first doped polysilicon layer and the interior of the silicon wafer, while also increasing the overall phosphorus doping concentration in the back double-layer polysilicon layer. Furthermore, retaining the intermediate layer only in the metal contact area can reduce light loss caused by the intermediate layer. When the intermediate layer has a thickness within the preferred range of 1-2 nm, it can effectively prevent high-concentration dopant elements from the outer doped polysilicon layer from diffusing into the inner doped polysilicon layer and the internal silicon wafer during the fabrication process.

[0110] The data in Examples 8-10 and 13 show that the second doped polysilicon layer on the back side can increase the phosphorus concentration in the polysilicon layer, enhancing the field passivation effect; removing the intermediate layer and the outer doped polysilicon layer in the non-metallic contact area can significantly reduce the optical parasitic absorption loss of the outer doped polysilicon layer. When the thickness of the second doped polysilicon layer is within the preferred range of 40-200 nm of the present invention, the overall doping concentration in the polysilicon can be increased, enhancing the field passivation effect. The data in Examples 11-12 show that the intermediate layers of aluminum oxide and transparent conductive layer materials can also effectively prevent phosphorus in the outer doped polysilicon layer from diffusing into the first doped polysilicon and the interior of the silicon wafer.

[0111] Example 15 This embodiment is used to illustrate the preparation method of the double-sided TOPCon solar cell of the present invention, which comprises the following steps: S1. Texturing an N-type silicon wafer to remove damage and forming a pyramid structure for surface light trapping on both the light-receiving side and the back side of the N-type silicon wafer to obtain a pre-treated silicon wafer. S2. After depositing an ultra-thin SiO2 layer on the front side using LPCVD, a 260nm thick B-doped polysilicon layer was deposited using silane, BCl3, and other gases. Chain HF cleaning was then used to remove the BSG that had spread around the back side and edges. A slot-type alkaline polishing process was then performed to remove the boron spread and polish the back side of the silicon wafer. A slot-type HF cleaning process was then used to remove the BSG on the front side, resulting in a back-polished silicon substrate. The thickness of the ultra-thin SiO2 layer was 1.2nm. The boron doping concentration in the B-doped polysilicon was 3×10 19 atom / cm 3 ; S3, under the condition of vacuum and nitrous oxide, forming a tunneling silicon oxide layer (SiO x ); SiH4, PH3 mixed with H2 are used to in-situ dope phosphorus on the surface of the tunneling silicon oxide layer by plate-type plasma-enhanced chemical vapor deposition to form a first initial phosphorus-doped amorphous silicon layer; wherein the thickness of the tunneling silicon oxide layer is 1.2 nm; the thickness of the first phosphorus-doped polycrystalline silicon layer is 30 nm, and the peak phosphorus doping concentration is 1×10 20 atoms / cm 3 ; S4, in a vacuum and with nitrous oxide introduced, using plate-type plasma enhanced chemical vapor deposition to form silicon oxide (SiO x ) middle layer, the thickness of the silicon oxide middle layer is 1.2 nm; S5. Phosphorus is in situ doped on the surface of the intermediate layer by plate-type plasma-enhanced chemical vapor deposition using SiH4, PH3 mixed with H2 to obtain a second initial phosphorus-doped amorphous silicon layer. The double-layer initial phosphorus-doped amorphous silicon layer on the back side is annealed to convert the first initial phosphorus-doped amorphous silicon layer into a first phosphorus-doped polycrystalline silicon layer. A second phosphorus-doped polycrystalline silicon layer and a phosphorus-silicate glass (PSG) layer are formed on the surface of the intermediate layer. The thickness of the second phosphorus-doped polycrystalline silicon layer is 80 nm, and the peak phosphorus doping concentration is 4×10 20 atoms / cm 3 ; The annealing temperature is 880℃; S6. Patterning the phosphosilicate glass layer using a laser, controlling the laser power to remove the phosphosilicate glass layer in the non-metal contact area, and then subjecting the laser-treated silicon wafer to wet alkaline etching to remove the second phosphorus-doped polysilicon and the intermediate layer in the laser-treated area, thereby obtaining a patterned silicon wafer; the laser-treated width is 100 μm; S7, placing the patterned silicon wafer in an alkaline texturing solution for texturing, so as to form a pyramid light trapping structure on the surface of the first phosphorus-doped polysilicon layer exposed in the laser processed area, wherein the reflectivity of the pyramid light trapping structure is 11%; S8, using chain pickling to remove the phosphorus-silicon glass layer covering the surface of the metal contact area; S9. Under vacuum conditions in the ALD chamber, TMA, N2, and H2O are periodically introduced to deposit aluminum oxide on the light-receiving surface of the cell; after the aluminum oxide is deposited, a silicon nitride passivation anti-reflection layer is deposited on the light-receiving surface and back of the cell by plasma-enhanced chemical vapor deposition (PECVD); wherein the thickness of the aluminum oxide passivation layer is 85 nm; the thickness of the silicon nitride passivation anti-reflection layer on the light-receiving surface is 3 nm, and the thickness of the silicon nitride passivation anti-reflection layer on the back is 80 nm; S10. The light-receiving surface and the back surface of the cell obtained in S9 are respectively formed into main and auxiliary grid lines by screen printing, and sintered at high temperature to form ohmic contacts to obtain a double-sided TOPCon solar cell.

[0112] Comparative Example 3 The method for preparing a double-sided TOPCon solar cell in this comparative example refers to Example 15, except that: Steps S6 to S7 are not performed; In S8, the back side of the silicon wafer and the expanded phosphosilicate glass layer are removed by pickling, and then S9 and S10 are performed.

[0113] The solar cells prepared in Example 15 and Comparative Example 3 were connected to an external circuit to test the power. The results are shown in Table 2.

[0114] Table 2

[0115] According to the data in Table 2, the passivation structure prepared by the method provided by the present invention is used in double-sided TOPCon cells, which is beneficial to reducing the photocurrent loss of solar cells, thereby improving the overall performance of the cells.

[0116] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the scope of protection of the present invention.

[0117] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. To avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0118] In addition, the various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A passivation structure, characterized in that: Applicable to the back side of a silicon substrate having a first conductivity type, comprising a tunneling silicon oxide layer and a first doped crystalline silicon layer disposed on the entire back side of the silicon substrate; a surface of the first doped crystalline silicon layer away from the tunneling silicon oxide layer comprises a non-metallic contact area and a metal contact area, wherein the non-metallic contact area is adjacent to the metal contact area and is spaced apart; The metal contact region is sequentially stacked with a first intermediate layer and a second doped crystalline silicon layer; The non-metallic contact area has a light trapping structure, or / and the non-metallic contact area is sequentially stacked with a second intermediate layer and a third doped crystalline silicon layer, the first doped crystalline silicon layer, the second doped crystalline silicon layer and the third doped crystalline silicon layer have the same conductivity type, the surface of the third doped crystalline silicon layer has a light trapping structure, and the thickness of the third doped crystalline silicon layer is less than the thickness of the second doped crystalline silicon layer.

2. The passivation structure according to claim 1, wherein: The thickness of the first intermediate layer and the second intermediate layer are each independently 0.5-3 nm; and / or, The materials of the first intermediate layer and the second intermediate layer are independently selected from one or more of aluminum oxide, silicon oxide and a transparent conductive layer.

3. The passivation structure according to claim 1 or 2, wherein: The back side of the silicon substrate is a smooth surface; The thickness of the tunneling silicon oxide layer is 0.5-2 nm.

4. The passivation structure according to claim 1, wherein: The first doped crystalline silicon layer includes a first doping element; the thickness of the first doped crystalline silicon layer is 20-80 nm, and the doping concentration is 1×10 18 -1×10 20 atoms / cm 3 ; The first doping element is phosphorus or boron.

5. The passivation structure according to claim 1 or 4, wherein: The second doped crystalline silicon layer and the third doped crystalline silicon layer include a second doping element; the doping concentration in the first doped crystalline silicon layer is less than the doping concentration in the second doped crystalline silicon layer and the third doped crystalline silicon layer; The thickness of the second doped crystalline silicon layer is 40-300 nm, and the doping concentration is 1×10 19 -1×10 21 atoms / cm 3 , and / or, The thickness of the third doped crystalline silicon layer is 0-100 nm; the doping concentration of the third doped crystalline silicon layer is 1×10 19 -1×10 21 atoms / cm 3 ; The ratio of the thickness of the third doped crystalline silicon layer to the thickness of the second doped crystalline silicon layer is (0-0.33):1; The second doping element is phosphorus or boron. The passivation structure according to claim 1 , wherein: A passivation anti-reflection layer is provided on the second doped crystalline silicon layer, and the passivation anti-reflection layer extends to the non-metallic region of the first doped crystalline silicon layer or the surface of the third doped crystalline silicon layer; The passivation anti-reflection layer is a composite film layer selected from one or more of a silicon oxide layer, a silicon oxynitride layer and a silicon nitride layer; The thickness of the passivation anti-reflection layer is 60-100 nm.

7. A method for preparing a passivation structure, characterized in that: The method comprises the following steps: providing a silicon substrate having a first conductivity type; forming a tunneling silicon oxide layer and a first doped crystalline silicon layer in sequence on the back side of the silicon substrate; Depositing an intermediate layer on the surface of the first doped crystalline silicon layer; forming a second doped crystalline silicon layer and a doped silicon glass layer on the surface of the intermediate layer; wherein the second doped crystalline silicon layer and the first doped crystalline silicon layer have the same conductivity type; Patterning the doped silicon glass layer in the non-metal contact area and removing a portion of the second doped crystalline silicon layer in the patterned area, or removing the second doped crystalline silicon layer and the intermediate layer in the patterned area to obtain a patterned silicon wafer; Placing the patterned silicon wafer in an alkaline texturing solution for texturing, so as to form a light trapping structure in the non-metallic contact area on the back side; The doped silicon glass layer covering the surface of the metal contact area is removed to obtain the passivation structure.

8. The method according to claim 7, wherein: The back side of the silicon substrate is a smooth surface; The intermediate layer is formed by plasma enhanced atomic layer deposition; the thickness of the intermediate layer is 0.5-3 nm; The material of the intermediate layer is selected from one or more of aluminum oxide, silicon oxide and a transparent conductive layer; Optionally, the thickness of the tunneling silicon oxide layer is 0.5-2 nm; and the method of forming the tunneling silicon oxide layer is selected from at least one of plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, and low pressure chemical vapor deposition.

9. The method according to claim 7 or 8, wherein The first doped crystalline silicon layer is deposited using plasma enhanced chemical vapor deposition, comprising: A first initial doped crystalline silicon layer is obtained by depositing a silicon thin film using plasma enhanced chemical vapor deposition while introducing a gas containing a first doping element; The first doping element is boron or phosphorus; The thickness of the first initial doped crystalline silicon layer is 20-80 nm; the doping concentration in the first initial doped crystalline silicon layer is 1×10 18 -1×10 20 atoms / cm 3 .

10. The method according to claim 9, wherein: The second doped crystalline silicon layer is deposited by plasma enhanced chemical vapor deposition, comprising: A second initial doped crystalline silicon layer is obtained by depositing a silicon thin film using plasma enhanced chemical vapor deposition while introducing a gas containing a second doping element; Annealing the first initial doped crystalline silicon layer and the second initial doped crystalline silicon layer to obtain the second doped crystalline silicon layer and the doped silicon glass layer; the doping concentration in the first doped crystalline silicon layer is lower than the doping concentration in the second doped crystalline silicon layer; The second doping element is boron or phosphorus; The thickness of the second initial doped crystalline silicon layer is 40-300 nm; the doping concentration in the second initial doped crystalline silicon layer is 1×10 19 -1×10 21 atoms / cm 3 ; The temperature of the annealing treatment is 800-1050°C.

11. The method according to claim 7, wherein: The thickness of the second doped crystalline silicon layer retained in the patterned processing area is 0-100 nm.

12. The method according to claim 7, wherein: The method further comprises: depositing a passivation anti-reflection layer on the surface of the passivation structure using plasma enhanced chemical vapor deposition; The passivation anti-reflection layer is a composite film layer selected from one or more of a silicon oxide layer, a silicon oxynitride layer and a silicon nitride layer; The thickness of the passivation anti-reflection layer is 60-100 nm.

13. A passivation structure prepared by the method according to any one of claims 9 to 12.

14. A solar cell, characterized in that: The solar cell comprises the passivation structure according to any one of claims 1 to 8 or 13; Optionally, the solar cell is selected from one of a TOPCon cell and a bifacial TOPCon cell.

Images