TOPCon battery structure and preparation method and splitting method thereof

Abstract

The invention discloses a TOPCon battery structure and a preparation method and a splintering method thereof, and the TOPCon battery comprises an N-type silicon wafer, an N-type silicon wafer, a P-type silicon wafer, a P-type silicon wafer and a P-type silicon wafer A dielectric film is arranged outside the N-type silicon wafer; the dielectric film on the front surface of the N-type silicon wafer is a front surface dielectric film, and the dielectric film on the back surface of the N-type silicon wafer is a back surface dielectric film; a front grid line pattern channel penetrating through a front dielectric film is arranged on the front dielectric film of the N-type silicon wafer; a discontinuous periodic P region is formed on the front surface of the N-type silicon wafer below the front surface grid line pattern channel, so that a discontinuous periodic PN junction is obtained on the N-type silicon wafer; a back grid line pattern channel is arranged on the back dielectric film of the N-type silicon wafer; and conductive grid lines are respectively arranged in the front grid line pattern channel and the back grid line pattern channel. The invention discloses a TOPCon battery structure and a preparation method and a splitting method thereof. The method has the effects of low-cost metallization of the battery and low-loss splitting, and the efficiency of the battery is also improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a TOPCon cell structure and a preparation method and a cell splitting method thereof. Background Art

[0002] Tunnel Oxide Passivated Contact (TOPCon) is a solar cell technology based on N-type monocrystalline silicon. It has become the mainstream product of high-efficiency solar cells in the photovoltaic industry, with high photoelectric conversion efficiency and performance stability.

[0003] Despite this, TOPCon batteries still face two major challenges: First, how to reduce the high metallization costs? High-temperature silver paste is typically screen-printed on the front and back of the cell, followed by sintering at 700-800°C to achieve both low-resistance silver grid lines and good silver / silicon contact. However, this results in a high silver consumption of 10mg / W. In recent years, low-temperature silver-coated copper paste has been used in crystalline silicon heterojunction (HJT) solar cells, significantly reducing the metallization costs of HJT cells. However, since silver-coated copper paste is highly susceptible to oxidation at high temperatures, resulting in a significant increase in resistance, it is difficult to apply to existing TOPCon cell structures.

[0004] Second, how to achieve low-loss battery splitting. Due to the high current working characteristics, the full-size TOPCon battery package has a high resistance loss (I 2 R), laser cleavage technology is typically used to split a full-size cell into two or more pieces, reducing current and resistive losses. However, because the light-receiving front side of conventional TOPCon cells has a continuous pn junction region, laser cleavage cuts through the pn junction. Dangling silicon atoms at the cleavage surface introduce surface energy levels into the pn junction, significantly increasing surface recombination and reducing cell efficiency. Summary of the Invention

[0005] The present invention overcomes the deficiencies of the prior art and provides a TOPCon battery structure and a preparation method and a splitting method thereof; it has the effects of low-cost metallization of the battery and low-loss splitting, and also improves the battery efficiency.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a TOPCon cell structure, comprising: an N-type silicon wafer; a dielectric film disposed on the outside of the N-type silicon wafer; wherein the dielectric film on the front side of the N-type silicon wafer is a front dielectric film, and the dielectric film on the back side of the N-type silicon wafer is a back dielectric film; a front gate line pattern channel penetrating the front dielectric film is disposed on the front dielectric film of the N-type silicon wafer; a discontinuous periodic P region is formed on the front side of the N-type silicon wafer below the front gate line pattern channel, thereby obtaining a discontinuous periodic PN junction on the N-type silicon wafer; a back gate line pattern channel is disposed on the back dielectric film of the N-type silicon wafer; and conductive gate lines are disposed in the front gate line pattern channel and the back gate line pattern channel, respectively.

[0007] In a preferred embodiment of the present invention, the conductive gate line includes a conductive seed layer disposed in the front gate line pattern trench and the back gate line pattern trench, and a copper-based paste layer attached to the outside of the conductive seed layer; A passivation contact layer is further provided between the back surface of the N-type silicon wafer and the back surface dielectric film.

[0008] In a preferred embodiment of the present invention, the front dielectric film includes SiO2 films formed on the front surface of the N-type silicon wafer from the inside to the outside. x layer, AlO x layer and SiN x Single or composite film layers; Alternatively, the passivation contact layer comprises SiO disposed on the back of the N-type silicon wafer. x layer and set on SiO x The back dielectric film includes SiN x layer, N-poly-Si layer is located on SiO x layer and SiN x between layers; The back gate electrode patterning is to use laser ablation to remove the SiN at the back gate pattern on the back dielectric film. x layer.

[0009] In a preferred embodiment of the present invention, the front dielectric film includes AlO2 and AlO3 layers formed successively from the inside to the outside on the front side of the N-type silicon wafer. x layer and SiN x layer, in which AlO x The layer thickness is 2-10nm, SiN x The layer thickness is 50-100 nm; and / or, SiO in the back dielectric film x The layer thickness is 1-3nm, the N-poly-Si layer thickness is 20-100nm, and the SiN x The layer thickness is 50-100 nm; And / or, the doping concentration of N-type silicon wafer is 10 10 -10 18 / cm 3 ; And / or, the doping concentration of the silicon substrate at the pattern of the front gate electrode is in the range of 10 16 -10 22 / cm 3 ; And / or, the material of the conductive seed layer includes one of Ni, Ag, Ti, and W; And / or, the conductive paste includes silver-coated copper paste or copper paste.

[0010] In a preferred embodiment of the present invention, a method for preparing a TOPCon battery comprises the following steps: Step S1, obtaining an N-type silicon wafer with a dielectric film; Step S2, performing gate line patterning processing on the surface of the N-type silicon wafer with the dielectric film to obtain a gate line pattern channel on the N-type silicon wafer with the dielectric film; Step S3, performing B diffusion on the N-type silicon wafer to obtain a P region on the N-type silicon wafer at the gate line pattern trench, and forming a discontinuous local PN junction region on the N-type silicon wafer; Step S4, preparing a conductive seed layer on the front and back sides of the N-type silicon wafer; Step S5: placing a conductive paste on the conductive seed layer and sintering the paste to form a conductive grid line to obtain a TOPCon battery.

[0011] In a preferred embodiment of the present invention, in step S1, obtaining an N-type silicon wafer with a dielectric film includes: Step S1.1, obtaining a pre-treated N-type silicon wafer, wherein the pre-treatment includes a cleaning process and a texturing process, to obtain a texturing N-type silicon wafer; The cleaning and texturing processes comprise the following steps: Clean the surface of N-type silicon wafer; Performing a texturing treatment on the cleaned N-type silicon wafer, wherein the texturing treatment includes performing alkali texturing on the N-type silicon wafer to form a pyramid texture surface on the surface of the N-type silicon wafer; Step S1.2, preparing a dielectric film on the front side of the N-type silicon wafer after texturing, as a front dielectric film.

[0012] In a preferred embodiment of the present invention, in step S2, the gate line patterning process includes: Patterning a front gate line electrode on a front dielectric film of an N-type silicon wafer with a dielectric film; The front gate line electrode is patterned by laser ablation to remove the front dielectric film at the gate line electrode pattern, and a gate line pattern channel is obtained on the N-type silicon wafer as the front gate line pattern channel.

[0013] In a preferred embodiment of the present invention, in step S3, the B diffusion comprises: Doping the N-type silicon wafer at the front gate line pattern channel to form a local doped P region on the N-type silicon wafer; The locally doped P region obtained after B diffusion is diffused with boron atoms using laser to increase the doping concentration of the P region; a discontinuous periodic P region is obtained on the N-type silicon wafer; In step S3, after forming a discontinuous local PN junction region on the N-type silicon wafer; Performing alkali polishing on the textured back side of the N-type silicon wafer to form a smooth N-type silicon wafer back side; Prepare a passivation contact layer and a back dielectric film on the back side of a flat N-type silicon wafer; Use wet etching to remove BSG generated by B diffusion on the front side of the N-type silicon wafer, as well as the wrap-around film generated during the preparation of the back dielectric film; The back side gate line electrode is patterned on the back side dielectric film of the N-type silicon wafer.

[0014] In a preferred embodiment of the present invention, in step S4, preparing a conductive seed layer on the front and back sides of the N-type silicon wafer includes: growing a conductive seed layer on the patterned regions of the gate line electrodes on the front and back sides of the N-type silicon wafer; In step S5, a conductive paste is provided on the conductive seed layer, including: printing the conductive paste on the conductive seed layer on the front and back surfaces by screen printing; In step S5, sintering includes: curing or sintering the conductive paste at 200-400° C. to form a conductive gate line in the patterned area of ​​the gate line electrode; The patterned area of ​​the conductive grid lines is subjected to LECO treatment.

[0015] In a preferred embodiment of the present invention, a method for preparing a TOPCon cell is provided, wherein the prepared TOPCon cell is split, and the splitting method comprises the following steps: Laser splitting is performed between the non-continuous local PN junction regions on the front of the TOPCon cell. The laser splitting track is parallel to the conductive grid line to divide the TOPCon cell into several pieces, and the crack surface only passes through the N region between the non-continuous local PN junction regions.

[0016] The present invention solves the defects existing in the technical background, and the beneficial technical effects of the present invention are: The TOPCon battery structure and its preparation method and splitting method of the present invention have the effects of low-cost battery metallization and low-loss splitting, and also improve battery efficiency.

[0017] 1. The fabrication method used in the structure of the present invention is a low-cost, medium-low temperature metallization technology. Ni / Ag@Cu metallization is performed simultaneously on both the front and back sides of the structure, significantly reducing the metallization cost.

[0018] 2. The structural process of the present invention can achieve medium-low temperature sintering at 200-400°C, reducing thermal damage to the battery.

[0019] 3. The cleavage method employed in the present invention's preparation method enables low-loss, multi-slicing. The present invention achieves cleavage in the n-region without exposing the pn junction, significantly reducing efficiency degradation caused by cleavage. Edge passivation is unnecessary, providing significant advantages when multiple cleavages are required.

[0020] 4. The present invention utilizes a laser patterning process followed by diffusion, resulting in a reduced laser damage effect. If diffusion is performed before laser patterning, the laser light will severely damage the crystal structure of the front core p-region, introducing numerous defects. These defects serve as strong recombination centers for intense photogenerated carriers, leading to a decrease in battery performance. However, laser patterning followed by diffusion allows the high-temperature diffusion process to repair the laser-damaged crystal structure, significantly reducing crystal defects in the core p-region. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described below with reference to the accompanying drawings and examples.

[0022] Figure 1 This is a schematic structural diagram of a TOPCon battery structure in a preferred embodiment of the present invention; Figure 2 1 is a schematic diagram of a process for preparing a TOPCon battery in a preferred embodiment of the present invention; Figure 3 Schematic diagram showing the effect of changes in the concentrations of the P region and the N region on the size of the formed PN junction region in a preferred embodiment of the present invention; Figure 4 This is an SEM image of the laser opening and B diffusion area of ​​the dielectric film on the front side of the battery of the present invention; Figure 5 is a photograph of the battery of the present invention; Figure 6 This is a photo of a half-cell battery of the present invention; Figure 7 1 is a comparison table of electrical parameters of the battery of the present invention, conventional batteries and half-cell batteries in the embodiments.

[0023] In the figure: 1. N-type silicon wafer; 11. Front dielectric film; 111. Front gate line pattern channel; 12. Back dielectric film; 120. Passivation contact layer; 121. Back gate line pattern channel; 13. P region; 14. Depletion layer; 2. Conductive gate line; 21. Conductive seed layer; 22. Copper-based slurry layer; 3. Laser cracking. DETAILED DESCRIPTION

[0024] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. These drawings are simplified schematic diagrams that only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0025] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, bottom, top, etc.), the directional indications are only used to explain the relative positional relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly. The terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. Unless otherwise clearly specified and defined, the terms "set", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be a communication between the internal parts of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] like Figure 1-Figure 3 As shown, a method for preparing a TOPCon battery includes the following steps: Step S1, obtaining an N-type silicon wafer 1 with a dielectric film.

[0027] In step S1, obtaining the N-type silicon wafer 1 with a dielectric film includes: Step S1.1, obtain a pre-treated N-type silicon wafer 1, the doping concentration of the N-type silicon wafer 1 is 10 10 -10 18 / cm 3 ; The preferred doping concentration is 10 12 -10 16 / cm 3 The pretreatment includes cleaning and texturing to obtain an N-type silicon wafer 1 after texturing; The cleaning and texturing processes comprise the following steps: Cleaning the surface of the N-type silicon wafer 1; Performing a texturing treatment on the cleaned N-type silicon wafer 1, wherein the texturing treatment includes performing alkali texturing on the N-type silicon wafer 1 to form a pyramid texture surface on the surface of the N-type silicon wafer 1; Step S1.2, a dielectric film is prepared on the front surface of the N-type silicon wafer 1 after texturing, as a front dielectric film 11; the front dielectric film 11 includes SiO x layer, AlO x layer and SiN x In this embodiment, the front dielectric film 11 preferably includes AlO prepared from the inside to the outside on the front of the N-type silicon wafer 1. x layer and SiN x layer, wherein the front dielectric film 11 has AlO x The layer thickness is 2-10nm, SiN x The layer thickness is 50-100 nm.

[0028] Step S2, performing gate line patterning processing on the surface of the N-type silicon wafer 1 with a dielectric film, the gate line patterning processing comprising: patterning a front gate line electrode on the front dielectric film 11 of the N-type silicon wafer 1 with a dielectric film; patterning the front gate line electrode by removing the front dielectric film 11 at the gate line electrode pattern using laser ablation, thereby obtaining a gate line pattern channel on the N-type silicon wafer 1 with a dielectric film as the front gate line pattern channel 111.

[0029] Step S3, B diffusion is performed on the N-type silicon wafer 1, and the B diffusion includes: doping the N-type silicon wafer 1 at the front gate line pattern channel 111, forming a local doped P region 13 on the N-type silicon wafer 1, and doping the silicon substrate at the front gate line electrode pattern with a doping concentration range of 10 16 -10 22 / cm 3 ; The preferred doping concentration is 10 18 -10 22 / cm 3 The local doped P region 13 obtained after B diffusion is subjected to laser boron diffusion SE to increase the doping concentration of the P region 13; the P region 13 is obtained on the N-type silicon wafer 1 at the gate line pattern channel; and a discontinuous local PN junction region is formed on the N-type silicon wafer 1.

[0030] Furthermore, after forming a discontinuous local PN junction region on the N-type silicon wafer 1; First, the textured back side of the N-type silicon wafer 1 is subjected to alkali polishing treatment to form a flat back side of the N-type silicon wafer 1 ; specifically, the alkali polishing treatment is used to remove the wrap-around coating, side junction and back junction on the front side.

[0031] Then, a passivation contact layer 120 and a back dielectric film 12 are prepared on the back of the flat N-type silicon wafer 1; the passivation contact layer 120 is formed on the back of the N-type silicon wafer 1 from the inside to the outside. x layer, N-poly-Si layer; the back dielectric film 12 includes SiN x layer, and the N-poly-Si layer is located on the SiO x layer and SiN x Between layers; SiO in the back dielectric film 12 x The layer thickness is 1-3nm, the N-poly-Si layer thickness is 20-100nm, and the SiN x The layer thickness is 50-100 nm.

[0032] Wet etching is used to remove the BSG (Borosilicate Glass) diffused on the front surface B of the N-type silicon wafer 1 and the wrap-around film produced during the preparation of the back dielectric film 12; Next, the back gate electrode is patterned on the back dielectric film 12 of the N-type silicon wafer 1; the back gate electrode patterning is to remove the SiN at the back gate pattern on the back dielectric film 12 by laser ablation. x layer.

[0033] Step S4 , preparing a conductive seed layer 21 on the front and back sides of the N-type silicon wafer 1 .

[0034] Specifically, the material of the conductive seed layer 21 includes one of Ni, Ag, Ti, and W. Preferably, the conductive seed layer 21 is formed by growing a Ni seed layer using electroplating technology, with a thickness of 50 nm to 500 nm.

[0035] Step S5: Screen-printing a conductive paste layer onto the conductive seed layer 21 on the front and back surfaces; the conductive paste layer comprises a silver-coated copper paste or a copper paste; preferably, a silver-coated copper paste is printed. The conductive paste layer is formed on the conductive seed layer 21 and sintered. The conductive paste layer is cured or sintered at 200-400°C to form a conductive gate line 2 in the patterned area of ​​the gate line electrode. The conductive gate line 2 is formed, and a TOPCon cell is obtained.

[0036] LECO (Laser-Enhanced Contact Optimization) processing is performed on the patterned areas of the gate line electrodes on the front and back sides of the N-type silicon wafer 1 .

[0037] Example 1, as Figure 1-Figure 3 As shown, a method for preparing a TOPCon battery includes the following steps: 1. Obtain a pre-treated N-type silicon wafer 1, the doping concentration of the N-type silicon wafer 1 is 10 10 / cm3 , performing a cleaning pretreatment on the obtained N-type silicon wafer 1, and performing an alkali texturing treatment on the clean N-type silicon wafer 1 to form a pyramid texturing surface on the surface of the N-type silicon wafer 1, thereby obtaining the texturized N-type silicon wafer 1; 2. Prepare AlO on the front of the N-type silicon wafer 1 from the inside to the outside after texturing. x layer and SiN x layer, serving as the front dielectric film 11. AlO x The layer thickness is 2nm, SiN x The layer thickness is 50 nm; 3. Laser ablation is used to remove the AlO in the front dielectric layer at the gate electrode pattern on the surface of the N-type silicon wafer 1 with the front dielectric layer. x layer and SiN x The layer is patterned with a gate line to expose the corresponding N-type silicon wafer 1 below, and a gate line pattern channel is obtained on the N-type silicon wafer 1 with a dielectric film, as a front gate line pattern channel 111; 4. B diffusion is performed on the N-type silicon wafer 1. B atoms diffuse into the N-type silicon wafer 1 at the front gate line pattern channel 111 to form a local doped P region 13 on the N-type silicon wafer 1. The doping concentration is 10 16 / cm 3 ; 5. Performing alkaline polishing on the textured back side of the N-type silicon wafer 1 to remove the wrap-around plating, edge junctions, and back junctions, so that the textured back side of the N-type silicon wafer 1 becomes a flat back side of the N-type silicon wafer 1; 6. Prepare a passivation contact layer 120 and a back dielectric film 12 on the back of the flat N-type silicon wafer 1; the passivation contact layer 120 includes SiO2 and SiO2 films formed successively from the inside to the outside on the back of the N-type silicon wafer 1. x layer, N-poly-Si layer, the back dielectric film 12 includes SiN x layer, N-poly-Si layer is located on SiO x layer and SiN x Between the layers. Among them, SiO x The layer thickness is 1nm, the N-poly-Si layer is 20nm, and the SiN x The layer thickness is 50 nm; 7. Use wet etching to remove the BSG generated by diffusion on the front side B of the N-type silicon wafer 1, as well as the wrap-around coating film generated during the preparation of the back side dielectric film 12; 8. On the back dielectric film 12 of the N-type silicon wafer 1, the SiN at the back gate line pattern on the back dielectric film 12 is removed by laser ablation. x Layer, patterning of the back gate electrode; 9. A conductive seed layer 21 is grown on the patterned areas of the gate electrodes on the front and back sides of the N-type silicon wafer 1 using electroplating technology. The conductive seed layer 21 is a Ni seed layer with a thickness of 50 nm. 10. Screen-printing conductive paste on the conductive seed layer 21 on the front and back surfaces, wherein the conductive paste is silver-coated copper paste; 11. Curing and sintering the conductive paste at 200° C. to form a conductive grid line 2; The conductive paste layer is subjected to LECO treatment to further improve the contact performance between the Ni seed layer and the N-type silicon wafer 1 .

[0038] Example 2, as Figure 1-Figure 3 As shown, a method for preparing a TOPCon battery includes the following steps: 1. Obtain a pre-treated N-type silicon wafer 1, the doping concentration of the N-type silicon wafer 1 is 10 14 / cm 3 , performing a cleaning pretreatment on the obtained N-type silicon wafer 1, and performing an alkali texturing treatment on the clean N-type silicon wafer 1 to form a pyramid texturing surface on the surface of the N-type silicon wafer 1, thereby obtaining the texturized N-type silicon wafer 1; 2. Prepare AlO on the front of the N-type silicon wafer 1 from the inside to the outside after texturing. x layer and SiN x layer, serving as the front dielectric film 11. AlO x The layer thickness is 6nm, SiN x The layer thickness is 75 nm; 3. Laser ablation is used to remove the AlO in the front dielectric layer at the gate electrode pattern on the surface of the N-type silicon wafer 1 with the front dielectric layer. x layer and SiN x The layer is patterned with a gate line to expose the corresponding N-type silicon wafer 1 below, and a gate line pattern channel is obtained on the N-type silicon wafer 1 with a dielectric film, as a front gate line pattern channel 111; 4. B diffusion is performed on the N-type silicon wafer 1. B atoms diffuse into the N-type silicon wafer 1 at the front gate line pattern channel 111 to form a local doped P region 13 on the N-type silicon wafer 1. The doping concentration is 10 18 / cm 3 ; 5. Performing alkaline polishing on the textured back side of the N-type silicon wafer 1 to remove the wrap-around plating, edge junctions, and back junctions, so that the textured back side of the N-type silicon wafer 1 becomes a flat back side of the N-type silicon wafer 1; 6. Prepare a passivation contact layer 120 and a back dielectric film 12 on the back of the flat N-type silicon wafer 1; the passivation contact layer 120 includes SiO2 and SiO2 films formed successively from the inside to the outside on the back of the N-type silicon wafer 1. xlayer, N-poly-Si layer, the back dielectric film 12 includes SiN x layer, N-poly-Si layer is located on SiO x layer and SiN x Between the layers. Among them, SiO x The layer thickness is 2nm, the N-poly-Si layer is 60nm, and the SiN x The layer thickness is 75 nm; 7. Use wet etching to remove the BSG generated by diffusion on the front side B of the N-type silicon wafer 1, as well as the wrap-around coating film generated during the preparation of the back side dielectric film 12; 8. On the back dielectric film 12 of the N-type silicon wafer 1, the SiN at the back gate line pattern on the back dielectric film 12 is removed by laser ablation. x Layer, patterning of the back gate electrode; 9. A conductive seed layer 21 is grown on the patterned areas of the gate electrodes on the front and back sides of the N-type silicon wafer 1 using electroplating technology. The conductive seed layer 21 is a Ni seed layer with a thickness of 280 nm. 10. Screen-printing conductive paste on the conductive seed layer 21 on the front and back surfaces, wherein the conductive paste is silver-coated copper paste; 11. Curing and sintering the conductive paste at 300° C. to form a conductive grid line 2; 12. Perform LECO treatment on the conductive gate line 2 to further improve the contact performance between the Ni seed layer and the N-type silicon wafer 1.

[0039] Example 3, as Figure 1-Figure 3 As shown, a method for preparing a TOPCon battery includes the following steps: 1. Obtain a pre-treated N-type silicon wafer 1, the doping concentration of the N-type silicon wafer 1 is 10 18 / cm 3 , performing a cleaning pretreatment on the obtained N-type silicon wafer 1, and performing an alkali texturing treatment on the clean N-type silicon wafer 1 to form a pyramid texturing surface on the surface of the N-type silicon wafer 1, thereby obtaining the texturized N-type silicon wafer 1; 2. Prepare AlO on the front of the N-type silicon wafer 1 from the inside to the outside after texturing. x layer and SiN x layer, serving as the front dielectric film 11. AlO x Layer thickness is 10nm, SiN x The layer thickness is 100 nm; 3. Laser ablation is used to remove the AlO in the front dielectric layer at the gate electrode pattern on the surface of the N-type silicon wafer 1 with the front dielectric layer. x layer and SiN xThe layer is patterned with a gate line to expose the corresponding N-type silicon wafer 1 below, and a gate line pattern channel is obtained on the N-type silicon wafer 1 with a dielectric film, as a front gate line pattern channel 111; 4. B diffusion is performed on the N-type silicon wafer 1. B atoms diffuse into the N-type silicon wafer 1 at the front gate line pattern channel 111 to form a local doped P region 13 on the N-type silicon wafer 1. The doping concentration is 10 22 / cm 3 ; 5. Performing alkaline polishing on the textured back side of the N-type silicon wafer 1 to remove the wrap-around plating, edge junctions, and back junctions, so that the textured back side of the N-type silicon wafer 1 becomes a flat back side of the N-type silicon wafer 1; 6. Prepare a passivation contact layer 120 and a back dielectric film 12 on the back of the flat N-type silicon wafer 1; the passivation contact layer 120 includes SiO2 and SiO2 films formed successively from the inside to the outside on the back of the N-type silicon wafer 1. x layer, N-poly-Si layer, the back dielectric film 12 includes SiN x layer, N-poly-Si layer is located on SiO x layer and SiN x Between the layers. Among them, SiO x The layer thickness is 3nm, the N-poly-Si layer is 100nm, and the SiN x The layer thickness is 100 nm; 7. Use wet etching to remove the BSG generated by diffusion on the front side B of the N-type silicon wafer 1, as well as the wrap-around coating film generated during the preparation of the back side dielectric film 12; 8. On the back dielectric film 12 of the N-type silicon wafer 1, the SiN at the back gate line pattern on the back dielectric film 12 is removed by laser ablation. x Layer, patterning of the back gate electrode; 9. A conductive seed layer 21 is grown on the patterned areas of the gate electrodes on the front and back sides of the N-type silicon wafer 1 using electroplating technology. The conductive seed layer 21 is a Ni seed layer with a thickness of 500 nm. 10. Screen-printing conductive paste on the conductive seed layer 21 on the front and back surfaces, wherein the conductive paste is silver-coated copper paste; 11. Curing and sintering the conductive paste at 400° C. to form a conductive grid line 2; 12. Perform LECO treatment on the conductive gate line 2 to further improve the contact performance between the Ni seed layer and the N-type silicon wafer 1.

[0040] Example 4, as Figure 1-Figure 3 As shown, a method for preparing a TOPCon battery includes the following steps: 1. Obtain a pre-treated N-type silicon wafer 1, the doping concentration of the N-type silicon wafer 1 is 1012 / cm 3 , performing a cleaning pretreatment on the obtained N-type silicon wafer 1, and performing an alkali texturing treatment on the clean N-type silicon wafer 1 to form a pyramid texturing surface on the surface of the N-type silicon wafer 1, thereby obtaining the texturized N-type silicon wafer 1; 2. Prepare AlO on the front of the N-type silicon wafer 1 from the inside to the outside after texturing. x layer and SiN x layer, serving as the front dielectric film 11. AlO x The layer thickness is 2nm, SiN x The layer thickness is 80 nm; 3. Laser ablation is used to remove the AlO in the front dielectric layer at the gate electrode pattern on the surface of the N-type silicon wafer 1 with the front dielectric layer. x layer and SiN x The layer is patterned with a gate line to expose the corresponding N-type silicon wafer 1 below, and a gate line pattern channel is obtained on the N-type silicon wafer 1 with a dielectric film, as a front gate line pattern channel 111; 4. B diffusion is performed on the N-type silicon wafer 1. B atoms diffuse into the N-type silicon wafer 1 at the front gate line pattern channel 111 to form a local doped P region 13 on the N-type silicon wafer 1. The doping concentration is 10 18 / cm 3 ; 5. Performing alkaline polishing on the textured back side of the N-type silicon wafer 1 to remove the wrap-around plating, edge junctions, and back junctions, so that the textured back side of the N-type silicon wafer 1 becomes a flat back side of the N-type silicon wafer 1; 6. Prepare a passivation contact layer 120 and a back dielectric film 12 on the back of the flat N-type silicon wafer 1; the passivation contact layer 120 includes SiO2 and SiO2 films formed successively from the inside to the outside on the back of the N-type silicon wafer 1. x layer, N-poly-Si layer, the back dielectric film 12 includes SiN x layer, N-poly-Si layer is located on SiO x layer and SiN x Between the layers. Among them, SiO x The layer thickness is 1nm, the N-poly-Si layer is 60nm, and the SiN x The layer thickness is 80 nm; 7. Use wet etching to remove the BSG generated by diffusion on the front side B of the N-type silicon wafer 1, as well as the wrap-around coating film generated during the preparation of the back side dielectric film 12; 8. On the back dielectric film 12 of the N-type silicon wafer 1, the SiN at the back gate line pattern on the back dielectric film 12 is removed by laser ablation. x Layer, patterning of the back gate electrode; 9. A conductive seed layer 21 is grown on the patterned areas of the gate electrodes on the front and back sides of the N-type silicon wafer 1 using electroplating technology. The conductive seed layer 21 is a Ni seed layer with a thickness of 100 nm. 10. Screen-printing conductive paste on the conductive seed layer 21 on the front and back surfaces, wherein the conductive paste is silver-coated copper paste; 11. Curing and sintering the conductive paste at 250° C. to form a conductive grid line 2; 12. Perform LECO treatment on the conductive gate line 2 to further improve the contact performance between the Ni seed layer and the N-type silicon wafer 1.

[0041] Example 5, as Figure 1-Figure 3 As shown, a method for preparing a TOPCon battery includes the following steps: 1. Obtain a pre-treated N-type silicon wafer 1, the doping concentration of the N-type silicon wafer 1 is 10 14 / cm 3 , performing a cleaning pretreatment on the obtained N-type silicon wafer 1, and performing an alkali texturing treatment on the clean N-type silicon wafer 1 to form a pyramid texturing surface on the surface of the N-type silicon wafer 1, thereby obtaining the texturized N-type silicon wafer 1; 2. Prepare AlO on the front of the N-type silicon wafer 1 from the inside to the outside after texturing. x layer and SiN x layer, serving as the front dielectric film 11. AlO x The layer thickness is 2nm, SiN x The layer thickness is 80 nm; 3. Laser ablation is used to remove the AlO in the front dielectric layer at the gate electrode pattern on the surface of the N-type silicon wafer 1 with the front dielectric layer. x layer and SiN x The layer is patterned with a gate line to expose the corresponding N-type silicon wafer 1 below, and a gate line pattern channel is obtained on the N-type silicon wafer 1 with a dielectric film, as a front gate line pattern channel 111; 4. B diffusion is performed on the N-type silicon wafer 1. B atoms diffuse into the N-type silicon wafer 1 at the front gate line pattern channel 111 to form a local doped P region 13 on the N-type silicon wafer 1. The doping concentration is 10 18 / cm 3 ; 5. Laser boron diffusion is used to SE the locally doped P region 13 obtained after B diffusion to increase the doping concentration of the P region 13; the doping concentration of the P region 13 reaches 10 20 / cm 3 ; Obtaining a P region 13 on the N-type silicon wafer 1 at the gate line pattern channel; forming a discontinuous local PN junction region on the N-type silicon wafer 1; 6. Performing alkaline polishing on the textured back side of the N-type silicon wafer 1 to remove the wrap-around plating, edge junctions, and back junctions, so that the textured back side of the N-type silicon wafer 1 becomes a flat back side of the N-type silicon wafer 1; 7. Prepare a passivation contact layer 120 and a back dielectric film 12 on the back of the flat N-type silicon wafer 1; the passivation contact layer 120 includes SiO2 and SiO2 films formed successively from the inside to the outside on the back of the N-type silicon wafer 1. x layer, N-poly-Si layer, the back dielectric film 12 includes SiN x layer, N-poly-Si layer is located on SiO x layer and SiN x Between the layers. Among them, SiO x The layer thickness is 1nm, the N-poly-Si layer is 60nm, and the SiN x The layer thickness is 80 nm; 8. Use wet etching to remove the BSG generated by diffusion on the front side B of the N-type silicon wafer 1, as well as the wrap-around film generated during the preparation of the back dielectric film 12; 9. On the back dielectric film 12 of the N-type silicon wafer 1, the SiN at the back gate line pattern on the back dielectric film 12 is removed by laser ablation. x Layer, patterning of the back gate electrode; 10. A conductive seed layer 21 is grown on the patterned areas of the gate electrodes on the front and back sides of the N-type silicon wafer 1 using electroplating technology. The conductive seed layer 21 is a Ni seed layer with a thickness of 100 nm. 11. Screen-printing conductive paste on the conductive seed layer 21 on the front and back surfaces, wherein the conductive paste is silver-coated copper paste; 12. Curing and sintering the conductive paste at 250° C. to form a conductive grid line 2; 13. Perform LECO treatment on the conductive gate line 2 to further improve the contact performance between the Ni seed layer and the N-type silicon wafer 1.

[0042] Example 6, as Figure 1-Figure 7 As shown, a method for preparing a TOPCon battery includes the following steps: 1. Obtain a pre-treated N-type silicon wafer 1, the doping concentration of the N-type silicon wafer 1 is 10 16 / cm 3 , performing a cleaning pretreatment on the obtained N-type silicon wafer 1, and performing an alkali texturing treatment on the clean N-type silicon wafer 1 to form a pyramid texturing surface on the surface of the N-type silicon wafer 1, thereby obtaining the texturized N-type silicon wafer 1; 2. Prepare AlO on the front of the N-type silicon wafer 1 from the inside to the outside after texturing. x layer and SiN x layer, serving as the front dielectric film 11. AlO x The layer thickness is 2nm, SiNx The layer thickness is 80 nm; 3. Laser ablation is used to remove the AlO in the front dielectric layer at the gate electrode pattern on the surface of the N-type silicon wafer 1 with the front dielectric layer. x layer and SiN x The layer is patterned with a gate line to expose the corresponding N-type silicon wafer 1 below, and a gate line pattern channel is obtained on the N-type silicon wafer 1 with a dielectric film, as a front gate line pattern channel 111; 4. B diffusion is performed on the N-type silicon wafer 1. B atoms diffuse into the N-type silicon wafer 1 at the front gate line pattern channel 111 to form a local doped P region 13 on the N-type silicon wafer 1. The doping concentration is 10 18 / cm 3 ; 5. Laser boron diffusion is used to SE the locally doped P region 13 obtained after B diffusion to increase the doping concentration of the P region 13; the doping concentration of the P region 13 reaches 10 20 / cm 3 ; Obtaining a P region 13 on the N-type silicon wafer 1 at the gate line pattern channel; forming a discontinuous local PN junction region on the N-type silicon wafer 1; 6. Performing alkaline polishing on the textured back side of the N-type silicon wafer 1 to remove the wrap-around plating, edge junctions, and back junctions, so that the textured back side of the N-type silicon wafer 1 becomes a flat back side of the N-type silicon wafer 1; 7. Prepare a passivation contact layer 120 and a back dielectric film 12 on the back of the flat N-type silicon wafer 1; the passivation contact layer 120 includes SiO2 and SiO2 films formed successively from the inside to the outside on the back of the N-type silicon wafer 1. x layer, N-poly-Si layer, the back dielectric film 12 includes SiN x layer, N-poly-Si layer is located on SiO x layer and SiN x Between the layers. Among them, SiO x The layer thickness is 1nm, the N-poly-Si layer is 60nm, and the SiN x The layer thickness is 80 nm; 8. Use wet etching to remove the BSG generated by diffusion on the front side B of the N-type silicon wafer 1, as well as the wrap-around film generated during the preparation of the back dielectric film 12; 9. On the back dielectric film 12 of the N-type silicon wafer 1, the SiN at the back gate line pattern on the back dielectric film 12 is removed by laser ablation. x Layer, patterning of the back gate electrode; 10. A conductive seed layer 21 is grown on the patterned areas of the gate electrodes on the front and back sides of the N-type silicon wafer 1 using electroplating technology. The conductive seed layer 21 is a Ni seed layer with a thickness of 100 nm. 11. Screen-printing conductive paste on the conductive seed layer 21 on the front and back surfaces, wherein the conductive paste is silver-coated copper paste; 12. Curing and sintering the conductive paste at 250° C. to form a conductive grid line 2; 13. Perform LECO treatment on the conductive gate line 2 to further improve the contact performance between the Ni seed layer and the N-type silicon wafer 1.

[0043] In the above embodiment, the change of the concentration of the P region 13 and the N region will lead to a large difference in the size of the PN junction region formed. When the distance between the conductive gate lines 2 is 1000μm, in order to simplify the calculation, it is assumed that the P region 13 and the depletion region are semicircular. The area of ​​the P region 13 = pr 2 / 2, Area of ​​N region = pR 2 / 2, L is the side length of the N-type silicon wafer 1; according to the principle of electrical neutrality, the number of majority electrons in the depletion layer 14 semicircle before diffusion should be approximately equal to the number of majority holes in the P region 13 semicircle after diffusion, assuming r = 1μm.

[0044] Therefore, it is estimated that the values ​​of R in Examples 4, 5, and 6 are 27 μm, 3 μm, and 1 μm, respectively, and the corresponding PN junction regions occupy 5.4%, 0.6%, and 0.2% of the front surface area, respectively. Therefore, when laser cleaving the cells in Examples 4, 5, and 6, the cleavage plane can be selected to avoid the PN junction region and only pass through the N region, thereby achieving low-loss cleavage and forming the laser cleavage plane 3 between the discontinuous localized PN junction regions on the front surface of the TOPCon cell.

[0045] In Example 7, in the method for preparing a TOPCon battery according to any one of Examples 1 to 6, the prepared TOPCon battery is split, and the splitting method comprises the following steps: Laser splitting is performed between the non-continuous local PN junction regions on the front of the TOPCon cell. The laser splitting track is parallel to the conductive grid line 2 to divide the TOPCon cell into several pieces. The split surface only passes through the N region between the non-continuous local PN junction regions, such as Figure 1 As shown, laser cleavage surfaces 3 are formed between discontinuous local PN junction regions on the front side of the TOPCon cell.

[0046] Example 8, a TOPCon battery structure, prepared using the preparation method of a TOPCon battery in any one of Examples 1 to 7, includes the following structure: N-type silicon wafer 1; A dielectric film is provided on the outside of the N-type silicon wafer 1; wherein the dielectric film on the front side of the N-type silicon wafer 1 is a front dielectric film 11, the dielectric film on the back side of the N-type silicon wafer 1 is a back dielectric film 12, and a passivation contact layer 120 is provided between the N-type silicon wafer 1 and the back dielectric film 12; A front gate line pattern channel 111 penetrating the front dielectric film 11 is provided on the front dielectric film 11 of the N-type silicon wafer 1; A P region 13 is formed on the front surface of the N-type silicon wafer 1 below the front gate line pattern channel 111; A back-side gate line pattern channel 121 is provided on the back-side dielectric film 12 of the N-type silicon wafer 1; Conductive gate lines 2 are respectively provided in the front gate line pattern channel 111 and the back gate line pattern channel 121, and the conductive gate lines 2 include a conductive seed layer 21 provided in the front gate line pattern channel 111 and the back gate line pattern channel 121, and a copper-based paste layer 22 attached to the outside of the conductive seed layer 21; A discontinuous periodic PN junction is obtained on the N-type silicon wafer 1 .

[0047] Example 9, based on Example 8, the front dielectric film 11 includes AlO prepared from the inside to the outside on the front of the N-type silicon wafer 1. x layer and SiN x or, the passivation contact layer 120 comprises SiO prepared from the inside to the outside on the back of the N-type silicon wafer 1 x layer, N-poly-Si layer, the back dielectric film 12 includes a SiNx layer, and the N-poly-Si layer is located on the SiO x layer and SiN x The back gate electrode patterning is to remove the SiN on the back gate pattern of the back dielectric film 12 by laser ablation. x Layer. AlO in the front dielectric film 11 x The layer thickness is 2-10nm, SiN x The layer thickness is 50-100 nm; the SiO2 of the passivation contact layer 120 x The thickness of the N-poly-Si layer of the passivation contact layer 120 is 1-3 nm, the thickness of the SiN layer of the back dielectric film 12 is 20-100 nm, and the thickness of the N-poly-Si layer of the passivation contact layer 120 is 20-100 nm. x The layer thickness is 50-100nm; the doping concentration of N-type silicon wafer 1 is 10 10 -10 18 / cm 3 The doping concentration of the silicon substrate at the front gate electrode pattern is in the range of 10 16 -10 22 / cm 3The conductive seed layer 21 is made of one of Ni, Ag, Ti, and W (tungsten). In this embodiment, the conductive seed layer 21 is preferably made of Ni. The conductive paste includes a silver-coated copper paste or a copper paste. In this embodiment, the conductive paste is a silver-coated copper paste.

[0048] Working principle: The present invention is a TOPCon battery structure and its preparation method and splitting method, which have the effects of low-cost metallization of the battery and low-loss splitting, and also improve the battery efficiency. The preparation method adopted by the structure of the present invention is a low-cost medium-low temperature metallization technology. Ni / Ag@Cu metallization is carried out simultaneously on the front and back of the structure, which greatly reduces the metallization cost. The metallization process in the present invention can achieve medium-low temperature sintering of 200-400°C, reducing thermal damage to the battery. The splitting method adopted in the preparation method of the present invention can achieve low-loss multiple splitting. The present invention splits in the N region, and the PN junction is not exposed when the split is achieved, which greatly reduces the efficiency drop caused by the split; no edge passivation is required; the advantage is particularly obvious when multiple splitting is required. The present invention adopts a laser patterning process first and then a diffusion process, so it has the effect of low laser damage. If diffusion is performed first and then laser patterning is performed, the laser will severely damage the crystal structure of the front core P region 13, introducing a large number of defects. These defects serve as strong recombination centers for strong photogenerated carriers, leading to a decrease in battery performance. However, if laser patterning is performed first and then diffusion is performed, the high-temperature diffusion process can repair the laser-damaged crystal structure, significantly reducing the crystal defects in the core P region 13. In this invention, the cross-section of the PN region of the discontinuous periodic PN junction on the front of the battery is reflective, unlike the traditional continuous planar P region.

[0049] The above specific implementation methods are specific support for the scheme ideas proposed in the present invention, and cannot be used to limit the scope of protection of the present invention. Any equivalent changes or equivalent modifications made on the basis of this technical scheme in accordance with the technical ideas proposed in the present invention still fall within the scope of protection of the technical scheme of the present invention.

Claims

1. A TOPCon battery structure, characterized in that: Includes the following structures: N-type silicon wafer; A dielectric film is provided on the outside of the N-type silicon wafer; wherein the dielectric film on the front side of the N-type silicon wafer is a front dielectric film, and the dielectric film on the back side of the N-type silicon wafer is a back dielectric film; A front gate line pattern trench penetrating the front dielectric film is provided on the front dielectric film of the N-type silicon wafer; A discontinuous periodic P region is formed on the front surface of the N-type silicon wafer below the front gate line pattern channel, thereby obtaining a discontinuous periodic PN junction on the N-type silicon wafer; A back-side gate line pattern trench is provided on the back-side dielectric film of the N-type silicon wafer; Conductive gate lines are respectively arranged in the front gate line pattern channel and the back gate line pattern channel.

2. A TOPCon battery structure according to claim 1, characterized in that: The conductive gate line includes a conductive seed layer arranged in the front gate line pattern channel and the back gate line pattern channel, and a copper-based paste layer attached to the outside of the conductive seed layer; A passivation contact layer is further provided between the back surface of the N-type silicon wafer and the back surface dielectric film.

3. A TOPCon battery structure according to claim 2, characterized in that: The front dielectric film includes SiO2 films formed on the front of the N-type silicon wafer from the inside to the outside. x layer, AlO x layer and SiN x Single or composite film layers; Alternatively, the passivation contact layer comprises SiO disposed on the back of the N-type silicon wafer. x layer and set on SiO x The back dielectric film includes SiN x layer, N-poly-Si layer is located on SiO x layer and SiN x between layers; The back gate electrode patterning is to use laser ablation to remove the SiN at the back gate pattern on the back dielectric film. x layer.

4. A TOPCon battery structure according to claim 3, characterized in that: The front dielectric film includes AlO2 and AlO3 layers formed on the front of the N-type silicon wafer from the inside to the outside. x layer and SiN x layer, in which AlO x The layer thickness is 2-10nm, SiN x The layer thickness is 50-100 nm; and / or, SiO in the back dielectric film x The layer thickness is 1-3nm, the N-poly-Si layer thickness is 20-100nm, and the SiN x The layer thickness is 50-100 nm; And / or, the doping concentration of N-type silicon wafer is 10 10 -10 18 / cm 3 ; And / or, the doping concentration of the silicon substrate at the pattern of the front gate electrode is in the range of 10 16 -10 22 / cm 3 ; And / or, the material of the conductive seed layer includes one of Ni, Ag, Ti, and W; And / or, the conductive paste includes silver-coated copper paste or copper paste.

5. A method for preparing a TOPCon battery, characterized in that: A method for preparing a TOPCon battery structure according to any one of claims 1 to 3, comprising the following steps: Step S1, obtaining an N-type silicon wafer with a dielectric film; Step S2, performing gate line patterning processing on the surface of the N-type silicon wafer with the dielectric film to obtain a gate line pattern channel on the N-type silicon wafer with the dielectric film; Step S3, performing B diffusion on the N-type silicon wafer to obtain a P region on the N-type silicon wafer at the gate line pattern trench, and forming a discontinuous local PN junction region on the N-type silicon wafer; Step S4, preparing a conductive seed layer on the front and back sides of the N-type silicon wafer; Step S5: placing a conductive paste on the conductive seed layer and sintering the paste to form a conductive grid line to obtain a TOPCon battery.

6. The method for preparing a TOPCon battery according to claim 5, characterized in that: In step S1, obtaining an N-type silicon wafer with a dielectric film includes: Step S1.1, obtaining a pre-treated N-type silicon wafer, wherein the pre-treatment includes a cleaning process and a texturing process, to obtain a texturing N-type silicon wafer; The cleaning and texturing processes comprise the following steps: Clean the surface of N-type silicon wafer; Performing a texturing treatment on the cleaned N-type silicon wafer, wherein the texturing treatment includes performing alkali texturing on the N-type silicon wafer to form a pyramid texture surface on the surface of the N-type silicon wafer; Step S1.2, preparing a dielectric film on the front side of the N-type silicon wafer after texturing, as a front dielectric film.

7. The method for preparing a TOPCon battery according to claim 6, characterized in that: In step S2, the gate line patterning process includes: Patterning a front gate line electrode on a front dielectric film of an N-type silicon wafer with a dielectric film; The front gate line electrode is patterned by laser ablation to remove the front dielectric film at the gate line electrode pattern, and a gate line pattern channel is obtained on the N-type silicon wafer as the front gate line pattern channel.

8. The method for preparing a TOPCon battery according to claim 7, characterized in that: In step S3, the B diffusion includes: Doping the N-type silicon wafer at the front gate line pattern channel to form a local doped P region on the N-type silicon wafer; The locally doped P region obtained after B diffusion is diffused with boron atoms using laser to increase the doping concentration of the P region; a discontinuous periodic P region is obtained on the N-type silicon wafer; In step S3, after forming a discontinuous local PN junction region on the N-type silicon wafer; Performing alkali polishing on the textured back side of the N-type silicon wafer to form a smooth N-type silicon wafer back side; Prepare a passivation contact layer and a back dielectric film on the back side of a flat N-type silicon wafer; Use wet etching to remove BSG generated by B diffusion on the front side of the N-type silicon wafer, as well as the wrap-around film generated during the preparation of the back dielectric film; The back side gate line electrode is patterned on the back side dielectric film of the N-type silicon wafer.

9. The method for preparing a TOPCon battery according to claim 8, characterized in that: In step S4, a conductive seed layer is prepared on the front and back sides of the N-type silicon wafer, including: growing the conductive seed layer on the patterned regions of the gate line electrodes on the front and back sides of the N-type silicon wafer; In step S5, a conductive paste is provided on the conductive seed layer, including: printing the conductive paste on the conductive seed layer on the front and back surfaces by screen printing; In step S5, sintering includes: curing or sintering the conductive paste at 200-400° C. to form a conductive gate line in the patterned area of ​​the gate line electrode; The patterned area of ​​the conductive grid lines is subjected to LECO treatment.

10. The method for preparing a TOPCon battery according to claim 5, characterized in that: The prepared TOPCon battery is split, and the splitting method includes the following steps: Laser splitting is performed between the non-continuous local PN junction regions on the front of the TOPCon cell. The laser splitting track is parallel to the conductive grid line to divide the TOPCon cell into several pieces, and the crack surface only passes through the N region between the non-continuous local PN junction regions.

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