Packaging structure and method based on inverted-cone-shaped copper cylinder stress and core-shell nanometer dispersion

Abstract

The invention relates to the technical field of packaging structures, and particularly discloses a packaging structure and method based on inverted-cone-shaped copper cylinder stress and core-shell nanometer dispersion, and the packaging structure comprises a bottom layer substrate, an inverted-cone-shaped copper cylinder array and a full-black nanometer packaging film. The inverted-cone-shaped copper column array is arranged on the bottom layer substrate. The all-black nano packaging film is covered on the inverted cone-shaped copper column array; the bottom layer substrate is specifically a PCB (Printed Circuit Board) substrate; the thermal expansion coefficient of the PCB substrate is 12-16ppm / DEG C, and the glass transition temperature is greater than or equal to 180 DEG C; the inverted-cone-shaped copper column array comprises a plurality of inverted-cone-shaped copper columns. The diameter of the top of each inverted-cone-shaped copper column is 12-18 microns. The diameter of the bottom is 15-21 [mu] m; the taper angle is 5-15 degrees; the height-diameter ratio is 1.5: 1 to 2.5: 1; according to the invention, the structure of the inverted-cone-shaped copper column array and the all-black nanometer packaging film is adopted, so that integration of high conductivity, high shading performance and good thermal matching performance is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of packaging structures, and in particular relates to a packaging structure and method based on inverted tapered copper column stress and core-shell nano-dispersion. Background Art

[0002] In the existing technology, there are the following difficulties: technical monopoly and high cost, thermal expansion mismatch failure, the contradiction between the light shielding and insulation performance of the PCB substrate, the thermal stress problem of the PCB substrate, and the pain points of industrialization for small and medium-sized manufacturers.

[0003] 1. The dilemma of technological monopoly and high cost. The production of glass substrates faces the dual challenges of technological monopoly and high cost. Its manufacturing is highly dependent on expensive imported evaporation equipment (such as Japan's ULVAC, which costs more than 20 million US dollars per set). At present, only a few leading companies such as BOE and Samsung have complete full-process production lines. For small and medium-sized manufacturers, the initial investment in establishing relevant production lines is huge, usually requiring more than 500 million yuan (according to SEMI, 2024 data). In addition, taking Corning's patent (US20210375689A1, publication date: December 2021) as an example, at a pad spacing of 20μm, the edge collapse rate of the glass substrate exceeds 15% when it is laser cut. To solve this problem, an additional 10μm thick edge strengthening layer is required, but this results in a final module thickness of more than 4mm, which cannot meet the urgent demand for lightweight applications such as AR glasses.

[0004] 2. Failure due to thermal expansion mismatch. The mismatch in the coefficient of thermal expansion (CTE) between the glass substrate and metal components (such as copper pillars) is another key issue. For example, BOE's patent (CN114551743A, publication date: May 2022) mentioned that when laser ablation is used to process micropores in a glass substrate, the CTE difference between the glass substrate (CTE = 3ppm / °C) and the copper pillar (CTE = 17ppm / °C) is significant. Under temperature cycles from -40°C to 85°C, this difference will produce a peak stress of up to 120MPa, resulting in a crack rate of more than 12% at the edge of the pad.

[0005] 3. The contradiction between the light shielding and insulation performance of the PCB substrate. For example, Samsung's patent (US20220165432A1) uses carbon black with a D50 of 80nm to prepare a black encapsulation film. To achieve a light shielding rate of 99% (at a wavelength of λ = 550nm, according to the formula T = exp(-ad / λ)), the thickness of the encapsulation film needs to be at least 50μm. However, in a hot and humid environment, the volume resistivity of such a thick film layer will drop from 10 9 Ω·cm decreased to 10 8Ω·cm, resulting in a short-circuit rate of more than 5% for the pad. After searching, the competing patent (US20220165432A1) uses a cylindrical copper column and does not optimize the crystal plane orientation. Its (111) crystal plane accounts for less than 60%, resulting in a shear strength of less than 150MPa (see comparative example), and the method for regulating the effect of thiourea concentration on the crystal plane orientation is not disclosed. The present invention achieves a (111) crystal plane ratio of more than 85% through a pulse electroplating process, and the shear strength is increased to 220MPa, which is clearly different from the prior art.

[0006] 4. Thermal stress problem of PCB substrate. According to a 2023 study in Advanced Materials (DOI: 10.1002 / adma.202300123), traditional cylindrical copper pillars have a crack rate of >10% due to stress concentration during temperature cycling, while the inverted cone structure can disperse stress by optimizing the cross-sectional moment of inertia, but has not yet solved the synergistic problem of crystal orientation and CTE mismatch. For example, Apple's patent (CN118034768A) uses cylindrical copper pillars (diameter ratio 1:1), but this does not fundamentally solve the CTE mismatch problem between the substrate material and the copper pillars. As a result, the crack rate of the pads still exceeds 8%. According to the finite element simulation of the literature (Zhang et al., Advanced Materials, 2023), the geometric symmetry of the cylindrical copper pillars causes stress to concentrate on the outer corners, and their VonMises stress can reach 120MPa.

[0007] 5. Pain points for small and medium-sized manufacturers in industrialization. Glass substrate production lines offer significant economies of scale, with a minimum economic production scale requirement of 1 million units per month. However, most small and medium-sized manufacturers only have a monthly production capacity of 100,000 to 500,000 units, far below this threshold. This results in unit production costs for small and medium-sized manufacturers being approximately 30% higher than those of leading companies. Summary of the Invention

[0008] In view of this, the purpose of the present invention is to provide a packaging structure and method based on inverted conical copper pillar stress and core-shell nano-dispersion. By adopting the structure of inverted conical copper pillar array and all-black nano-packaging film, the integration of high conductivity, high light shielding and good thermal matching is achieved.

[0009] To achieve the above object, the present invention provides the following technical solutions:

[0010] A packaging structure based on inverted tapered copper pillar stress and core-shell nano-dispersion, comprising: a bottom substrate, an inverted tapered copper pillar array, and a fully black nano-encapsulation film;

[0011] The inverted tapered copper pillar array is provided on the bottom substrate; the all-black nano-encapsulation film covers the inverted tapered copper pillar array;

[0012] The bottom substrate includes: a PCB substrate; the thermal expansion coefficient of the PCB substrate is 12-16 ppm / °C, and the glass transition temperature is ≥180°C;

[0013] The inverted tapered copper pillar array comprises: a plurality of inverted tapered copper pillars; each of the inverted tapered copper pillars has a top diameter of 12-18 μm; a bottom diameter of 15-21 μm; an aspect ratio of 1.5:1-2.5:1; a taper angle θ of the inverted tapered copper pillars is 5°-15°; and a bottom surface roughness Ra of the inverted tapered copper pillars is ≤0.1 μm;

[0014] The thickness of the all-black nano-encapsulation film is 25-35 μm, D50=30-50 nm, and the BET specific surface area is ≥250 m 2 / g, volume resistivity>10 12 Ω·cm.

[0015] Furthermore, the distribution density of the inverted tapered copper pillar array is 1000-1500 per cm 2 The distance between adjacent inverted tapered copper pillars is 50-80 μm.

[0016] The present invention also provides a packaging method based on inverted tapered copper pillar stress and core-shell nano-dispersion, comprising the following steps:

[0017] S1, using an electroplating solution on the pads of the bottom substrate and forming an inverted tapered copper pillar array by pulse electroplating;

[0018] S2, coating a full black nano-encapsulation film on the inverted tapered copper pillar array, and controlling the film thickness of the full black nano-encapsulation film by slit coating; wherein the full black nano-encapsulation film comprises silane-modified nano-carbon black, modified epoxy resin, star-shaped leveling agent and bisphenol A epoxy resin microcapsule curing agent;

[0019] S3, performing gradient lamination on the all-black nano-encapsulation film and performing chemical mechanical polishing.

[0020] Furthermore, in S1, the electroplating solution comprises: 250±10g / L CuSO4·5H2O, 50±5ppm Cl - , 50±5g / L H2SO4 and 0.1±0.05ppm thiourea.

[0021] Furthermore, in the S1, during the pulse electroplating process, forward pulses and reverse pulses are alternately formed to form an inverted conical copper pillar array with a cone angle θ=10°±1° and a (111) crystal plane ratio greater than 85%.

[0022] Furthermore, the current density of the forward pulse is 20 mA / cm 2, the duration is 10 milliseconds; the current density of the reverse pulse is 5 mA / cm 2 , with a duration of 2 milliseconds.

[0023] Furthermore, in S2, the film thickness of the all-black nano-encapsulation film is 30±2 μm, and the leveling time is 3 min;

[0024] The alkyl-modified nano-carbon black adopts KH-550 silane coupling agent, and the surface hydroxyl content of the carbon black obtained after modification is less than 5%; the modified epoxy resin is 70-80%; the star-shaped leveling agent is 2-4%; the bisphenol A epoxy resin microcapsule curing agent is 1-3%; the mass proportion of the alkyl-modified nano-carbon black is 18-22%,

[0025] The fluorine-containing grafting rate of the modified epoxy resin is ≥15%; the glass transition temperature Tg of the modified epoxy resin is 160±5°C;

[0026] The slit coating speed is 10-15 m / min, the pre-curing temperature after coating is 80-90°C, and the pre-curing time after coating is 2-5 minutes;

[0027] The particle size of the bisphenol A epoxy resin microcapsule is 5-10 μm, and the coverage rate is 95%.

[0028] Furthermore, in said S3, the gradient pressing process includes: vacuum step, dynamic pressure and temperature control;

[0029] The vacuum ladder includes three stages: first, at a pressure of 10 -3 Pa for 10 minutes, then -1 Maintain at Pa for 5 minutes and then return to normal pressure;

[0030] The dynamic pressure includes three stages: the first stage is: the initial pressure is 0; the second stage is: the pressure increases linearly from 0.5kg / min to 1kg / cm 2 The third stage is: continue to increase linearly at a rate of 1kg / min to 2kg / cm 2 , total time is 15 minutes;

[0031] The temperature threshold of the gradient lamination is 105-115° C.; the heating rate is 5° C. / min, the temperature is controlled at 110±1° C., and maintained for 20 minutes.

[0032] Furthermore, in said S3, the chemical mechanical polishing adopts colloidal SiO2 polishing liquid with a pH of 8.0-9.0, and the surface roughness Ra of the all-black nano-encapsulation film after polishing is ≤ 0.2 μm;

[0033] The bottom surface roughness of the inverted-tapered copper column Ra is less than or equal to 0.1 μm, which is achieved by electrochemical polishing.

[0034] Furthermore, in S2, the star-shaped leveling agent is polyether-modified siloxane, and the added amount is 3±0.5% of the total mass of the all-black nano-encapsulation film.

[0035] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0036] (1) The present invention comprehensively improves the core problems of the existing technology, such as thermal expansion mismatch, thermal stress, shading and insulation balance, by selecting a PCB substrate with a better CTE match, adopting an inverted tapered copper pillar structure that can disperse stress, and utilizing a high-efficiency, high-insulation all-black nano-encapsulation film. It is expected to achieve a more reliable, lighter and thinner packaging structure with better performance.

[0037] (2) The present invention achieves a (111) crystal plane ratio of >85% through a pulse electroplating process, and the shear strength is increased to 220 MPa; the inverted cone structure can disperse stress by optimizing the cross-sectional moment of inertia, but the synergistic problem of crystal plane orientation and CTE mismatch has not yet been solved; the inverted cone structure of the present invention disperses bending stress by optimizing the cross-sectional moment of inertia (formula I = πr4 / 4), verifying the theoretical advantages of the inverted cone design.

[0038] (3) The packaging structure of the inverted cone-shaped copper column stress and core-shell nano-dispersion in the present invention has also broken through the industrialization barrier of the traditional glass substrate process (equipment investment > 500 million yuan, yield < 80%), and achieved the mass production capacity of small and medium-sized production lines (yield > 98%, investment ≤ 120 million yuan) for MicroLED modules with a PPI of more than 500. The present invention is also suitable for MicroLED giant screen TVs, educational electronic blackboards, all-in-one conference machines, AR / VR, high-end wearables, car displays and other scenarios, and is particularly suitable for high-density packaging of MicroLED display modules, solving the problems of thermal expansion mismatch, the contradiction between shading and insulation performance, and the high industrialization cost of small and medium-sized manufacturers. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0040] The packaging structure and method based on inverted tapered copper pillar stress and core-shell nano-dispersion of the present invention will be further described below with reference to the accompanying drawings;

[0041] Figure 1Schematic diagram of the inverted tapered copper pillar structure in the packaging structure based on inverted tapered copper pillar stress and core-shell nano-dispersion provided by the present invention;

[0042] Figure 2 This is a gradient pressing pressure-temperature time series curve diagram of Example 2 provided by the present invention;

[0043] Figure 3 The cost-yield-investment relationship curve diagram of Example 3 of the present invention is used;

[0044] Figure 4 This is a diagram showing the effect of blocking carrier tunneling using the silane layer of Example 2 of the present invention.

[0045] Description of the accompanying drawings: 1. Bottom substrate; 2. Inverted tapered copper pillar array. DETAILED DESCRIPTION

[0046] The following embodiments of the present invention are described in further detail with reference to the accompanying drawings and examples. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0047] In order to better understand the purpose, structure and function of the present invention, the present invention is further described in detail below with reference to the accompanying drawings.

[0048] Example 1

[0049] The present invention provides a packaging structure based on inverted tapered copper pillar stress and core-shell nano-dispersion, comprising: a bottom substrate 1, an inverted tapered copper pillar array and a full black nano-packaging film;

[0050] The inverted tapered copper pillar array is provided on the bottom substrate; the all-black nano-encapsulation film covers the inverted tapered copper pillar array;

[0051] The bottom substrate includes: a PCB substrate; the PCB substrate has a thermal expansion coefficient of 12-16 ppm / °C and a glass transition temperature of ≥180°C (IPC-4101 standard), and can replace a glass substrate to reduce costs;

[0052] like Figure 1 As shown, the inverted tapered copper pillar array includes: a plurality of inverted tapered copper pillars 2; each of the inverted tapered copper pillars 2 has a top diameter of 12-18 μm; a bottom diameter of 15-21 μm; a taper angle of 5-15°; and a height-to-diameter ratio of 1.5:1-2.5:1 (measured by SEM, with an error of ±0.5 μm);

[0053] In this embodiment, according to the elastic mechanics formula K=1+2(h / r)sinθ, when the cone angle θ of the inverted conical copper pillar 2 is 10° and the aspect ratio is 2:1, the stress concentration coefficient K drops from 3.2 to 1.6, and the peak stress drops from 120MPa→45MPa; while in this embodiment, the bottom diameter is 15-21μm; the aspect ratio is 1.5:1-2.5:1; the cone angle θ of the inverted conical copper pillar 2 is 5°-15°; the bottom surface roughness Ra of the inverted conical copper pillar 2 is ≤0.1μm, which is achieved by electrochemical polishing; when θ=10°, the (111) crystal plane of the inverted conical copper pillar 2 accounts for >85%, the shear strength is ≥220MPa, and the thermal stress peak is reduced by 62% compared with the prior art.

[0054] Because the geometric symmetry of traditional cylindrical copper pillars leads to stress concentration at the outer corners, their Von Mises stress can reach 120 MPa. However, the inverted tapered copper pillars have a taper angle θ of 5° to 15°, satisfying the following relationship: K = 1 + 2(h / r) sinθ ≤ 1.8, where h is the pillar height, r is the base radius, and θ is the taper angle. This significantly reduces the stress concentration factor to 1.6, resolving the problem of cracks caused by CTE mismatch.

[0055] Finite element simulation data show that when the diameter of the inverted tapered copper pillar 2 increases, the maximum equivalent stress at the outer corner and the bottom decreases significantly, which is consistent with the trend of stress concentration coefficient change predicted by the formula.

[0056] The (111) crystal plane of each inverted tapered copper pillar 2 accounts for more than 85% (XRD test, JCPDS 04-0836 standard), and the shear strength is increased to 220 MPa (ASTM D1002);

[0057] The thickness of the all-black nano-encapsulation film is 25-35 μm (laser thickness gauge test, ISO4593 standard), D50=30-50 nm (laser particle size analyzer test, ISO 13320 standard), and BET specific surface area ≥250 m 2 / g, volume resistivity>10 12 Ω·cm (IPC-TM-650 test, 25°C / 60%RH), light shielding rate ΔE=0.015 (spectrophotometer test, λ=550nm).

[0058] In this embodiment, when D50=30-50nm (silane modification) and the film thickness is 25-35μm, the light shielding rate ΔE=0.015 and the resistivity is 1.2×10 13 Ω·cm.

[0059] The distribution density of the inverted tapered copper pillar array is 1000-1500 / cm 2The distance between adjacent inverted tapered copper pillars is 50-80 μm.

[0060] Example 2

[0061] The present invention also provides a collaborative packaging method based on inverted tapered copper pillar stress and core-shell nano-dispersion, comprising the following steps:

[0062] S1, using an electroplating solution on the pads of the bottom substrate and forming an inverted tapered copper pillar array by pulse electroplating;

[0063] S2, coating a full black nano-encapsulation film on the inverted tapered copper pillar array, and controlling the film thickness of the full black nano-encapsulation film by slit coating; wherein the full black nano-encapsulation film comprises silane-modified nano-carbon black, modified epoxy resin, star-shaped leveling agent and bisphenol A epoxy resin microcapsule curing agent;

[0064] In this embodiment, the all-black nano-encapsulation film (thickness 25-35 μm, containing 20±2% silane-modified nano-carbon black, D50=30-50 nm, BET≥250 nm) 2 / g, volume resistivity>10 12 Ω·cm); (Volume resistivity is calculated using the formula T = exp(-ad / λ), λ = 550nm); the thermal weight loss rate of the all-black nano-encapsulation film at 200°C is less than 0.3% (TGA test); and the height loss of the copper pillar is less than 0.5μm.

[0065] Specifically, modified epoxy resin (75%, fluorine-containing grafting Tg = 160 ° C) + silane modified nano carbon black (20% ± 2%, D50 = 35nm, BET = 280m 2 / g) + star-shaped leveling agent (3%, viscosity 2500 cPs) + microcapsule curing agent (2%, 10 min delayed curing), epoxy resin penetrates the gaps between copper pillars, forming a dual interface of mechanical anchoring and chemical bonding; the volume resistivity is 1.2×10 13 Ω·cm (IPC-TM-650), which is 4 orders of magnitude higher than the traditional process.

[0066] Moreover, the 2-5nm SiO2 modified layer formed by the silane coupling agent (KH-560) formed by the all-black nano-encapsulation film has a contact angle from 75° to 110°, a filler spacing from 5nm to 8nm, and a quantum tunneling current density reduced to 10-15A / cm 2 (The calculation formula for quantum tunneling current density is like Figure 4 shown.

[0067] S3, performing gradient lamination on the all-black nano-encapsulation film and performing chemical mechanical polishing.

[0068] The plating solution includes but is not limited to 250±10g / L CuSO4·5H2O, 50±5ppm Cl - , 50±5g / LH2SO4 and 0.1±0.05ppm thiourea; 0.1±0.05ppm thiourea is used to inhibit dendrites.

[0069] When the thiourea concentration is greater than 0.15ppm, the copper pillar cone angle is out of control (θ>15°); when the thiourea concentration is less than 0.05ppm, the (111) crystal plane accounts for less than 70%; when the electroplating solution Cl-±10%, the yield changes from 98.5% to 97.2%, and the copper pillar diameter tolerance is ≤±0.5μm.

[0070] Therefore, this embodiment uses: 250±10g / L CuSO4·5H2O main salt to provide copper ions; 50±5ppmCl - , used to promote anodic dissolution; 50±5g / L H2SO4, used to improve solution conductivity; 0.1±0.05ppm thiourea, a crystal face regulator, used to inhibit (100) face dendrite growth.

[0071] In S1, during the pulse electroplating process, forward pulses and reverse pulses are alternately formed to form an inverted conical copper pillar array with a cone angle θ=10°±1° and a (111) crystal plane ratio greater than 80%.

[0072] In this embodiment, the pulse plating process (forward 20mA / cm 2 / 10ms+reverse 5mA / cm 2 / 2ms) makes the (111) crystal plane ratio of the inverted conical copper column greater than 80%, and increases the shear strength by 47% (150MPa→220MPa).

[0073] In S2, the film thickness of the all-black nano-encapsulation film is 30±2 μm, and the leveling time is 3 min;

[0074] The mass proportion of the alkane-modified nano-carbon black is 18-22%, and the KH-550 silane coupling agent is used. The surface hydroxyl content of the modified carbon black is less than 5%; the modified epoxy resin is 70-80%; the star-shaped leveling agent is 2-4%; and the bisphenol A epoxy resin microcapsule curing agent is 1-3%.

[0075] The fluorine-containing grafting rate of the modified epoxy resin is ≥15%; the glass transition temperature Tg of the modified epoxy resin is 160±5°C;

[0076] The slit coating speed is 10-15 m / min, the pre-curing temperature after coating is 80-90°C, and the pre-curing time is 2-5 minutes;

[0077] The particle size of the bisphenol A epoxy resin microcapsule is 5-10 μm, and the coverage rate is above 95%.

[0078] In said S3, the gradient pressing process includes: vacuum step, dynamic pressure and temperature control;

[0079] Among them, Figure 2 As shown, the vacuum ladder includes three stages: the first stage is at a pressure of 10 -3 Pa for 10 minutes, then -1 Maintain at Pa for 5 minutes and then return to normal pressure;

[0080] The dynamic pressure includes three stages: the first stage is: the initial pressure is 0; the second stage is: the pressure increases linearly from 0.5kg / min to 1kg / cm 2 The third stage is: continue to increase linearly at a rate of 1kg / min to 2kg / cm 2 , total time is 15 minutes.

[0081] Since the yield rate increases from 98.7% to 98.1% when the temperature of gradient pressing is ±5°C, the temperature threshold of gradient pressing in this embodiment is 105-115°C; the heating rate is 5°C / min, and the temperature in the insulation stage is controlled at 110±1°C and maintained for 20 minutes.

[0082] In said S3, chemical mechanical polishing includes using colloidal SiO2 with a pH of 8.0-9.0; the polishing liquid has Ra≤0.2 μm.

[0083] The bottom surface roughness of the inverted-tapered copper column Ra is less than or equal to 0.1 μm, which is achieved by electrochemical polishing.

[0084] In the above-mentioned S2, the star-shaped leveling agent is polyether-modified siloxane, and the added amount is 3±0.5% of the total mass.

[0085] Example 3

[0086] The present invention also compared with the competing products to test the crack rate of 500 hot and cold cycles and the resistivity of 85℃ / 85%RH 1000h. Figure 4 As shown, we get:

[0087] The crack rate of Huaxing CT-2024 (glass substrate) after 500 hot and cold cycles is 8.7%, while the crack rate of the present invention after 500 hot and cold cycles is 0.2%;

[0088] The resistivity of Huaxing CT-2024 (glass substrate) decreased by 82% after being exposed to 85°C / 85% RH for 1000 hours, while the resistivity of the glass substrate of the present invention decreased by less than 5% after being exposed to 85°C / 85% RH for 1000 hours.

[0089] Example 4

[0090] 1. This embodiment provides the thermal stress peak, crack rate, shear strength and (111) crystal plane ratio of the inverted conical copper pillar when the cone angle θ is 5°, 10° and 15° respectively, as shown in Table 1:

[0091] Table 1

[0092]

[0093]

[0094] The stress concentration factor at different cone angles was calculated using the elastic mechanics formula K = 1 + 2(h / r) sinθ. Experimental data showed that when the cone angle θ = 10° and the aspect ratio was 2:1, the peak stress of the copper pillar dropped to 45 MPa, which is highly consistent with the value predicted by the formula (K = 1.6), verifying the effectiveness of the inverted cone design.

[0095] Conclusion: The comprehensive performance is optimal when the cone angle θ=10°, which verifies the rationality of the cone angle range of 5-15°.

[0096] To verify the universality of the cone angle range (5°-15°), long-term reliability test data under extreme parameters is supplemented (see Table 8):

[0097] Test standards: Temperature cycling (IPC-9701), damp heat aging (JEDEC JESD22-A101D), mechanical shock (MIL-STD-883H).

[0098] Conclusion: Even if the cone angle is 5° or 15°, the crack rate (0.25%-0.3%) is still significantly lower than that of the traditional cylindrical structure (>8%), proving the rationality of the "cone angle 5-15°" in the claim.

[0099] 2. This example provides the effects of different thiourea concentrations on the electroplating process, see Table 2:

[0100] Table 2

[0101]

[0102] Conclusion: When the thiourea concentration is 0.1±0.05ppm, the process stability is optimal.

[0103] 3. This example provides the effects of different thicknesses of the all-black nanofilm on light shielding rate, volume resistivity, damp heat aging degradation, and adhesion, as shown in Table 3:

[0104] Table 3

[0105]

[0106]

[0107] Conclusion: The comprehensive performance is best when the film thickness is 30±5μm.

[0108] 4. This embodiment shows the specific test data of different test items under various test conditions for the packaging structure of the present invention, see Table 4:

[0109] Table 4

[0110]

[0111]

[0112] 5. This embodiment also provides a comparison of the industrialization costs between the PCB substrate of the present invention and the traditional process, see Table 5:

[0113] Table 5

[0114]

[0115] Note: Explanation of key elastic mechanics formulas and parameters used in the examples

[0116] (1) Relationship between Hooke's law and thermal stress:

[0117] σ=E·ɑ·△T

[0118] Where: σ is thermal stress, E is elastic modulus, ɑ is thermal expansion coefficient, and △T is temperature change.

[0119] Application Scenario: Explain the CTE mismatch between PCB substrates (CTE = 12-16 ppm / °C) and copper pillars (CTE = 17 ppm / °C) and quantify the source of thermal stress.

[0120] (2) Bending stress formula for thin-walled structures:

[0121] σ bend =(M·y) / I

[0122] Where: M is the bending moment, y is the distance from the neutral axis, and I is the moment of inertia of the area.

[0123] Application scenario: The inverted tapered copper column disperses bending stress by optimizing the cross-sectional moment of inertia (larger bottom diameter), thus avoiding stress concentration in traditional cylindrical structures.

[0124] (3) Von Mises stress criterion:

[0125] σ vm =√[(σ1-σ2) 2 +(σ2-σ3) 2 +(σ3-σ1)2 ] / 2

[0126] Application scenarios: Combined with finite element simulation results, it is shown that the Von Mises stress distribution of the inverted tapered copper pillar is more uniform, verifying its crack resistance advantage.

[0127] Example 5

[0128] This embodiment provides an in-depth comparative analysis of the present invention and the prior art in terms of core structure, packaging materials, process technology, thermal stress performance, cost and industrialization, long-term reliability, and applicable scenarios.

[0129] 1. Technology comparison table (innovation and technical barriers of the present invention compared with existing technologies), see Table 6:

[0130] Table 6

[0131]

[0132]

[0133]

[0134]

[0135]

[0136] The present invention summarizes the technical barriers relative to the prior art:

[0137] a. Structural innovation: Inverted tapered copper column design + crystal orientation control solves the stress concentration problem of traditional cylindrical structures.

[0138] b. Material breakthrough: Ultrafine nano-carbon black (D50 = 30-50nm) and silane modification technology balance the light-shielding and insulation contradictions.

[0139] c. Process collaboration: pulse plating + gradient pressing to achieve low-cost, high-yield mass production.

[0140] d. Cost advantage: PCB substrates replace glass substrates, reducing the investment threshold by 76%, making it suitable for small and medium-sized manufacturers.

[0141] e. Performance crushing: core indicators such as crack rate, resistivity, thermal stress, etc. are comprehensively superior to existing technologies.

[0142] 2. A technical comparison between the present invention and the existing technologies (BOE and Corning) in terms of substrate type, thermal stress and crack rate, packaging materials, and industrialization cost is shown in Table 7:

[0143] Table 7

[0144]

[0145]

[0146]

[0147]

[0148] 3. Extreme parameter experimental data

[0149] Experiment 1: The present invention provides long-term reliability tests when the cone angles of the inverted tapered copper pillars are 5°, 10°, and 15°, as shown in Table 8:

[0150] The test conditions are:

[0151] Temperature Cycle: 1000 cycles (IPC-9701 standard)

[0152] Damp heat aging: 85°C / 85% RH, 2000 hours (JEDEC JESD22-A101D standard)

[0153] Mechanical shock: 15,000 times / 0.5ms (MIL-STD-883H Method 2002 standard)

[0154] Table 8

[0155]

[0156]

[0157] in conclusion:

[0158] When the cone angles are 5° and 15°, the performance is still better than that of the traditional cylindrical structure (crack rate > 8%); therefore, the rationality of the cone angle range (5-15°) is verified, and the industrialization requirements are still met under extreme parameters.

[0159] Experiment 2: Dendrite risk analysis at thiourea concentrations of 0.05ppm and 0.15ppm, see Table 9: Test method:

[0160] Electron microscopy observation: SEM analysis of the dendrite density (number of dendrites per unit area) on the surface of the copper pillar.

[0161] Electrochemical testing: Cyclic voltammetry (CV) was used to evaluate the dendrite activity.

[0162] Yield statistics: process stability test of 1000 samples.

[0163] Table 9

[0164]

[0165]

[0166] in conclusion:

[0167] When the thiourea concentration deviates from the optimal value (0.1±0.05ppm), the risk of dendrites increases significantly, but it is still better than the traditional thiourea-free process (dendrite density>20 / μm 2 ).

[0168] This example verifies the process stability within the thiourea concentration range of the present invention, and the process is controllable even at extreme concentrations.

[0169] The technical advantages of the present invention are summarized as follows:

[0170] a. Comprehensive coverage of competitor pain points:

[0171] Compared with the glass substrate solutions of BOE and Corning, the present invention completely solves the problems of CTE mismatch, high cost and thick film through the design of PCB substrate + inverted tapered copper pillars;

[0172] The insulation-light-shielding balance performance of the all-black nano-encapsulation film surpasses traditional packaging materials from Samsung, Apple and other companies.

[0173] b. Extreme parameter reliability verification:

[0174] Indicators such as crack rate and resistivity at cone angles of 5° and 15° are still significantly better than industry standards; the dendrite risk at a thiourea concentration of 0.05-0.15ppm is controllable, supporting the rationality of the claim scope.

[0175] c. By optimizing the copper pillar crystal plane orientation ((111) crystal plane ratio>80%) and the all-black nanofilm (D50=30-50nm, volume resistivity>10 12 Ω·cm), solving the problems of thermal expansion mismatch, light shielding-insulation contradiction, and high cost. This structure exhibits a crack rate of only 0.2% under cycling conditions from -40°C to 85°C, and a resistivity drop of <5% after damp heat aging, making it suitable for mass production of MicroLED modules (yield >98%, investment ≤120 million yuan).

[0176] Example 6

[0177] The present invention is explained with reference to the accompanying drawings through the following tables:

[0178] 1. The present invention is Figure 1 The following explanations are given:

[0179] Inverted tapered copper pillar structure: stress distribution simulated using ANSYS Mechanical (mesh accuracy 0.1 μm); color mapping: MATLAB post-processing script (HSV color scale);

[0180] Angle measurement: SEM image analysis (JEOL JSM-7800F, error ±0.5°);

[0181] Size measurement: Laser confocal microscope (Olympus LEXT OLS5000,

[0182] ±0.1μm); specifically: height (h) = 60μm, bottom radius (r) = 30μm, ratio 2:1;

[0183] (111) The atomic structure of the crystal plane is an atomic-level view showing a face-centered cubic lattice with hexagonal symmetry and an interplanar spacing of 0.208 nm. Crystal plane analysis: High-resolution transmission electron microscopy (HRTEM, JEOL JEM-ARM300F);

[0184] Fiber diameter of PCB fiber structure: SEM measurement (JEOL JSM-7800F); resin composition: Fourier transform infrared spectroscopy (FTIR, Thermo Nicolet iS50);

[0185] Scale bar calibration: NIST standard sample (SRM 4840); grid generation: ImageJ software (Fiji plug-in).

[0186] 2. The present invention is shown in Table 10. Figure 2 The following explanations are given:

[0187] Table 10: Figure 2 Annotation table (gradient pressing pressure-temperature time series curve)

[0188]

[0189]

[0190] 3. The present invention provides the following explanations on the SiO2 modified layer:

[0191] 1) The thickness of the 2-5 nm SiO2 modified layer was measured by high-resolution TEM (JEOL JEM-ARM300F, ±0.1 nm);

[0192] 2) The contact angle of the SiO2 modified layer was measured from 75° to 110° using an optical contact angle meter (Dataphysics OCA50, ASTM D7334);

[0193] 3) The filler spacing of the SiO2 modified layer is 5nm→8nm, and the spacing analysis is as follows: Spacing analysis: TEM image measurement (ImageJ software, ±0.5nm);

[0194] 4) The tunneling current formula is: Quantum mechanics simulation (COMSOL Multiphysics, equation);

[0195] 5) Technical comparison: In a comparative experiment, the same batch of samples was divided into two groups (modified group / control group);

[0196] 6) Scientific annotation: scale calibration, NIST standard sample (SRM 4840); grid generation: Gwyddion software. 4. The present invention uses Table 13 to Figure 3 The following explanations are given:

[0197] 4. The present invention is Figure 3 The following explanations are given:

[0198] 1) Cost data is calculated based on the SEMI E10 standard; yield statistics are based on a 10,000-piece pilot production batch (IPC-A-600).

[0199] 2) Economic model: Excel capacity-cost model (ROI ≥ 15%);

[0200] 3) Pain point data source: competitor patent examples (US20220165432A1, CN118034768A);

[0201] 4) Coordinate calibration: MATLAB 3D drawing tool (meshgrid function);

[0202] 5) Three-axis precise marking: X = investment (100 million yuan), Y = yield (%), Z = cost (USD / dm 2 ).

[0203] 5. The present invention is shown in Table 11. Figure 4 The following explanations are given:

[0204] Table 11: Figure 4 Annotation Table (Silane layer blocking carrier tunneling effect diagram)

[0205]

[0206]

[0207] Example 7 (extreme environment verification):

[0208] The test conditions are:

[0209] 1) High temperature and high humidity: 125℃ / 95%RH, continuous 2000 hours

[0210] 2) Low temperature shock: 1000 cycles.

[0211] Performance data are shown in Table 12:

[0212] Table 12 Performance data

[0213] Test items The present invention Traditional process (glass substrate) Resistivity change +3％ +92％ Interface shedding rate 0.05％ 5.2％ Shear strength retention rate 95％ 58％

[0214] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A packaging structure based on inverted tapered copper pillar stress and core-shell nano-dispersion, characterized in that: include: bottom substrate, inverted tapered copper pillar array, and all-black nano-encapsulation film; The inverted tapered copper pillar array is provided on the bottom substrate; The all-black nano-encapsulation film covers the inverted tapered copper pillar array; The bottom substrate includes: a PCB substrate; the thermal expansion coefficient of the PCB substrate is 12-16 ppm / °C, and the glass transition temperature is ≥180°C; The inverted tapered copper pillar array comprises: a plurality of inverted tapered copper pillars; each of the inverted tapered copper pillars has a top diameter of 12-18 μm; a bottom diameter of 15-21 μm; an aspect ratio of 1.5:1-2.5:1; a taper angle θ of the inverted tapered copper pillars is 5°-15°; and a bottom surface roughness Ra of the inverted tapered copper pillars is ≤0.1 μm; The thickness of the all-black nano-encapsulation film is 25-35 μm, D50=30-50 nm, and the BET specific surface area is ≥250 m 2 / g, volume resistivity>10 12 Ω·cm.

2. The packaging structure based on inverted tapered copper pillar stress and core-shell nano-dispersion according to claim 1, characterized in that: The distribution density of the inverted tapered copper pillar array is 1000-1500 / cm 2 The distance between adjacent inverted tapered copper pillars is 50-80 μm.

3. A packaging method based on inverted tapered copper pillar stress and core-shell nano-dispersion, applied to the packaging structure based on inverted tapered copper pillar stress and core-shell nano-dispersion according to any one of claims 1-2, characterized in that: The following steps are involved: S1, using an electroplating solution on the pads of the bottom substrate and forming an inverted tapered copper pillar array by pulse electroplating; S2, coating a full black nano-encapsulation film on the inverted tapered copper pillar array, and controlling the film thickness of the full black nano-encapsulation film by slit coating; wherein the full black nano-encapsulation film comprises silane-modified nano-carbon black, modified epoxy resin, star-shaped leveling agent and bisphenol A epoxy resin microcapsule curing agent; S3, performing gradient pressing on the all-black nano-encapsulation film and performing chemical mechanical polishing.

4. The packaging method based on inverted tapered copper pillar stress and core-shell nano-dispersion according to claim 3, characterized in that: In S1, the plating solution includes: 250±10g / L CuSO4·5H2O, 50±5ppm Cl - , 50±5g / L H2SO4 and 0.1±0.05ppm thiourea.

5. The packaging method based on inverted tapered copper pillar stress and core-shell nano-dispersion according to claim 3, characterized in that: In S1, during the pulse electroplating process, forward pulses and reverse pulses are alternately formed to form an inverted conical copper pillar array with a cone angle θ=10°±1° and a (111) crystal plane ratio greater than 85%.

6. The packaging method based on inverted tapered copper pillar stress and core-shell nano-dispersion according to claim 5, characterized in that: The current density of the forward pulse is 20 mA / cm 2 , the duration is 10 milliseconds; the current density of the reverse pulse is 5 mA / cm 2 , with a duration of 2 milliseconds.

7. The packaging method based on inverted tapered copper pillar stress and core-shell nano-dispersion according to claim 3, characterized in that: In S2, the film thickness of the all-black nano-encapsulation film is 30±2 μm, and the leveling time is 3 min; The alkyl-modified nano-carbon black adopts KH-550 silane coupling agent, and the surface hydroxyl content of the carbon black obtained after modification is less than 5%; the modified epoxy resin is 70-80%; the star-shaped leveling agent is 2-4%; the bisphenol A epoxy resin microcapsule curing agent is 1-3%; the mass proportion of the alkyl-modified nano-carbon black is 18-22%, The fluorine-containing grafting rate of the modified epoxy resin is ≥15%; the glass transition temperature Tg of the modified epoxy resin is 160±5°C; The slit coating speed is 10-15 m / min, the pre-curing temperature after coating is 80-90°C, and the pre-curing time after coating is 2-5 minutes; The particle size of the bisphenol A epoxy resin microcapsule is 5-10 μm, and the coverage rate is 95%.

8. The packaging method based on inverted tapered copper pillar stress and core-shell nano-dispersion according to claim 3, characterized in that: In said S3, the gradient pressing process includes: vacuum step, dynamic pressure and temperature control; The vacuum ladder includes three stages: first, at a pressure of 10 -3 Pa for 10 minutes, then -1 Maintain at Pa for 5 minutes and then return to normal pressure; The dynamic pressure includes three stages: the first stage is: the initial pressure is 0; the second stage is: the pressure increases linearly from 0.5kg / min to 1kg / cm 2 The third stage is: continue to increase linearly at a rate of 1kg / min to 2kg / cm 2 , total time is 15 minutes; The temperature threshold of the gradient lamination is 105-115° C.; the heating rate is 5° C. / min, the temperature is controlled at 110±1° C., and maintained for 20 minutes.

9. The packaging method based on inverted tapered copper pillar stress and core-shell nano-dispersion according to claim 3, characterized in that: In said S3, chemical mechanical polishing uses colloidal SiO2 polishing liquid with a pH of 8.0-9.0, and the surface roughness Ra of the all-black nano-encapsulation film after polishing is ≤ 0.2 μm; The bottom surface roughness of the inverted-tapered copper column Ra is less than or equal to 0.1 μm, which is achieved by electrochemical polishing.

10. The packaging method based on inverted tapered copper pillar stress and core-shell nano-dispersion according to claim 3, characterized in that: In the above-mentioned S2, the star-shaped leveling agent is polyether-modified siloxane, and the added amount is 3±0.5% of the total mass of the all-black nano-encapsulation film.

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