Display device, method for manufacturing display device, and head mounted display

Abstract

The invention provides a display device, a method for manufacturing the display device, and a head-mounted display. The display device includes: an insulating layer disposed on a substrate; the first electrode is arranged on the insulating layer; a first pixel defining layer covering a portion of the first electrode; a second pixel defining layer disposed on the first pixel defining layer; a trench penetrating the first pixel defining layer and the second pixel defining layer; a light emitting stack disposed on an upper surface of the first electrode and an upper surface of the second pixel defining layer; and a second electrode disposed on the light emitting stack. A width of an inlet of the groove in one direction is greater than a width of a lower surface of the groove in the one direction.

Description

Technical Field

[0001] Aspects of one or more embodiments of the present disclosure relate to a display device, a method for manufacturing the display device, and a head-mounted display including the display device. Background Art

[0002] A head-mounted display (HMD) is an image display device worn on the user's head in the form of glasses or a helmet, with the image focused at a close distance in front of the user's eyes. A head-mounted display can realize virtual reality (VR) or augmented reality (AR).

[0003] A head-mounted display magnifies an image displayed in a small display device by using multiple lenses and displays the magnified image. Therefore, the display device applied to the head-mounted display needs to provide a high-resolution image, for example, an image with a resolution of 3000 PPI (pixels per inch) or higher. For this purpose, an organic light-emitting diode on silicon (OLEDoS), which is a high-resolution small organic light-emitting display device, is used as a display device applied to the head-mounted display. OLEDoS is an image display device in which an organic light-emitting diode (OLED) is provided on a semiconductor wafer substrate including a complementary metal oxide semiconductor (CMOS).

[0004] It will be understood that this background technology section is intended, in part, to provide a useful background for understanding the technology. However, this background technology section may also include ideas, concepts, or realizations that were not already known or understood as part of the subject matter disclosed herein before the corresponding effective filing date by those skilled in the relevant art. Summary of the Invention

[0005] Aspects of the present disclosure include a display device capable of providing high-resolution images.

[0006] Aspects of the present disclosure include a method for manufacturing a display device capable of providing high-resolution images.

[0007] Aspects of the present disclosure include a head-mounted display capable of providing high-resolution images.

[0008] However, the embodiments are not limited to those set forth herein. The above and other embodiments will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given hereinafter.

[0009] According to the present disclosure, a display device may include: an insulating layer disposed on a substrate; a first electrode disposed on the insulating layer; a first pixel-defining layer covering a portion of the first electrode; a second pixel-defining layer disposed on the first pixel-defining layer; a groove penetrating the first pixel-defining layer and the second pixel-defining layer; a light-emitting stack disposed on upper surfaces of the first electrode and the second pixel-defining layer; and a second electrode disposed on the light-emitting stack. A width of an entrance of the groove in one direction is greater than a width of a lower surface of the groove in the one direction.

[0010] A length of a sidewall of the trench defined by the insulating layer may be greater than a length of a sidewall of the trench defined by the first pixel defining layer and the second pixel defining layer.

[0011] The height of the groove can be from about to approximately within the range.

[0012] The display device may further include: a third pixel defining layer disposed on the second pixel defining layer. The groove may penetrate the third pixel defining layer.

[0013] A sum of the thickness of the first pixel defining layer, the thickness of the second pixel defining layer, and the thickness of the third pixel defining layer may be less than or equal to about 1 / 4 of the height of the trench.

[0014] An angle formed between an upper surface of the third pixel defining layer and a tangent line of a sidewall of the trench at the entrance of the trench may be in a range of about 80° to about 90°.

[0015] The light emitting stack may include: a first stack layer disposed at an edge of the entrance of the groove; and a second stack layer disposed on the first stack layer.

[0016] The light emitting stack may further include a third stack layer disposed on the second stack layer, wherein the third stack layer covers the entrance of the groove.

[0017] The display device may further include: a third pixel defining layer disposed on the second pixel defining layer. The third pixel defining layer may be disposed on the sidewalls of the groove and the lower surface.

[0018] The light emitting stack may include: a first stack layer disposed on the third pixel defining layer; and a second stack layer disposed on the first stack layer.

[0019] A thickness of a portion of the first stacked layer disposed on a sidewall of the trench defined by the insulating layer may be smaller than a thickness of a portion of the first stacked layer disposed on the lower surface of the trench.

[0020] A thickness of a portion of the first stacked layer disposed on a sidewall of the trench defined by the second pixel defining layer may be greater than a thickness of a portion of the first stacked layer disposed on a sidewall of the trench defined by the insulating layer.

[0021] The light emitting stack may further include a third stack layer disposed on the second stack layer, wherein the third stack layer covers the entrance of the groove.

[0022] According to the present disclosure, a method for manufacturing a display device may include: forming an insulating layer on a substrate, and forming a plurality of first electrodes on the insulating layer; forming a pixel-defining layer covering the plurality of first electrodes; forming a plurality of grooves penetrating the pixel-defining layer; etching the pixel-defining layer to form a pixel-defining layer to partially expose each of the plurality of first electrodes; forming a first stacked layer on a portion of each of the plurality of first electrodes and the pixel-defining layer; forming a second stacked layer on the first stacked layer; and forming a second electrode covering the second stacked layer. The first stacked layer is disposed at an edge of an entrance of the groove, and the second stacked layer covers the entrance of the groove.

[0023] The forming of the pixel defining layer may include forming a first pixel defining layer covering the plurality of first electrodes, forming a second pixel defining layer covering the first pixel defining layer, and forming a third pixel defining layer covering the second pixel defining layer.

[0024] The etching of the pixel defining layer to form a pixel defining layer to locally expose each of the multiple first electrodes may include: forming a first mask pattern on a portion of the third pixel defining layer, and etching portions of the third pixel defining layer not covered by the first mask pattern to form a third pixel defining layer; forming a second mask pattern on a portion of the second pixel defining layer and all portions of the third pixel defining layer, and etching portions of the second pixel defining layer not covered by the second mask pattern to form a second pixel defining layer; and forming a third mask pattern on a portion of the first pixel defining layer, all portions of the second pixel defining layer, and all portions of the third pixel defining layer, and etching portions of the first pixel defining layer not covered by the third mask pattern to locally expose each of the multiple first electrodes.

[0025] According to the present disclosure, a method for manufacturing a display device may include: forming an insulating layer on a substrate and forming a plurality of first electrodes on the insulating layer; forming a first pixel defining layer covering the plurality of first electrodes and forming a second pixel defining layer on the first pixel defining layer; forming a plurality of trenches penetrating the first pixel defining layer and the second pixel defining layer; forming a third pixel defining layer on the second pixel defining layer; etching each of the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer to form a first pixel defining layer, a second pixel defining layer, and a third pixel defining layer to partially expose each of the plurality of first electrodes; forming a first stacked layer on a portion of each of the plurality of first electrodes, the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer; forming a second stacked layer on the first stacked layer; and forming a second electrode covering the second stacked layer. The third pixel defining layer is disposed on the sidewalls and lower surface of the trench. The first stacked layer is disposed on the third pixel defining layer. The second stacked layer covers the entrance of the trench.

[0026] The forming of the first pixel defining layer and the second pixel defining layer may include: forming a first pixel defining layer covering the plurality of first electrodes; and forming a second pixel defining layer covering the first pixel defining layer.

[0027] The etching of each of the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer to form the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer to locally expose each of the multiple first electrodes may include: forming a first mask pattern on a portion of the third pixel defining layer, and etching the portion of the third pixel defining layer not covered by the first mask pattern to form a third pixel defining layer; forming a second mask pattern on a portion of the second pixel defining layer and all portions of the third pixel defining layer, and etching the portion of the second pixel defining layer not covered by the second mask pattern to form a second pixel defining layer; and forming a third mask pattern on a portion of the first pixel defining layer, all portions of the second pixel defining layer, and all portions of the third pixel defining layer, and etching the portion of the first pixel defining layer not covered by the third mask pattern to locally expose each of the multiple first electrodes.

[0028] According to the present disclosure, a head-mounted display may include: at least one display device; a display device housing accommodating the at least one display device; and an optical member that amplifies a display image of the at least one display device or changes an optical path. The at least one display device may include: an insulating layer disposed on a substrate; a first electrode disposed on the insulating layer; a first pixel-defining layer covering a portion of the first electrode; a second pixel-defining layer disposed on the first pixel-defining layer; a groove penetrating the first pixel-defining layer and the second pixel-defining layer; a light-emitting stack disposed on the upper surface of the first electrode and the upper surface of the second pixel-defining layer; and a second electrode disposed on the light-emitting stack. The width of the entrance of the groove in one direction is greater than the width of the lower surface of the groove in the one direction.

[0029] According to the present disclosure, the first stacked layer, the second stacked layer, and the charge generation layer between the first and second stacked layers can be cut off by multiple grooves. Therefore, it is possible to prevent the current flowing in each of the multiple sub-pixels from flowing to the adjacent sub-pixels via the charge generation layer.

[0030] According to the present disclosure, a plurality of grooves can be formed by a photolithography process using argon fluoride (ArF) as a light source, so that the width of the groove entrance can be formed to be greater than about 100 nm and less than about 130 nm. Therefore, the first stacked layer, the second stacked layer, and the charge generation layer between the first stacked layer and the second stacked layer can be reliably cut off in the grooves.

[0031] According to the present disclosure, when a groove is formed by a photolithography process using krypton fluoride (KrF), it is difficult to control the width of the entrance of the groove to be less than about 130nm. Therefore, the third pixel defining layer can be formed on the sidewall and lower surface of the groove. Therefore, the width of the entrance of the groove can be formed to be greater than about 100nm and less than about 130nm by the third pixel defining layer, so that the first stacked layer, the second stacked layer, and the charge generation layer between the first stacked layer and the second stacked layer can be reliably cut off in the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other embodiments and features of the present disclosure will become more apparent by describing aspects of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is an exploded schematic perspective view showing a display device according to an embodiment;

[0034] Figure 2 is a block diagram showing a display device according to an embodiment;

[0035] Figure 3is a schematic diagram of an equivalent circuit of a first sub-pixel according to an embodiment;

[0036] Figure 4 is a plan view showing an example of a display panel according to an embodiment;

[0037] Figure 5 and Figure 6 It shows Figure 4 A plan view of an embodiment of a display area;

[0038] Figure 7 It is shown along Figure 5 A schematic cross-sectional view of an example of a display panel taken along line I1-I1';

[0039] Figure 8 It is shown in detail Figure 7 A schematic cross-sectional view of a region A1 of FIG.

[0040] Figure 9 It shows Figure 8 A schematic cross-sectional view of an example of a region A2;

[0041] Figure 10 It shows Figure 7 A schematic cross-sectional view of another example of a region A1;

[0042] Figure 11 It shows Figure 10 A schematic cross-sectional view of an example of a region A3;

[0043] Figure 12 is a flowchart illustrating a method for manufacturing a display device (including a display panel) according to an embodiment;

[0044] Figures 13 to 18 is a schematic cross-sectional view showing a region A1 in detail to describe a method for manufacturing a display device (including a display panel) according to an embodiment;

[0045] Figure 19 is a flowchart illustrating a method for manufacturing a display device (including a display panel) according to an embodiment;

[0046] Figures 20 to 24 is a schematic cross-sectional view showing a region A1 in detail to describe a method for manufacturing a display device (including a display panel) according to an embodiment;

[0047] Figure 25 is a schematic perspective view showing a head-mounted display according to an embodiment;

[0048] Figure 26 It shows Figure 25 an exploded schematic perspective view of an example of a head-mounted display; and

[0049] Figure 27 is a schematic perspective view showing a head-mounted display according to the embodiment. DETAILED DESCRIPTION

[0050] By referring to the detailed description of the embodiments and the accompanying drawings, the aspects and features of the embodiments of the present disclosure and the methods for realizing these aspects and features can be more easily understood. Hereinafter, the aspects of the embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various different forms and should not be interpreted as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described.

[0051] Unless otherwise noted, throughout the drawings and written description, like reference numerals, characters or combinations thereof represent like elements, and therefore, description thereof will not be repeated. In addition, for clarity of description, parts (parts) not relevant to the description of one or more embodiments may not be shown.

[0052] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, sizes, proportions, commonalities between illustrated elements, and / or any other features, attributes, characteristics, etc. for elements.

[0053] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Furthermore, the structural or functional descriptions disclosed herein are for the purpose of describing embodiments according to the present disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the specific illustrated shapes of the regions, but rather include deviations in shapes due to, for example, manufacturing.

[0054] For example, an implanted region shown as a rectangle may have rounded or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may produce some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to be limiting. Furthermore, as will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the scope of the present disclosure.

[0055] In the detailed description, for purposes of explanation, numerous details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these details or with one or more equivalent arrangements. In other instances, structures and devices may be shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0056] For ease of explanation, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as being "under" or "below" or "below" another element or feature will subsequently be positioned as being "above" the other element or feature. Thus, the example terms "under" or "below" can encompass both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used herein should be interpreted accordingly. Similarly, when a first component is described as being arranged "on" a second component, this indicates that the first component is arranged at the upper or lower side of the second portion, and is not limited to its upper side based on the direction of gravity.

[0057] The term "overlap" or "overlapped" means that a first object may be above or below a second object or on one side of the second object, and vice versa. In addition, the term "overlap" or "overlapped" may include layering, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0058] The terms "facing" and "facing" indicate that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other but still facing each other.

[0059] When an element is described as “not overlapping or to not overlap” another element, this may include the elements being spaced apart, offset or separated from each other, or any other suitable terminology as will be appreciated and understood by one of ordinary skill in the art.

[0060] Furthermore, in this specification, the phrase “on a plane” or “in a plan view” means observing a target portion from the top, and the phrase “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0061] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "coupled to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, on, directly connected to, or directly coupled to the other element, layer, region, or component, such that one or more intervening elements, layers, regions, or components may exist. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or electrically coupled to the other layer, region, and / or component, or there may be intervening layers, regions, or components. However, "directly connected / directly coupled" refers to one component being directly connected or directly coupled to another component without an intervening component. Other expressions such as "between," "directly between," or "adjacent to," and "directly adjacent to," that describe a relationship between components may be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0062] For the purposes of this disclosure, expressions such as “at least one of,” “one of,” and “at least one selected from” when following a list of elements modify the entire list of elements, rather than the individual elements in the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as meaning only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ, or any variation thereof). Similarly, expressions such as “at least one of A and B” may include A, B, or both.

[0063] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, a statement such as "A and / or B" may include A, B, or A and B. In addition, when describing embodiments of the present disclosure, the use of "may" refers to one or more embodiments of the present disclosure.

[0064] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section described below may be referred to as a second element, component, region, layer, or section without departing from the scope of this disclosure.

[0065] In this example, the first direction DR1, the second direction DR2, and / or the third direction DR3 are not limited to directions indicated by the three axes of a rectangular coordinate system and can be interpreted in a broad sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the X direction, the Y direction, and / or the Z direction.

[0066] The terms used herein are for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are also intended to include the plural forms.

[0067] It will also be understood that when used in this specification, the terms “comprises,” “comprising,” “have,” “having,” and “includes,” “including,” specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0068] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account the measurements in question and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within the range of acceptable deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0069] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in a reverse order to the described order.

[0070] Moreover, any numerical range disclosed and / or listed herein is intended to include all subranges of the same numerical precision contained in the listed range. For example, the range of "1.0 to 10.0" is intended to include all subranges between the listed minimum value of 1.0 and the listed maximum value of 10.0 (and including the listed minimum value of 1.0 and the listed maximum value of 10.0), for example, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0 (such as 2.4 to 7.6). Any maximum numerical limit listed herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit listed in this specification is intended to include all higher numerical limits contained therein.

[0071] The electronic devices or electrical devices and / or any other related devices or any other related components described herein according to one or more embodiments of the present disclosure can be implemented using any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0072] In addition, the various components of these devices can be processes or threads that run in one or more computing devices, on one or more processors, execute computer program instructions and interact with other system components to perform the various functions described herein. Computer program instructions are stored in a memory that can be implemented in a computing device using a standard memory device (such as a random access memory (RAM) as an example). Within the scope of the present disclosure, computer program instructions may also be stored in other non-transitory computer-readable media (such as a read-only compact disc memory (CD-ROM) or a flash drive, etc. as an example). Moreover, it should be appreciated by those skilled in the art that, without departing from the scope of the present disclosure, the functions of the various computing devices may be combined or integrated into a single computing device, or the functions of the computing device may be distributed among one or more other computing devices.

[0073] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technical field and / or in the specification, and should not be interpreted in an idealized or overly formal sense.

[0074] Figure 1 is an exploded schematic perspective view showing a display device according to an embodiment. Figure 2 is a block diagram illustrating a display device according to an embodiment.

[0075] Reference Figure 1 and Figure 2, the display device 10 according to the embodiment is a device that displays a moving image or a still image. Within the scope of the present disclosure, the display device 10 according to the embodiment can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 according to the embodiment can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) terminal. For example, within the scope of the present disclosure, the display device 10 according to the embodiment can be applied to smart watches, watch phones, and head-mounted displays (HMDs) for realizing virtual reality and augmented reality.

[0076] The display device 10 according to the embodiment may include a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0077] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a selected curvature. The planar shape of the display panel 100 is not limited to a quadrilateral and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the embodiments of the present specification are not limited thereto.

[0078] The display panel 100 may include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, a plurality of data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. Figure 2 As shown in FIG, the display panel 100 may be divided into a display area DAA where an image is displayed and a non-display area NDA where no image is displayed.

[0079] A plurality of pixels PX may be provided in the display area DAA. The plurality of pixels PX may be arranged or disposed in a matrix in a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 and be disposed in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and be disposed in the first direction DR1.

[0080] The plurality of scan lines SL may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0081] The plurality of pixels PX includes a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include Figure 3 The plurality of pixel transistors shown in FIG. 3 and FIG. 4 can be formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see FIG. 3 ). Figure 7 For example, the plurality of pixel transistors of the plurality of sub-pixels SP1, SP2, and SP3 may be formed of a complementary metal oxide semiconductor (CMOS), but the embodiments of the present specification are not limited thereto.

[0082] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to any one of a plurality of write scan lines GWL, any one of a plurality of control scan lines GCL, any one of a plurality of bias scan lines EBL, any one of a plurality of first emission control lines EL1, any one of a plurality of second emission control lines EL2, and any one of a plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and emit light from the light-emitting element according to the data voltage.

[0083] The scan driver 610 , the emission driver 620 , and the data driver 700 may be disposed in the non-display area NDA.

[0084] The scan driver 610 may include a plurality of scan transistors, and the emission driver 620 may include a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 7 For example, the plurality of scanning transistors and the plurality of light emitting transistors may be formed by CMOS, but the embodiments of the present specification are not limited thereto.

[0085] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400 (timing controller). The write scan signal output unit 611 may generate a plurality of write scan signals based on the scan timing control signal SCS from the timing control circuit 400 and sequentially output them to the write scan line GWL. The control scan signal output unit 612 may generate a plurality of control scan signals in response to the scan timing control signal SCS and sequentially output them to the control scan line GCL. The bias scan signal output unit 613 may generate a plurality of bias scan signals based on the scan timing control signal SCS and sequentially output them to the bias scan line EBL.

[0086] The emission driver 620 may include a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate a plurality of first emission control signals based on the emission timing control signal ECS and sequentially output them to the first emission control line EL1. The second emission control driver 622 may generate a plurality of second emission control signals based on the emission timing control signal ECS and sequentially output them to the second emission control line EL2.

[0087] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see FIG. 1 ) through a semiconductor process. Figure 7 For example, the plurality of data transistors may be formed of CMOS, but the embodiments of the present specification are not limited thereto.

[0088] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into analog data voltages according to the data timing control signal DCS and outputs the analog data voltages to the data lines DL. For example, sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and data voltages may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0089] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is a thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface or one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a graphite layer or a metal layer having high thermal conductivity, such as a silver (Ag) layer, a copper (Cu) layer, or an aluminum (Al) layer.

[0090] The circuit board 300 may be electrically connected to the first pad portion PDA1 of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive layer (see FIG. Figure 4 ) of a plurality of first pads PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board having a flexible material or a flexible film. Figure 1 Although shown as unfolded in FIG, the circuit board 300 may be bent. For example, one end or one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 may be connected to the first pad portion PDA1 of the display panel 100 (see FIG. 1 ) by using a conductive adhesive member. Figure 4 ) of a plurality of first pads PD1 (see Figure 4 ). One end of the circuit board 300 may be an opposite end to the other end of the circuit board 300.

[0091] The timing control circuit 400 can receive digital video data DATA and timing signals input from the outside. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0092] The power supply circuit 500 (power supply unit) can generate a plurality of panel driving voltages according to the power voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD and a third driving voltage VINT and supply them to the display panel 100. Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described.

[0093] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface or one surface of the circuit board 300. For example, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 via the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 via the circuit board 300.

[0094] For example, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be provided in the non-display area NDA of the display panel 100. For example, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on the semiconductor substrate SSUB (see FIG. 1 ) via a semiconductor process. Figure 7 ). For example, a plurality of timing transistors and a plurality of power transistors may be formed of CMOS, but the embodiments of the present specification are not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 may be provided between the data driver 700 and the first pad portion PDA1 (see Figure 4 )between.

[0095] Figure 3 is a schematic diagram of an equivalent circuit of a first sub-pixel according to an embodiment.

[0096] Reference Figure 3 , the first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2 and the data line DL. In addition, the first sub-pixel SP1 can be connected to the first driving voltage VSS corresponding to the low potential voltage (see Figure 2 ) is applied to the first driving voltage line VSL, the second driving voltage VDD corresponding to the high potential voltage (see Figure 2 ) is applied to the second driving voltage line VDL, and the third driving voltage VINT corresponding to the initialization voltage (see Figure 2 ) is applied to a third driving voltage line VIL. For example, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. For example, the first driving voltage VSS may be lower than the third driving voltage VINT. The second driving voltage VDD may be higher than the third driving voltage VINT.

[0097] The first subpixel SP1 may include a plurality of transistors T1 to T6 , a light emitting element LE, a first capacitor CP1 , and a second capacitor CP2 .

[0098] The light-emitting element LE emits light in response to the driving current Ids flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE may be proportional to the driving current Ids. The light-emitting element LE may be arranged between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer arranged between the first electrode and the second electrode, but the embodiments of the present specification are not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode. In this case, the light-emitting element LE may be an inorganic light-emitting diode.

[0099] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (also referred to herein as "driving current Ids") flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 may include a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0100] The second transistor T2 may be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL may be applied to one electrode of the first capacitor CP1. The second transistor T2 may include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0101] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a write control signal from a write control line (control scan line) GCL to connect the first node N1 to the second node N2. To this end, when the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 may operate like a diode. The third transistor T3 may include a gate electrode connected to the write control line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0102] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Therefore, the driving current Ids flowing through the channel of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 may include a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0103] The fifth transistor T5 may be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the bias scan line EBL to connect the third node N3 to the third drive voltage line VIL. Thus, the third drive voltage VINT of the third drive voltage line VIL may be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 may include a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0104] The sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0105] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 may include one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0106] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 may include one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0107] The first node N1 is the junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0108] Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but the embodiments of the present specification are not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. For example, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0109] Despite Figure 3 FIG. 4 shows that the first sub-pixel SP1 may include six transistors T1 to T6 and two capacitors CP1 and CP2 , but it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to FIG. Figure 3 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 3 The quantity shown in .

[0110] In addition, the second sub-pixel SP2 (see Figure 2 ) and the equivalent circuit diagram of the third sub-pixel SP3 (see Figure 2 ) can be combined with the equivalent circuit diagram Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same as that of the first sub-pixel SP1, and therefore, descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 may be omitted in the specification.

[0111] Figure 4 is a plan view showing an example of a display panel according to an embodiment.

[0112] Reference Figure 4 The display area DAA of the display panel 100 according to the embodiment may include a plurality of pixels PX arranged or disposed in a matrix form. The non-display area NDA of the display panel 100 according to the embodiment may include a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0113] The scan driver 610 may be provided on a first side of the display area DAA, and the emission driver 620 may be provided on a second side of the display area DAA. For example, the scan driver 610 may be provided on one side or one side of the display area DAA in the first direction DR1, and the emission driver 620 may be provided on the other side of the display area DAA in the first direction DR1. For example, the scan driver 610 may be provided on the left side of the display area DAA, and the emission driver 620 may be provided on the right side of the display area DAA. However, the embodiments of the present specification are not limited thereto, and the scan driver 610 and the emission driver 620 may be provided on both the first side and the second side of the display area DAA.

[0114] The first pad portion PDA1 may include a portion connected to the circuit board 300 (see FIG. Figure 1 ) of the data driver 700. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side or one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be disposed outside the data driver 700 in the second direction DR2. For example, the first pad portion PDA1 may be disposed closer to an edge of the display panel 100 than the data driver 700.

[0115] The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 is operating normally. The plurality of second pads PD2 may be connected to a jig or a probe during an inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0116] The second pad portion PDA2 may be disposed on a fourth side of the display area DAA. For example, the second pad portion PDA2 may be disposed on another side of the display area DAA in the second direction DR2. The second pad portion PDA2 may be disposed outside the second distribution circuit 720 in the second direction DR2. For example, the second pad portion PDA2 may be disposed closer to an edge of the display panel 100 than the second distribution circuit 720.

[0117] The first distribution circuit 710 distributes the data voltage applied via the first pad portion PDA1 to the plurality of data lines DL (see Figure 3). For example, the first distribution circuit 710 may distribute the data voltage applied via one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, and as a result, the number of the plurality of first pads PD1 may be reduced. The first distribution circuit 710 may be disposed on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be disposed on one side or one side of the display area DAA in the second direction DR2. For example, the first distribution circuit 710 may be disposed on the lower side of the display area DAA.

[0118] The second distribution circuit 720 distributes the signal applied via the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 can be disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on another side of the display area DAA in the second direction DR2. For example, the second distribution circuit 720 can be disposed on an upper side of the display area DAA.

[0119] Figure 5 and Figure 6 It shows Figure 4 A plan view of an embodiment of a display area.

[0120] Reference Figure 5 and Figure 6 , each of the plurality of pixels PX may include a first emission area EA1 as an emission area of ​​the first sub-pixel SP1, a second emission area EA2 as an emission area of ​​the second sub-pixel SP2, and a third emission area EA3 as an emission area of ​​the third sub-pixel SP3.

[0121] Each of the first, second, and third emission regions EA1, EA2, and EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an atypical shape in a plan view.

[0122] The maximum length of the third emission area EA3 in the first direction DR1 may be less than the maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the first emission area EA1 in the first direction DR1. The maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the first emission area EA1 in the first direction DR1 may be substantially the same.

[0123] The maximum length of the third emission area EA3 in the second direction DR2 may be greater than the maximum length of the second emission area EA2 in the second direction DR2 and the maximum length of the first emission area EA1 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 may be greater than the maximum length of the second emission area EA2 in the second direction DR2. The present disclosure is not limited thereto. In an embodiment, the maximum length of the first emission area EA1 in the second direction DR2 may be less than the maximum length of the second emission area EA2 in the second direction DR2.

[0124] like Figure 5 and Figure 6 As shown in FIG, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a hexagonal shape formed by six straight lines in a plan view, but the embodiments of the present specification are not limited thereto. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a hexagonal shape, a circular shape, an elliptical shape, or an atypical shape in a plan view.

[0125] like Figure 5 As shown in FIG, in each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1. In addition, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. The second emission area EA2 and the third emission area EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first emission area EA1, the area of ​​the second emission area EA2, and the area of ​​the third emission area EA3 may be different.

[0126] For example, Figure 6 As shown in , the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1, but the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first oblique direction DD1, and the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2, and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0127] The first emission area EA1 may emit a first light, the second emission area EA2 may emit a second light, and the third emission area EA3 may emit a third light. Here, the first light may be light in a blue wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a red wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 370 nm to approximately 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 480 nm to approximately 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 600 nm to approximately 750 nm.

[0128] exist Figure 5 and Figure 6 , each of the plurality of pixels PX may include three emission areas EA1, EA2, and EA3, but the embodiments of the present specification are not limited thereto. For example, each of the plurality of pixels PX may include four emission areas.

[0129] The plane of the emission area of ​​the plurality of pixels PX is not limited to Figure 5 and Figure 6 For example, Figure 6 As shown in FIG, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the emission regions are arranged or arranged in a first direction DR1, a diamond structure in which the emission regions are arranged or arranged, or a stripe structure in which the emission regions are arranged or arranged in a diamond shape. A structure or a hexagonal structure in which emission areas having a hexagonal shape in a plan view are arranged or disposed side by side.

[0130] Figure 7 It is shown along Figure 5 Schematic cross-sectional view of an example of a display panel taken along line I1-I1'. Figure 8 It is shown in detail Figure 7 Schematic cross-sectional view of region A1 of FIG.

[0131] Reference Figure 7 and Figure 8 , the display panel 100 (see Figure 1 ) may include a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate POL.

[0132] The semiconductor backplane SBP may include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR. Figure 4 The first transistor T1 to the sixth transistor T6 are described.

[0133] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be provided on the upper surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the aforementioned first-type impurities. For example, if the first-type impurities are P-type impurities, the second-type impurities may be N-type impurities. For example, if the first-type impurities are N-type impurities, the second-type impurities may be P-type impurities.

[0134] Each of the plurality of well regions WA may include a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0135] The lower insulating layer BINS may be disposed between the gate electrode GE and the well area WA. The side insulating layer SINS may be disposed on a side surface of the gate electrode GE. The side insulating layer SINS may be disposed on the lower insulating layer BINS.

[0136] Each of the source region SA and the drain region DA may be a region doped with first-type impurities. The gate electrode GE of the pixel transistor PTR may overlap with the well region WA in the third direction DR3. The channel region CH may overlap with the gate electrode GE in the third direction DR3. The source region SA may be provided on one side or one side of the gate electrode GE, and the drain region DA may be provided on the other side of the gate electrode GE.

[0137] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. Due to the lower insulating layer BINS, the first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA. Due to the lower insulating layer BINS, the second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA may be increased. Therefore, the length of the channel region CH of each of the multiple pixel transistors PTR may be increased, so that punch-through and hot carrier phenomena that may be caused by a short channel may be prevented.

[0138] The first semiconductor insulating layer SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be made of silicon carbonitride (SiCN) or silicon oxide (SiO x) type inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0139] The second semiconductor insulating layer SINS2 may be provided on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be made of silicon oxide (SiO x ) type inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0140] A plurality of contact terminals CTE may be provided on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, source area SA, and drain area DA of each of the plurality of pixel transistors PTR via a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these.

[0141] The third semiconductor insulating layer SINS3 may be provided on the side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be made of silicon oxide (SiO x ) type inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0142] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as a polyimide substrate. For example, a thin film transistor can be provided on a glass substrate or a polymer resin substrate. A glass substrate can be a rigid substrate that does not bend, and a polymer resin substrate can be a flexible substrate that can be bent or curved.

[0143] The light emitting element back plate EBP may include a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating layers INS1 to INS9. The light emitting element back plate EBP may include a plurality of insulating layers INS1 to INS9 disposed between the first to eighth conductive layers ML1 to ML8.

[0144] The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect a plurality of contact terminals CTE exposed from the semiconductor backplane SBP to achieve Figure 3 For example, the first transistor T1 (see Figure 3 ) to the sixth transistor T6 (see Figure 3 ) may be formed in the semiconductor back plate SBP, and the first to sixth transistors T1 to T6 and the first capacitor CP1 (see Figure 3 ) and the second capacitor CP2 (see Figure 3 ) is connected via the first conductive layer ML1 to the eighth conductive layer ML8. Figure 3 ) of the drain electrode, corresponding to the drain region of the fifth transistor T5 (see Figure 3 ) and the first electrode AND of the light emitting element LE are also connected via the first to eighth conductive layers ML1 to ML8.

[0145] A first insulating layer INS1 may be provided on the semiconductor backplane SBP. Each of a plurality of first vias VA1 may penetrate the first insulating layer INS1 to connect to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of a plurality of first conductive layers ML1 may be provided on the first insulating layer INS1 and may be connected to the first vias VA1.

[0146] The second insulating layer INS2 may be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each of the plurality of second via holes VA2 may penetrate the second insulating layer INS2 and be connected to the exposed first conductive layer ML1. Each of the plurality of second conductive layers ML2 may be disposed on the second insulating layer INS2 and may be connected to the second via hole VA2.

[0147] The third insulating layer INS3 may be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each of the plurality of third via holes VA3 may penetrate the third insulating layer INS3 and be connected to the exposed second conductive layer ML2. Each of the plurality of third conductive layers ML3 may be disposed on the third insulating layer INS3 and may be connected to the third via hole VA3.

[0148] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of the plurality of fourth via holes VA4 may penetrate the fourth insulating layer INS4 and be connected to the exposed third conductive layer ML3. Each of the plurality of fourth conductive layers ML4 may be disposed on the fourth insulating layer INS4 and may be connected to the fourth via hole VA4.

[0149] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of the plurality of fifth via holes VA5 may penetrate the fifth insulating layer INS5 and be connected to the exposed fourth conductive layer ML4. Each of the plurality of fifth conductive layers ML5 may be disposed on the fifth insulating layer INS5 and may be connected to the fifth via hole VA5.

[0150] The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of the plurality of sixth via holes VA6 may penetrate the sixth insulating layer INS6 and be connected to the exposed fifth conductive layer ML5. Each of the plurality of sixth conductive layers ML6 may be disposed on the sixth insulating layer INS6 and may be connected to the sixth via hole VA6.

[0151] The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of the plurality of seventh via holes VA7 may penetrate the seventh insulating layer INS7 and be connected to the exposed sixth conductive layer ML6. Each of the plurality of seventh conductive layers ML7 may be disposed on the seventh insulating layer INS7 and may be connected to the seventh via hole VA7.

[0152] The eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the plurality of eighth via holes VA8 may penetrate the eighth insulating layer INS8 and be connected to the exposed seventh conductive layer ML7. Each of the plurality of eighth conductive layers ML8 may be disposed on the eighth insulating layer INS8 and may be connected to the eighth via hole VA8.

[0153] The first conductive layer ML1 to the eighth conductive layer ML8 and the first via holes VA1 to the eighth via holes VA8 may be formed of substantially the same material. The first conductive layer ML1 to the eighth conductive layer ML8 and the first via holes VA1 to the eighth via holes VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd), or an alloy including any one of them. The first via holes VA1 to the eighth via holes VA8 may be made of substantially the same material. The first insulating layer INS1 to the eighth insulating layer INS8 may be made of silicon oxide (SiO x ) type inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0154] The thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 may be respectively greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately

[0155] The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be approximately And the thickness of each of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6 may be approximately

[0156] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately The thickness of each of the seventh via hole VA7 and the eighth via hole VA8 may be approximately

[0157] The ninth insulating layer INS9 may be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 may be made of silicon oxide (SiO x ) type inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0158] Each of the plurality of ninth via holes VA9 may penetrate the ninth insulating layer INS9 and be connected to the exposed eighth conductive layer ML8. The ninth via hole VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the ninth via hole VA9 may be about

[0159] The display element layer EML may be disposed on the light emitting element backplane EBP. The display element layer EML may include: light emitting elements LE, each including a reflective electrode layer RL, a tenth insulating layer INS10, a tenth via hole VA10, a first electrode AND, a light emitting stack IL, and a second electrode CAT; a pixel defining layer PDL; and a plurality of trenches TRC.

[0160] The reflective electrode layer RL may be disposed on the ninth insulating layer INS9. The reflective electrode layer RL may include one or more reflective electrodes RL1, RL2, RL3, and RL4, a first stepped layer STPL1, and a second stepped layer STPL2. For example, Figure 7 It is illustrated that the one or more reflective electrodes RL1 , RL2 , RL3 , and RL4 include a first reflective electrode RL1 , a second reflective electrode RL2 , a third reflective electrode RL3 , and a fourth reflective electrode RL4 , but embodiments of the present disclosure are not limited thereto.

[0161] Each of the plurality of first reflective electrodes RL1 may be disposed on the ninth insulating layer INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0162] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. For example, the second reflective electrode RL2 may include aluminum (Al).

[0163] The first stepped layer STPL1 may be disposed on the second reflective electrode RL2 in the second and third sub-pixels SP2 and SP3. The first stepped layer STPL1 may not be disposed on the second reflective electrode RL2 in the first sub-pixel SP1.

[0164] The second stepped layer STPL2 may be disposed on the first stepped layer STPL1 in the third subpixel SP3. The second stepped layer STPL2 may not be disposed on the second reflective electrode RL2 in the first subpixel SP1. The second stepped layer STPL2 may not be disposed on the first stepped layer STPL1 in the second subpixel SP2.

[0165] The thickness of the first stepped layer STPL1 may be set in consideration of the wavelength of the first light and the distance from the light emitting stack IL of the second sub-pixel SP2 to the fourth reflective electrode RL4, so as to favorably reflect the light of the first color emitted from the light emitting stack IL. The thickness of the second stepped layer STPL2 may be set in consideration of the wavelength of the first light and the distance from the light emitting stack IL of the third sub-pixel SP3 to the fourth reflective electrode RL4, so as to favorably reflect the first light emitted from the light emitting stack IL.

[0166] The first stepped layer STPL1 and the second stepped layer STPL2 may be made of silicon carbonitride (SiCN) or silicon oxide (SiO x ) type inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0167] In the first subpixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. In the second subpixel SP2, the third reflective electrode RL3 may be disposed on the first stepped layer STPL1. In the third subpixel SP3, the third reflective electrode RL3 may be disposed on the second stepped layer STPL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0168] At least one of the first reflective electrode RL1 , the second reflective electrode RL2 , and the third reflective electrode RL3 may be omitted.

[0169] The plurality of fourth reflective electrodes RL4 may be respectively disposed on the plurality of third reflective electrodes RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the light emitting stack IL. The fourth reflective electrode RL4 may include a metal having a high reflectivity to advantageously reflect light. Since the fourth reflective electrode RL4 is substantially reflective of light from the light emitting element LE (see Figure 3), the fourth reflective electrode RL4 may be thicker than each of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. For example, the fourth reflective electrode RL4 may include aluminum (Al) or titanium (Ti).

[0170] The tenth insulating layer INS10 may be provided on the ninth insulating layer INS9 and the fourth reflective electrode RL4. The tenth insulating layer INS10 may be an optical auxiliary layer through which light reflected by the reflective electrode layer RL, among light emitted from the light emitting element LE, passes. The tenth insulating layer INS10 may be made of silicon oxide (SiO x ) type inorganic layer is formed, but the embodiments of this specification are not limited thereto.

[0171] Each of the plurality of tenth via holes VA10 may penetrate the tenth insulating layer INS10 and be connected to the exposed reflective electrode layer RL. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0172] The thickness of the tenth via hole VA10 may vary in the first, second, and third subpixels SP1, SP2, and SP3 to adjust the resonance distance of light emitted from the light-emitting element LE in at least one of the first, second, and third subpixels SP1, SP2, and SP3. For example, the thickness of the tenth via hole VA10 in the third subpixel SP3 may be smaller than the thickness of the tenth via hole VA10 in each of the first and second subpixels SP1 and SP2. Furthermore, the thickness of the tenth via hole VA10 in the second subpixel SP2 may be smaller than the thickness of the tenth via hole VA10 in the first subpixel SP1. For example, the distance between the light-emitting stack IL and the reflective electrode layer RL may be different in the first, second, and third subpixels SP1, SP2, and SP3.

[0173] In summary, in order to adjust the distance between the light emitting stack IL and the reflective electrode layer RL according to the main wavelength of light emitted from the sub-pixel, the presence or absence of the first step layer STPL1 and the second step layer STPL2 in the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 and the thickness of each of the first step layer STPL1 and the second step layer STPL2 can be set.

[0174] The first electrode AND of each of the plurality of light-emitting elements LE can be disposed on the tenth insulating layer INS10 and connected to the tenth via VA10. The first electrode AND of each of the plurality of light-emitting elements LE can be connected to the drain area DA or the source area SA of the pixel transistor PTR via the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. For example, the first electrode AND of each of the plurality of light-emitting elements LE can be titanium nitride (TiN).

[0175] The pixel defining layer (PDL) may be disposed on a portion of the first electrode AND of each of the plurality of light emitting elements LE. The pixel defining layer (PDL) may cover an edge of the first electrode AND of each of the plurality of light emitting elements LE. The pixel defining layer (PDL) may be used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0176] The first emission area EA1 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT may be sequentially stacked on one another in the first sub-pixel SP1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT may be sequentially stacked on one another in the second sub-pixel SP2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT may be sequentially stacked on one another in the third sub-pixel SP3 to emit light.

[0177] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be disposed on an edge of the first electrode AND of each of the plurality of light emitting elements LE, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO x ) type inorganic layer is formed, but the embodiments of the present specification are not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2 and the third pixel defining layer PDL3 may each have an area of ​​approximately thickness.

[0178] In the case where the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 are formed into one pixel defining layer, the height of the one pixel defining layer increases, so that the first encapsulating inorganic layer TFE1 may be cut due to step coverage. Step coverage refers to the ratio of the extent of the thin film coated on the inclined portion to the extent of the thin film coated on the flat portion. The lower the step coverage, the more likely the thin film will be cut at the inclined portion.

[0179] Therefore, to prevent the first encapsulating inorganic layer TFE1 from being cut due to step coverage, the first pixel defining layer (PDL1), the second pixel defining layer (PDL2), and the third pixel defining layer (PDL3) may have a cross-sectional structure with stepped portions. For example, the width of the first pixel defining layer (PDL1) may be greater than the widths of the second pixel defining layer (PDL2) and the third pixel defining layer (PDL3), and the width of the second pixel defining layer (PDL2) may be greater than the width of the third pixel defining layer (PDL3). The width of the first pixel defining layer (PDL1) refers to the horizontal length of the first pixel defining layer (PDL1) defined in the first direction (DR1) and the second direction (DR2).

[0180] Each of the plurality of trenches TRC may penetrate the first pixel defining layer PDL1 , the second pixel defining layer PDL2 , and the third pixel defining layer PDL3 . In addition, the tenth insulating layer INS10 may be partially recessed at each of the plurality of trenches TRC.

[0181] At least one trench TRC may be provided between adjacent sub-pixels SP1, SP2, and SP3. Figure 7 It is shown that two trenches TRC are provided between adjacent sub-pixels SP1 , SP2 , and SP3 , but the embodiments of this specification are not limited thereto.

[0182] The light emitting stack IL may include a plurality of intermediate layers. Figure 7 The light emitting stack IL is shown to have a three-series structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3, but the embodiments of the present specification are not limited thereto. For example, the light emitting stack IL may have a two-series structure including two stack layers.

[0183] In the triple-series structure, the light emitting stack IL may have a series structure including a plurality of stacked layers IL1, IL2, and IL3 that emit different lights. For example, the light emitting stack IL may include a first stacked layer IL1 that emits a first light, a second stacked layer IL2 that emits a third light, and a third stacked layer IL3 that emits a second light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 may be stacked one above the other.

[0184] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting the first light, and a first electron transport layer may be stacked one after another. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting the third light, and a second electron transport layer may be stacked one after another. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting the second light, and a third electron transport layer may be stacked one after another.

[0185] A first charge generation layer for supplying holes to the second stack layer IL2 and electrons to the first stack layer IL1 may be disposed between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack layer IL1 and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0186] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be provided between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0187] The first stacked layer IL1 can be arranged on the first electrode AND and the pixel defining layer PDL. The remaining stacked layer RIL made of the same material as the first stacked layer IL1 can be arranged on the lower surface of each of the multiple trenches TRC. Due to the trench TRC, the first stacked layer IL1 can be cut off between adjacent sub-pixels SP1, SP2 and SP3. The second stacked layer IL2 can be arranged on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be cut off between adjacent sub-pixels SP1, SP2 and SP3. A gap ES or empty space can be provided between the remaining stacked layer RIL and the second stacked layer IL2 in each trench TRC. The third stacked layer IL3 can be provided on the second stacked layer IL2. The third stacked layer IL3 is not cut off by the trench TRC and can be provided in each of the multiple trenches TRC to cover the second stacked layer IL2. For example, in a three-series structure, each of the plurality of trenches TRC may be a structure for cutting off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML, the first charge generation layer, and the second charge generation layer between adjacent sub-pixels SP1, SP2, and SP3.

[0188] In the two-tandem structure, each of the plurality of trenches TRC may be a structure for cutting off the charge generation layer and the lower stack layer provided between the lower stack layer and the upper stack layer.

[0189] In order to stably cut off the first stacked layer IL1 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. In order to cut off the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, another structure may be present instead of the groove TRC. For example, a reversely tapered partition wall may be provided on the pixel defining layer PDL instead of the groove TRC.

[0190] Figure 7 and Figure 8 The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are shown as all disposed in the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the embodiments of the present specification are not limited thereto. For example, the first stacked layer IL1 may be disposed in the first emission area EA1, and may not be disposed in the second emission area EA2 and the third emission area EA3. In addition, the second stacked layer IL2 may be disposed in the second emission area EA2, and may not be disposed in the first emission area EA1 and the third emission area EA3. In addition, the third stacked layer IL3 may be disposed in the third emission area EA3, and may not be disposed in the first emission area EA1 and the second emission area EA2. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0191] The second electrode CAT may be disposed on the third stacked layer IL3. The second electrode CAT may be disposed on the third stacked layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of the semi-transmissive conductive material, the light emission efficiency of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be improved due to the microcavity effect.

[0192] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic layer TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0193] The first encapsulation inorganic layer TFE1 may be provided on the second electrode CAT. The first encapsulation inorganic layer TFE1 may be formed of a material selected from silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and silicon oxide (SiO x ) may be a multilayer of one or more inorganic layers alternately stacked with each other. The first encapsulation inorganic layer TFE1 may be formed by a chemical vapor deposition (CVD) process.

[0194] The second encapsulating inorganic layer TFE2 may be disposed on the first encapsulating inorganic layer TFE1. The second encapsulating inorganic layer TFE2 may be made of titanium oxide (TiO x ) or aluminum oxide (AlO x ) is formed, but the embodiments of the present specification are not limited thereto. The second encapsulation inorganic layer TFE2 may be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic layer TFE2 may be less than the thickness of the first encapsulation inorganic layer TFE1.

[0195] The organic layer APL may be a layer for increasing the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL may be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0196] The optical layer OPL may include a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the organic layer APL.

[0197] The first color filter CF1 may overlap the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit the first light, for example, light in the blue wavelength band. Therefore, the first color filter CF1 may transmit the first light among the light emitted from the first emission area EA1.

[0198] The second color filter CF2 may overlap the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit the second light, for example, light in the green wavelength band. Therefore, the second color filter CF2 may transmit the second light among the light emitted from the second emission area EA2.

[0199] The third color filter CF3 may overlap the third emission area EA3 of the third subpixel SP3. The third color filter CF3 may transmit the third light, for example, light in the red wavelength band. Therefore, the third color filter CF3 may transmit the third light among the lights emitted from the third emission area EA3.

[0200] The plurality of lenses LNS may be respectively provided on the first color filter CF1, the second color filter CF2 and the third color filter CF3. Each of the plurality of lenses LNS may be used to increase the orientation of the display device 10 (see FIG. Figure 1 Although each of the plurality of lenses LNS is illustrated as having an upwardly convex cross-sectional shape, embodiments of the present disclosure are not limited thereto.

[0201] A filling layer FIL may be provided on the plurality of lenses LNS. The filling layer FIL may have a refractive index selected so that light propagates in the third direction DR3 at the interface between the filling layer FIL and the plurality of lenses LNS. Furthermore, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0202] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. If the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. For example, the filling layer FIL may be used to bond the cover layer CVL. If the cover layer CVL is a glass substrate, the cover layer CVL may serve as an encapsulation substrate. If the cover layer CVL is a polymer resin, the cover layer CVL may be directly coated onto the filling layer FIL.

[0203] The polarizing plate POL may be provided on one or more surfaces of the cover layer CVL. The polarizing plate POL may be a structure for preventing visibility reduction caused by reflection of external light. The polarizing plate POL may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter wavelength plate), but the embodiments of the present specification are not limited thereto. However, if the first color filter CF1, the second color filter CF2, and the third color filter CF3 are sufficient to overcome the visibility reduction caused by reflection of external light, the polarizing plate POL may be omitted.

[0204] Figure 9 It shows Figure 8 Schematic cross-sectional view of an example of area A2.

[0205] Reference Figure 9The trench TRC may be a structure for cutting off the charge generation layer between the first stack layer IL1 and the second stack layer IL2 of the light emitting stack IL. The trench TRC may be defined as a hole that penetrates the pixel defining layer PDL and in which the tenth insulating layer INS10 is partially recessed. The trench TRC may be formed by a photolithography process using argon fluoride (ArF) as a light source.

[0206] The trench TRC may include an entrance ENT, sidewalls SW, and a bottom surface FS.

[0207] The entrance ENT of the trench TRC may be an opening area defined by the third pixel defining layer PDL3 at the top of the trench TRC. The entrance ENT of the trench TRC may be covered by the light emitting stack IL. For example, the first stack layer IL1 and the second stack layer IL2 may be sequentially arranged at the edge of the entrance ENT of the trench TRC. The entrance ENT of the trench TRC that is not covered by the first stack layer IL1 and the second stack layer IL2 and is exposed may be covered by the third stack layer IL3.

[0208] The sidewall SW of the trench TRC may be a side surface connecting the entrance ENT of the trench TRC to the lower surface FS of the trench TRC. The sidewall SW of the trench TRC may be defined by the tenth insulating layer INS10 and the pixel defining layer PDL. The length of the sidewall SW of the trench TRC defined by the tenth insulating layer INS10 may be greater than the length of the sidewall SW of the trench TRC defined by the pixel defining layer PDL.

[0209] The lower surface FS of the trench TRC may be a closed region defined by the tenth insulating layer INS10 at a lower portion of the trench TRC. A remaining stack layer RIL made of the same material as the first stack layer IL1 may be disposed on the lower surface FS of the trench TRC.

[0210] The height Htrc of the trench TRC may be defined as the maximum distance from the lower surface FS of the trench TRC to the entrance ENT of the trench TRC in the third direction DR3. In order to cut off the first stack layer IL1 and the second stack layer IL2, the first charge generation layer and the second charge generation layer in each of the plurality of trenches TRC, the height Htrc of the trench TRC may be defined as the maximum distance from the lower surface FS of the trench TRC to the entrance ENT of the trench TRC in the third direction DR3. to approximately For example, the height of the pixel definition layer PDL can be about For example, the sum of the thicknesses of the first pixel defining layer PDL1 , the second pixel defining layer PDL2 , and the third pixel defining layer PDL3 may be less than or equal to ¼ of the height Htrc of the trench TRC.

[0211] In order to cut off the first stacked layer IL1 and the second stacked layer IL2, and the first charge generation layer and the second charge generation layer in each of the plurality of trenches TRC, the angle θent1 formed between the tangent line TL of the sidewall SW of the trench TRC and the upper surface of the third pixel defining layer PDL3 at the entrance ENT of the trench TRC may be in a range of about 80° to about 90°. Therefore, the maximum width Wsw1 of the trench TRC in one direction or one direction at the center of the sidewall SW may be greater than the width Went1 of the entrance ENT in one direction or one direction and the width Wfs1 of the lower surface FS in one direction or one direction. For example, each of the plurality of trenches TRC may have a substantially can-shaped cross-section.

[0212] In addition, in order to cut off the first stacked layer IL1 and the second stacked layer IL2 and the first charge generation layer and the second charge generation layer in each of the plurality of trenches TRC, the width Went1 of the entrance ENT of the trench TRC may be greater than about 100 nm and less than about 130 nm. The width Wfs1 of the lower surface of the trench TRC in one direction or one direction may be smaller than the width Went1 of the entrance ENT of the trench TRC in one direction or one direction.

[0213] The first stack layer IL1 and the second stack layer IL2 may be sequentially disposed at an edge of the entrance ENT of each trench TRC. The first stack layer IL1 may be disposed closer to the edge of the entrance ENT of each trench TRC than the second stack layer IL2. The third stack layer IL3 may be disposed to cover the remaining portion of the entrance ENT of each trench TRC that is not covered by the first stack layer IL1 and the second stack layer IL2.

[0214] Figure 10 It shows Figure 7 FIG1 is a schematic cross-sectional view of another example of an area A1 of FIG1 . Figure 11 It shows Figure 10 Schematic cross-sectional view of an example of area A3.

[0215] Figure 10 and Figure 11 Examples and Figure 8 and Figure 9 The embodiment of the present invention may be different in that the trench TRC may not penetrate the third pixel defining layer PDL3. Figure 10 and 11 In the description, the Figure 8 and 9 The differences between the embodiments.

[0216] Reference Figure 10 and Figure 11The trench TRC may be defined as a hole that penetrates the first pixel defining layer PDL1 and the second pixel defining layer PDL2 and in which the tenth insulating layer INS10 is partially recessed. The third pixel defining layer PDL3 may be disposed on the sidewalls SW and the lower surface FS of the trench TRC. The trench TRC may be formed by a photolithography process using krypton fluoride (KrF) as a light source.

[0217] The trench TRC may include an entrance ENT, sidewalls SW, and a bottom surface FS.

[0218] The entrance ENT of the trench TRC may be an opening area defined by the second pixel defining layer PDL2 at the top of the trench TRC. The entrance ENT of the trench TRC may be covered by the light emitting stack IL. For example, the third pixel defining layer PDL3, the first stack layer IL1, and the second stack layer IL2 may be sequentially disposed at the edge of the entrance ENT of the trench TRC. The entrance ENT of the trench TRC that is not covered by the third pixel defining layer PDL3, the first stack layer IL1, and the second stack layer IL2 and is exposed may be covered by the third stack layer IL3.

[0219] The sidewall SW of the trench TRC may be a side surface connecting the entrance ENT of the trench TRC to the lower surface FS of the trench TRC. The sidewall SW of the trench TRC may be defined by the tenth insulating layer INS10, the first pixel defining layer PDL1, and the second pixel defining layer PDL2. The length of the sidewall SW of the trench TRC defined by the tenth insulating layer INS10 may be greater than the length of the sidewall SW of the trench TRC defined by the first pixel defining layer PDL1 and the second pixel defining layer PDL2. The sum of the thickness of the first pixel defining layer PDL1 and the thickness of the second pixel defining layer PDL2 may be less than or equal to 1 / 4 of the height Htrc of the trench TRC.

[0220] In order to cut off the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer and the second charge generation layer in the trench TRC, the angle θent2 formed between the tangent line TL of the sidewall SW of the trench TRC and the upper surface of the second pixel defining layer PDL2 at the entrance ENT of the trench TRC can be in a range of from about 80° to about 90°. Therefore, the maximum width Wsw2 of the trench TRC in one direction or one direction at the center of the sidewall SW can be greater than the width Went2 of the entrance ENT in one direction or one direction and the width Wfs2 of the lower surface FS in one direction or one direction. The width Wfs2 of the lower surface of the trench TRC in one direction or one direction can be less than the width Went2 of the entrance ENT of the trench TRC in one direction or one direction. For example, the trench TRC can have a substantially can-shaped cross-section.

[0221] On the other hand, in the case of forming the trench TRC by a photolithography process using krypton fluoride (KrF), it is difficult to control the width Went2 of the entrance ENT of the trench TRC to be less than about 130nm. In the case where the width Went2 of the entrance ENT of the trench TRC is greater than about 130nm, it may occur that the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer and the second charge generation layer are not cut off in the trench TRC. Therefore, the third pixel defining layer PDL3 can be set to surround the sidewall SW and the lower surface FS of the trench TRC. For example, the width Went3 of the entrance ENT of the trench TRC redefined by the third pixel defining layer PDL3 can be greater than about 100nm and less than about 130nm. Therefore, the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer and the second charge generation layer can be reliably cut off in the trench TRC.

[0222] The third pixel defining layer PDL3, the first stacked layer IL1, and the second stacked layer IL2 may be sequentially disposed at the edge of the entrance ENT of each trench TRC. The third pixel defining layer PDL3 may be disposed closer to the edge of the entrance ENT of each trench TRC than the first stacked layer IL1. In addition, the first stacked layer IL1 may be disposed closer to the edge of the entrance ENT of each trench TRC than the second stacked layer IL2. The third stacked layer IL3 may be disposed to cover the remaining portion of the entrance ENT of each trench TRC that is not covered by the third pixel defining layer PDL3, the first stacked layer IL1, and the second stacked layer IL2.

[0223] Figure 12 is a flowchart illustrating a method for manufacturing a display device (including a display panel) according to an embodiment. Figures 13 to 18 is a schematic cross-sectional view showing a region A1 in detail to describe a method for manufacturing a display device (including a display panel) according to an embodiment.

[0224] In the following, reference will be made to Figure 7 and Figures 12 to 18 A method for manufacturing a display device (including a display panel) according to an embodiment is described in detail.

[0225] First, combine Figure 7 ,like Figure 13 As shown in FIG, a tenth insulating layer INS10 is formed on the semiconductor substrate SSUB, and a plurality of first electrodes AND ( Figure 12 Step S110).

[0226] The light emitting element back plate EBP is formed on the semiconductor back plate SBP, and a first electrode layer and a passivation layer may be formed on the light emitting element back plate EBP.

[0227] First to eighth conductive layers ML1 to ML8 , first to ninth via holes VA1 to VA9 , and first to ninth insulating layers INS1 to INS9 of the light emitting element back plate EBP are formed on the semiconductor substrate SSUB (specifically, the semiconductor back plate SBP).

[0228] For example, a first insulating layer INS1 is formed on a semiconductor substrate SSUB, a plurality of first vias VA1 are formed through a photolithography process and are connected to the plurality of contact terminals CTE of the semiconductor substrate SSUB, respectively. A plurality of first conductive layers ML1 are formed through a photolithography process and are connected to the plurality of first vias VA1, respectively. A second insulating layer INS2 may be formed on the first conductive layer ML1, a plurality of second vias VA2 are formed through a photolithography process and are connected to the plurality of first conductive layers ML1, respectively. A plurality of second conductive layers ML2 are formed through a photolithography process and are connected to the plurality of second vias VA2, respectively. A third insulating layer INS3 may be formed on the second conductive layer ML2, a plurality of third vias VA3 are formed through a photolithography process and are connected to the plurality of second conductive layers ML2, respectively. A plurality of third conductive layers ML3 are formed through a photolithography process and are connected to the plurality of third vias VA3, respectively. The fourth insulating layer INS4 can be formed on the third conductive layer ML3, and a plurality of fourth via holes VA4 respectively connected to the plurality of third conductive layers ML3 are formed by a photolithography process while penetrating the fourth insulating layer INS4, and a plurality of fourth conductive layers ML4 respectively connected to the plurality of fourth via holes VA4 are formed on the fourth insulating layer INS4 by a photolithography process.

[0229] A fifth insulating layer INS5 may be formed on the fourth conductive layer ML4. A plurality of fifth vias VA5, each connected to the plurality of fourth conductive layers ML4, may be formed through a photolithography process while penetrating the fifth insulating layer INS5. A plurality of fifth conductive layers ML5, each connected to the plurality of fifth vias VA5, may be formed through a photolithography process on the fifth insulating layer INS5. A sixth insulating layer INS6 may be formed on the fifth conductive layer ML5. A plurality of sixth vias VA6, each connected to the plurality of fifth conductive layers ML5, may be formed through a photolithography process while penetrating the sixth insulating layer INS6. A plurality of sixth conductive layers ML6, each connected to the plurality of sixth vias VA6, may be formed through a photolithography process on the sixth insulating layer INS6. A seventh insulating layer INS7 may be formed on the sixth conductive layer ML6. A plurality of seventh vias VA7, each connected to the plurality of sixth conductive layers ML6, may be formed through a photolithography process while penetrating the seventh insulating layer INS7. A plurality of seventh conductive layers ML7, each connected to the plurality of seventh vias VA7, may be formed through a photolithography process on the seventh insulating layer INS7. An eighth insulating layer INS8 may be formed on the seventh conductive layer ML7, and a plurality of eighth via holes VA8 respectively connected to the plurality of seventh conductive layers ML7 while penetrating the eighth insulating layer INS8 may be formed by a photolithography process, and a plurality of eighth conductive layers ML8 respectively connected to the plurality of eighth via holes VA8 may be formed on the eighth insulating layer INS8 by a photolithography process. A ninth insulating layer INS9 may be formed on the eighth conductive layer ML8, and a plurality of ninth via holes VA9 respectively connected to the plurality of eighth conductive layers ML8 while penetrating the ninth insulating layer INS9 may be formed by a photolithography process.

[0230] A plurality of first reflective electrodes RL1 of the reflective electrode layer RL, each connected to the plurality of ninth via holes VA9, may be formed on the ninth insulating layer INS9, and a plurality of second reflective electrodes RL2 of the reflective electrode layer RL may be formed on the plurality of first reflective electrodes RL1. A first stepped layer STPL1 may be formed on the second reflective electrode RL2 of the reflective electrode layer RL in the second subpixel SP2 and the third subpixel SP3, and a second stepped layer STPL2 may be formed on the first stepped layer STPL1 in the third subpixel SP3. Thereafter, a plurality of third reflective electrodes RL3 of the reflective electrode layer RL may be formed on the second reflective electrode RL2 of the reflective electrode layer RL in the first subpixel SP1, the first stepped layer STPL1 in the second subpixel SP2, and the second stepped layer STPL2 in the third subpixel SP3, and a plurality of fourth reflective electrodes RL4 of the reflective electrode layer RL may be formed on the plurality of third reflective electrodes RL3 of the reflective electrode layer RL.

[0231] A tenth insulating layer INS10 covering the reflective electrode layer RL may be formed, and a plurality of tenth via holes VA10 penetrating the tenth insulating layer INS10 to be respectively connected to the plurality of fourth reflective electrodes RL4 may be formed. In addition, a plurality of first electrodes AND correspondingly connected to the plurality of tenth via holes VA10 may be formed on the tenth insulating layer INS10.

[0232] Second, if Figure 14 As shown in FIG, pixel defining layers PDLL1, PDLL2, and PDLL3 covering a plurality of first electrodes AND are formed. Figure 12 Step S120).

[0233] The pixel defining layers PDLL1, PDLL2, and PDLL3 include a first pixel defining layer PDLL1, a second pixel defining layer PDLL2, and a third pixel defining layer PDLL3. The first pixel defining layer PDLL1 may be formed to cover the plurality of first electrodes AND. The first pixel defining layer PDLL1 may be formed to cover the upper surface and side surfaces of each of the plurality of first electrodes AND. The second pixel defining layer PDLL2 may be formed on the first pixel defining layer PDLL1, and the third pixel defining layer PDLL3 may be formed on the second pixel defining layer PDLL2. The first pixel defining layer PDLL1, the second pixel defining layer PDLL2, and the third pixel defining layer PDLL3 may be made of silicon oxide (SiO x ) is made.

[0234] Third, if Figure 15 As shown in FIG, a plurality of trenches TRC are formed to penetrate the pixel defining layers PDLL1, PDLL2, and PDLL3 ( Figure 12 Step S130).

[0235] Each of the plurality of trenches TRC may be a hole penetrating the first pixel defining layer PDLL1, the second pixel defining layer PDLL2, and the third pixel defining layer PDLL3 and in which the tenth insulating layer INS10 is partially recessed. The plurality of trenches TRC may be formed by a photolithography process using argon fluoride (ArF) as a light source. For example, Figure 9 As shown in FIG, a width Went1 of an entrance ENT of the trench TRC may be formed to be greater than about 100 nm and less than about 130 nm so that the first and second stack layers IL1 and IL2 and the first and second charge generation layers may be reliably cut off in the trench TRC.

[0236] Fourth, if Figure 16 As shown in FIG, the pixel defining layers PDLL1, PDLL2, and PDLL3 are etched to form a pixel defining layer PDL and partially expose each of the plurality of first electrodes AND ( Figure 12 Step S140).

[0237] First, a first mask pattern is formed on the third pixel defining layer PDLL3 (see Figure 15 ), and a portion of the third pixel defining layer PDLL3 not covered by the first mask pattern is etched to form a third pixel defining layer PDL3.

[0238] Covering the second pixel defining layer PDLL2 (see Figure 15 ) and a second mask pattern covering a portion of the third pixel defining layer PDL3 may be formed, and a portion of the second pixel defining layer PDLL2 not covered by the second mask pattern is etched to form the second pixel defining layer PDL2.

[0239] Covering the first pixel defining layer PDLL1 (see Figure 15 A third mask pattern including a portion of the first pixel defining layer PDLL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be formed, and portions of the first pixel defining layer PDLL1 not covered by the third mask pattern are etched to form the first pixel defining layer PDL1. Therefore, since the pixel defining layer PDL covers only the edge of each of the plurality of first electrodes AND, a central portion of each of the plurality of first electrodes AND may be exposed.

[0240] Fifth, if Figure 17 As shown in FIG, a light emitting stack IL is formed on a portion of each of the plurality of first electrodes AND and the pixel defining layer PDL. Figure 12 Step S150).

[0241] The first stack layer IL1, the second stack layer IL2 and the third stack layer IL3 of the light emitting stack IL can be formed on the plurality of first electrodes AND, the first pixel defining layer PDL1, the second pixel defining layer PDL2 and the third pixel defining layer PDL3. The first stack layer IL1 and the second stack layer IL2 can be cut off in each of the plurality of trenches TRC. Therefore, the first charge generation layer provided between the first stack layer IL1 and the second stack layer IL2 and the second charge generation layer provided between the second stack layer IL2 and the third stack layer IL3 can also be cut off. Therefore, in the sub-pixels SP1, SP2 and SP3 (see Figure 7 ) can be prevented from flowing to an adjacent sub-pixel via the first charge generation layer and the second charge generation layer.

[0242] Sixth, as Figure 18 As shown in FIG, a second electrode CAT and an encapsulation layer TFE ( Figure 12 Step S160).

[0243] The second electrode CAT is formed on the third stacked layer IL3, and the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE2 of the encapsulation layer TFE are sequentially formed on the second electrode CAT. The first encapsulation inorganic layer TFE1 can be formed by a chemical vapor deposition (CVD) process, and the second encapsulation inorganic layer TFE2 can be formed by an atomic layer deposition (ALD) process.

[0244] The organic layer APL is formed on the encapsulation layer TFE and the first color filter CF1 (see FIG. 1 ) overlaps the first emission area EA1. Figure 7 ), the second color filter CF2 overlapping with the second emission area EA2 (see Figure 7 ) and the third emission area EA3 (see Figure 7 ) overlapped third color filter CF3 (see Figure 7 ) may be formed on the organic layer APL.

[0245] Thereafter, a plurality of lenses LNS (see Figure 7 ) are formed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. For example, a plurality of lenses LNS may be formed to correspond one to one to the color filters CF1, CF2, and CF3.

[0246] Filling layer FIL (see Figure 7 ) is formed on the plurality of lenses LNS, and a cover layer CVL (see Figure 7 ) can be provided on the filling layer FIL.

[0247] The cover layer CVL can be a glass substrate or a polymer resin. In the case where the cover layer CVL is a glass substrate, the cover layer CVL can be used as a packaging substrate, and the filler layer FIL can be used to adhere the cover layer CVL. In the case where the cover layer CVL is a polymer resin, the cover layer CVL can be directly applied to the filler layer FIL.

[0248] Polarizer POL (see Figure 7 ) can be attached to the cover layer CVL.

[0249] Figure 19 is a flowchart illustrating a method for manufacturing a display device (including a display panel) according to an embodiment. Figures 20 to 24 is a schematic cross-sectional view showing a region A1 in detail to describe a method for manufacturing a display device (including a display panel) according to an embodiment.

[0250] In the following, reference will be made to Figure 7 and Figures 19 to 24 A method for manufacturing a display device (including a display panel) according to an embodiment is described in detail.

[0251] First, combine Figure 7 ,like Figure 20 As shown in FIG, a tenth insulating layer INS10 is formed on the semiconductor substrate SSUB, and a plurality of first electrodes AND ( Figure 19 Step S210).

[0252] because Figure 19 Step S210 and Figure 12 The step S110 is basically the same as that of Figure 19 Detailed description of step S210.

[0253] Second, if Figure 20 As shown in FIG, a first pixel defining layer PDLL1 and a second pixel defining layer PDLL2 ( Figure 19 Step S220).

[0254] The first pixel defining layer PDLL1 may be formed to cover the plurality of first electrodes AND. The first pixel defining layer PDLL1 may be formed to cover the upper surface and side surfaces of each of the plurality of first electrodes AND. The second pixel defining layer PDLL2 may be formed on the first pixel defining layer PDLL1. The first pixel defining layer PDLL1 and the second pixel defining layer PDLL2 may be made of silicon oxide (SiO x ) is made.

[0255] Third, if Figure 21 As shown in FIG, a plurality of trenches TRC ( Figure 19 Step S230).

[0256] Each of the plurality of trenches TRC may be a hole penetrating the first and second pixel defining layers PDLL1 and PDLL2 and in which the tenth insulating layer INS10 is partially recessed. The plurality of trenches TRC may be formed by a photolithography process using krypton fluoride (KrF) as a light source.

[0257] Fourth, if Figure 22 As shown in FIG, a third pixel defining layer PDLL3 is formed on the second pixel defining layer PDLL2 ( Figure 19 Step S240).

[0258] like Figure 11As shown in , in the case where the trench TRC is formed by a photolithography process using krypton fluoride (KrF), it is difficult to control the width Went2 of the entrance ENT of the trench TRC to be less than about 130nm. In the case where the width Went2 of the entrance ENT of the trench TRC is greater than about 130nm, it may occur that the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer and the second charge generation layer are not cut off in the trench TRC. Therefore, in the case where the third pixel defining layer PDLL3 is formed on the second pixel defining layer PDLL2, the third pixel defining layer PDLL3 can be formed on the sidewall SW and the lower surface FS of each of the multiple trenches TRC. Therefore, as Figure 11 As shown in FIG, the width Went3 of the entrance ENT of the trench TRC, which is redefined by the third pixel defining layer PDL3, can be reduced compared to the width Went2 of the original entrance ENT of the trench TRC. For example, the width Went3 of the entrance ENT of the trench TRC, which is redefined by the third pixel defining layer PDL3, can be greater than about 100 nm and less than about 130 nm. Therefore, the first and second stacked layers IL1 and IL2, and the first and second charge generation layers, can be reliably cut off in the trench TRC.

[0259] Fifth, if Figure 23 As shown in FIG, the first pixel defining layer PDLL1 is etched (see Figure 22 ), the second pixel defining layer PDLL2 (see Figure 22 ) and the third pixel defining layer PDLL3 (see Figure 22 ) to form a pixel defining layer PDL, and partially expose each of the plurality of first electrodes AND ( Figure 19 Step S250).

[0260] because Figure 19 Step S250 and Figure 12 The step S140 is basically the same as that of Figure 19 Detailed description of step S250.

[0261] Sixth, as Figure 24 As shown in FIG, a light emitting stack IL is formed on a portion of each of the plurality of first electrodes AND and the pixel defining layer PDL. Figure 19 In addition, a second electrode CAT and an encapsulation layer TFE ( Figure 19 Step S270).

[0262] because Figure 19 Step S260 and Figure 12 The step S150 is basically the same as that of Figure 19 Detailed description of step S260.

[0263] Figure 25 is a schematic perspective view showing a head-mounted display according to the embodiment. Figure 26 It shows Figure 25 An exploded schematic perspective view of an example of a head-mounted display.

[0264] Reference Figure 25 and Figure 26 According to an embodiment, the head-mounted display 1000 may include a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, a middle frame 1400, a first optical member 1510, a second optical member 1520 and a control circuit board 1600.

[0265] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figure 1 and Figure 2 The display devices 10 described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 may be omitted.

[0266] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0267] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0268] The control circuit board 1600 may be provided between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 via a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA (see Figure 2 ), and transmits the digital video data DATA to the first display device 10_1 and the second display device 10_2 via the connector.

[0269] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. For example, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0270] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is provided to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210, where the user's left eye is located, and a second eyepiece 1220, where the user's right eye is located. In an embodiment, one side of the housing cover 1200 may extend in the X direction, another side of the housing cover 1200 may extend in the Y direction, and the Z direction may be perpendicular to the plane defined by the X and Y directions. Figure 25 and Figure 26 The first eyepiece 1210 and the second eyepiece 1220 are shown as being separately provided, but the embodiments of the present specification are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0271] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user can observe the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can observe the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0272] The head-mounted strap 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain respectively positioned on the user's left eye and right eye. In the case where the display device housing 1100 is implemented to be lightweight and compact, the head-mounted display 1000 can be provided with an eyeglass frame (such as a pair of glasses). Figure 27 ) instead of the headband 1300.

[0273] The head-mounted display 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0274] Figure 27 is a schematic perspective view showing a head-mounted display according to the embodiment.

[0275] Reference Figure 27 The head-mounted display 1000_1 according to an embodiment may be a glasses-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to an embodiment may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and the display device housing 1200_1.

[0276] The display device housing 1200_1 may include a display device 10_3, an optical member 1060, and an optical path changing member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060 and provided to the right eye of the user via the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user can observe, via the right eye, an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed via the right-eye lens 1020 are combined.

[0277] Figure 27 The display device housing 1200_1 is shown as being disposed at the right end of the support frame 1030, but embodiments of the present specification are not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, and, for example, the image of the display device 10_3 may be provided to the user's left eye. For example, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, and, for example, the user may view the image displayed on the display device 10_3 through both the left eye and the right eye.

[0278] However, it should be understood that the aspects and features of the embodiments are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the claims and their equivalents therein.

Claims

1. A display device, wherein: The display device includes: an insulating layer disposed on the substrate; a first electrode, disposed on the insulating layer; a first pixel defining layer, covering a portion of the first electrode; a second pixel defining layer, disposed on the first pixel defining layer; a groove penetrating the first pixel defining layer and the second pixel defining layer; a light emitting stack disposed on an upper surface of the first electrode and an upper surface of the second pixel defining layer; and a second electrode disposed on the light-emitting stack, The width of the entrance of the groove in one direction is greater than the width of the lower surface of the groove in the one direction.

2. The display device according to claim 1, wherein A length of a sidewall of the trench defined by the insulating layer is greater than a length of a sidewall of the trench defined by the first pixel defining layer and the second pixel defining layer.

3. The display device according to claim 1, wherein The height of the groove is to within the range.

4. The display device according to claim 1, wherein The display device further includes: a third pixel defining layer, disposed on the second pixel defining layer; Wherein, the groove penetrates the third pixel defining layer.

5. The display device according to claim 4, wherein The sum of the thickness of the first pixel defining layer, the thickness of the second pixel defining layer, and the thickness of the third pixel defining layer is less than or equal to 1 / 4 of the height of the groove. The display device according to claim 4 , wherein: An angle formed between an upper surface of the third pixel defining layer and a tangent line of a sidewall of the trench at the entrance of the trench is in a range of 80° to 90°.

7. The display device according to claim 1, wherein The light emitting stack comprises: a first stacked layer disposed at an edge of the inlet of the groove; and The second stacking layer is arranged on the first stacking layer.

8. The display device according to claim 7, wherein: The light emitting stack further includes a third stack layer disposed on the second stack layer, wherein the third stack layer covers the entrance of the groove.

9. The display device according to claim 1, wherein The display device further includes: a third pixel defining layer, disposed on the second pixel defining layer; Wherein, the third pixel defining layer is arranged on the sidewalls and the lower surface of the groove.

10. The display device according to claim 9, wherein The light emitting stack comprises: a first stacked layer disposed on the third pixel defining layer; and The second stacking layer is arranged on the first stacking layer.

11. The display device according to claim 10, wherein: A thickness of a portion of the first stacked layer disposed on a sidewall of the trench defined by the insulating layer is smaller than a thickness of a portion of the first stacked layer disposed on the lower surface of the trench.

12. The display device according to claim 10, wherein: A thickness of a portion of the first stacked layer disposed on a sidewall of the trench defined by the second pixel defining layer is greater than a thickness of a portion of the first stacked layer disposed on a sidewall of the trench defined by the insulating layer.

13. The display device according to claim 10, wherein: The light emitting stack further includes a third stack layer disposed on the second stack layer, wherein the third stack layer covers the entrance of the groove.

14. A method for manufacturing a display device, wherein: The method comprises: forming an insulating layer on a substrate, and forming a plurality of first electrodes on the insulating layer; forming a pixel defining layer covering the plurality of first electrodes; forming a plurality of grooves penetrating the pixel defining layer; etching the pixel defining layer to form a pixel defining layer to partially expose each of the plurality of first electrodes; forming a first stacked layer on a portion of each of the plurality of first electrodes and the pixel defining layer; forming a second stacked layer on the first stacked layer; and forming a second electrode covering the second stacked layer, The first stacked layer is disposed at an edge of an entrance of the groove, and the second stacked layer covers the entrance of the groove.

15. The method according to claim 14, wherein The forming of the pixel defining layer includes forming a first pixel defining layer covering the plurality of first electrodes, forming a second pixel defining layer covering the first pixel defining layer, and forming a third pixel defining layer covering the second pixel defining layer.

16. The method according to claim 15, wherein The etching the pixel defining layer to form the pixel defining layer to partially expose each of the plurality of first electrodes comprises: forming a first mask pattern on a portion of the third pixel defining layer, and etching a portion of the third pixel defining layer not covered by the first mask pattern to form a third pixel defining layer; forming a second mask pattern on a portion of the second pixel defining layer and all portions of the third pixel defining layer, and etching a portion of the second pixel defining layer not covered by the second mask pattern to form a second pixel defining layer; and A third mask pattern is formed on a portion of the first pixel defining layer, all portions of the second pixel defining layer, and all portions of the third pixel defining layer, and portions of the first pixel defining layer not covered by the third mask pattern are etched to partially expose each of the plurality of first electrodes.

17. A method for manufacturing a display device, wherein: The method comprises: forming an insulating layer on a substrate, and forming a plurality of first electrodes on the insulating layer; forming a first pixel defining layer covering the plurality of first electrodes, and forming a second pixel defining layer on the first pixel defining layer; forming a plurality of grooves penetrating the first pixel defining layer and the second pixel defining layer; forming a third pixel defining layer on the second pixel defining layer; etching each of the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer to form a first pixel defining layer, a second pixel defining layer, and a third pixel defining layer to partially expose each of the plurality of first electrodes; forming a first stacked layer on a portion of each of the plurality of first electrodes, the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer; forming a second stacked layer on the first stacked layer; and forming a second electrode covering the second stacked layer, Wherein, the third pixel defining layer is arranged on the sidewall and lower surface of the groove, The first stacked layer is disposed on the third pixel defining layer, and The second stacked layer covers the entrance of the groove.

18. The method according to claim 17, wherein The forming of the first pixel defining layer and the second pixel defining layer includes: forming a first pixel defining layer covering the plurality of first electrodes; and A second pixel defining layer is formed to cover the first pixel defining layer.

19. The method according to claim 18, wherein The etching each of the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer to form the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer to partially expose each of the plurality of first electrodes includes: forming a first mask pattern on a portion of the third pixel defining layer, and etching a portion of the third pixel defining layer not covered by the first mask pattern to form a third pixel defining layer; forming a second mask pattern on a portion of the second pixel defining layer and all portions of the third pixel defining layer, and etching a portion of the second pixel defining layer not covered by the second mask pattern to form a second pixel defining layer; and A third mask pattern is formed on a portion of the first pixel defining layer, all portions of the second pixel defining layer, and all portions of the third pixel defining layer, and portions of the first pixel defining layer not covered by the third mask pattern are etched to partially expose each of the plurality of first electrodes.

20. A head-mounted display, wherein: The head-mounted display comprises: at least one display device; a display device housing accommodating the at least one display device; and an optical component for amplifying a display image of the at least one display device or changing an optical path, wherein: The at least one display device comprises: an insulating layer disposed on the substrate; a first electrode, disposed on the insulating layer; a first pixel defining layer, covering a portion of the first electrode; a second pixel defining layer, disposed on the first pixel defining layer; a groove penetrating the first pixel defining layer and the second pixel defining layer; a light emitting stack disposed on an upper surface of the first electrode and an upper surface of the second pixel defining layer; and a second electrode disposed on the light-emitting stack, A width of the inlet of the groove in one direction is greater than a width of the lower surface of the groove in the one direction.

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