Light emitting apparatus, wearable device, display apparatus, photoelectric conversion apparatus, and electronic equipment

Abstract

The invention provides a light emitting apparatus, a wearable device, a display apparatus, a photoelectric conversion apparatus, and an electronic apparatus. The light emitting device includes a plurality of pixels arranged in a substrate, in which the plurality of pixels each include a first isolation portion configured in a trench type to isolate two adjacent regions having different conductivity types from each other, and a second isolation portion configured in a trench type to isolate two adjacent regions having different conductivity types from each other. The second isolation portion is configured in a trench type to isolate two adjacent regions having the same conductivity type from each other, and a depth of the second isolation portion is greater than a depth of the first isolation portion.

Description

Technical Field

[0001] The present invention relates to a light-emitting device, a wearable device, a display device, a photoelectric conversion device and electronic equipment. Background Art

[0002] Organic EL elements are becoming the main light-emitting devices (display devices) to replace liquid crystals due to their low power consumption and fast response speed, and are in need of further performance improvement. The organic EL element includes a pixel array of an organic layer that emits light. In the pixel array, a plurality of transistors are provided for passing currents corresponding to various brightness signal voltages. It is known to use shallow trench isolation (STI) with a groove structure to electrically isolate multiple transistors. Japanese Patent Laid-Open No. 2020-71323 discloses that STI is formed at a constant depth within a pixel.

[0003] In the arrangement disclosed in Japanese Patent Laid-Open No. 2020-71323, in order to increase pixel density and achieve higher resolution in the future, it may be required to reduce the isolation width between transistors in the pixel array, thereby reducing the pixel size. If this requirement is simply met by reducing the isolation width between transistors, it will be difficult to maintain the breakdown voltage within the pixel, and degradation of image quality (i.e., reduction in display quality) such as reduction in display contrast due to leakage current between pixels may occur. Summary of the Invention

[0004] For example, the present invention provides a technique that facilitates both maintenance of breakdown voltage within a pixel and reduction of pixel size in a light emitting device.

[0005] According to one aspect of the present invention, a light-emitting device is provided, which includes a plurality of pixels arranged in a substrate, wherein each of the plurality of pixels includes a first isolation portion and a second isolation portion, the first isolation portion is configured in a groove type to isolate two adjacent regions with different conductivity types from each other, the second isolation portion is configured in a groove type to isolate two adjacent regions with the same conductivity type from each other, and the depth of the second isolation portion is greater than the depth of the first isolation portion.

[0006] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram showing an example of the arrangement of a light emitting device according to the first embodiment;

[0008] Figure 2 is an enlarged plan view of one pixel in the light emitting device according to the first embodiment;

[0009] Figure 3is a cross-sectional view of each pixel in the light emitting device according to the first embodiment;

[0010] Figures 4A to 4D A diagram for explaining a method of forming a first element isolation portion and a second element isolation portion in a semiconductor substrate;

[0011] Figure 5 is a cross-sectional view of each pixel in a light emitting device according to a second embodiment;

[0012] Figure 6A and Figure 6B is a cross-sectional view showing an example of pixel arrangement of a light emitting device according to various embodiments;

[0013] Figure 7 is a diagram illustrating an example of a display device using the light emitting device according to each embodiment;

[0014] Figure 8 is a diagram illustrating an example of a photoelectric conversion device using the light emitting device according to each embodiment;

[0015] Figure 9 is a diagram showing an example of electronic equipment using the light emitting device according to various embodiments;

[0016] Figure 10A and Figure 10B are diagrams each showing an example of a display device using the light emitting device according to each embodiment; and

[0017] Figure 11A and Figure 11B are diagrams each showing an example of a wearable device using a light emitting device according to each embodiment. DETAILED DESCRIPTION

[0018] The following embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention. While a plurality of features are described in the embodiments, the present invention is not limited to requiring all of these features, and a plurality of such features may be appropriately combined. In addition, in the accompanying drawings, the same reference numerals are given to the same or similar configurations, and redundant descriptions thereof are omitted.

[0019] Note that all the following embodiments are merely examples of the present invention, and numerical values, shapes, materials, components, and arrangements and connections of the components are not intended to limit the scope of the present invention.

[0020] <First embodiment>

[0021] A first embodiment according to the present invention will be described. Figure 11 is a block diagram illustrating an example arrangement of a light-emitting device 10 according to this embodiment. A pixel array 100 (pixel unit) includes a plurality of pixels 101 arranged two-dimensionally (in a matrix) across a plurality of rows and columns on a substrate. Control signals are input to each pixel 101 from a vertical scanning circuit 102 via scan lines 103, and luminance signal voltages are input to each pixel 101 from a signal output circuit 104 via signal lines 105. The vertical scanning circuit 102 and the signal output circuit 104 are controlled by a control circuit 106 (control unit). The signal output circuit 104 converts image data input to the pixels in each column scanned by the horizontal scanning circuit into analog signal voltages and outputs luminance signal voltages corresponding to the analog signal voltages to signal lines 105.

[0022] Figure 2 This is an enlarged plan view of a pixel 101 in the light-emitting device 10 according to the present embodiment, and shows an example of arranging two sub-pixels (a first sub-pixel 206 and a second sub-pixel 207) with different luminous colors. Each sub-pixel can be formed as a unit by a switching transistor 201, a driving transistor 202, a reset transistor 203, a selection transistor 204, and a well contact 205. The switching transistor 201 controls the light emission of the light-emitting element. The driving transistor 202 supplies a current corresponding to the data input as a brightness signal from the selection transistor 204 to the light-emitting element, thereby driving the light-emitting element. The reset transistor 203 resets the light-emitting element. The selection transistor 204 controls the input of data to the pixel (light-emitting element). The well contact 205 electrically connects the well in the semiconductor substrate and the wiring layer arranged on the semiconductor substrate. In the present embodiment, the switching transistor 201, the driving transistor 202, the reset transistor 203, and the selection transistor 204 each include a source / drain formed by a p-type semiconductor region, and the well contact 205 is formed by an n-type semiconductor region. The various transistors and the well contacts are electrically isolated by a trench-type (groove structure) element isolation portion to be described later. As the trench-type element isolation portion, shallow trench isolation (STI) can be used. Note that in this embodiment, the description will be given assuming that each of the various types of transistors has p-type conductivity, but each transistor may have n-type conductivity.

[0023] Figure 3 An example of a cross-sectional view of each pixel 101 in the light emitting device 10 according to the present embodiment is shown. Figure 3 A cross-sectional view is for example along Figure 2' is a cross-sectional view taken along line Y-Y' in FIG. Each pixel 101 in the present embodiment may include a light-emitting element 312 and a pixel circuit 311 that drives the light-emitting element 312. In addition, in each pixel 101 in the present embodiment, a first element isolation portion 301 and a second element isolation portion 302 are formed in the semiconductor substrate 300 as a trench-type element isolation portion that isolates various transistors and well contacts in the pixel circuit 311. The first element isolation portion 301 and the second element isolation portion 302 have different depths (trench depths). More specifically, the depth of the second element isolation portion 302 is greater than the depth of the first element isolation portion 301. Note that the following description will be given assuming that the pixel circuit 311 has p-type conductivity, but the pixel circuit 311 may have n-type conductivity.

[0024] The pixel circuit 311 constituting the pixel array 100 (each pixel 101) is arranged in the semiconductor substrate 300, and various transistors are formed in the pixel circuit 311. Each of the various transistors includes an n-type well 320, a p-type lightly doped region 321, a p-type source / drain 322, a gate electrode 303, a sidewall 304, and a silicide prevention film 305. Two transistors adjacent to each other are isolated by the first element isolation portion 301 or the second element isolation portion 302. Figure 3 As shown, the first element isolation portion 301 and the second element isolation portion 302 can be appropriately used in a single sub-pixel or between multiple sub-pixels. In the latter case, for example, the first element isolation portion 301 can be used alone in one sub-pixel, and the second element isolation portion 302 can be used alone in another sub-pixel. In other words, various variations and combinations of the first element isolation portion 301 and the second element isolation portion 302 are possible.

[0025] Silicide 306 is formed on the portion where the silicide prevention film 305 is not provided so that the semiconductor substrate 300 (e.g., silicon) is exposed. A wiring interlayer film 307, a plug 308, wiring 309, and a metal electrode 310 are formed on the silicide 306. The metal electrode 310 is divided into B sub-pixels 331, G sub-pixels 332, and R sub-pixels 333. Light-emitting elements 312 that emit light of each color are formed on the metal layer 310 of each sub-pixel.

[0026] The light-emitting element 312 includes an optical adjustment layer 334 that highly satisfies the optical interference conditions for each luminescent color, a transparent anode electrode 335, a pixel isolation layer 336, an organic light-emitting layer 337, and a cathode electrode 338. A protective layer 339 is formed on the cathode electrode 338, and a blue filter 341b, a green filter 341g, and a red filter 341r, each having the spectral characteristics of the color of the corresponding sub-pixel, are arranged on the protective layer 339. Thus, light emission corresponding to the luminance signal voltage input to each sub-pixel can be obtained.

[0027] In the light-emitting device 10 according to this embodiment, the first element isolation portion 301 or the second element isolation portion 302 is arranged between the element regions (transistor region and well contact region) in the pixel circuit 311, depending on the required breakdown voltage. This makes it possible to achieve both maintenance of the breakdown voltage in the pixel 101 and reduction in pixel size. Note that, as described above, the second element isolation portion 302 is formed to have a trench depth greater than the trench depth of the first element isolation portion 301.

[0028] The first element isolation portion 301 (first isolation portion) is arranged to electrically isolate two adjacent regions having different conductivity types. In this embodiment, the first element isolation portion 301 can be arranged between the well contact 205 and the adjacent switch transistor 201 and / or between the well contact 205 and the adjacent drive transistor 202. The first element isolation portion 301 can also be arranged between the well contact 205 and the adjacent reset transistor 203 and / or between the well contact 205 and the adjacent select transistor 204.

[0029] For example, in Figure 3 In the example shown, the conductivity type of the semiconductor region 351a (first semiconductor region) forming the source / drain of the transistor 351 is different from the conductivity type of the semiconductor region 352 (third semiconductor region) forming the adjacent well contact. Therefore, the first element isolation unit 301 is arranged between the transistor 351 (semiconductor region 351a) and the well contact (semiconductor region 352).

[0030] On the other hand, the second element isolation portion 302 (second isolation portion) is arranged to electrically isolate two adjacent regions having the same conductivity type. In the present embodiment, the second element isolation portion 302 can be arranged between two drive transistors 202 arranged adjacent to each other and / or between two reset transistors 203 arranged adjacent to each other. The second element isolation portion 302 can be arranged between two switch transistors arranged adjacent to each other. The second element isolation portion 302 can be arranged between the reset transistor and the adjacent switch transistor 201 and / or between the switch transistor 201 and the adjacent select transistor 204.

[0031] For example, in Figure 3 In the example shown, the semiconductor region 353a (first semiconductor region) forming the source / drain of the transistor 353 and the semiconductor region 354a (second semiconductor region) forming the source / drain of the adjacent transistor 354 have the same conductivity type. Therefore, the second element isolation unit 302 is arranged between the transistor 353 (semiconductor region 353a) and the transistor 354 (semiconductor region 354a).

[0032] The reasons and effects of appropriately using the first element isolation portion 301 and the second element isolation portion 302 in the light emitting device 10 according to the present embodiment will be described below.

[0033] The source / drain region of each driver transistor is formed by a p-type semiconductor region. Therefore, between two adjacent driver transistors, a PNP parasitic bipolar transistor consisting of a p-type source / drain 322, an n-type well 320 and a p-type source / drain 322 can be formed via an element isolation portion. In order to reduce the current flowing through the PNP parasitic bipolar transistor, it is effective to increase the base width (i.e., the width of the n-type region) of the parasitic bipolar transistor. However, increasing the width of the element isolation portion in a direction parallel to the surface of the semiconductor substrate 300 to increase the base width (the width of the n-type region) can make it difficult to reduce the pixel size. Therefore, in this embodiment, in order to increase the base width (the width of the n-type region) of the parasitic bipolar transistor, the depth of the element isolation portion arranged between the two adjacent driver transistors is increased. That is, the second element isolation portion 302 is arranged between the two adjacent driver transistors. This can suppress the operation of the parasitic bipolar transistor while suppressing the increase in the width of the element separation portion in a direction parallel to the surface of the semiconductor substrate 300.

[0034] The drive transistor is a transistor configured to flow a current corresponding to an arbitrary brightness signal voltage for each pixel. Therefore, a higher voltage is applied to the source / drain region of the drive transistor than to other transistors such as the reset transistor, the switch transistor, or the select transistor. Depending on the brightness signal in the pixel, the maximum voltage in the sub-pixel can be applied to the source / drain region of the drive transistor. Therefore, the highest breakdown voltage in the pixel is required between the source / drain region of the drive transistor and the source / drain region of the adjacent drive transistor.

[0035] For the above reasons, in the light-emitting device 10 according to this embodiment, the second element isolation portion 302 is arranged between a drive transistor (e.g., transistor 353) and an adjacent drive transistor (e.g., transistor 354). For the same reason, the second element isolation portion 302 may be arranged between two adjacent regions of the same conductivity type, such as between a reset transistor and an adjacent reset transistor.

[0036] On the other hand, the first element isolation portion 301 having a depth less than that of the second element isolation portion 302 can be arranged between the well contact and the adjacent reset transistor. Between the well contact and the adjacent reset transistor, a pn junction consisting of a p-type source / drain 322, an n-type well 320 and an n-type source / drain is simply formed via the element isolation portion. As described above, there are two pn junctions between the drive transistor and the adjacent drive transistor, and the operation of the parasitic bipolar transistor needs to be suppressed. On the other hand, only one pn junction is formed near the well contact. Therefore, the breakdown voltage has a low dependence on the width of the n-type region. That is, the depth of the first element isolation portion 301 can be made less than (shallower than) the depth of the second element isolation portion 302. Generally, the smaller the depth of the element isolation portion, the better the embedding characteristics of the insulating film. Therefore, a finer isolation width can be achieved, which is conducive to reducing the pixel size.

[0037] Furthermore, by arbitrarily controlling the well potential via the well contact portion, leakage current flowing between the source and drain of the transistor can be reduced by utilizing the back-gate effect on the transistor in pixel circuit 311. In this case, by reducing the depth of the element isolation portion around the well contact portion, the distance from the well contact region is shortened, and the potential drop can be reduced. Due to the reduced potential drop, variations in the back-gate effect can be reduced.

[0038] In this way, by appropriately using the first element isolating portion 301 and the second element isolating portion 302 in the light-emitting device 10 according to this embodiment, the aforementioned effects can be achieved. Specifically, in locations where breakdown voltage is required, the second element isolating portion 302 can be used to reduce leakage current within the pixel, while in locations where there is a margin for breakdown voltage, the width of the element isolating portion can be reduced by using the first element isolating portion 301. Consequently, it is possible to achieve both maintaining the breakdown voltage within the pixel of the light-emitting device 10 (suppressing degradation in display quality) and reducing pixel size.

[0039] (Method for manufacturing light-emitting device)

[0040] The following will refer to Figure 3 Cross-sectional view and Figures 4A to 4D The cross-sectional view of FIG1 exemplarily describes a method for manufacturing the light emitting device 10. First, referring to FIG1 . Figures 4A to 4D , an example of a method of forming the first element isolation portion 301 and the second element isolation portion 302 in the semiconductor substrate 300 will be described.

[0041] Figure 4AThe following figure shows the steps for forming the trench Tr1 constituting the first element isolation unit 301 in the semiconductor substrate 300. More specifically, a hard mask formed of an oxide film 401, polysilicon 402, and a silicon nitride film 403 is deposited on the semiconductor substrate 300, and a first photoresist 404 is applied over the hard mask. The first photoresist 404 is then patterned using photolithography to form an opening only in the region where the first element isolation unit 301 is to be formed. After patterning, dry etching is performed using the first photoresist 404 as a mask, thereby forming the trench Tr1 in the semiconductor substrate 300.

[0042] Figure 4B The step of forming the trench Tr2 constituting the second element isolation unit 302 in the semiconductor substrate 300 is shown. More specifically, after removing the first photoresist 404, a second photoresist 405 is applied to the semiconductor substrate 300. Then, the second photoresist 405 is patterned by photolithography to form an opening only in the region where the second element isolation unit 302 is to be formed. After patterning, dry etching is performed using the second photoresist 405 as a mask, thereby forming the trench Tr2 in the semiconductor substrate 300.

[0043] Through the above steps, the depth of the groove (recess) of each of the first element isolation portion 301 and the second element isolation portion 302 can be arbitrarily changed. As an example, the depth of the groove is approximately 100 to 400 nm in the first element isolation portion 301, and approximately 400 to 800 nm in the second element isolation portion 302. In other words, the depth of the groove of the second element isolation portion 302 can be four to eight times the depth of the groove of the first element isolation portion 301.

[0044] Figure 4C The steps of forming an insulator in each of the trenches Tr1 and Tr2 formed in the semiconductor substrate 300 are shown. More specifically, an insulating film is formed on the inner wall (side and bottom) of each of the trenches Tr1 and Tr2 using thermal oxidation in an oxidizing gas environment. Thereafter, an insulator is filled into each of the trenches Tr1 and Tr2 to cover the insulating film formed on the inner wall of each of the trenches Tr1 and Tr2. The insulator to be filled into each of the trenches Tr1 and Tr2 is, for example, a silicon oxide film formed by a high-density plasma CVD method. The insulator is deposited to a film thickness that allows it to fill each of the trenches Tr1 and Tr2 to become the first element isolation portion 301 and the second element isolation portion 302, respectively. The insulator filled in each trench Tr1 can be flattened by a combination of etching and chemical mechanical polishing (CMP).

[0045] Figure 4DA step of removing the hard mask on the semiconductor substrate 300 is shown. More specifically, the silicon nitride film 403 and the polysilicon 402 on the semiconductor substrate 300 are removed. Before removing the polysilicon 402, the film thickness of the insulator in each of the trenches Tr1 and Tr2 can be adjusted by wet etching. The oxide film 401 on the semiconductor substrate 300 can also be removed. With this step, the trench Tr1 is formed as the first element isolation portion 301, and the trench Tr2 is formed as the second element isolation portion 302. Here, since the first element isolation portion 301 and the second element isolation portion 302 have different trench depths, the height (protrusion amount) from the surface of the semiconductor substrate 300 can be different between the first element isolation portion 301 and the second element isolation portion 302. Alternatively, wet etching can be used to control the height of the first element isolation portion 301 and the second element isolation portion 302 (i.e., the amount of protrusion from the semiconductor substrate 300) to be the same.

[0046] Next, refer to Figure 3 , an example of a method of manufacturing the pixel array 100 from the semiconductor substrate 300 on which the first element isolation portion 301 and the second element isolation portion 302 are formed will be described.

[0047] pass Figure 4D In the above steps shown, after forming the first element isolation portion 301 and the second element isolation portion 302 in the semiconductor substrate 300, a thermal oxide film is formed on the surface of the semiconductor substrate 300. The thermal oxide film is provided to suppress channeling during ion implantation. In a state where a predetermined area is protected by a resist, an n-type well 320 is formed by multi-stage ion implantation. For example, an acceleration energy of 10 to 2000 keV and an ion implantation temperature of about 1×10 11 to 5×10 13 / cm 2 The multi-stage ion implantation can be adjusted within a range of a desired dose. The dose can be changed depending on the depth of the multi-stage ion implantation. The n-type well 320 can be formed to have a high concentration in a region shallower than the bottom of the first element isolation portion 301 and the second element isolation portion 302, and a low concentration in a region deeper than the bottom of the first element isolation portion 301 and the second element isolation portion 302.

[0048] Then, a gate oxide film and a gate electrode 303 are formed. Thereafter, a p-type lightly doped region 321 is formed by ion implantation in a state where a predetermined region is protected by a resist. For example, the p-type lightly doped region 321 can be formed at an acceleration energy of 10 to 150 keV and a temperature of about 1×10 11 to 5×10 14 / cm 2 The dose can be adjusted within a range of doses. The dose can be changed according to the depth of the multi-stage ion implantation.

[0049] Then, the sidewalls 304 of the transistor are formed. The sidewalls 304 can be formed by depositing a silicon oxide film and a silicon nitride film and then etching them back. The sidewalls 304 can be a single layer of a silicon oxide film or a silicon nitride film, or can have a stacked structure thereof.

[0050] Then, in a state where the predetermined area is protected by the resist, the p-type source / drain 322 is formed by ion implantation. At this time, in order to form an offset MOSFET, the resist pattern can be formed so that the p-type source / drain 322 is implanted at a predetermined distance from the end of the gate electrode 303. For example, the p-type source / drain 322 can be implanted at an acceleration energy of 3 to 30 keV and about 1e 13 to 7e 15 / cm 2 Then, a heat treatment for dopant activation may be performed in sequence.

[0051] Here, it is desirable that the second element isolation portion 302 is formed to have a depth greater than that of the first element isolation portion 301 by 0.3 μm or more. Note that it is desirable that the second element isolation portion 302 is formed to have a depth shallower than the bottom of the n-type well 320. This is because if the depth of the second element isolation portion 302 is deeper than the bottom of the well 320, the potential of the well 320 becomes floating, and leakage current may be generated.

[0052] It is also desirable that the first element isolation portion 301 (trench Tr1) is formed to have an opening width narrower than the opening width of the second element isolation portion 302 (trench Tr2) in a direction parallel to the surface of the semiconductor substrate 300. This is to shorten the distance between the well contact and the transistor and reduce the potential drop. The minimum opening width of the first element isolation portion 301 is preferably 0.1 μm or greater and less than 0.2 μm, and the minimum opening width of the second element isolation portion 302 is preferably 0.2 μm or greater and less than 0.5 μm. The depth and opening width of each element isolation portion can be appropriately changed according to the voltage required for each pixel. By using the first element isolation portion 301 in a position where the source-drain breakdown voltage is not required, the opening width can be reduced, and this can contribute to a reduction in pixel pitch.

[0053] Note that in this embodiment, an example has been described in which two types of element isolating portions (first element isolating portion 301 and second element isolating portion 302) are provided in each pixel 101, but the present invention is not limited thereto. Three or more types of element isolating portions having different depths or opening widths may be provided in each pixel 101.

[0054] Then, to define the metal silicide region, a silicide protection layer using an oxide film is formed. The silicide protection layer is formed to prevent the formation of metal silicide in the lightly doped drain (LDD) region. After that, contact plugs are formed, and a multilayer wiring layer is formed.

[0055] An optical adjustment layer 334 having different heights is formed on the metal electrode 310 based on the interference of the emission wavelengths of the B sub-pixels 331, G sub-pixels 332, and R sub-pixels 333. A transparent anode electrode 335, a pixel isolation layer 336 for isolating pixels, an organic light-emitting layer 337, and a cathode electrode 338 are sequentially deposited on the optical adjustment layer 334. After a protective layer 339 is further deposited on the cathode electrode 338, a blue filter 341b, a green filter 341g, and a red filter 341r are formed on the protective layer 339.

[0056] As described above, in each pixel 101 of the light-emitting device 10 according to the present embodiment, a first trench-type element isolation portion 301 and a second trench-type element isolation portion 302 having a depth greater than that of the first element isolation portion 301 are arranged. The first element isolation portion 301 is arranged to electrically isolate two adjacent regions having different conductivity types, and the second element isolation portion 302 is arranged to electrically isolate two adjacent regions having the same conductivity type. This can achieve both the maintenance of the breakdown voltage in the pixel 101 and the reduction of the pixel size. Here, the light-emitting device 10 according to the present embodiment does not need to always be formed according to the above-mentioned manufacturing method and step sequence, and replacement and change of various steps are possible. The groove depth and the step sequence can be reversed. This embodiment is for illustrating several modes to which the present invention can be applied. Various changes and deformations can be appropriately made without departing from the spirit and scope of the present invention.

[0057] <Second embodiment>

[0058] A second embodiment according to the present invention will be described. This embodiment basically succeeds the first embodiment, and matters not mentioned below can follow the first embodiment.

[0059] Figure 5 An example of a cross-sectional view of each pixel 101 in the light-emitting device 10 according to this embodiment is shown. In this embodiment, an example will be described in which the second element isolation portion 302 is formed to include an upper layer portion 302a and a lower layer portion 302b stacked on each other. Note that in this embodiment, an example will be described in which the second element isolation portion 302 has a two-stage structure combining the upper layer portion 302a and the lower layer portion 302b. However, the present invention is not limited to this, and a three-stage or more-stage structure combining three or more layer portions may be used.

[0060] The second element isolation portion 302 in this embodiment is formed by connecting the lower portion 302b to a portion of the bottom surface of the upper portion 302a. The width (diameter or area) of the portion of the bottom surface of the upper portion 302a connected to the lower portion 302b is preferably smaller than the width (diameter or area) of the bottom surface of the upper portion 302a. The "portion of the bottom surface of the upper portion 302a connected to the lower portion 302b" can be understood as the upper portion (connecting portion) of the lower portion 302b connected to the upper portion 302a. The maximum width (diameter or area) of the lower portion 302b is preferably smaller than the width (diameter or area) of the bottom surface of the upper portion 302a.

[0061] In the second element isolation part 302 of the present embodiment, the depth of the lower portion 302b is preferably greater than the depth of the upper portion 302a. That is, the ratio of the depth of the lower portion 302b to the depth of the upper portion 302a is preferably 1 or greater. In addition, in the second element isolation part 302 of the present embodiment, the opening width of the groove constituting the upper portion 302a is preferably greater than the opening width of the groove constituting the lower portion 302b. Thus, the width of the active region of the transistor in the semiconductor region can be arbitrarily controlled by the opening width of the upper portion 302a of the second element isolation part 302.

[0062] As described above, in the present embodiment, the second element isolation portion 302 is formed by the upper portion 302a and the lower portion 302b. This allows the upper portion 302a of the second element isolation portion 302 and the first element isolation portion 301 to be formed in the same step. Therefore, the effect of making the height from the surface of the semiconductor substrate 300 constant (the same) between the first element isolation portion 301 and the second element isolation portion 302 can be obtained. When the height from the surface of the semiconductor substrate 300 is constant between the element isolation portions 301 and 302, the flatness of the semiconductor substrate 300 during processing is improved, making it possible to process the gate electrode and the like more finely. In addition, according to the present embodiment, the depth of the upper portion 302a of the second element isolation portion 302 can be made smaller (shallower) than the depth of the entire second element isolation portion 302 in the first embodiment. Therefore, the insulator is more advantageously (easily) embedded in the trench Tr2, and the trench width itself can also be formed more finely.

[0063] [Configuration of organic light-emitting elements]

[0064] An organic light-emitting element is constructed by forming an insulating layer, a first electrode, an organic compound layer, and a second electrode on a substrate. A protective layer, a color filter, a microlens, and the like may be provided on the cathode. If a color filter is provided, a planarization layer may be provided between the protective layer and the color filter. The planarization layer may be made of, for example, acrylic resin. This also applies to the case where a planarization layer is provided between the color filter and the microlens.

[0065] [Substrate]

[0066] Quartz, glass, silicon wafers, resins, metals, and the like can be used as the substrate. Furthermore, switching elements such as transistors and wiring can be provided on the substrate, and an insulating layer can be provided thereon. The insulating layer can be made of any material as long as contact holes can be formed so that wiring can be formed between the insulating layer and the first electrode and insulation from unconnected wiring can be ensured. For example, resins such as polyimide, silicon oxide, and silicon nitride can be used.

[0067] [electrode]

[0068] A pair of electrodes can serve as electrodes. This pair of electrodes can be an anode and a cathode. If an electric field is applied in the direction in which the organic light-emitting element emits light, the electrode with the higher potential becomes the anode, and the other becomes the cathode. Alternatively, the electrode that supplies holes to the light-emitting layer is the anode, and the electrode that supplies electrons is the cathode.

[0069] As the constituent material of the anode, it is preferable to use a material with a work function as large as possible. For example, materials such as gold, platinum, silver, copper, nickel, palladium, cobalt, selenium, vanadium, or tungsten, mixtures containing some of them, alloys obtained by combining some of them, or metal oxides such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), or zinc indium oxide can be used. In addition, conductive polymers such as polyaniline, polypyrrole, or polythiophene can also be used.

[0070] One of these electrode materials may be used alone, or two or more of these electrode materials may be used in combination. The anode may be formed of a single layer or a multilayer.

[0071] If the anode is used as a reflective electrode, for example, chromium, aluminum, silver, titanium, tungsten, molybdenum, alloys thereof, stacked layers thereof, etc. can be used. The above materials can be used as a reflective film that does not function as an electrode. If the anode is used as a transparent electrode, an oxide transparent conductive layer made of indium tin oxide (ITO), indium zinc oxide, etc. can be used, but the present invention is not limited thereto. The electrode can be formed using photolithography technology.

[0072] On the other hand, as a constituent material of the cathode, a material having a small work function is preferably used. Examples of such materials include alkali metals such as lithium, alkaline earth metals such as calcium, metals such as aluminum, titanium, manganese, silver, lead or chromium, and mixtures containing some of them. Alternatively, alloys obtained by combining these metals can also be used. For example, magnesium-silver alloys, aluminum-lithium alloys, aluminum-magnesium alloys, silver-copper alloys, zinc-silver alloys, etc. can be used. Metal oxides such as indium tin oxide (ITO) can also be used. One of these electrode materials can be used alone, or two or more of these electrode materials can be used in combination. The cathode can have a single-layer structure or a multilayer structure. Among them, silver is preferably used. In order to suppress the agglomeration of silver, a silver alloy is more preferably used. The ratio of the alloy is not limited as long as the agglomeration of silver can be suppressed. For example, the ratio between silver and the other metals can be 1:1, 3:1, etc.

[0073] The cathode may be a top-emitting element using an oxide conductive layer made of ITO or the like, or may be a bottom-emitting element using a reflective electrode made of aluminum (Al) or the like, and is not particularly limited. The method for forming the cathode is not particularly limited, but DC sputtering or AC sputtering is preferably used because good film coverage is provided and resistance is easily reduced.

[0074] [Pixel Isolation Layer]

[0075] The pixel isolation layer is formed of a silicon nitride (SiN) film, a silicon oxynitride (SiON) film, or a silicon oxide (SiO) film formed using a chemical vapor deposition method (CVD method). In order to increase the in-plane resistance of the organic compound layer, the organic compound layer, especially the hole transport layer, is preferably deposited thinly on the sidewalls of the pixel isolation layer. More specifically, by increasing the taper angle of the sidewalls of the pixel isolation layer or the film thickness of the pixel isolation layer to increase the vignetting effect during vapor deposition, the organic compound layer can be deposited to have a thin film thickness on the sidewalls.

[0076] On the other hand, the taper angle of the sidewalls of the pixel isolation layer or the film thickness of the pixel isolation layer is preferably adjusted to a level that does not create spaces in the protective layer formed on the pixel isolation layer. Since no spaces are formed in the protective layer, the generation of defects in the protective layer can be reduced. This reduction in the generation of defects in the protective layer can also reduce reliability degradation caused by the generation of dark spots or poor conductivity of the second electrode.

[0077] According to the present embodiment, even if the taper angle of the side wall of the pixel isolation layer is not sharp, the leakage of charge to the adjacent pixels can be effectively suppressed. As a result of this consideration, it has been found that a taper angle of 60° (including the end value) to 90° (including the end value) can sufficiently reduce the occurrence of defects. The film thickness of the pixel isolation layer is expected to be 10nm (including the end value) to 150nm (including the end value). A similar effect can be obtained in a configuration that includes only pixel electrodes but no pixel isolation layer. However, in this case, the film thickness of the pixel electrode is preferably set to be equal to or less than half the film thickness of the organic layer, or the end of the pixel electrode is preferably formed to have a forward tapered shape of less than 60°, because the short circuit of the organic light emitting element can be reduced.

[0078] [Organic compound layer]

[0079] The organic compound layer may be formed of a single layer or multiple layers. If the organic compound layer includes multiple layers, these layers may be referred to as a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer according to the functions of these layers. The organic compound layer is mainly formed of an organic compound, but may contain inorganic atoms and inorganic compounds. For example, the organic compound layer may contain copper, lithium, magnesium, aluminum, iridium, platinum, molybdenum, zinc, etc. The organic compound layer may be arranged between the first electrode and the second electrode, and may be arranged to contact the first electrode and the second electrode.

[0080] If multiple light-emitting layers are provided, the charge generation unit can be arranged between the first and second light-emitting layers. The charge generation unit can include an organic compound having a lowest unoccupied molecular orbital energy (LUMO) of -5.0 eV or less. This also applies to the case where the charge generation unit is arranged between the second and third light-emitting layers.

[0081] [Protective layer]

[0082] A protective layer can be provided on the second electrode. For example, by attaching glass provided with a desiccant to the second electrode, water and the like can be suppressed from penetrating into the organic compound layer, and the occurrence of display defects can be suppressed. In addition, as another embodiment, a passivation film made of silicon nitride and the like can be provided on the cathode to suppress water and the like from penetrating into the organic compound layer. For example, a protective layer can be formed by forming a cathode, transferring the cathode to another chamber without breaking the vacuum, and forming a silicon nitride film with a thickness of 2 μm by a CVD method. After deposition using the CVD method, an atomic deposition method (ALD method) can be used to provide a protective layer. The material of the film formed by the ALD method is not limited, but can be silicon nitride, silicon oxide, aluminum oxide, etc. The silicon nitride film can be further formed on the film formed by the ALD method by a CVD method. The film formed by the ALD method can have a film thickness that is smaller than the film thickness of the film formed by the CVD method. More specifically, the film thickness of the film formed by the ALD method can be 50% or less, or 10% or less.

[0083] [Color Filter]

[0084] A color filter may be provided on the protective layer. For example, a color filter adapted to the size of the organic light-emitting element may be provided on another substrate, and this substrate may be bonded to the substrate on which the organic light-emitting element is provided. Alternatively, the color filter may be patterned on the protective layer using photolithography techniques. The color filter may be formed from a polymer material.

[0085] [Planarization layer]

[0086] A planarization layer may be provided between the color filter and the protective layer. The planarization layer is provided to reduce the unevenness of the underlying layer. The planarization layer may be referred to as a resin layer, without limiting its purpose. The planarization layer may be formed from an organic compound and may be made from either a low-molecular-weight material or a polymer material. However, polymer materials are more preferred.

[0087] A planarization layer may be provided above and below the color filter, and the same or different materials may be used therefor. More specifically, examples of the material include polyvinyl carbazole resin, polycarbonate resin, polyester resin, ABS resin, acrylic resin, polyimide resin, phenolic resin, epoxy resin, silicone resin, and urea-formaldehyde resin.

[0088] [Microlens]

[0089] The organic light-emitting device may include an optical component such as a microlens on the light-emitting side. The microlens may be made of acrylic resin, epoxy resin, etc. The microlens may be intended to increase the amount of light extracted from the organic light-emitting device and control the direction of the light to be extracted. The microlens may have a hemispherical shape. If the microlens has a hemispherical shape, then among the tangents that contact the hemisphere, there is a tangent that is parallel to the insulating layer, and the contact point between the tangent and the hemisphere is the vertex of the microlens. Even in an arbitrary cross-sectional view, the vertex of the microlens can be determined in the same way. That is, among the tangents of the semicircle that contacts the microlens in the cross-sectional view, there is a tangent that is parallel to the insulating layer, and the contact point between the tangent and the semicircle is the vertex of the microlens.

[0090] The midpoint of the microlens can also be defined. In a cross-section of a microlens, a line segment is defined from one end of an arc to another end of another arc, and the midpoint of this line segment can be referred to as the midpoint of the microlens. The cross-section used to determine the vertex and midpoint can be a cross-section perpendicular to the insulating layer.

[0091] The microlens includes a first surface including a protrusion and a second surface opposite the first surface. The second surface is preferably arranged on the functional layer side of the first surface. For this configuration, the microlens needs to be formed on a light-emitting device. If the functional layer is an organic layer, it is preferable to avoid high-temperature processing during the manufacturing steps. Furthermore, if the second surface is arranged on the functional layer side of the first surface, the glass transition temperature of all organic compounds forming the organic layer is preferably 100°C or higher, more preferably 130°C or higher.

[0092] [Counter substrate]

[0093] A counter substrate may be provided on the planarization layer. The counter substrate is so-called because it is provided at a position corresponding to the aforementioned substrate. The counter substrate may be made of the same material as the aforementioned substrate. If the aforementioned substrate is the first substrate, the counter substrate may be the second substrate.

[0094] [Organic layer]

[0095] The organic compound layers (hole injection layer, hole transport layer, electron blocking layer, light emitting layer, hole blocking layer, electron transport layer, electron injection layer, etc.) forming the organic light emitting element according to the first embodiment of the present invention are formed by the following method.

[0096] The organic compound layer forming the organic light-emitting element according to an embodiment of the present invention can be formed by a dry method using a vacuum deposition method, an ionization deposition method, a sputtering method, a plasma method, etc. Instead of the dry method, a wet method can be used, which forms a layer by dissolving a solute in an appropriate solvent and using a well-known coating method (for example, a spin coating method, a dipping method, a casting method, an LB method, an inkjet method, etc.).

[0097] Here, when the layer is formed by vacuum deposition, solution coating, etc., crystallization etc. hardly occurs, and excellent temporal stability is obtained. In addition, when the layer is formed using a coating method, a film can be formed in combination with a suitable binder resin.

[0098] Examples of the binder resin include polyvinyl carbazole resin, polycarbonate resin, polyester resin, ABS resin, acrylic resin, polyimide resin, phenol resin, epoxy resin, silicone resin, and urea resin. However, the binder resin is not limited thereto.

[0099] One of these binder resins can be used as homopolymer or copolymer separately, and perhaps two or more than two in these binder resins can be used in combination.In addition, also can use the additive such as well-known plasticizer, antioxidant and ultraviolet light absorber etc. as required.

[0100] [Pixel circuit]

[0101] The light-emitting device may include a pixel circuit connected to a light-emitting element. The pixel circuit may be an active matrix circuit that independently controls the light emission of a first light-emitting element and a second light-emitting element. The active matrix circuit may be a voltage- or current-programmable circuit. The driver circuit includes a pixel circuit for each pixel. The pixel circuit may include a light-emitting element, a transistor for controlling the brightness of the light-emitting element, a transistor for controlling the timing of light emission, a capacitor for maintaining the gate voltage of the transistor for controlling the brightness of the light-emitting element, and a transistor for connecting to ground without the intervention of the light-emitting element.

[0102] A light-emitting device includes a display area and a peripheral area arranged around the display area. The light-emitting device includes a pixel circuit in the display area and a display control circuit in the peripheral area. The mobility of transistors forming the pixel circuit may be smaller than the mobility of transistors forming the display control circuit.

[0103] The slope of the current-voltage characteristic of the transistor forming the pixel circuit may be smaller than the slope of the current-voltage characteristic of the transistor forming the display control circuit. The slope of the current-voltage characteristic can be measured by the so-called Vg-Ig characteristic.

[0104] The transistor forming the pixel circuit is a transistor connected to a light-emitting element such as the first light-emitting element.

[0105] [Pixels]

[0106] An organic light-emitting device includes a plurality of pixels. Each pixel includes sub-pixels that emit light components of different colors. The sub-pixels each include, for example, R, G, and B emission colors.

[0107] In each pixel, an area also referred to as a pixel opening emits light. This area is the same as the first area. The pixel opening can have a size of 5 μm (inclusive) to 15 μm (inclusive). More specifically, the pixel opening can have a size of 11 μm, 9.5 μm, 7.4 μm, 6.4 μm, etc.

[0108] The distance between sub-pixels may be 10 μm or less, and more specifically, may be 8 μm, 7.4 μm, or 6.4 μm.

[0109] In a plan view, the pixels may have a known arrangement. For example, the pixels may have a stripe arrangement, a triangular arrangement, a pentagonal arrangement, or a Bayer arrangement. The shape of each sub-pixel in a plan view may be any known shape. For example, a quadrilateral such as a rectangle or a rhombus, or a hexagon, etc. are feasible. Here, these shapes do not have to be exact shapes, and shapes close to a rectangle are also included in a rectangle. The shape of the sub-pixel and the pixel arrangement may be used in combination.

[0110] [Application of the Organic Light-Emitting Element of the Embodiments of the Present Invention]

[0111] The organic light-emitting element according to the embodiment of the present invention can be used as a component of a display device or a lighting device. In addition, the organic light-emitting element can be applied to the exposure light source of an electrophotographic image forming device, the backlight of a liquid crystal display device, a light-emitting device including a color filter in a white light source, etc.

[0112] The display device may be an image information processing device including an image input unit for inputting image information from an area CCD, a line CCD, a memory card, etc. and an information processing unit for processing the input information, and displays the input image on the display unit.

[0113] Furthermore, the display unit included in the imaging device or inkjet printer may have a touch panel function. The driving type of the touch panel function may be infrared, capacitive, resistive film, or electromagnetic induction, and there are no particular limitations. The display device may be used in a display unit of a multifunction printer.

[0114] A display device according to the present embodiment will be described with reference to the accompanying drawings.

[0115] Figure 6A and Figure 6B1 is a schematic cross-sectional view showing an example of a display device including an organic light-emitting element and a transistor connected to the organic light-emitting element. The transistor is an example of an active element. The transistor may be a thin film transistor (TFT).

[0116] Figure 6A An example of a pixel as a component of a display device according to the present embodiment is shown. The pixel includes a sub-pixel 810 (pixel PIX). The light components emitted by the sub-pixels are divided into sub-pixels 810R, 810G, and 810B. The luminous color can be distinguished by the wavelength of the light component emitted from the light-emitting layer, or the light emitted from each sub-pixel can be selectively transmitted or undergo color conversion through a color filter or the like. Each sub-pixel includes a reflective electrode 802 as a first electrode on an interlayer insulating layer 801, an insulating layer 803 covering the end of the reflective electrode 802, an organic compound layer 804 covering the first electrode and the insulating layer, a transparent electrode 805 as a second electrode, a protective layer 806, and a color filter 807.

[0117] The interlayer insulating layer 801 may include a transistor and a capacitor arranged in a layer in or below the interlayer insulating layer 801. The transistor and the first electrode may be electrically connected via a contact hole (not shown) or the like.

[0118] The insulating layer 803 is also called a bank or a pixel isolation film. The insulating layer 803 covers the end of the first electrode and is arranged to surround the first electrode. The portion where the insulating layer is not arranged is in contact with the organic compound layer 804 to form a light-emitting region.

[0119] The organic compound layer 804 includes a hole injection layer 841 , a hole transport layer 842 , a first light-emitting layer 843 , a second light-emitting layer 844 , and an electron transport layer 845 .

[0120] The second electrode 805 may be a transparent electrode, a reflective electrode, or a semi-transmissive electrode.

[0121] The protective layer 806 inhibits water from penetrating into the organic compound layer. The protective layer is shown as a single layer, but may include multiple layers. Each layer may be an inorganic compound layer or an organic compound layer.

[0122] The color filter 807 is divided into color filters 807R, 807G and 807B by color. The color filter can be formed on a planarization film (not shown). A resin protective layer (not shown) can be arranged on the color filter. The color filter can be formed on the protective layer 806. Alternatively, the color filter can be provided on an opposing substrate such as a glass substrate, and then the substrates can be bonded.

[0123] Figure 6BThe display device 800 shown (corresponding to the light-emitting device 10 according to the above-described embodiment) is provided with an organic light-emitting element 826 and a TFT 818, which is an example of a transistor. A substrate 811 made of glass, silicon, or the like is provided, and an insulating layer 812 is provided on the substrate 811. An active element 818, such as a TFT, is arranged on the insulating layer, and a gate electrode 813, a gate insulating film 814, and a semiconductor layer 815 of the active element are provided. The TFT 818 also includes the semiconductor layer 815, a drain electrode 816, and a source electrode 817. An insulating film 819 is provided on the TFT 818. The source electrode 817 and an anode 821 forming the organic light-emitting element 826 are connected via a contact hole 820 formed in the insulating film.

[0124] Note that the method of electrically connecting the electrodes (anode and cathode) included in the organic light-emitting element 826 and the electrodes (source electrode and drain electrode) included in the TFT is not limited to Figure 6B That is, one of the anode and cathode and one of the source and drain electrodes of the TFT are electrically connected. TFT stands for thin film transistor.

[0125] exist Figure 6B In the display device 800 shown, the organic compound layer is shown as a single layer. However, the organic compound layer 822 may include multiple layers. A first protective layer 824 and a second protective layer 825 are provided on the cathode 823 to suppress degradation of the organic light emitting element.

[0126] Transistors are used as Figure 6B The display device 800 is shown with a switching element, but other switching elements may be used instead.

[0127] Figure 6B The transistors used in the display device 800 shown are not limited to those using a single-crystal silicon wafer and may be thin-film transistors including an active layer on an insulating surface of a substrate. Examples of active layers include single-crystal silicon, amorphous silicon, non-single-crystal silicon such as microcrystalline silicon, and non-single-crystal oxide semiconductors such as indium zinc oxide and indium gallium zinc oxide. Note that thin-film transistors are also referred to as TFT elements.

[0128] Figure 6B The transistor included in the display device 800 shown may be formed in a substrate such as a Si substrate. Forming a transistor in a substrate means forming the transistor by processing a substrate such as a Si substrate. That is, when the transistor is included in the substrate, it can be considered that the substrate and the transistor are formed integrally.

[0129] The luminous brightness of the organic light-emitting element according to this embodiment can be controlled by a TFT as an example of a switching element, and a plurality of organic light-emitting elements can be arranged in a plane to display an image using the luminous brightness of each element. Note that the switching element according to this embodiment is not limited to a TFT, and may be a transistor formed of low-temperature polysilicon or an active matrix driver formed on a substrate such as a Si substrate. The term "on a substrate" may mean "in a substrate." Whether to set a transistor in the substrate or to use a TFT is selected based on the size of the display unit. For example, if the size is about 0.5 inches, the organic light-emitting element is preferably arranged on a Si substrate.

[0130] Figure 7 1000 is a schematic diagram illustrating an example of a display device according to this embodiment. Display device 1000 may include a touch panel 1003, a display panel 1005, a frame 1006, a circuit board 1007, and a battery 1008 between an upper cover 1001 and a lower cover 1009. Flexible printed circuits (FPCs) 1002 and 1004 are connected to touch panel 1003 and display panel 1005, respectively. Transistors are printed on circuit board 1007. If the display device is not portable equipment, battery 1008 is unnecessary. Even when the display device is portable equipment, battery 1008 may be provided elsewhere.

[0131] The display device according to the present embodiment may include red, green, and blue color filters, which may be arranged in a triangular array.

[0132] The display device according to this embodiment can be used as a display unit of a portable terminal. In this case, the display unit can have both a display function and an operation function. Examples of portable terminals are portable phones such as smartphones, tablet computers, and head-mounted displays.

[0133] The display device according to this embodiment can be used as a display unit of an imaging device, which includes an optical unit having multiple lenses and an image sensor for receiving light that has passed through the optical unit. The imaging device can also include a display unit for displaying information acquired by the image sensor. The display unit can be a display unit exposed to the outside of the imaging device or a display unit arranged in a viewfinder. The imaging device can be a digital still camera or a digital video camera.

[0134] Figure 811 is a schematic diagram illustrating an example of an imaging device according to this embodiment. Imaging device 1100 may include a viewfinder 1101, a rear display 1102, an operating unit 1103, and a housing 1104. Viewfinder 1101 may include a display device according to this embodiment. In this case, the display device may not only display the image to be captured, but also display environmental information, imaging instructions, and the like. Examples of environmental information include the intensity and direction of external light, the speed of movement of the subject, and the likelihood that the subject is obscured by an obstacle.

[0135] The time required for image capture is very short, so information should be displayed as quickly as possible. Therefore, it is preferable to use a display device using an organic light-emitting element according to the present invention. This is because organic light-emitting elements have a high response speed. Compared to liquid crystal display devices, display devices using organic light-emitting elements can be more preferably used in devices that require high display speeds.

[0136] The imaging device 1100 includes an optical unit (not shown). The optical unit has a plurality of lenses and forms an image on an imaging element housed in a housing 1104. The focus of the plurality of lenses can be adjusted by adjusting their relative positions. This operation can also be performed automatically. The imaging device can be referred to as a photoelectric conversion device. As an imaging method, the photoelectric conversion device may include a method of detecting a difference from a previous image and a method of extracting an image from an image that is always recorded, rather than a method of sequentially capturing images.

[0137] Figure 9 1 is a schematic diagram showing an example of electronic equipment according to the present embodiment. Electronic equipment 1200 includes a display unit 1201, an operating unit 1202, and a housing 1203. The housing 1203 can accommodate a circuit, a printed circuit having the circuit, a battery, and a communication unit. The operating unit 1202 can be a button or a touch panel type reaction unit. The operating unit can also be a biometric authentication unit for unlocking, etc. by authenticating a fingerprint. Electronic equipment including a communication unit can also be regarded as communication equipment. By including a lens and an image sensor, the electronic equipment can also have a camera function. The image captured by the camera function is displayed on the display unit. Examples of electronic equipment are smartphones and laptop computers.

[0138] Figure 10A and Figure 10B is a schematic diagram illustrating an example of the display device according to the present embodiment. Figure 10A 13. A display device such as a television monitor or a PC monitor is shown. The display device 1300 includes a frame 1301 and a display unit 1302. The light emitting device according to the present embodiment can be used for the display unit 1302.

[0139] The display device 1300 includes a support frame 1301 and a base 1303 of a display unit 1302. The base 1303 is not limited to Figure 10A The lower side of the frame 1301 can also be used as a base.

[0140] In addition, the frame 1301 and the display unit 1302 may be curved, and the curvature radius in this case may be 5000 mm (inclusive) to 6000 mm (inclusive).

[0141] Figure 10B is a schematic diagram showing another example of the display device according to the present embodiment. Figure 10B The display device 1310 shown is foldable and is a so-called foldable display device. The display device 1310 includes a first display unit 1311, a second display unit 1312, a housing 1313, and a bending point 1314. The first display unit 1311 and the second display unit 1312 can each include a light-emitting device according to this embodiment. The first display unit 1311 and the second display unit 1312 can also be a seamless display device. The first display unit 1311 and the second display unit 1312 can be divided by a bending point. The first display unit 1311 and the second display unit 1312 can display different images, and the first display unit and the second display unit can also display a single image together.

[0142] Will refer to Figure 11A and Figure 11B Application examples of the display device according to each of the above embodiments will be described. The display device can be applied to a system that can be worn as a wearable device such as smart glasses, head-mounted displays (HMDs), or smart contact lenses. The imaging display device used in this application example includes an imaging device capable of photoelectrically converting visible light and a display device capable of emitting visible light.

[0143] Will refer to Figure 11A Glasses 1600 (smart glasses) according to one application example are described. An imaging device 1602 such as a CMOS sensor or SPAD is provided on the front surface side of a lens 1601 of the glasses 1600. In addition, the display device according to each of the above embodiments is provided on the back surface side of the lens 1601.

[0144] The glasses 1600 also include a control device 1603. The control device 1603 serves as a power source for supplying power to the imaging device 1602 and the display device according to various embodiments. Furthermore, the control device 1603 controls the operation of the imaging device 1602 and the display device. An optical system configured to converge light toward the imaging device 1602 is formed on the lens 1601.

[0145] Will refer to Figure 11BGlasses 1610 (smart glasses) according to an example application are described. Glasses 1610 include a control device 1612. A camera and a display device corresponding to camera 1602 are mounted on control device 1612. An optical system configured to project light emitted from the display device in control device 1612 is formed in lens 1611, and an image is projected onto lens 1611. Control device 1612 serves as a power supply to supply power to the camera and display devices and controls their operation. The control device may include a line of sight detection unit that detects the wearer's line of sight. Line of sight detection may be accomplished using infrared light. An infrared emitting unit emits infrared light toward the eye of a user who is looking at a displayed image. The camera unit, which includes a light receiving element, detects light reflected from the eye by the emitted infrared light, thereby obtaining a captured image of the eye. A reduction unit is provided for reducing light from the infrared emitting unit to the display unit in a plan view, thereby reducing degradation in image quality.

[0146] The user's gaze toward the displayed image is detected from an image of the eye obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eye. For example, a gaze detection method based on a Purkinje image obtained by reflecting irradiated light off the cornea can be used.

[0147] More specifically, gaze detection processing based on pupil center corneal reflection is performed. Using pupil center corneal reflection, a gaze vector representing the direction (rotation angle) of the eyeball is calculated based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0148] The display device according to the embodiment of the present invention may include an imaging device having a light receiving element, and control an image displayed on the display device based on visual line information of a user from the imaging device.

[0149] More specifically, the display device determines a first display area that the user is looking at and a second display area other than the first display area based on the line of sight information. The first display area and the second display area may be determined by a control device of the display device, or may receive those areas determined by an external control device. Within the display areas of the display device, the display resolution of the first display area may be controlled to be higher than the display resolution of the second display area. In other words, the resolution of the second display area may be lower than the resolution of the first display area.

[0150] In addition, the display area includes a first display area and a second display area different from the first display area, and a higher priority area is determined from the first display area and the second display area based on the line of sight information. The first display area and the second display area can be determined by the control device of the display device, or can receive those areas determined by an external control device. The resolution of the higher priority area can be controlled to be higher than the resolution of areas other than the higher priority area. In other words, the resolution of the relatively low priority area can be lower.

[0151] Note that AI can be used to determine the first display area or a higher priority area. The AI ​​can be a model configured to use an image of the eyeball and the actual viewing direction of the eyeball in the image as supervision data to estimate the angle of sight and the distance to the target in front of the sight from the image of the eyeball. The AI ​​program can be maintained by the display device, the camera device, or an external device. If the external device maintains the AI ​​program, it is transmitted to the display device via communication.

[0152] When display control is performed based on line of sight detection, it can be appropriately applied to smart glasses that further include a camera configured to capture external images. The smart glasses can display the captured external information in real time.

[0153] As described above, when the device using the organic light emitting element according to this embodiment is used, high-quality stable display can be performed even during long-term display.

[0154] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A light emitting device comprising a plurality of pixels arranged in a substrate, wherein: Each of the plurality of pixels includes a first isolation portion configured in a trench type to isolate two adjacent regions having different conductivity types from each other, and a second isolation portion configured in a trench type to isolate two adjacent regions having the same conductivity type from each other, and The second isolation portion has a depth greater than that of the first isolation portion.

2. The light emitting device according to claim 1, wherein The depth of the second isolation portion is greater than the depth of the first isolation portion by not less than 0.3 μm.

3. The light emitting device according to claim 1, wherein In a direction parallel to the surface of the substrate, an opening width of the first isolation portion is narrower than an opening width of the second isolation portion.

4. The light emitting device according to claim 1, wherein A height from the surface of the substrate is different between the first isolation portion and the second isolation portion.

5. The light emitting device according to claim 1, wherein The second isolation portion includes an upper portion and a lower portion stacked on each other, and The lower layer portion is connected to a portion of a bottom surface of the upper layer portion. The light emitting device according to claim 5 , wherein: The depth of the lower portion is greater than the depth of the upper portion.

7. The light emitting device according to claim 5, wherein The maximum width of the lower portion is smaller than the width of the bottom surface of the upper portion.

8. The light emitting device according to claim 1, wherein The plurality of pixels each include a first semiconductor region, a second semiconductor region having the same conductivity type as that of the first semiconductor region, and a third semiconductor region having a different conductivity type from that of the first semiconductor region, and The first isolation portion is provided between the first semiconductor region and the third semiconductor region disposed adjacent to each other, and the second isolation portion is provided between the first semiconductor region and the second semiconductor region disposed adjacent to each other.

9. The light emitting device according to claim 8, wherein Each of the plurality of pixels includes a light emitting element and a pixel circuit configured to drive the light emitting element, and The pixel circuit includes a selection transistor configured to control input of data to a pixel and a drive transistor configured to drive the light emitting element according to the input data.

10. The light emitting device according to claim 9, wherein The second isolation portion is provided between two driving transistors arranged adjacent to each other.

11. The light emitting device according to claim 9, wherein The pixel circuit further includes a switching transistor configured to control light emission of the light emitting element and a reset transistor configured to reset the light emitting element.

12. The light emitting device according to claim 11, wherein The second isolation portion is provided between two reset transistors arranged adjacent to each other.

13. The light emitting device according to claim 11, wherein The second isolation portion is provided between the reset transistor and a switch transistor adjacent to the reset transistor.

14. The light emitting device according to claim 11, wherein The second isolation portion is provided between the switch transistor and a selection transistor adjacent to the switch transistor.

15. The light emitting device according to claim 11, wherein The first isolation portion is provided between a well contact of a pixel and a reset transistor adjacent to the well contact.

16. The light emitting device according to claim 9, wherein The first isolation portion is provided between a well contact of a pixel and a selection transistor adjacent to the well contact.

17. The light emitting device according to claim 9, wherein The first isolation portion is provided between a well contact of a pixel and a driving transistor adjacent to the well contact.

18. A wearable device comprising a display device configured to display an image, in, The display device comprises a light emitting device as defined in any one of claims 1 to 17.

19. A display device comprising a light emitting device as defined in any one of claims 1 to 17 and an active element connected to the light emitting device.

20. A photoelectric conversion device comprising: an optical unit comprising a plurality of lenses; an image sensor configured to receive light that has passed through the optical unit; and a display unit configured to display an image, The display unit displays the image captured by the image sensor and includes the light emitting device defined in any one of claims 1 to 17.

21. An electronic device comprising a housing provided with a display unit and a communication unit provided in the housing and configured to perform external communication, in, The display unit comprises a light emitting device as defined in any one of claims 1 to 17.

Images