Display panel, preparation method of display panel and display device

Abstract

The invention discloses a display panel, a preparation method of the display panel and a display device.The display panel comprises a display area and further comprises a substrate; the at least one first conductive layer is positioned on one side of the substrate; the insulating layer is located on one side of the first conductive layer away from the substrate; the insulating layer comprises at least one via hole, the at least one via hole is formed in the display area, and the side wall angle of the at least one via hole is larger than or equal to 45 degrees; the second conducting layer is located on the side, away from the substrate, of the insulating layer, and the second conducting layer is connected with the at least one first conducting layer through at least one via hole. According to the display panel, the preparation method of the display panel and the display device, the film thickness difference of the second conducting layer at the side wall climbing position is reduced, and the display effect is improved. The flatness of the side layer structure, away from the substrate, of the second conductive layer is improved, and therefore the color cast problem generated by a follow-up structure is solved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel, a method for manufacturing a display panel, and a display device. Background Art

[0002] With the development of display technology, organic light emitting diode (OLED) display panels have been widely used due to their advantages such as self-luminescence, low power consumption and fast response speed.

[0003] The display area of ​​an OLED display panel often has an uneven insulating layer structure, which results in poor display. Summary of the Invention

[0004] The present invention provides a display panel, a method for manufacturing a display panel, and a display device, which reduce the thickness difference of the second conductive layer at the sidewall climbing part, improve the flatness of the layer structure of the second conductive layer away from the substrate, and thus improve the color deviation problem caused by subsequent structures.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, the display panel including a display area, and the display panel further including:

[0006] substrate,

[0007] At least one first conductive layer is located on one side of the substrate,

[0008] an insulating layer, located on a side of the first conductive layer away from the substrate, the insulating layer comprising via holes, the via holes being arranged in the display area, and at least one of the via holes having a sidewall angle greater than or equal to 45°;

[0009] The second conductive layer is located on a side of the insulating layer away from the substrate, and the second conductive layer is connected to at least one layer of the first conductive layer through at least one via hole.

[0010] Optionally, the display panel includes a non-display area; a sidewall angle of at least one of the via holes is greater than or equal to a sidewall angle of the insulating layer in the non-display area;

[0011] Optionally, a sidewall angle of at least one of the via holes is greater than or equal to 60°;

[0012] Optionally, a sidewall angle of any of the via holes is greater than or equal to 60°;

[0013] Optionally, the opening size of the via hole on a side away from the substrate is 2.5 μm-8 μm.

[0014] Optionally, a sidewall angle of any of the via holes is greater than a sidewall angle of the insulating layer in the non-display area.

[0015] Optionally, the insulating layer includes a planar layer, and the second conductive layer includes an anode layer;

[0016] The flat layer is located on a side of the first conductive layer away from the substrate, and the anode layer is located on a side of the flat layer away from the substrate; the via includes a first via, and the anode layer is connected to at least one layer of the first conductive layer through the first via;

[0017] Optionally, the display panel further comprises a pixel definition layer located on a side of the anode layer away from the substrate, and in the display area, the pixel definition layer comprises a pixel opening;

[0018] The orthographic projection of the side wall of the first via hole on the substrate does not overlap with the orthographic projection of the surface of the pixel opening close to the substrate on the substrate.

[0019] Optionally, the insulating layer includes an intermediate dielectric layer, and the second conductive layer includes an intermediate conductive layer;

[0020] The intermediate dielectric layer is located on the side of the first conductive layer away from the substrate, and the intermediate conductive layer is located on the side of the intermediate dielectric layer away from the substrate; the via includes a second via, and the intermediate conductive layer is connected to the at least one first conductive layer through at least one second via.

[0021] In a second aspect, an embodiment of the present invention provides a method for manufacturing a display panel, wherein the display panel includes a display area, and the manufacturing method includes:

[0022] providing a substrate;

[0023] forming at least one first conductive layer on one side of the substrate;

[0024] forming an insulating layer on a side of the first conductive layer away from the substrate, wherein the insulating layer includes at least one via hole, the via hole is disposed in the display area, and a sidewall angle of at least one of the via holes is greater than or equal to 45°;

[0025] A second conductive layer is formed on a side of the insulating layer away from the substrate, and the second conductive layer is connected to the at least one first conductive layer through at least one via hole.

[0026] Optionally, the display panel includes a non-display area; an insulating layer is formed on a side of the first conductive layer away from the substrate, the insulating layer further includes a sidewall in the non-display area, and an angle of the sidewall of at least one of the via holes is greater than or equal to an angle of the sidewall of the insulating layer in the non-display area;

[0027] Optionally, a sidewall angle of at least one of the via holes is greater than or equal to 60°;

[0028] Optionally, a sidewall angle of any of the via holes is greater than or equal to 60°;

[0029] Optionally, a sidewall angle of any of the via holes is greater than a sidewall angle of the insulating layer in the non-display area.

[0030] Optionally, an insulating layer is formed on a side of the first conductive layer away from the substrate, the insulating layer further comprises sidewalls in the non-display area, and the sidewall angle of at least one of the via holes is greater than the sidewall angle of the insulating layer in the non-display area, including:

[0031] coating an insulating material on a side of the first conductive layer away from the substrate to form the insulating layer;

[0032] In the non-display area, forming a sidewall of the insulating layer by a grayscale mask process;

[0033] In the display area, forming the via hole by dry etching process;

[0034] Optionally, after forming the sidewall of the insulating layer, the method further comprises:

[0035] baking and curing the insulating layer;

[0036] Alternatively, an insulating layer is formed on a side of the first conductive layer away from the substrate, the insulating layer further comprises a sidewall in the non-display area, and the sidewall angle of at least one of the via holes is equal to the sidewall angle of the insulating layer in the non-display area, including:

[0037] coating an insulating material on a side of the first conductive layer away from the substrate to form the insulating layer;

[0038] Simultaneously forming the via hole in the display area and the sidewall of the insulating layer in the non-display area by a dry etching process;

[0039] Optionally, after forming the sidewall of the insulating layer, the method further comprises:

[0040] baking and curing the insulating layer;

[0041] Optionally, before forming the via hole in the display area by a dry etching process, the method further includes:

[0042] A groove of a preset depth is formed at a position corresponding to the via hole of the insulating layer.

[0043] Optionally, the insulating layer includes a planar layer, and the second conductive layer includes an anode layer;

[0044] forming the flat layer on a side of the first conductive layer away from the substrate;

[0045] The anode layer is formed on a side of the flat layer away from the substrate; wherein the via hole includes a first via hole, and the anode layer is connected to at least one layer of the first conductive layer through the first via hole;

[0046] Optionally, a pixel definition layer is formed on a side of the anode layer away from the substrate, and in the display area, the pixel definition layer includes a pixel opening;

[0047] The orthographic projection of the side wall of the first via hole on the substrate does not overlap with the orthographic projection of the surface of the pixel opening close to the substrate on the substrate.

[0048] Optionally, the insulating layer includes an intermediate dielectric layer, and the second conductive layer includes an intermediate conductive layer;

[0049] forming the intermediate dielectric layer on a side of the first conductive layer away from the substrate;

[0050] The intermediate conductive layer is formed on a side of the intermediate dielectric layer away from the substrate; the via hole includes a second via hole, and the intermediate conductive layer is connected to at least one layer of the first conductive layer through the second via hole.

[0051] In a third aspect, an embodiment of the present invention provides a display device, comprising the display panel described in any embodiment of the present invention.

[0052] According to the technical solution provided by an embodiment of the present invention, in the display area, the insulating layer is provided with at least one via hole, and at least one first conductive layer and the second conductive layer on both sides of the insulating layer are electrically connected through at least one via hole, wherein the sidewall angle of at least one via hole is greater than or equal to 45°. The steeper sidewall of the via hole can make it easier to achieve uniform deposition of the second conductive layer during the preparation process, reduce the film thickness difference of the second conductive layer at the side wall climbing, and improve the flatness of the layer structure of the second conductive layer away from the substrate, thereby improving the problem of color deviation generated in subsequent structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a structural diagram of a display panel in the related art;

[0054] Figure 2 A schematic structural diagram of a display panel is provided for an embodiment of the present invention;

[0055] Figure 3 A structural diagram of another display panel is provided for an embodiment of the present invention;

[0056] Figure 4 A schematic diagram of the structure of another related art display panel;

[0057] Figure 5 A schematic diagram of a partial structure of another display panel is provided for an embodiment of the present invention;

[0058] Figure 6 A schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present invention;

[0059] Figure 7 A schematic diagram of the structure of an insulating layer after surface pretreatment provided by an embodiment of the present invention;

[0060] Figure 8 A schematic flow chart of another method for manufacturing a display panel provided in an embodiment of the present invention;

[0061] Figure 9 A schematic flow chart of another method for manufacturing a display panel provided in an embodiment of the present invention;

[0062] Figure 10 A structural schematic diagram of a display device is provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0064] In the display panel structure of related art, the insulating layer of the display area is usually provided with at least one via hole, and the conductive layers on both sides of the insulating layer are electrically connected by the via hole. The morphology of the conductive layer on one side of the via hole is affected by the morphology of the via hole. For example, Figure 1 This is a schematic diagram of the structure of the display panel in the related art, see Figure 1 In a pixel unit, the anode layer 120 and the conductive layer 130 on both sides of the planar layer 110 can be electrically connected through the via holes in the planar layer 110. However, the thickness of the anode layer 120 is usually low at the slope 150 of the via hole, which will also affect the flatness within the pixel opening 140 on one side of the anode layer 120, thereby causing color shift problems at different viewing angles. As the number of pixels per inch (PPI) increases, color shift increasingly affects display quality.

[0065] In view of this, Figure 2 A schematic diagram of the structure of a display panel is provided in accordance with an embodiment of the present invention. Figure 2, the display panel includes a display area 210, and the display panel further includes: a substrate 230;

[0066] A first conductive layer 240 is located on one side of the substrate 230;

[0067] The insulating layer 250 is located on a side of the first conductive layer 240 away from the substrate 230 . The insulating layer 250 includes at least one via hole 260 . The at least one via hole 260 is disposed in the display area 210 . The sidewall angle of the at least one via hole 260 is greater than or equal to 45°.

[0068] The second conductive layer 270 is located on the side of the insulating layer 250 away from the substrate 230 , and the second conductive layer 270 is connected to the at least one first conductive layer 240 through at least one via 260 ;

[0069] In one embodiment, the first conductive layer 240 may have multiple layers, and an insulating layer 250 is disposed on a side of any first conductive layer 240 away from the substrate 230 .

[0070] Specifically, at least one first conductive layer 240 and a second conductive layer 270 are disposed on either side of the insulating layer 250. In the display area 210, the insulating layer 250 is provided with at least one via 260, and the at least one first conductive layer 240 and the second conductive layer 270 are electrically connected through the at least one via 260. The sidewall angle of the at least one via 260 refers to the angle between the via sidewall and the horizontal direction X. In the display area 210, the sidewall angle of the at least one via 260 is greater than or equal to 45°. By increasing the steepness of the via sidewall, the opening size of the via on the side away from the substrate 230 in the horizontal direction X can be reduced while the via diameter is determined. This reduces the difference between the opening size of the via on the side away from the substrate 230 and the width of the via on the side closer to the substrate 230, thereby improving the dimensional accuracy of the via. The larger the sidewall angle of the via, the more conducive it is for the deposited material to grow along the sidewall during the deposition of the second conductive layer 270, thereby reducing deposition dead angles and improving the uniformity of the distribution of the deposited material in the hole, thereby reducing the film thickness difference of the second conductive layer 270 at the sidewall climbing, improving the flatness of the layer structure of the second conductive layer 270 away from the substrate, and improving the subsequent color deviation problem. For example, in order to increase the sidewall angle of at least one via 260 in the display area 210, at least one via 260 in the display area 210 can be prepared by a dry etching process, and the dry etching process is used to achieve a hole of a specific shape and size. For example, after forming the insulating layer 250, the insulating layer 250 is dry-etched in the display area 210. The aperture of the via after dry etching can be more accurately expressed, and the sidewall angle of the via is steeper, so that the via morphology can be better controlled.

[0071] Continue to see Figure 2Optionally, the display panel further includes a non-display area 220; wherein the non-display area 220 is arranged on one side of the display area 210, and the insulating layer 250 has patterns such as hollowing and vias in the non-display area 220, and the boundary of the pattern is the sidewall 221 of the insulating layer 250 in the non-display area 220. When the sidewall angle of at least one via 260 in the display area 210 is greater than the sidewall angle of the insulating layer 250 in the non-display area 220, the sidewall 221 of the insulating layer 250 in the non-display area 220 can be formed first in the process, and then the at least one via 260 is formed on the insulating layer 250 in the display area 210. In other words, the pattern on the insulating layer 250 in the non-display area 220 can be prepared using the original preparation process, such as the gray tone mask process (GTM). As for the vias 260 on the insulating layer 250 in the display area 210, a dry etching process can be used to prepare the vias 260. The etching accuracy of the dry etching process is higher than that of the GTM process. Therefore, compared with the original preparation process, a sidewall angle of the via can be obtained that is greater than the sidewall angle of the insulating layer in the non-display area, thereby better controlling the via morphology in the display area and ensuring that the sidewall angle of the via meets the requirements. For example, the process of preparing the insulating layer 250 can first be to form the insulating layer 250 by coating the insulating material, then perform exposure and development in the non-display area 220 to form the pattern of the non-display area 220, while the display area 210 does not have a corresponding via pattern. After the film layer is baked, a photoresist is applied, and a mask template of the corresponding via pattern is set in the display area 210 through the photoresist. The cured insulating layer 250 film is dry-etched to form at least one via 260 in the display area 210, and then the photoresist is stripped and cleaned. That is, different fabrication processes are used to pattern the insulating layer 250 in the display area 210 and non-display area 220. When fabricating the pattern for the non-display area 220, existing processes can be used, while dry etching can be used for the pattern for the display area 210. The dry etching process can achieve the requirement that the sidewall angle of each via 260 in the display area 210 is greater than or equal to 45°. In an embodiment of the present invention, depending on the precision of the dry etching process, the sidewall angle of at least one or any via can be made greater than or equal to 60°, further increasing the steepness of the via sidewall, thereby reducing the opening size of the via on the side away from the substrate 230 in the horizontal direction X and improving the dimensional accuracy of the via. Furthermore, the larger sidewall angle of the via reduces deposition dead angles and improves the uniformity of the deposited material within the via. Depending on the sidewall angle of the via 260 and the thickness of the insulating layer 250, the opening size of the via 260 on the side away from the substrate can be controlled to be between 2.5μm and 8μm, thereby improving the uniformity of the deposited material within the via. For example, the opening size of the via hole 260 may be 2.5 μm, 3.5 μm, 4.5 μm, 5.5 μm, 6.5 μm, 7.5 μm, or 8 μm.

[0072] In some other optional embodiments, the sidewall angle of the via 260 in the display area 210 may also be equal to the sidewall angle of the insulating layer 250 in the non-display area 220. Therefore, in the process of preparing the insulating layer 250, the sidewall of the insulating layer 250 in the non-display area 220 and at least one via 260 on the insulating layer 250 in the display area 210 may be simultaneously formed using the same process. In order to achieve a better performance of the sidewall angle of the via, it may be prepared by a dry etching process, thereby better controlling the via morphology. Exemplarily, the process of preparing the insulating layer 250 is to form the insulating layer 250 by coating an insulating material, baking the film, and then applying photoresist. By exposure and development, the photoresist forms a mask template of the corresponding via pattern in the display area 210 and the non-display area 220. Then, all patterns are dry-etched, thereby better controlling the morphology of the patterns.

[0073] Optional, Figure 3 A schematic diagram of another display panel structure is provided for an embodiment of the present invention. Figure 3 , the insulating layer 250 includes a planar layer 110 , and the second conductive layer 270 includes an anode layer 120 ;

[0074] The flat layer 110 is located on the side of the first conductive layer 240 away from the substrate 230, and the anode layer 120 is located on the side of the flat layer 110 away from the substrate 230; the via 260 includes a first via 261, and the anode layer 120 is connected to at least one layer of the first conductive layer 240 through the first via 261;

[0075] Specifically, a light-emitting device is disposed on the substrate 230 in the display area 210. The light-emitting device includes an anode layer 120, a light-emitting layer, and a cathode layer, which are sequentially stacked along a side away from the substrate 230. In some embodiments, the at least one first conductive layer 240 may include a first metal layer 241, wherein the first metal layer 241 is electrically connected to the drain D of the transistor device 160 in the pixel circuit array. The insulating layer 250 may include a planar layer 110. The second conductive layer 270 may include the anode layer 120 of the light-emitting device. A first via 261 is disposed in the planar layer 110. The first via 261 may expose the electrical connection area of ​​the first metal layer 241. The anode layer 120 is electrically connected to the first metal layer 241 through the first via 261. Among them, the first via 261 of the flat layer 110 of the insulating material can be prepared by dry etching, so that the side wall angle of the first via 261 is greater than or equal to 45°. Therefore, when the diameter size of the first via 261 is determined, the larger the side wall angle of the first via 261, the steeper the side wall of the first via 261. Therefore, it is easier to achieve uniform deposition in the process of preparing the anode layer 120, reduce the film thickness difference of the anode layer 120 at the side wall climbing of the first via 261, and improve the flatness of the layer structure of the anode layer 120 away from the substrate, thereby improving the problem of color deviation in the subsequent structure.

[0076] Optionally, the display panel further includes a pixel definition layer 280 located on a side of the anode layer 120 away from the substrate 230 . In the display area 210 , the pixel definition layer 280 includes a pixel opening 140 .

[0077] The orthographic projection of the sidewall of the first via hole 261 on the substrate 230 does not overlap with the orthographic projection of the surface of the pixel opening 140 close to the substrate 230 on the substrate 230 .

[0078] Specifically, when the distance between the first via hole 261 and the pixel opening 140 in the horizontal direction X is relatively close, the sidewall of the first via hole 261 may affect the light emission direction in the pixel opening 140 , thereby causing a color shift problem. Figure 4 This is a structural diagram of another related art display panel, see Figure 4 The distance a between the bottom edge of the first via hole 261 and the bottom edge of the pixel opening 140 is too small, causing the sidewall of the first via hole 261 to be exposed in the pixel opening 140. Since the sidewall of the first via hole 261 has an inclination angle, the light transmission direction will be offset, resulting in the problem of display color deviation. In the embodiment of the present invention, Figure 5 A partial structural diagram of another display panel is provided for an embodiment of the present invention, Figure 3 , see Figure 5The sidewall angle of the first via hole 261 is greater than or equal to 45°. That is, given a given diameter, the larger the sidewall angle of the first via hole 261, the steeper the sidewall of the first via hole 261 appears. Consequently, the horizontal dimension X of the surface of the first via hole 261 away from the substrate 230 is correspondingly reduced. Without changing the position of the pixel opening 140, this is equivalent to increasing the distance between the lower bottom edge of the first via hole 261 and the lower bottom edge of the pixel opening 140. By increasing the distance a between the lower bottom edge of the first via hole 261 and the lower bottom edge of the pixel opening 140, the orthographic projection of the sidewall of the first via hole 261 on the substrate 230 and the orthographic projection of the surface of the pixel opening 140 closer to the substrate 230 on the substrate 230 do not overlap. This improves the flatness within the pixel opening 140, reduces the deviation in the light transmission direction, and improves the displayed color shift. For example, when the aperture of the first via hole 261 is relatively small, such as 2.5*2.5 um, combined with a relatively large sidewall angle, the influence of the via hole morphology on the light-emitting area within the pixel opening 140 can be better controlled.

[0079] Continue to see Figure 3 , Optionally, the insulating layer 250 includes an intermediate dielectric layer 310 , and the second conductive layer 270 includes an intermediate conductive layer 320 ;

[0080] The intermediate dielectric layer 310 is located on the side of the first conductive layer 240 away from the substrate 230 , and the intermediate conductive layer 320 is located on the side of the intermediate dielectric layer 310 away from the substrate 230 ; the via 260 includes a second via 262 , and the intermediate conductive layer 320 is connected to at least one first conductive layer 240 through the second via 262 .

[0081] Specifically, in the display area 210, a pixel circuit array is further provided on the substrate 230. The pixel circuit array is provided between the substrate 230 and the light-emitting device. The pixel circuit array includes a transistor device 160 and a capacitor device 170. The at least one first conductive layer 240 may include a second metal layer 242 and a third metal layer 243. The second metal layer 242 may serve as the gate of the transistor device 160 and one plate of the capacitor device 170. The third metal layer 243 may serve as the other plate of the capacitor device 170. The at least one first conductive layer 240 may also include a conductive layer for the source S and drain D of the transistor device 160.

[0082] The second conductive layer 270 may include an intermediate conductive layer 320, which is electrically connected to the source S of the transistor device 160 via a second via 262. In an embodiment of the present invention, the intermediate conductive layer 320 and the first metal layer 241 may be provided on the same layer, and the first metal layer 241 is directly electrically connected to the drain D of the transistor device 160 via the second via 262. In other display panel structures, the intermediate conductive layer 320 and the first metal layer 241 may also be provided on different layers, and the intermediate conductive layer 320 and the first metal layer 241 may be utilized to rearrange the lead-out positions of the source S and drain D of the transistor device 160.

[0083] An intermediate dielectric layer 310 is used to provide insulation protection between the second metal layer 242 and the intermediate conductive layer 320. A second via 262 is provided in the intermediate dielectric layer 310 of the display area 210. The second via 262 can expose the electrical connection area of ​​the source and drain of the transistor device 160. The intermediate conductive layer 320 is electrically connected to the source S of the transistor device 160 through the second via 262, and the first metal layer 241 is electrically connected to the drain D of the transistor device 160 through the second via 262.

[0084] Among them, the second via 262 in the intermediate dielectric layer 310 can also be prepared by dry etching, so that the sidewall angle of the second via 262 is greater than or equal to 45°. When the diameter size of the second via 262 is determined, the larger the sidewall angle of the second via 262, the steeper the sidewall of the second via 262. Therefore, it is easier to achieve uniform deposition in the process of preparing the intermediate conductive layer 320 and the first metal layer 241, reduce the film thickness difference at the sidewall climbing point of the second via 262, and improve the flatness of the layer structure of the intermediate conductive layer 320 away from the substrate, thereby effectively improving the subsequent color deviation problem.

[0085] Figure 6 A schematic diagram of a method for manufacturing a display panel according to an embodiment of the present invention is provided. Figure 2 The display panel includes a display area 210; the preparation method includes:

[0086] S110, providing a substrate 230;

[0087] S120, forming at least one first conductive layer 240 on one side of the substrate 230;

[0088] S130, forming an insulating layer 250 on a side of the first conductive layer 240 away from the substrate 230, wherein the insulating layer 250 includes at least one via hole 260, the at least one via hole 260 is disposed in the display area 210, and a sidewall angle of the at least one via hole 260 is greater than or equal to 45°;

[0089] Specifically, the sidewall angle refers to the angle between the via sidewall and the horizontal direction X. In the display area 210, the sidewall angle of at least one via 260 is greater than or equal to 45°. By increasing the steepness of the via sidewall, the opening size of the via on the side away from the substrate 230 in the horizontal direction X can be reduced, while the diameter of the via is determined. This reduces the difference in width between the opening on the side of the via away from the substrate 230 and the surface of the via on the side close to the substrate 230, thereby improving the dimensional accuracy of the via. The larger the via sidewall angle, the more conducive it is for the deposited material to grow along the sidewall during the deposition of the second conductive layer 270, thereby reducing deposition dead angles and improving the uniformity of the deposited material distribution within the via. This in turn reduces the thickness variation of the second conductive layer 270 at the sidewall slope, improves the flatness of the layer structure on the side of the second conductive layer 270 away from the substrate, and alleviates the subsequent color shift problem.

[0090] For example, to improve the sidewall angle of the at least one via hole 260 in the display area 210, the at least one via hole 260 in the display area 210 can be prepared using a dry etching process. The dry etching process can achieve a hole of a specific shape and size. For example, after forming the insulating layer 250, the insulating layer 250 is dry-etched in the display area 210. The dry-etched via hole can produce a more accurate aperture and a steeper sidewall angle, thereby better controlling the via hole morphology.

[0091] S140 , forming a second conductive layer 270 on a side of the insulating layer 250 away from the substrate 230 , wherein the second conductive layer 270 is connected to at least one first conductive layer 240 through at least one via 260 .

[0092] Optionally, the display panel includes a non-display area 220; an insulating layer 250 is formed on the side of the first conductive layer 240 away from the substrate 230, and the insulating layer 250 also includes a side wall in the non-display area 220, and the side wall angle of at least one via 260 is greater than or equal to the side wall angle of the insulating layer 250 in the non-display area 220.

[0093] Specifically, the non-display area 220 is disposed on one side of the display area 210 , and the insulating layer 250 has patterns such as hollowing and vias in the non-display area 220 , and the boundary of the pattern is the side wall of the insulating layer 250 in the non-display area 220 .

[0094] When the sidewall angle of at least one via hole 260 in the display area 210 is greater than the sidewall angle of the insulating layer 250 in the non-display area 220, the sidewall of the insulating layer 250 in the non-display area 220 can be formed first in the process, and then the at least one via hole 260 on the insulating layer 250 in the display area 210 can be formed. In other words, the pattern on the insulating layer 250 in the non-display area 220 can be prepared using the original preparation process, such as the gray tone mask process (GTM). The via hole 260 on the insulating layer 250 in the display area 210 can be prepared using a dry etching process. The etching accuracy of the dry etching process is higher than that of the GTM process. Therefore, compared with the original preparation process, the sidewall angle of the via hole can be obtained that is greater than the sidewall angle of the insulating layer in the non-display area, thereby better controlling the via hole morphology in the display area and ensuring that the sidewall angle of the via hole meets the requirements.

[0095] When the sidewall angle of at least one via 260 in the display area 210 is equal to the sidewall angle of the insulating layer 250 in the non-display area 220, the same process can be used to simultaneously form the sidewall of the insulating layer 250 in the non-display area 220 and at least one via 260 on the insulating layer 250 in the display area 210. In order to make the sidewall angle of the via better, it can be prepared through a dry etching process, so that the via morphology can be better controlled.

[0096] Optionally, when the sidewall angle of at least one via hole 260 in the display area 210 is greater than the sidewall angle of the insulating layer 250 in the non-display area 220, the sidewall of the insulating layer 250 may be formed in the non-display area 220 by a grayscale mask process; and in the display area 210, the at least one via hole 260 may be formed by a dry etching process.

[0097] Specifically, the preparation process of the insulating layer 250 is as follows: an insulating material is coated to form the insulating layer 250, and then exposure and development are performed in the non-display area 220 to form a pattern in the non-display area 220, while no corresponding via pattern is set in the display area 210. After the film layer is baked and cured, photoresist is applied, and a mask template with a corresponding via pattern is set in the display area 210 using the photoresist. The cured insulating layer 250 is dry-etched to form at least one via 260 in the display area 210, and then the photoresist is stripped and cleaned. In other words, the patterns of the insulating layer 250 in the display area 210 and the non-display area 220 are set using different preparation processes. When preparing the pattern of the non-display area 220, the existing process can be used, and the pattern of the display area 210 can be dry-etched.

[0098] Optionally, when the sidewall angle of the at least one via hole 260 in the display area 210 is equal to the sidewall angle of the insulating layer 250 in the non-display area 220 , the at least one via hole 260 in the display area 210 and the sidewall of the insulating layer 250 in the non-display area 220 may be formed simultaneously by a dry etching process;

[0099] Specifically, the preparation process of the insulating layer 250 is as follows: an insulating material is coated to form the insulating layer 250, the film layer is baked, and then a photoresist is coated. Through exposure and development, the photoresist forms a mask template with corresponding via patterns in the display area 210 and the non-display area 220, and then all patterns are dry-etched, so that the morphology of the patterns can be better controlled.

[0100] Furthermore, before forming at least one via hole 260 in the display area 210 by a dry etching process, the method further includes forming a groove of a preset depth at a position corresponding to the at least one via hole 260 in the insulating layer 250 . Figure 7 A schematic diagram of the structure of an insulating layer after surface pretreatment is provided in an embodiment of the present invention. Before forming the pattern of at least one via 260 by a dry etching process, a mask template of the via pattern can be used in advance to perform exposure and development after the insulating layer 250 is formed, and pretreatment is performed in advance at the corresponding position of at least one via 260 to form a groove 410 of a preset depth. The groove 410 is used to thin the film layer at the via in advance, and the dry etching time can be shortened when the via is subsequently formed by dry etching. In addition, since there is lateral etching in the dry etching process, the groove 410 can be used to guide the plasma movement trajectory, thereby reducing the lateral expansion of the via side wall, and further reducing the size of the via away from the surface of the substrate 230.

[0101] Exemplary preparation process of the insulating layer 250: an insulating material is coated to form the insulating layer 250, and pre-treatment is performed at the corresponding position of the via hole 260 in the display area 210 to form a groove of a preset depth, so that the film layer at the via hole will become thinner. After the film layer is baked and cured, photoresist is applied, and a mask template with a corresponding via pattern is set in the display area 210 through the photoresist. The cured insulating layer 250 film is dry-etched to form the corresponding pattern of the via hole 260 in the display area 210, and then the photoresist is stripped and cleaned. By pre-treating the corresponding position of at least one via hole 260 in the insulating layer 250 to form a groove of a preset depth in advance, the dry etching time can be shortened compared to directly dry etching to form the via hole, and the size of the via hole away from the surface of the substrate 230 can be further reduced.

[0102] Figure 8 A schematic diagram of a process for manufacturing another display panel provided by an embodiment of the present invention, combined with Figure 3The insulating layer 250 includes a planar layer 110 , and the second conductive layer 270 includes an anode layer 120 ; the at least one via hole 260 includes a first via hole 261 , and a sidewall angle of the first via hole 261 is greater than or equal to 45°;

[0103] The preparation method comprises:

[0104] S210 , forming a flat layer 110 on a side of the first conductive layer 240 away from the substrate 230 ;

[0105] Specifically, the at least one first conductive layer 240 may include a first metal layer 241, wherein the first metal layer 241 is directly or indirectly electrically connected to the drain of the transistor device 160 in the pixel circuit array. A planar layer 110 is formed on a side of the first metal layer 241 away from the substrate 230.

[0106] S220, forming an anode layer 120 on a side of the planar layer 110 away from the substrate 230; wherein the at least one via 260 includes a first via 261, and the anode layer 120 is connected to the at least one first conductive layer 240 through the first via 261;

[0107] Specifically, the insulating layer 250 may include a planar layer 110, and the second conductive layer 270 may include an anode layer 120 of the light-emitting device. A first via 261 is provided on the planar layer 110. The first via 261 may expose the electrical connection area of ​​the first metal layer 241. The anode layer 120 is electrically connected to the first metal layer 241 through the first via 261. The sidewall angle of the first via 261 is greater than or equal to 45°. That is, when the diameter of the first via 261 is determined, the larger the sidewall angle of the first via 261, the steeper the sidewall of the first via 261. Therefore, uniform deposition is more easily achieved during the preparation of the anode layer 120, reducing the thickness difference of the anode layer 120 at the sidewall slope of the first via 261, and improving the flatness of the layer structure of the anode layer 120 away from the substrate, thereby improving the problem of subsequent color shift.

[0108] The first via hole 261 on the flat layer 110 in the display area 210 can be formed simultaneously with the sidewalls of the flat layer 110 in the non-display area 220. To achieve a better sidewall angle for the first via hole 261, a dry etching process can be used to better control the via hole morphology. For example, the preparation process of the flat layer 110 is as follows: an insulating material is coated to form the flat layer 110. A single mask can be used to dry-etch all patterns in the flat layer 110 in the display area 210 and the non-display area 220, thereby better controlling the pattern morphology.

[0109] The first via hole 261 on the flat layer 110 of the display area 210 can be prepared by different processes from the sidewalls of the flat layer 110 of the non-display area 220. For example, the sidewalls of the flat layer 110 of the non-display area 220 can be formed first, and then the first via hole 261 on the flat layer 110 of the display area 210 can be formed. In other words, the pattern on the flat layer 110 of the non-display area 220 can be prepared using the original preparation process, such as the GTM process. As for the first via hole 261 on the flat layer 110 of the display area 210, it can be prepared by a dry etching process, so that the via hole morphology can be better controlled. Exemplary preparation process of the flat layer 110: an insulating material is coated to form the flat layer 110, and the non-display area 220 is exposed and developed to form the pattern of the flat layer 110 in the non-display area 220, while the display area 210 is not provided with a corresponding first via hole 261 pattern. After the film layer is baked and cured, photoresist is applied. A mask with a corresponding via pattern is formed in the display area 210 using the photoresist. The cured planar layer 110 is dry-etched to form the first vias 261 in the display area 210. The photoresist is then stripped and cleaned. In other words, different fabrication processes are used to pattern the planar layer 110 in the display area 210 and the non-display area 220. For example, existing processes can be used to pattern the non-display area 220, while dry etching can be used to pattern the display area 210.

[0110] S230 , forming a pixel definition layer 280 on a side of the anode layer 120 away from the substrate 230 , wherein the pixel definition layer 280 includes a pixel opening 140 in the display area 210 ;

[0111] The orthographic projection of the sidewall of the first via hole 261 on the substrate 230 does not overlap with the orthographic projection of the surface of the pixel opening 140 close to the substrate 230 on the substrate 230 .

[0112] Specific, combined Figure 4 With the diameter of the first via hole 261 fixed, the larger the sidewall angle of the first via hole 261, the steeper the sidewall of the first via hole 261 appears. Therefore, the horizontal dimension X of the surface of the first via hole 261 away from the substrate 230 is correspondingly reduced, which is equivalent to increasing the distance between the lower bottom edge of the first via hole 261 and the lower bottom edge of the pixel opening 140. By increasing the distance between the lower bottom edge of the first via hole 261 and the lower bottom edge of the pixel opening 140, the orthographic projection of the sidewall of the first via hole 261 on the substrate 230 and the orthographic projection of the surface of the pixel opening 140 closer to the substrate 230 on the substrate 230 do not overlap, thereby improving the flatness of the pixel opening 140 and reducing the impact of color shift.

[0113] Figure 9A schematic diagram of a process for manufacturing another display panel provided by an embodiment of the present invention, combined with Figure 3 The insulating layer 250 includes an intermediate dielectric layer 310, and the second conductive layer 270 includes an intermediate conductive layer 320; the at least one via 260 includes a second via 262, and the sidewall angle of the second via 262 is greater than or equal to 45 degrees;

[0114] The preparation method comprises:

[0115] S310, forming an intermediate dielectric layer 310 on a side of the first conductive layer 240 away from the substrate 230;

[0116] Specifically, in the display area 210, a pixel circuit array is further provided on the substrate 230. The pixel circuit array is provided between the substrate 230 and the light-emitting device. The pixel circuit array includes a transistor device 160 and a capacitor device 170. The at least one first conductive layer 240 may include a second metal layer 242 and a third metal layer 243. The second metal layer 242 may serve as the gate of the transistor device 160 and one plate of the capacitor device 170. The third metal layer 243 may serve as the other plate of the capacitor device 170. The at least one first conductive layer 240 may also include a conductive layer 130 serving as the source and drain of the transistor device 160.

[0117] S320 , forming an intermediate conductive layer 320 on a side of the intermediate dielectric layer 310 away from the substrate 230 ; at least one via 260 includes a second via 262 , and the intermediate conductive layer 320 is connected to at least one first conductive layer 240 through the second via 262 .

[0118] Specifically, the second conductive layer 270 may include an intermediate conductive layer 320, which is electrically connected to the source S of the transistor device 160 via a second via 262. In an embodiment of the present invention, the intermediate conductive layer 320 and the first metal layer 241 may be provided on the same layer, and the first metal layer 241 is directly electrically connected to the drain D of the transistor device 160 via the second via 262. In other display panel structures, the intermediate conductive layer 320 and the first metal layer 241 may also be provided on different layers, and the intermediate conductive layer 320 and the first metal layer 241 may be utilized to rearrange the lead-out positions of the source S and drain D of the transistor device 160.

[0119] An intermediate dielectric layer 310 is used to provide insulation protection between the second metal layer 242 and the intermediate conductive layer 320. A second via 262 is provided in the intermediate dielectric layer 310 of the display area 210. The second via 262 can expose the electrical connection area of ​​the source and drain of the transistor device 160. The intermediate conductive layer 320 is electrically connected to the source S of the transistor device 160 through the second via 262, and the first metal layer 241 is electrically connected to the drain D of the transistor device 160 through the second via 262. Among them, the side wall angle of the second via 262 is greater than or equal to 45°, that is, when the diameter size of the second via 262 is determined, the larger the side wall angle of the second via 262, the steeper the side wall of the second via 262. Therefore, it is easier to achieve uniform deposition in the process of preparing the intermediate conductive layer 320 and the first metal layer 241, reduce the film thickness difference at the side wall climbing of the second via 262, and improve the flatness of the layer structure of the intermediate conductive layer 320 away from the substrate, thereby effectively improving the problem of color deviation in subsequent structures.

[0120] The second via 262 on the intermediate dielectric layer 310 in the display area 210 can be formed simultaneously on the sidewalls of the intermediate dielectric layer 310 in the non-display area 220. To achieve a better sidewall angle for the second via 262, a dry etching process can be used to better control the via morphology. For example, the intermediate dielectric layer 310 is prepared by coating an insulating material to form the intermediate dielectric layer 310. A single mask can be used to dry-etch all patterns in the intermediate dielectric layer 310 in the display area 210 and the non-display area 220, thereby better controlling the pattern morphology.

[0121] The second via 262 on the intermediate dielectric layer 310 of the display area 210 can be prepared using different processes than the sidewalls of the intermediate dielectric layer 310 of the non-display area 220. For example, the sidewalls of the intermediate dielectric layer 310 of the non-display area 220 can be formed first, and then the second via 262 on the intermediate dielectric layer 310 of the display area 210 can be formed. In other words, the pattern on the intermediate dielectric layer 310 of the non-display area 220 can be prepared using the original preparation process, such as the GTM process. The second via 262 on the intermediate dielectric layer 310 of the display area 210 can be prepared using a dry etching process, thereby better controlling the via morphology. Exemplary preparation process of the intermediate dielectric layer 310: an insulating material is coated to form the intermediate dielectric layer 310, which is then exposed and developed in the non-display area 220 to form the pattern of the intermediate dielectric layer 310 in the non-display area 220, while the display area 210 does not have a corresponding second via 262 pattern. After the film layer is baked and cured, photoresist is applied. A mask with a corresponding via pattern is formed in the display area 210 using the photoresist. The cured intermediate dielectric layer 310 is dry-etched to form the second via 262 in the display area 210. The photoresist is then stripped and cleaned. In other words, the intermediate dielectric layer 310 in the display area 210 and the non-display area 220 is patterned using different fabrication processes. For example, the pattern in the non-display area 220 can be fabricated using existing processes, while the pattern in the display area 210 can be dry-etched.

[0122] Figure 10 A schematic diagram of the structure of a display device is provided in an embodiment of the present invention. Figure 10 , including the display panel 10 of any embodiment of the present invention. Figure 10 The display device shown is for illustrative purposes only. The display device may include any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, without limitation. The specific beneficial effects of the display panel 10 have been described in detail in the above embodiments. This display device has the same beneficial effects as the above display panel, and therefore will not be further described here.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A display panel, characterized in that: The display panel includes a display area, and the display panel further includes: substrate, At least one first conductive layer is located on one side of the substrate, an insulating layer, located on a side of the first conductive layer away from the substrate, the insulating layer comprising via holes, the via holes being arranged in the display area, and at least one of the via holes having a sidewall angle greater than or equal to 45°; The second conductive layer is located on a side of the insulating layer away from the substrate, and the second conductive layer is connected to at least one layer of the first conductive layer through at least one via hole.

2. The display panel according to claim 1, wherein: The display panel includes a non-display area; the sidewall angle of at least one of the via holes is greater than or equal to the sidewall angle of the insulating layer in the non-display area; Preferably, the sidewall angle of at least one of the via holes is greater than or equal to 60°; Preferably, the sidewall angle of any of the via holes is greater than or equal to 60°; Preferably, the sidewall angle of any of the via holes is greater than the sidewall angle of the insulating layer in the non-display area; Preferably, the opening size of the via hole at a side away from the substrate is 2.5 μm-8 μm.

3. The display panel according to any one of claims 1 to 2, wherein: The insulating layer includes a planar layer, and the second conductive layer includes an anode layer; The flat layer is located on a side of the first conductive layer away from the substrate, and the anode layer is located on a side of the flat layer away from the substrate; the via includes a first via, and the anode layer is connected to at least one layer of the first conductive layer through the first via; Preferably, the display panel further comprises a pixel definition layer located on a side of the anode layer away from the substrate, and in the display area, the pixel definition layer comprises a pixel opening; The orthographic projection of the side wall of the first via hole on the substrate does not overlap with the orthographic projection of the surface of the pixel opening close to the substrate on the substrate.

4. The display panel according to any one of claims 1 to 2, wherein: The insulating layer includes an intermediate dielectric layer, and the second conductive layer includes an intermediate conductive layer; The intermediate dielectric layer is located on the side of the first conductive layer away from the substrate, and the intermediate conductive layer is located on the side of the intermediate dielectric layer away from the substrate; the via includes a second via, and the intermediate conductive layer is connected to the at least one first conductive layer through at least one second via.

5. A method for preparing a display panel, wherein the display panel comprises a display area, characterized in that: The preparation method comprises: providing a substrate; forming at least one first conductive layer on one side of the substrate; forming an insulating layer on a side of the first conductive layer away from the substrate, wherein the insulating layer includes at least one via hole, the via hole is disposed in the display area, and a sidewall angle of at least one of the via holes is greater than or equal to 45°; A second conductive layer is formed on a side of the insulating layer away from the substrate, and the second conductive layer is connected to the at least one first conductive layer through at least one via hole.

6. The method for manufacturing a display panel according to claim 5, wherein: The display panel includes a non-display area; an insulating layer is formed on a side of the first conductive layer away from the substrate, the insulating layer further includes a sidewall in the non-display area, and the sidewall angle of at least one of the via holes is greater than or equal to the sidewall angle of the insulating layer in the non-display area; Preferably, the sidewall angle of at least one of the via holes is greater than or equal to 60°; Preferably, the sidewall angle of any of the via holes is greater than or equal to 60°; Preferably, a sidewall angle of any of the via holes is greater than a sidewall angle of the insulating layer in the non-display area.

7. The method for manufacturing a display panel according to claim 6, wherein: An insulating layer is formed on a side of the first conductive layer away from the substrate, the insulating layer further comprising a sidewall in the non-display area, and an angle of the sidewall of at least one of the via holes is greater than an angle of the sidewall of the insulating layer in the non-display area, comprising: coating an insulating material on a side of the first conductive layer away from the substrate to form the insulating layer; In the non-display area, forming a sidewall of the insulating layer by a grayscale mask process; In the display area, forming the via hole by dry etching process; Preferably, after forming the sidewall of the insulating layer, the method further comprises: baking and curing the insulating layer; Alternatively, an insulating layer is formed on a side of the first conductive layer away from the substrate, the insulating layer further comprises a sidewall in the non-display area, and the sidewall angle of at least one of the via holes is equal to the sidewall angle of the insulating layer in the non-display area, including: coating an insulating material on a side of the first conductive layer away from the substrate to form the insulating layer; Simultaneously forming the via hole in the display area and the sidewall of the insulating layer in the non-display area by a dry etching process; Preferably, after forming the sidewall of the insulating layer, the method further comprises: baking and curing the insulating layer; Preferably, before forming the via hole in the display area by dry etching, the method further comprises: A groove of a preset depth is formed at a position corresponding to the via hole of the insulating layer.

8. The method for manufacturing a display panel according to any one of claims 5 to 7, wherein: The insulating layer includes a planar layer, and the second conductive layer includes an anode layer; forming the flat layer on a side of the first conductive layer away from the substrate; The anode layer is formed on a side of the flat layer away from the substrate; wherein the via hole includes a first via hole, and the anode layer is connected to at least one layer of the first conductive layer through the first via hole; Preferably, a pixel definition layer is formed on the side of the anode layer away from the substrate, and in the display area, the pixel definition layer includes a pixel opening; The orthographic projection of the side wall of the first via hole on the substrate does not overlap with the orthographic projection of the surface of the pixel opening close to the substrate on the substrate.

9. The method for manufacturing a display panel according to any one of claims 5 to 7, wherein: The insulating layer includes an intermediate dielectric layer, and the second conductive layer includes an intermediate conductive layer; forming the intermediate dielectric layer on a side of the first conductive layer away from the substrate; The intermediate conductive layer is formed on a side of the intermediate dielectric layer away from the substrate; the via hole includes a second via hole, and the intermediate conductive layer is connected to at least one layer of the first conductive layer through the second via hole.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 4.

Images