Method for improving nano-scale small suede PL blackening of perovskite crystal silicon bottom cell

Abstract

The invention relates to the technical field of perovskite cells, in particular to a method for improving PL blackening of a nano-scale suede of a perovskite crystalline silicon bottom cell, and the method comprises the steps: preparing a micropore array on a silicon wafer with a nano-scale suede, and enabling the micropore array to serve as an impurity trap, and transferring metal impurities into micropores from an active region; the method further comprises an ion exchange resin adsorption step, the ion exchange resin adsorption step is the last step, impurities obtained by cleaning the silicon wafer and impurities appearing in the tank body in the cleaning process are adsorbed by resin ball particles, and the impurities are prevented from being secondarily diffused and attached to the silicon wafer. After the nanometer suede silicon wafer is processed, the PL blackening defect of the nanometer suede silicon wafer is reduced to be within 0.01% from 30%, and the product yield is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of perovskite cells, and in particular to a method for improving the blackening of nanoscale small velvet surfaces of perovskite crystalline silicon bottom cells. Background Art

[0002] The textured surface of single-crystal silicon is formed by etching with an alkaline solution of sodium hydroxide or potassium hydroxide to form a pyramidal structure. While this micron-scale uneven surface enhances light absorption, the densely packed micron-sized pyramids within the ravines and gaps easily attract particulate matter and organic residues. Contaminants (such as the textured solution, additives, metal ions, and dust) can easily become lodged in the pyramid gaps, making them difficult to completely remove with conventional rinsing, thus posing a cleaning challenge. This is particularly true for perovskite / silicon tandem solar cells, where the textured surface is smaller, transitioning from micron- to nanometer-scale. This is achieved by ensuring better wettability of the perovskite solution, enabling conformal coverage and avoiding film fractures or voids caused by the large pyramid structures. Furthermore, the nanoscale confinement effect induces vertical growth of perovskite grains, improving crystal quality. Furthermore, the nanostructure promotes carrier separation and collection, and the nanotexture helps release residual stress in the perovskite film, enhancing device stability in the perovskite tandem cell.

[0003] While nanoscale textures offer excellent properties as a perovskite stack substrate, they can lead to deep contaminant retention. After the subsequent PECVD process, these deeply trapped areas can form localized high-resistance regions or micro-short-circuit channels. This leads to increased carrier recombination in these areas during PL (photoluminescence) testing, resulting in dark patches and a black appearance. This deteriorates the performance of the finished battery stack. This is primarily due to the nanoscale texture's dense submicron grooves or pores (typically <500nm) that can reach micron depths, creating an ultra-high aspect ratio structure. Once external contaminants (such as metal particles and organic matter) enter the bottom of the grooves, conventional water shear forces cannot dislodge them. Furthermore, the nanoscale pores generate strong capillary forces that actively adsorb impurity particles from the liquid, making it easier for contaminants to embed within the structure rather than remain on the surface.

[0004] At present, in order to improve the problem of residual pollutants or incomplete cleaning on nano-scale velvet surfaces, the bubbling parameters are adjusted to enhance the permeability of the drug solution, the water flow rate is increased to improve the hydrophobicity, the slow pulling speed is optimized to reduce the liquid film residue, high-frequency ultrasonic cleaning, low surface tension solvent cleaning, etc. This method has obvious effects on micron-scale velvet surfaces, but is not significant in the nano-scale velvet state. Therefore, it is necessary to study new technical means and new devices to systematically solve the problems of residual pollutants and deep retention during the growth of nano-scale velvet surfaces. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for improving the blackening of the nanoscale small velvet surface PL of perovskite crystalline silicon bottom cells, and to solve the technical problems of residual pollutants and deep retention during the growth of nanoscale velvet in the prior art.

[0006] The present invention discloses a method for improving the blackening of nanoscale small textured surfaces of perovskite crystalline silicon bottom cells. A micropore array is prepared on a silicon wafer with a nanoscale textured surface. The micropore array acts as an impurity trap to transfer metal impurities from the active area to the micropores.

[0007] Furthermore, the diameter of the micropores of the micropore array is 10-50 nm.

[0008] Furthermore, the micropore array is obtained by helium ion treatment and then annealing.

[0009] Furthermore, the micropore array is specifically prepared by injecting helium ions and annealing at 750-850° C. for 4-10 minutes to form the micropore array through annealing.

[0010] Furthermore, the helium ions are implanted with an energy of 5–20 keV and an implantation dose of 1×10 12 -1×10 13 cm -2 .

[0011] Furthermore, it also includes an ion exchange resin adsorption step. The ion exchange resin adsorption is the last step, in which impurities cleaned from the silicon wafer and impurities appearing in the tank during the cleaning process are adsorbed by resin ball particles to prevent the impurities from diffusing secondary and adhering to the silicon wafer.

[0012] Furthermore, the exchange resin adsorption step includes removing the phosphosilicate glass and impurity layer on the surface of the silicon wafer and cleaning the residual cleaning solution on the surface of the silicon wafer.

[0013] Furthermore, the removal of the phosphosilicate glass and impurity layer on the surface of the silicon wafer is specifically as follows: the silicon wafer is placed in a cleaning solution mixed with a first ion exchange resin for cleaning for 60-120 seconds at a temperature of 20-30° C. to remove the phosphosilicate glass and impurity layer on the surface of the silicon wafer.

[0014] Furthermore, the first ion exchange resin is a macroporous adsorption resin that mechanically intercepts suspended matter and adsorbs hydrophobic organic matter.

[0015] Furthermore, the cleaning solution has a volume ratio of HF / HCL=1:0.2-0.3.

[0016] Furthermore, the residual cleaning solution on the surface of the silicon wafer is cleaned by placing the silicon wafer in pure water mixed with a second ion exchange resin for 60-120 seconds at a temperature of 20-30° C., thereby simultaneously removing residual anions and cations while improving purity and adsorbing hydrophobic organic matter.

[0017] Furthermore, the second ion exchange resin is a resin in which cationic and anionic resins are uniformly mixed.

[0018] Furthermore, after the residual cleaning solution is cleaned, it is rinsed and dried to complete the treatment.

[0019] Furthermore, the rinsing is performed in a slow pulling tank containing the third ion exchange resin balls, with a cleaning time of 200-300s and a temperature of 50-70°C.

[0020] Furthermore, the third ion exchange resin ball is a mixed bed resin.

[0021] Furthermore, after the microporous array is prepared, the steps of cleaning, high-temperature phosphorus diffusion deep treatment, overall plasma discharge etching and ion exchange resin adsorption are also included.

[0022] Furthermore, after annealing is completed, cleaning is performed to remove surface residues and metal impurities that have migrated to the surface.

[0023] Furthermore, the cleaning is specifically as follows: first, a 0.8% concentration HF solution is used to dissolve the surface silicon oxide microporous array generated by annealing, with a cleaning time of 30-120s and a temperature of 20-125°C to avoid blocking the penetration of subsequent cleaning agents; secondly, an ammonia-hydrogen peroxide mixture is used to remove organic matter, particulate pollutants, and complexed alkali metals (sodium, potassium ions), and the process parameters are 3-5 minutes at 60-80°C; then a hydrochloric acid-hydrogen peroxide mixture is used to remove transition metals (iron, copper, etc.) and SC-1 residues, and the process parameters are 3-5 minutes at 60-80°C; finally, pure water cleaning and drying are performed.

[0024] Furthermore, the texture of the silicon wafer has a size of 100-900 nm and a depth of 100-900 nm.

[0025] Furthermore, the high-temperature phosphorus diffusion deep treatment is to precipitate impurities in the deep grooves of the nano-texture surface to the surface through high-temperature phosphorus gettering.

[0026] Furthermore, the plasma discharge etching ionizes the impurities precipitated from the micropore array and the high-temperature phosphorus diffusion deep treatment as well as the impurities deep in the suede grooves, so as to make them into a loose and delaminated state.

[0027] Furthermore, the plasma source material in the plasma discharge etching is a mixed gas of CF4 and O2, the reaction gas volume ratio CF4:O2=1:0.05~0.15, the RF power is 100-300W, the processing time is 1-3 minutes, and the chamber pressure is 50-200Pa.

[0028] A perovskite crystalline silicon bottom cell is prepared using the above method.

[0029] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention sequentially performs bulk helium ion primary treatment on the nano-textured silicon wafer, internal high-temperature phosphorus diffusion deep treatment, and overall plasma bombardment, forming a systematic process of impurity removal from the surface to the interior to the entire wafer, effectively removing surface contaminants on the nano-textured silicon wafer and residues deep within the textured surface. 2. The present invention cleans the ion exchange resin ball tank containing the silicon wafer after system treatment, ensuring that the impurities cleaned from the silicon wafer are adsorbed on the one hand, and the impurities in the solution are adsorbed on the other hand. As a result, the dirt on the silicon wafer and the solution are adsorbed by the resin ball particles at the same time, preventing the contaminants from diffusing secondary in the tank and adhering to the silicon wafer, keeping the tank solution clean. In this way, the strong capillary force generated by the pores of the nano-textured silicon wafer actively adsorbs impurity particles in the liquid, preventing the contaminants from embedding into the structure and on the surface. 3. By subjecting the nano-textured silicon wafer to external, internal, and overall system impurity absorption and ion exchange resin ball adsorption cleaning, a 1+1>2 effect was achieved. After treatment, the PL blackening defect rate of the nano-textured silicon wafer dropped from 30% to less than 0.01%, significantly improving the product yield. After treatment with the process of the present invention, the minority carrier lifetime of the nano-textured silicon wafer was increased from 970μs to 2500μs, ultimately increasing the conversion efficiency of the stacked battery by 0.8%. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only represent some embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 This is a PL test image of the nano-texture after being processed by the embodiment of the present invention.

[0032] Figure 2 This is the PL test image of the nano-texture after the process of comparative example 1. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0034] Example 1 This embodiment discloses a method for improving the blackening of the nanoscale fine velvet surface of a perovskite crystalline silicon bottom cell, comprising the following steps: Step 1: Pre-cleaning, phosphorus gettering, texturing, pickling, water washing, and drying the single crystal silicon wafer to obtain a nano-textured silicon wafer. The texture size of the nano-textured silicon wafer is 500nm and the depth is 500nm. Step 2: Perform helium ion primary treatment on the surface of the nanotextured silicon wafer by injecting helium ions and annealing at 800°C for 6 minutes. After annealing, a micropore array with a diameter of 30 nm is formed. These micropores act as impurity traps and can transfer metal impurities from the active area to the micropores. The helium ions are injected with an energy of 10 keV and an injection dose of 1×10 13 cm -2 .

[0035] Step 3: After annealing, clean the surface to remove any residues and metal impurities that may have migrated to the surface. First, use a 0.5% HF solution to dissolve the surface silicon oxide generated by annealing. The cleaning time is 80 seconds at a temperature of 50°C to avoid blocking the penetration of subsequent cleaning agents. Next, use an ammonia-hydrogen peroxide mixture to remove organic matter, particulate contaminants, and complexed alkali metals (sodium and potassium ions). The process parameters are 80°C for 5 minutes. Then, use a hydrochloric acid-hydrogen peroxide mixture to remove transition metals (iron, copper, etc.) and SC-1 residues. The process parameters are 80°C for 3 minutes. Finally, rinse with pure water and dry.

[0036] Step 4: Perform high-temperature phosphorus diffusion deep treatment inside the nano-suede surface to remove impurities deep in the grooves of the nano-suede surface through high-temperature phosphorus gettering; Step 5: Perform plasma discharge etching on the entire nano-texture silicon wafer to ionize the impurities adsorbed by the micropores, the impurities precipitated after the phosphorus diffusion treatment, and the impurities deep in the texture grooves, making them loose and delaminated; the plasma source material is a mixture of CF4 and O2, the reaction gas ratio CF4:O2=1:0.05 (volume ratio), the RF power is 100W, the processing time is 3 minutes, and the chamber pressure is 100Pa.

[0037] Step 6: Place the nano-silicon wafer in the ion exchange resin ball tank for cleaning. The impurities cleaned from the wafer and impurities that appear in the tank during the cleaning process are adsorbed by the resin ball particles to prevent the impurities from diffusing and adhering to the wafer. This step also includes the following steps: (1) First, the silicon wafer is placed in an HF / HCL tank containing an ion exchange resin ball tank for cleaning to remove the phosphosilicate glass and impurity layer on the surface of the silicon wafer. The ion exchange resin in the tank uses a macroporous adsorption resin to mechanically intercept suspended matter and adsorb hydrophobic organic matter. The cleaning solution formula is HF / HCL = 1:0.2 (volume ratio), the cleaning time is 120s, and the temperature is 25℃.

[0038] (2) Place the wafer in a pure water tank containing ion exchange resin balls for cleaning, and clean the residual cleaning solution on the surface of the silicon wafer; the ion exchange resin in the tank is a uniform mixture of positive and negative resins, which simultaneously removes residual anions and cations while improving purity and adsorbing hydrophobic organic matter. The cleaning time is 100s and the temperature is 25°C.

[0039] (3) Place the slow pull tank containing the ion exchange resin ball tank for final rinsing; the cleaning time is 300s and the temperature is 70℃.

[0040] (4) Drying; Step 7: Use PECVD to coat amorphous silicon / microcrystalline silicon thin films on the front and back of the completed nano-silicon wafer, and measure the minority carrier lifetime and PL; Step 9: Use PVD to coat transparent conductive film on the front and back of the silicon wafer; Step 10: Print metal electrodes on the P-side silicon wafer, and sequentially deposit a hole transport layer, a perovskite layer, an organic passivation layer, an electron transport layer, a tin oxide buffer layer, a transparent conductive film layer, and print metal electrodes on the N-side to form a stacked cell. Step 11: Test the electrical performance and efficiency of the stacked battery.

[0041] Example 2 The only change on the basis of Example 1 is that step 2 is annealed at 850°C for 5 minutes to form a micropore array with a diameter of 50 nm. These micropores act as impurity traps and can transfer metal impurities from the active area to the micropores. Helium ions are injected with an energy of 15 keV and an injection dose of 1×10 12 cm -2 .

[0042] Example 3 The only change on the basis of Example 1 is that in step 6, the nano-silicon wafer is placed in the ion exchange resin ball tank for cleaning, wherein the cleaning solution formula is HF / HCL=1:0.3 (volume ratio), the cleaning time is 100s, and the temperature is 30°C.

[0043] Comparative Example 1 The only change on the basis of Example 1 is that the bottom cell and the stacked cell are prepared using the traditional process, that is, only the traditional process of step 1 is used to pre-clean, phosphorus doping, texturing, pickling, water washing and drying the single crystal silicon wafer to obtain a nano-textured silicon wafer with a texture size of 500nm and a depth of 500nm. Then, the silicon wafer is processed by traditional process steps such as CVD and PVD to prepare a finished cell.

[0044] Comparative Example 2 The only change on the basis of Example 1 is that step 2 of performing primary helium ion treatment on the surface of the nano-textured silicon wafer is not included, that is, after step 1, step 4 and subsequent steps are directly performed.

[0045] Comparative Example 3 The only change on the basis of Example 1 is that step 6 of placing the nano-silicon wafers in the ion exchange resin ball tank for cleaning is not included. Instead, the conventional cleaning process is used for cleaning, that is, the conventional cleaning tank is placed with chemical liquid, and no adsorption device or structure is placed or designed.

[0046] Comparative Example 4 The only change on the basis of Example 1 is that after the helium ions are injected in step 2, annealing is performed at 500° C. for 3 minutes to form a micropore array with a diameter of 10 nm.

[0047] Comparative Example 5 The only change on the basis of Example 1 is that, in step 6, the ion resin tank is not used for cleaning and adsorption, but the traditional filter element filtration tank is used for cleaning and adsorption.

[0048] Comparative tests of PL, minority carrier lifetime, and conversion efficiency were performed on the examples and comparative examples: (1) PL testing That is, photoluminescence testing uses a laser with a wavelength of 500-800nm ​​as an excitation light source. The laser light source excites the silicon wafer, causing the silicon wafer to emit fluorescence with an infrared light peak of around 1150nm. A highly sensitive and high-resolution camera is then used for photosensitivity and imaging. Finally, data processing is used to determine the defects on the surface of the solar cell.

[0049] After the nano-textured silicon wafer was processed by the invented process and passed through the CVD process, the PL was tested. The test results are shown in Table 1: Table 1 Comparison of PL defects

[0050] As can be seen from Table 1, the PL ratio of the embodiment is between 0.00% and 0.01%, and that of the comparative example is between 7.66% and 30.08%. The embodiment of the process of the present invention has a significant effect on improving the PL of the nano-textured silicon wafer, and the PL defect ratio has dropped from 30% to less than 0.01%. Figures 1 to 2 It can be seen that there are a lot of defects in the PL test graph of the nano-suede after the comparative example process, and the PL is black. There is no abnormality in the PL test graph of the nano-suede after the embodiment process.

[0051] From Comparative Example 1 (traditional process), it can be seen that the PL defect ratio of the nano-textured silicon wafer prepared by the traditional process reaches 22.85%-30.08%, which is the highest PL defect ratio.

[0052] It can be seen from Comparative Example 2 that step 2 is not included to perform primary helium ion treatment on the surface of the nano-textured silicon wafer, that is, step 4 and subsequent steps are directly entered after step 1. Although the defective ratio is reduced by about 50% compared with Comparative Example 1, the overall ratio is still 9.56%-30.08%. Of course, it also reflects that if step 2 is not adopted and the subsequent process of the present invention is used to treat the nano-textured silicon wafer, there will be improvement.

[0053] As can be seen from Comparative Example 3, in step 6, the nano-silicon wafers are placed in an ion exchange resin ball tank for cleaning, but a traditional cleaning process is used for cleaning. That is, the traditional cleaning tank is placed in a chemical liquid, and no adsorption device or structure is placed or designed. As the number of silicon wafer cleaning times increases, the PL defect rate begins to increase. From silicon wafer batch 1 to silicon wafer batch 5, the PL defect rate gradually increases from 9.17% to 13.15% → 13.67% → 15.29% → 18.07%. This indicates that as the number of cleaning times increases, the residual impurities in the tank liquid increase accordingly, thereby affecting the liquid's cleaning ability for the silicon wafers and causing secondary residues on the silicon wafers. This proves that the process of the present invention cleans the ion exchange resin ball tank containing the silicon wafer after system treatment, ensuring on the one hand that the impurities cleaned out of the silicon wafer are adsorbed, and on the other hand that the impurities present in the solution are adsorbed, thereby forming a situation where the dirt on the silicon wafer and the dirt in the solution are adsorbed on the resin ball particles at the same time, preventing the pollutants from diffusing secondary in the tank and attaching to the silicon wafer, keeping the tank solution clean, thereby offsetting the strong capillary force generated by the pores of the nano-scale velvet silicon wafer to actively adsorb the impurity particles in the liquid, so that the pollutants are embedded in the structure and on the surface.

[0054] As can be seen from Comparative Example 4, after helium ion injection, annealing was performed at 500°C for 3 minutes, forming a micropore array with a diameter of 10 nm. Compared with the annealing temperature of 750-850°C in Example 4, insufficient annealing resulted in incomplete micropore formation and incomplete impurity removal, resulting in a high PL defect rate of 15.20%-21.33%.

[0055] Comparative Example 5 shows that in step 6, ion resin tank cleaning and adsorption were not used, but a traditional filter cartridge was used. Although the filter cartridge had a certain adsorption capacity, the PL defect rate was still 8%-15%, and the PL defect rate gradually increased with the increase in cleaning times, reaching 15.13%. The process of the present invention proposes using different ion resin tanks for cleaning and adsorption in different tanks. For example, the pickling tank uses a macroporous adsorption resin to mechanically intercept suspended matter and adsorb hydrophobic organic matter; the water washing tank uses a uniform mixture of positive and negative resins; and the slow pull tank uses a mixed bed resin for cleaning and adsorption. This provides a highly purified cleaning environment for the tanks, ensuring the surface cleanliness of the nano-scale silicon wafers and preventing the formation of recombination centers on the silicon wafer surface, thereby improving PL defects.

[0056] (2) Minority carrier lifetime test The test was conducted using a WCT-120 minority carrier lifetime tester from Sinton, USA. Using the Quasi-Steady-State Photoconductivity (QSSPC) testing principle, the quality of silicon wafers is assessed by measuring the minority carrier lifetime under illumination. This principle is based on the recombination process of photogenerated carriers in semiconductor materials under illumination. By analyzing changes in the recombination rate, material defects (such as trap density and surface recombination) can be revealed.

[0057] After the nano-textured silicon wafer was processed by the invented process and passed through the CVD process, the minority carrier lifetime was tested. The test results are shown in Table 2: Table 2 Comparison of minority carrier lifetime test data

[0058] As can be seen from Table 2, the minority carrier lifetime of the embodiment is between 2197μs and 2503μs, and that of the comparative example is between 970μs and 1719μs. The embodiment of the process of the present invention significantly improves the minority carrier lifetime of the nano-textured silicon wafer, and the minority carrier lifetime is increased from 970μs to a maximum of 2503μs. A high minority carrier lifetime means a lower defect density, a higher probability of photogenerated carriers being collected, and less carrier recombination, thereby improving battery efficiency.

[0059] It can be seen from Comparative Example 1 (traditional process) that the minority carrier lifetime of the nano-textured silicon wafer prepared by the traditional process is 970μs-1329μs, which is the lowest.

[0060] It can be seen from Comparative Example 2 that step 2 is not included in the primary surface helium ion treatment of the nano-textured silicon wafer, that is, step 4 and subsequent steps are directly entered after step 1. Although the minority carrier lifetime is increased by about 500 μs relative to that of Comparative Example 1, the overall minority carrier lifetime is still between 1528 μs and 1709 μs. Of course, this also indirectly reflects that if step 2 is not adopted, there will be improvement in treating the nano-textured silicon wafer using the subsequent process of the present invention.

[0061] As can be seen from Comparative Example 3, in step 6, the nano-silicon wafers are placed in the ion exchange resin ball tank for cleaning, but the traditional cleaning process is used for cleaning, that is, the traditional cleaning tank is used to place chemical liquid, and no adsorption device or structure is placed or designed. As the number of silicon wafer cleaning times increases, the minority carrier lifetime begins to decrease. From silicon wafer batch 1 to silicon wafer batch 5, the minority carrier lifetime gradually decreases from 1699μs to 1652μs→1530μs→1406μs→1364μs, indicating that as the number of cleaning times increases, the residual impurities in the tank liquid increase accordingly, thereby affecting the cleaning ability of the liquid on the silicon wafer and will remain on the silicon wafer for a second time, forming a recombination center, and reducing the minority carrier lifetime. This proves that the process of the present invention cleans the ion exchange resin ball tank containing the silicon wafer after system treatment, ensuring on the one hand that the impurities cleaned out of the silicon wafer are adsorbed, and on the other hand that the impurities present in the solution are adsorbed, thereby forming a situation where the dirt on the silicon wafer and the dirt in the solution are adsorbed on the resin ball particles at the same time, preventing the pollutants from diffusing secondary in the tank and attaching to the silicon wafer, keeping the tank solution clean, thereby offsetting the strong capillary force generated by the pores of the nano-scale velvet silicon wafer to actively adsorb impurity particles in the liquid, and preventing the pollutants from being embedded in the structure and on the surface.

[0062] It can be seen from Comparative Example 4 that after the helium ion injection, annealing is performed at 500°C for 3 minutes, and a micropore array with a diameter of 10 nm is formed by annealing. Compared with the annealing temperature of 750-850°C in the embodiment, insufficient annealing in Comparative Example 4 will lead to incomplete micropore formation and incomplete impurity removal. The minority carrier lifetime is 1307μs-1554μs, which is about 800μs-1000μs lower than the minority carrier lifetime of 2197μs-2503μs in the embodiment.

[0063] As can be seen from Comparative Example 5, in step 6, the ion resin tank is not used for cleaning and adsorption, but a traditional filter element is used for cleaning and adsorption. Although the filter element has a certain adsorption capacity, due to the lack of ion conversion function, the minority carrier lifetime is 1406μs-1937μs, which is about 600μs-7000μs lower than the minority carrier lifetime of 2197μs-2503μs in the embodiment. As the number of cleaning times increases, the minority carrier lifetime decreases. The process of the present invention proposes using different ion resin tanks for cleaning and adsorption for different tanks. For example, the pickling tank uses a macroporous adsorption resin to mechanically intercept suspended matter and adsorb hydrophobic organic matter; the water washing tank uses a resin that is a uniform mixture of positive and negative resins; and the slow pulling tank uses a mixed bed resin for cleaning and adsorption, providing a relatively pure cleaning environment for the tank, ensuring the surface cleanliness of the nano-scale silicon wafer, preventing the formation of complex centers on the silicon wafer surface, and ensuring a high minority carrier lifetime.

[0064] (3) Photoelectric conversion efficiency test Using standard test conditions (STC), AM1.5 spectrum, 1000W / m² irradiance, and 25°C battery temperature environment, the nano-texture surface treated by the process of the present invention was prepared into a stacked battery, and the efficiency was tested. The test results are shown in Table 3: Table 3 Comparison of photoelectric conversion efficiency

[0065] Table 3 shows that the average efficiency of the tandem cells prepared using the inventive process is 31.56%, while that of the tandem cells prepared in the comparative example is 30.75%. The efficiency of the inventive process is 0.81% higher than that of the comparative example. The comparative example's electrical performance, primarily characterized by lower open-circuit voltage and fill factor, is lower than that of the example. Comparative Example 1 (conventional process) shows that the tandem cell prepared using the conventional process has the lowest conversion efficiency of 19.37%, 1.19% lower than the comparative example. The main differences are a 0.4V lower open-circuit voltage and a 0.65% lower fill factor. This indicates that the nanoscale silicon wafers are not cleanly processed, with high-density defects or contamination, leading to increased bulk and surface recombination, resulting in blackening in PL measurements and a decrease in open-circuit voltage. These recombination centers hinder carrier transport, increase equivalent series resistance, and thus reduce fill factor. Comparative Examples 2-5, due to the use of the inventive partial process, achieve higher conversion efficiencies than Comparative Example 1. Overall, the inventive process offers significant advantages in terms of improved yield, increased minority carrier lifetime, and increased conversion efficiency.

[0066] The above are the implementation methods listed in this embodiment, but this embodiment is not limited to the above optional implementation methods. Those skilled in the art can arbitrarily combine the above methods to obtain other various implementation methods. Anyone can derive other various forms of implementation methods based on the inspiration of this embodiment. The above specific implementation methods should not be understood as limiting the scope of protection of this embodiment. The scope of protection of this embodiment shall be based on the definition in the claims, and the description can be used to interpret the claims.

Claims

1. A method for improving the blackening of the nanoscale fine velvet surface of perovskite silicon bottom cells, characterized by: A micropore array is prepared on a silicon wafer with a nanoscale textured surface, and the micropore array acts as an impurity trap to transfer metal impurities from the active area to the micropores; It also includes an ion exchange resin adsorption step, which is the last step. The impurities cleaned from the silicon wafer and impurities appearing in the tank during the cleaning process are adsorbed by the resin ball particles to prevent the impurities from diffusing secondary and adhering to the silicon wafer.

2. The method for improving the blackening of the nanoscale fine suede surface of the perovskite silicon bottom cell according to claim 1, characterized in that: The diameter of the micropores of the micropore array is 10-50 nm.

3. The method for improving the blackening of the nanoscale fine textured surface of the perovskite silicon bottom cell according to claim 1, characterized in that: The microwell array is obtained by helium ion treatment and then annealing.

4. The method for improving the blackening of the nanoscale fine textured surface of the perovskite silicon bottom cell according to claim 3, characterized in that: The specific preparation steps of the microporous array are: injecting helium ions, annealing at 750-850° C. for 4-10 minutes, and forming the microporous array through annealing.

5. The method for improving the blackening of the nanoscale fine textured surface of the perovskite silicon bottom cell according to claim 1, characterized in that: The exchange resin adsorption step includes removing the phosphorus-silicate glass and impurity layer on the surface of the silicon wafer and cleaning the residual cleaning solution on the surface of the silicon wafer.

6. The method for improving the blackening of the nanoscale fine textured surface of the perovskite silicon bottom cell according to claim 5, characterized in that: The method of removing the phosphosilicate glass and impurity layer on the surface of the silicon wafer is specifically as follows: the silicon wafer is placed in a cleaning solution mixed with a first ion exchange resin for cleaning, with a cleaning time of 60-120 seconds and a temperature of 20-30° C. to remove the phosphosilicate glass and impurity layer on the surface of the silicon wafer.

7. The method for improving the blackening of the nanoscale fine textured surface of the perovskite silicon bottom cell according to claim 5, characterized in that: The cleaning solution for cleaning the residual cleaning liquid on the surface of the silicon wafer is specifically placed in pure water mixed with a second ion exchange resin, with a cleaning time of 60-120 seconds and a temperature of 20-30°C, which simultaneously removes residual anions and cations while improving purity and adsorbing hydrophobic organic matter.

8. The method for improving the blackening of the nanoscale fine textured surface of the perovskite silicon bottom cell according to claim 1, characterized in that: After the microporous array is prepared, the steps of cleaning, high-temperature phosphorus diffusion deep treatment, overall plasma discharge etching and ion exchange resin adsorption are further included.

9. The method for improving the blackening of the nanoscale fine textured surface of the perovskite silicon bottom cell according to claim 1, characterized in that: The silicon wafer texture surface has a size of 100-900 nm and a depth of 100-900 nm.

10. A perovskite crystalline silicon bottom cell, characterized in that: It is prepared by using a method for improving the blackening of nanoscale small velvet surface PL of perovskite crystalline silicon bottom cells according to any one of claims 1 to 9.

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