Thermal mitigation system and method for multi-core processor

Abstract

A system for performing thermal mitigation in a multi-core processor determines which processing core of the processor causes a temperature rise to an undesired level, and then performs one or more thermal mitigation steps only in the responsible core to avoid degrading performance of other cores. The system monitors digital activity (DA) of a pipeline phase of the core, determines when the DA of a processing phase has raised temperature to a certain level, and then reduces the DA of at least one processing phase of the responsible core in order to reduce temperature. The system may also take one or more other thermal mitigation steps based on the monitored temperature values, such as reducing clock frequency or selecting different V / F angles for the core of responsibility.

Description

[0001] Related technical description

[0002] A computing device may include multiple processor-based subsystems. Such a computing device may be, for example, a portable computing device ("PCD") such as a laptop or palmtop computer, a cellular phone or smartphone, a portable digital assistant, a portable game console, or the like. Still other types of PCDs may be included in automotive and Internet of Things ("IoT") applications.

[0003] Multiple subsystems may be included within the same integrated circuit chip or in different chips. A "system on a chip" or "SoC" is an example of such a chip that integrates numerous components to provide system-level functionality. For example, an SoC may include one or more types of processors, such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a digital signal processor ("DSP"), and a neural processing unit ("NPU"). An SoC may include other subsystems, such as a transceiver or "modem" subsystem that provides wireless connectivity, a memory subsystem, and the like.

[0004] For example, processors in SoCs, such as CPUs, GPUs, and DSPs, sometimes experience temperature increases due to external environmental factors and / or internal factors. Current SoCs employ one or more temperature sensors that sense temperature and output a temperature value. Thermal management circuitry employed in the SoC processes the temperature value and performs thermal mitigation procedures to mitigate these temperature increases.

[0005] Current CPUs and GPUs in SoCs are typically multi-core processors with thermal management circuitry that performs this type of thermal mitigation process. Thermal mitigation becomes necessary when a device begins to overheat. As algorithm complexity, system core frequencies, and integration levels continue to increase, and as package and form factor sizes decrease, thermal mitigation becomes increasingly important. Summary of the Invention

[0006] Systems, methods, and other examples are disclosed for performing thermal mitigation in a multi-core processor.

[0007] An exemplary embodiment of the method includes generating at least a first set of digital activity (DA) values ​​and a second set of DA values, respectively, using at least a first digital activity (DA) sensor and a second digital activity (DA) sensor disposed in a first processing core and a second processing core of a multi-core processor. The exemplary method may also include receiving the first set of DA values ​​and the second set of DA values ​​in a processing unit, and processing the first set of DA values ​​and the second set of DA values ​​in the processing unit to determine whether at least one of the DA values ​​exceeds a DA threshold (TH) value. The exemplary method may also include, upon determining that a DA value exceeds the DA TH value, reducing the digital activity of at least one processing stage of one of the first processing core and the second processing core, the at least one processing stage being associated with the DA value that exceeds the DA TH value.

[0008] An exemplary embodiment of the system includes a first DA sensor and a second DA sensor, the first DA sensor and the second DA sensor being disposed in a first processing core and a second processing core of a multi-core processor, respectively, the first DA sensor and the second DA sensor being configured to generate a first set of DA values ​​and a second set of DA values, respectively. The system may also include processing circuitry configured to receive the first set of DA values ​​and the second set of DA values, and process the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds a DATH value. The processing circuitry may also be configured to, if a DA value is determined to exceed the DATH value, reduce the digital activity of at least one processing stage of at least one of the first processing core and the second processing core, the at least one processing stage being associated with the DA value that exceeds the DATH value.

[0009] An exemplary embodiment of a computer-readable medium includes computer instructions for execution by processing circuitry of a multi-core processor to perform thermal mitigation in the multi-core processor. The computer instructions may include a first set of computer instructions for receiving at least a first set of DA values ​​and a second set of DA values ​​generated by a first DA sensor and a second DA sensor, respectively, disposed in a first processing core and a second processing core of the multi-core processor. The computer-readable medium may also include a second set of instructions for processing the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds a DATH value. The computer-readable medium may also include a third set of computer instructions for execution by the processing circuitry if it is determined that at least one of the DA values ​​exceeds the DATH value. Executing the third set of instructions reduces the digital activity of at least one processing stage of at least one of the first processing core and the second processing core, the at least one processing stage being associated with the DA value exceeding the DATH value.

[0010] Another exemplary embodiment of the system may include means for receiving at least a first set of DA values ​​and a second set of DA values ​​generated by first and second DA sensors disposed in first and second processing cores, respectively, of the multi-core processor. The system may also include means for processing the first and second sets of DA values ​​to determine whether at least one of the DA values ​​exceeds a DA TH value. The system may also include means for reducing the digital activity of at least one processing stage of at least one of the first and second processing cores if it is determined that at least one of the DA values ​​exceeds the DA TH value.

[0011] These and other features and advantages will become apparent from the following description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with alphabetic designations, such as "101a" or "101b," the alphabetic designations may distinguish between two similar parts or elements in the same figure. When the intention is for a reference numeral to encompass all parts having the same reference numeral in all figures, the alphabetic designation may be omitted.

[0013] Figure 1 is a block diagram of a system for performing thermal mitigation in a multi-core processor according to an exemplary embodiment.

[0014] Figure 2 is a block diagram of another system for performing thermal mitigation in a multi-core processor according to an exemplary embodiment.

[0015] Figure 3 is a flowchart illustrating a method for performing thermal mitigation in a multi-core processor according to an exemplary embodiment.

[0016] Figure 4 is a flow chart illustrating another method for performing thermal mitigation in a multi-core processor according to an exemplary embodiment.

[0017] Figure 5 is a flow chart illustrating another method for performing thermal mitigation in a multi-core processor according to an exemplary embodiment.

[0018] Figure 6 is a block diagram of a system for performing thermal mitigation in a multi-core processor according to an exemplary embodiment.

[0019] Figure 7 is a block diagram of a PCD including a system on a chip (SoC) according to an exemplary embodiment, which may be incorporated into Figure 1 、 Figure 2 and Figure 6 A system is shown for performing thermal mitigation in a multi-core processor. DETAILED DESCRIPTION

[0020] The present disclosure discloses a system and method for performing thermal mitigation in a multi-core processor by determining which processing core of the multi-core processor is causing the processor's temperature to rise to an undesirable level, and then performing one or more thermal mitigation steps only in the responsible core to avoid degrading the performance of other cores. The system and method may include monitoring digital activity in processing stages of the cores and, if the monitored digital activity exceeds a specific digital activity level, reducing the digital activity of at least one stage of at least one of the cores.

[0021] In the following detailed description, exemplary or representative embodiments of the disclosure details are set forth for the purpose of explanation rather than limitation, so as to provide a thorough understanding of the embodiments according to the present teachings. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". The word "exemplary" may be used synonymously with "exemplary" herein. Any aspect described herein as "exemplary" is not necessarily to be construed as being preferred or having advantages over other aspects. However, it will be apparent to those skilled in the art who benefit from this disclosure that other embodiments according to the present teachings that depart from the specific details disclosed herein are still within the scope of the appended claims. In addition, descriptions of well-known devices and methods may be omitted so as not to obscure the description of the example embodiments. Such methods and devices are clearly within the scope of the present teachings.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. The defined terms are in addition to the technical and scientific meanings of the defined terms as commonly understood and accepted in the art to which the present teachings pertain.

[0023] As used in the specification and the appended claims, the terms "a," "an," and "the" include both singular and plural referents unless the context clearly dictates otherwise. Thus, for example, "a device" includes one device and a plurality of devices.

[0024] Relative terms may be used to describe the relationship of various elements to each other as illustrated in the figures. These relative terms are intended to encompass different orientations of the device and / or elements in addition to the orientation depicted in the figures.

[0025] It will be understood that when an element is described as being “connected to”, “coupled to” or “electrically coupled to” another element, the elements can be directly connected or coupled or intervening elements may be present.

[0026] As used herein, the term "memory" or "memory device" is intended to refer to a non-transitory computer-readable storage medium capable of storing computer instructions or computer code for execution by one or more processors. References to "memory" or "memory device" herein should be interpreted as referring to one or more memories or multiple memory devices. For example, a memory may be multiple memories within the same computer system. A memory may also be multiple memories distributed across multiple computer systems or computing devices.

[0027] As used herein, the term "processor" encompasses an electronic component capable of executing a computer program or executable computer instructions. References herein to a computer comprising a "processor" should be interpreted as referring to one or more processors. A processor may, for example, be a multi-core processor comprising multiple processing cores, each of which may include multiple processing stages of a processing pipeline. A processor may also refer to a collection of processors within a single computer system or distributed across multiple computer systems.

[0028] A computing device may include multiple subsystems, cores, or other components. Such a computing device may be, for example, a PCD such as a laptop or palmtop computer, a cellular phone or smartphone, a portable digital assistant, a portable game console, an automotive safety system for an autonomous vehicle, or the like.

[0029] Currently used thermal mitigation schemes may adversely impact overall performance. In one specific implementation of a SoC used in a PCD, a first-order temperature threshold (TH) value and a second-order temperature threshold (TH) value are employed in a first-order thermal emergency management circuit and a second-order thermal emergency management circuit, respectively, for processing sensed temperature values. The first-order thermal emergency mitigation circuit is configured to ensure that the SoC makes intelligent decisions to achieve a good trade-off between dynamic power (and therefore temperature) and performance. The second-order thermal emergency circuit does not take performance into account because the SoC is operating at its thermal design point (TDP) and it is critical to immediately reduce the heat flux.

[0030] The first-order TH value and the second-order TH value are typically programmed to 102 degrees Celsius (°C) and 95°C, respectively. In the event that the sensed temperature exceeds the second-order TH value, the thermal emergency mitigation circuit reduces the voltage / frequency (V / F) angle used by the processor in an attempt to reduce the temperature below the second-order TH value. In the event that reducing the V / F angle is insufficient to alleviate the temperature increase and the temperature continues to rise until it exceeds the first-order TH value, the thermal emergency mitigation circuit reduces the frequency of the processor by half (F / 2) until the temperature drops below the first-order TH value, and then restores the original frequency.

[0031] The SoC typically implements an operating point plan (OPP) based on the relationship between supply voltage and operating frequency, as defined by a V / F curve. High-level software running on the SoC votes on one of several V / F angles based on the current computational load. In typical scenarios where T exceeds the second-order TH value by a preselected ΔT magnitude, a lower V / F angle is used, causing the SoC to operate at a lower frequency and voltage, dynamically reducing power and, therefore, heat flux and temperature.

[0032] The drawback of this type of thermal management solution is that even if the temperature increase can be attributed to as few as a single processing stage on a single core, reducing the F or V / F angle can adversely affect the performance of other processing cores in a multicore processor. In situations where multiple clock domains share the same power rail, it is impossible to uniquely detect which clock domain is causing the rapid increase in thermal envelope temperature. Thermal mitigation is applied to all clock domains belonging to the shared rail, resulting in performance degradation for all cores, even those with moderate loads. As a result, overall performance is adversely affected.

[0033] The present disclosure provides a thermal management solution that overcomes these drawbacks, as will now be referred to. Figures 1 to 7 The exemplary embodiments shown are described.

[0034] Figure 1 is a block diagram of a system 100 according to a representative embodiment that can be embedded in a multi-core processor of the type typically employed in a SoC in a PCD (such as in a CPU, GPU, and DSP), for example, although the principles and concepts of the present invention are not limited to the type of multi-core processor in which the principles and concepts of the present invention are employed. The principles and concepts of the present invention are also not limited to where the system 100 is located. For example, a portion of the system 100 can be embedded within the multi-core processor, and a portion of the system 100 can be external to the multi-core processor, such as in a logic component external to the multi-core processor, but located on the same SoC as the multi-core processor.

[0035] according to Figure 1 In the representative embodiment of the system 100 shown, each core 1021 to 102 M Each core processes stages 1011 to 101 N In addition to its normal logic configuration, it also includes temperature sensors 1031 to 103 N and digital activity (DA) sensors 1041 to 104 N , where N and M are positive integers greater than or equal to 1 and typically greater than or equal to 2. For example, a typical data processing pipeline of a processing core of a multi-core processor includes six processing stages, namely, an instruction fetch unit (IF), a decode unit (DU), a reservation station unit (RSU), an execution unit (EU), a floating point unit (FPU), and a reorder buffer unit (ROBU). For ease of discussion, it will be assumed that cores 1021 to 102 M Each core in includes these six stages, but it should be understood that the principles and concepts of the present invention are applicable to any type of processing pipeline, regardless of the types of stages used in the pipeline.

[0036] Each temperature sensor 1031 to 103 N is configured to sense the corresponding processing stages 1011 to 101N The DA sensors 1041 to 1044 detect the temperature and output corresponding temperature values ​​indicating the corresponding sensed temperature. N is configured to sense the corresponding processing stages 1011 to 101 N The processing cores 1021 to 102 M Each processing core in the embodiment preferably has temperature and DA monitoring circuits 1051 to 105 disposed thereon. M , the temperature and DA monitoring circuit is configured to monitor the temperature of the corresponding sensors 1031 to 103 N and 1041 to 104 N Sensed temperature value and DA value.

[0037] It should be noted that although the temperature and DA monitoring circuits 1051 to 105 M exist Figure 1 are shown as being provided in the corresponding cores 1021 to 102 M However, they can be on the corresponding cores 1020 to 102 N It should also be noted that although each core processes stages 1011 to 101 N exist Figure 1 is shown as having temperature sensors 1031 to 103 N and DA sensors 1041 to 104 N , but each core 1021 to 102 N Core processing stages 1011 to 101 N As few as a single core processing stage in a process may have temperature sensors 1031 to 103 disposed thereon. N A temperature sensor and DA sensors 1041 to 104 N A DA sensor, as will be referred to below Figure 2 For ease of discussion, it will be assumed that each core 1021 to 102 N Each processing stage 1011 to 101 N Having temperature sensors 1031 to 103 disposed thereon N A temperature sensor and DA sensors 1041 to 104 N A DA sensor in the.

[0038] Temperature and DA monitoring circuits 1051 to 105 M From the corresponding core 1021 to 102 M Core processing stages 1011 to 101 NThe temperature value and the DA value are received and forwarded to the temperature and DA processing circuit 110 along with the processing core identifier. The core identifier identifies the processing core 1021 to 102 associated with the temperature value and the DA value. M , and the stage identifier identifies the processing stages 1011 to 101 in which the temperature value and the DA value are sensed. N The temperature and DA processing circuit 110 is configured to process the temperature value, the DA value, and the identifier to generate the thermal mitigation control signals 1111 to 111 M , for controlling the cores 1021 to 102 based on the temperature value and the DA value N Thermal mitigation in, as will be discussed in more detail below.

[0039] Typically, the control signals 1111 to 111 M Causes one or both of the following: (1) Core 1021 to 102 M At least one of the core stages 1011 to 101 N The temperature and DA processing circuit 110 determines that the at least one core causes the temperature to increase to a level exceeding one or more TH values, and (2) the cores 1021 to 102 M At least one of the core stages 1011 to 101 N The reduction of digital activity in at least one of the stages, the temperature and the DA processing circuit 110 determine that the at least one core causes the temperature to rise to a level exceeding one or more TH values. The reduction in clock frequency may adversely affect the performance of all processing cores sharing the same clock domain, and therefore it is preferred to reduce digital activity by throttling instruction execution. This can be done by, for example, inserting idle instructions into the responsible cores 1021 to 102 M Processing stages 1011 to 101 N It can be implemented in any processing stage of the EU stage.

[0040] DA sensors 1041 to 104 N The processing stages 1011 to 101 can be detected in a variety of ways N Digital activities, as will be referred to below Figure 2 One way to evaluate digital activity is to base it on the process of performing the activities described in stages 1011 to 101 N The number and / or type of instructions executed by one or more stages in the N Some stages in the core 1021 to 1022 will be more active in executing instructions than other stages, and the more active a stage is, the more power that stage consumes, and thus the power that stage has on the corresponding core 1021 to 1022. MIn addition, the core 1021 to 102 M An increase in the temperature of one core may cause the adjacent cores 1021 to 102 M The temperature of the DA sensor 1041 to 104 N The level of digital activity is sensed and a corresponding DA value is generated.

[0041] In processing stages 1011 to 101 N The total power dissipated in total It can be expressed as dynamic power usage P dynamic and power leakage P leakage The sum of:

[0042] P total =P dynamic +P leakage

[0043]

[0044] Dynamic power P dynamic The power consumed by switching during instruction execution is usually expressed as αCVdd 2 f, where α is the fraction of the clock period when the gate switches, C is the dynamic capacitance associated with the switching, and f is the period from 1011 to 101 N The clock frequency, and V dd It is stage 1011 to 101 N According to a representative embodiment, the DA sensors 1041 to 104 N Each DA sensor includes a dynamic capacitance sensor and a corresponding DA sensor 104 1 to 104 N Associated corresponding core processing stage 101 1 to 101 N A combination of processing logic.

[0045] A typical CPU instruction set architecture has millions of instructions of various categories, and each category of instructions is used for different purposes throughout the software application. Therefore, the digital activity of these instructions will vary based on which stage of the pipeline they are in and on the DA sensor 104. 1 to 104 N The instruction class varies depending on which other classes of instructions are occupied at other pipeline stages in a given sample window of .

[0046] One of the possible implementation scenarios is that each DA sensor 104 1 to 104 N The processing logic includes programmable energy polynomials, such as for example:

[0047]

[0048] Among them a0, a1, a2...a n is the energy coefficient with weights assigned based on the class of events in the sample window of the processor pipeline, a n is the energy coefficient of the nth class of instruction in the pipeline, and x identifies the stage of the pipeline that includes the instruction. x and a n The value of is programmable and is programmed with a default value that may require pre-processing characterization for optimal DA sensing. The CPU instruction may generate an event at each pipeline stage that is given to the DA sensors 1041 to 104 N The DA sensor uses the programmed energy coefficient and event type to derive the DA value at a given sample window.

[0049] However, it should be noted that other methods of assessing DA can be used for this purpose.

[0050] The dynamic capacitance can be calculated as the polynomial equation set forth above, where the polynomial order and coefficients are weighted by the events generated by the instructions executed in the different stages of the pipeline. As indicated above, the coefficients and order can be programmed or hardwired for custom events. This is a viable low-cost solution for obtaining the dynamic capacitance at runtime, but other solutions are possible. Therefore, the principles and concepts of the present invention are not limited to this solution for obtaining the DA value. In view of this disclosure, it will be apparent to those skilled in the art that many other solutions can be designed for this purpose.

[0051] Generally speaking, and as will be described in more detail below, the temperature and DA processing circuit 110 processes the DA value, the associated temperature value, and the associated core identifier to determine the cores 102 1 to 102 M Which core (and preferably, the stages 1011 to 101 within the core N The temperature and DA processing circuit 110 then generates a signal for controlling the cores 1021 to 102 based on the sensed temperature value and DA value. N Thermal mitigation control signals 1111 to 111 for thermal mitigation in M .

[0052] Figure 2 is a block diagram of a system 200 for managing a plurality of application processing core clusters 1151 to 115 according to a representative embodiment. PThermal mitigation in a multi-core processor of , where P is a positive integer greater than or equal to 1. In this example, two application processing core clusters are shown, namely core cluster 1151 and core cluster 115 P . Figure 2 Also shown is an expanded view of one of the cores 1023 in the core cluster 1151. In this example, each cluster 1151 to 115 P There are four cores 1021 to 1024 , and each core has a known processing pipeline configuration consisting of six processing stages, namely, IFU 1011 , DI 1012 , RSU 1013 , EU 1014 , FPU 1015 , and ROBU 1016 .

[0053] Each cluster 1151 to 115 P Each core 1021 to 1024 also includes temperature and DA monitoring circuits 1051 to 105 M In addition, each cluster 1151 to 115 P Each of the cores 1021-1024 also includes an instance of a throttling circuit 1071-1074. The throttling circuit 1071-1074 performs the function described above of reducing the digital activity of at least the EU stage 1014 of at least one of the cores 1021-1024 that the temperature and DA processing circuit 110 determines is causing the temperature to rise to a level exceeding one or more TH values. The digital activity can be reduced in a variety of ways, such as, for example, by inserting idle instruction cycles into the processing pipeline, which reduces the instructions per cycle in a given sample cycle, thereby reducing dynamic energy and, therefore, reducing temperature.

[0054] according to Figure 2 In the representative embodiment of the system 200 shown, the temperature and DA processing circuit 110 includes a temperature sensing controller 110a, a DA aggregator 110b, P limit managers (LMs) 110c1 to 110c P and thermal mitigation circuit 110d. Clusters 1151 to 115 P The cores 1021 to 1024 of all clusters in the system communicate with the temperature and DA processing circuit 110 via a bus 117 over which temperature and DA values ​​as well as phase and core identifiers are transmitted to the temperature sensing controller 110a and the DA aggregator 110b.

[0055] According to this representative embodiment, LMs 110c1 to 110c P Each LM in the process targets core clusters 1151 to 115 P The corresponding core cluster in the limit management. The following will refer to Figure 3 Describing in more detail, LM 110c1 to 110cP Each LM in the cluster 1151 to 1152 combines the first-order temperature TH value and the second-order temperature TH value with the temperature sensing controller 110a. P The thermal mitigation circuit 110d compares the received temperature value with the core and forwards the result to the thermal mitigation circuit 110d.

[0056] According to the representative embodiment, the DA aggregator 110b determines the maximum DA value for each sample window for each core and forwards the maximum DA value to the LMs 110c1 to 110c P LM 110c1 to 110c P Each LM in the DA TH value is associated with the corresponding cluster 1151 to 115 P The maximum DA value of the core is compared and the result is forwarded to the thermal mitigation circuit 110d. Preferably, the LM 110c1 to 110c P All of the TH values ​​used are programmable to allow them to be set and changed as needed. It is not necessary to have a separate LM, but doing so allows them to be operated in parallel and have one LM per power domain so that the separate LM can have power domain independence.

[0057] Thermal mitigation circuit 110d from LM 110c1 to 110c P The result of the comparison and the core identifier associated with the temperature value and the DA value are received, and the thermal mitigation control signals 1111 to 111 are generated based on the result and the associated core identifier. M Thermal mitigation control signal 1111 to 111 M Control throttle circuits 1071 to 107 M These throttling circuits reduce the cores 1021 to 102 that cause the temperature to rise. M As indicated above, reducing digital activity may mean, for example, reducing digital activity for a single phase, such as the EU phase 1014, since the EU phase is typically the phase where core digital activity is most active.

[0058] Figure 3The flowchart of a method for performing thermal mitigation in a multi-core processor according to a representative embodiment is shown. At least a first temperature sensor and a second temperature sensor are provided in a first processing stage and a second processing stage of a first data processing pipeline and a second data processing pipeline, respectively, of a first processing core and a second processing core, respectively, for sensing a first set of temperature values ​​and a second set of temperature values, respectively, as indicated by block 301. At least a first DA sensor and a second DA sensor are provided in the first data processing stage and the second data processing stage, respectively, for sensing a first set of DA values ​​and a second set of DA values, respectively, as indicated by block 302. First and second temperature and DA monitoring circuits are provided on the first processing core and the second processing core, respectively, for monitoring the first set of temperature and DA values ​​and the second set of temperature and DA values, respectively, and forwarding them to a temperature and DA processing circuit, as indicated by block 303. The first set of temperature and DA values ​​and the second set of temperature and DA values ​​are received and processed in the temperature and DA processing circuit to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core, as indicated by block 304.

[0059] It should be noted that Figure 3 The processes represented by the flowcharts may be modified in various ways, that is, steps not shown may be added, and steps shown may be deleted or modified.

[0060] Figure 4 is a circuit for processing temperature values ​​and DA values ​​in the temperature and DA processing circuit 110 according to a representative embodiment. Figure 3 304 of the flowchart of the method. The temperature value and the DA value are received in the temperature and DA processing circuit 110, as indicated by block 401. The temperature and DA processing circuit 110 compares each temperature value with a first-order TH value to determine whether the temperature value exceeds the first-order temperature TH value, as indicated by block 402. If so, then at block 403 it is determined whether a reduction in clock frequency is considered a good method for mitigating temperature, and if so, block 404 indicates that the temperature and DA value processing circuit 110 generates thermal mitigation control signals 1111 to 111 M The thermal mitigation control signal causes the clock frequency of the core causing the temperature increase to be reduced (eg, to f / 2).

[0061] As indicated above, reducing the clock frequency may not always be enough to alleviate the temperature rise, and in this case, it may be necessary to take other thermal mitigation steps. For example, the clock frequency of the core may have been reduced to a point where performance is impaired but the temperature has not yet significantly decreased. Frame 403 represents a step of determining whether further reducing the clock frequency is still a good method for reducing the temperature. Various factors may be considered when making this determination, such as the number of times the clock frequency has been halved and / or whether the previous reduction in clock frequency has caused a significant decline in temperature. If the temperature rise is caused by external environmental factors, for example, a further reduction in clock frequency may not cause the temperature of the core to drop to the desired level.

[0062] If it is determined at block 403 that reducing the clock frequency of the core is still a good approach, the clock frequency is reduced at block 404, and the process returns to block 402 where it is determined whether the most recent reduction in clock frequency has caused the current temperature value to be below the first-order temperature TH value. If not, the process remains in a loop including blocks 402 to 404 until the current temperature value drops below the first-order temperature TH value, or it is determined at block 403 that further reducing the clock frequency is not a good or feasible solution for reducing the temperature of the core.

[0063] Once it is determined at block 402 that the current temperature value no longer exceeds the first-order temperature TH value or at block 403 that no further reduction in clock frequency should be performed, the process moves to block 405, where it is determined whether the current temperature value exceeds the second-order temperature TH value. If not, no thermal mitigation steps are performed. If so, a determination is made at block 406 whether the core's maximum DA value exceeds the DA TH value. If not, the temperature increase is assumed to be due to the external ambient temperature, and the V / F is reduced, as indicated by block 407. It should be noted that the steps represented by blocks 401, 402, 404, and 407 are currently performed in a known thermal mitigation process, as described above in the background, but the known process does not take digital activity into account when determining whether thermal mitigation steps need to be performed.

[0064] If it is determined at block 406 that the maximum DA value exceeds the DA TH value, the process moves to block 408, which indicates that the thermal mitigation control signals 1111 to 111 d generated by the thermal mitigation circuit 110d of the temperature and DA processing circuit 110 are output. M Make a stage in the stage (for example, Figure 3 The process preferably returns to block 406 to determine whether the recent decrease in digital activity has caused the current maximum DA value to drop below the DA TH value. The loop including blocks 406 and 408 may continue until it is determined at block 406 that the maximum DA value no longer exceeds the DA TH value, or until the process ends, restarts, or returns to Figure 4A preselected number of cycles may be performed before some other step shown.

[0065] It should be noted that Figure 4 The process represented by the flowchart of FIG. 4 may be modified in various ways, i.e., steps not shown may be added, and steps shown may be deleted or modified. For example, in some embodiments, blocks 401 through 405 may be part of some other process or may be deleted, such that the process represented by blocks 406 through 408 is performed as a separate, independent thermal mitigation process. For example, the process including blocks 401 through 405 may be performed as a separate process that triggers execution of the process represented by the loop including blocks 405 through 408 only if the answer to the question posed at blocks 402 or 403 is "no."

[0066] Figure 5 Shown include Figure 4 Flowchart of blocks 407 to 408, which are relabeled as blocks 507 to 508, respectively. Figure 5 The process 500 represented by the flowchart of FIG. 5 may be a stand-alone thermal mitigation process, or it may be combined with the thermal mitigation process described above. Figure 4 For example, for exemplary purposes, the process represented by blocks 401 to 405 is used together. Figure 5 The process of representation will be described as being Figure 6 The illustrated system 600 performs a standalone thermal mitigation process, which may be part of a multi-core processor in a SoC, such as a SoC in a PCD.

[0067] Figure 5 The box 501 shows Figure 6 The processing core stages 6011 to 601 of the system 600 are shown. N DA sensors that generate DA values, these DA values ​​are Figure 6 is received in the processing circuit 610 shown. Figure 6 The processing core stages 6011 to 601 are shown N These can be processing stages on the same core or on different cores. Figure 5 The block 506 represents the Figure 6 The processing circuit 610 performs a process of determining whether one of the DA values ​​exceeds the DA TH value. The DA value compared with the DA TH value may be the maximum DA value determined after the above-described aggregation process, or alternatively, each DA value may be compared with the DA TH value.

[0068] If the processing circuit 610 does not find that the DA value exceeds the DA TH value, this may mean that the higher temperature is due to high ambient temperature. In one embodiment, this may mean that a reduced V / F angle should be used to reduce the temperature, or alternatively, no thermal mitigation is needed, depending on how the process is implemented. If the processing circuit 610 determines that the DA value exceeds the DA TH value, the processing circuit transmits one or more control signals 611 to the stage associated with the DA value, such as Figure 5 As indicated by block 508 of .

[0069] Figure 7 Examples of PCD 700 are illustrated, such as a mobile phone, smart phone, or portable game console (such as an extended reality (XR) device, a virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device), an automotive autonomous driving system, etc., in which exemplary embodiments of systems, methods, computer-readable media, and other examples of providing thermal mitigation solutions according to the principles and concepts of the present invention may be implemented. For clarity, Figure 7 Some interconnects, signals, etc. are not shown.

[0070] PCD 700 may include SoC 702. SoC 702 may include CPU 704, NPU 705, GPU 706, DSP 707, analog signal processor 708, modem / modem subsystem 754, or other processors. CPU 704 may include one or more CPU cores, such as a first CPU core 7041, a second CPU core 7042, and so on to a Mth CPU core 704. M .

[0071] Core 7041 to 704 M You can refer to the above Figure 1 、 Figure 2 and Figure 6 The CPU cores 7041 to 504 are configured in the manner described above to perform the operations described above of the thermal mitigation system and method of the present disclosure. M Also perform other operations of the type they would normally perform in a PCD. Alternatively or in addition, any processor of the processor (such as NPU 705, GPU 706, DSP 707, etc.) may be referred to above. Figure 1 、 Figure 2 and Figure 6 The described manner is configured to perform the above-described operations of the thermal mitigation system and method of the present disclosure.

[0072] A display controller 709 and a touch screen controller 712 may be coupled to the CPU 704. A touch screen display 714 external to the SoC 702 may be coupled to the display controller 710 and the touch screen controller 712. The PCD 700 may further include a video decoder 716 coupled to the CPU 704. A video amplifier 718 may be coupled to the video decoder 716 and the touch screen display 714. A video port 720 may be coupled to the video amplifier 718. A universal serial bus ("USB") controller 722 may also be coupled to the CPU 704, and a USB port 724 may be coupled to the USB controller 722. A subscriber identity module ("SIM") card 726 may also be coupled to the CPU 704.

[0073] One or more memories 728 may be coupled to the CPU 704. The one or more memories 704 may include both volatile memory and non-volatile memory. Examples of volatile memory include static random access memory ("SRAM") and dynamic random access memory ("DRAM"). Such memory may be external to the SoC 702 or internal to the SoC 702. The one or more memories 728 may include local cache memory or system-level cache memory.

[0074] A stereo audio CODEC 734 may be coupled to the analog signal processor 708. Furthermore, an audio amplifier 736 may be coupled to the stereo audio CODEC 734. A first stereo speaker 738 and a second stereo speaker 740 may each be coupled to the audio amplifier 736. Furthermore, a microphone amplifier 742 may be coupled to the stereo audio CODEC 734, and a microphone 744 may be coupled to the microphone amplifier 742. A frequency modulation ("FM") radio tuner 746 may be coupled to the stereo audio CODEC 734. An FM antenna 748 may be coupled to the FM radio tuner 746. Furthermore, stereo headphones 750 may be coupled to the stereo audio CODEC 734. Examples of other devices that may be coupled to the CPU 704 include one or more digital (e.g., CCD or CMOS) cameras 752.

[0075] A modem or RF transceiver 754 may be coupled to the analog signal processor 708 and the CPU 704. An RF switch 756 may be coupled to the RF transceiver 754 and the RF antenna 758. In addition, a keypad 760 and a mono headset 762 with a microphone may be coupled to the analog signal processor 708. M In addition to the thermal sensors in or near the SoC 702, the SoC 702 may also have one or more internal or on-chip thermal sensors 770. A power supply 774 and a PMIC 776 may provide power to the SoC 702.

[0076] The firmware or software may be stored in any of the aforementioned memories, or in local memory directly accessible to the processor hardware on which the software or firmware is executed. Execution of such firmware or software may control aspects of any of the aforementioned methods or configure aspects of any of the aforementioned systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium," as that term is understood in patent dictionaries.

[0077] Specific implementation examples are described in the following numbered clauses.

[0078] 1. A method for performing thermal mitigation in a multi-core processor, the method comprising:

[0079] generating a first set of DA values ​​and a second set of DA values ​​using at least a first digital activity (DA) sensor and a second digital activity (DA) sensor disposed in a first processing core and a second processing core of the multi-core processor, respectively; and

[0080] In the processing circuit, the first set of DA values ​​and the second set of DA values ​​are received and the first set of DA values ​​and the second set of DA values ​​are processed to determine whether at least one of the DA values ​​exceeds a DA threshold (TH) value, wherein upon determining that at least one of the DA values ​​exceeds the DA TH value, the digital activity of at least one processing stage of one of the first processing core and the second processing core is reduced, the at least one processing stage being associated with the DA value that exceeds the DA TH value.

[0081] 2. The method according to clause 1, further comprising:

[0082] generating a first set of temperature values ​​and a second set of temperature values, respectively, using a first temperature sensor and a second temperature sensor disposed in a first processing core and a second processing core of the multi-core processor, respectively;

[0083] In the processing circuitry, the first set of temperature values ​​and the second set of temperature values ​​are received, and the first set of temperatures and the second set of temperatures are processed to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core.

[0084] 3. The method of clause 2, wherein processing the first set of temperature values ​​and the second set of temperature values ​​in the processing circuit comprises:

[0085] Prior to processing, in the processing circuitry, the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds the DA TH value:

[0086] comparing each temperature value with a first-order temperature TH value to determine whether any of the temperature values ​​exceeds the first-order temperature TH value; and

[0087] In a case where it is determined that at least one of the temperature values ​​in the first set of temperature values ​​exceeds the first-order temperature TH value, the clock frequency of the first processing core is reduced, and in a case where it is determined that at least one of the temperature values ​​in the second set of temperature values ​​exceeds the first-order temperature TH value, the clock frequency of the second processing core is reduced.

[0088] 4. The method of clause 3, wherein the processing of the first set of temperature values ​​and DA values ​​and the second set of temperature values ​​and DA values ​​in the processing circuit further comprises:

[0089] Prior to processing said first set of DA values ​​and said second set of DA values ​​to determine whether at least one of said DA values ​​exceeds a DA TH value:

[0090] When it is determined that a certain temperature value does not exceed the first-order temperature TH value compared with the first-order temperature TH value, the temperature value not exceeding the first-order temperature TH value is compared with a second-order temperature TH value smaller than the first-order temperature TH value.

[0091] 5. The method of clause 4, wherein the step of processing the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds a DA TH value comprises:

[0092] aggregating the DA values ​​and determining a first maximum DA value in the first set of DA values ​​and a second maximum DA value in the second set of DA values, respectively;

[0093] comparing the first maximum DA value with the DA TH value if the temperature value belongs to the first set of temperature values ​​and exceeds the second-order temperature TH value compared to the second-order temperature TH value;

[0094] upon determining that the first maximum DA value exceeds the DA TH value, reducing digital activity of at least a first processing stage of the first processing core;

[0095] If the temperature value belongs to the second set of temperature values ​​and exceeds the second-order temperature TH value compared to the second-order temperature TH value, comparing the second maximum DA value with the DA TH value; and

[0096] Upon determining that the second maximum DA value exceeds the DA TH value, the digital activity of at least a second processing stage of the second processing core is reduced.

[0097] 6. A method according to clause 5, wherein the first processing stage of the first processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing the number of instructions per cycle (IPC) executed by the EU processing stage.

[0098] 7. A method according to clause 5, wherein the second processing stage of the second processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing the number of instructions per cycle (IPC) executed by the EU processing stage.

[0099] 8. The method according to any one of clauses 5 to 7, further comprising:

[0100] Upon determining that the first maximum DA value does not exceed the DA TH value, a supply voltage / clock frequency (V / F) angle used by the first processing core is reduced.

[0101] 9. The method according to any one of clauses 5 to 8, further comprising:

[0102] Upon determining that the second maximum DA value does not exceed the DA TH value, a supply voltage / clock frequency (V / F) angle used by the second processing core is reduced.

[0103] 10. The method of any of clauses 1 to 9, wherein the multi-core processor is a multi-core processor of a system-on-chip (SoC) integrated circuit (IC) package of a portable computing device (PCD).

[0104] 11. A system for performing thermal mitigation in a multi-core processor, the system comprising:

[0105] a first digital activity (DA) sensor and a second digital activity (DA) sensor, the first digital activity (DA) sensor and the second digital activity (DA) sensor being disposed in a first processing core and a second processing core of the multi-core processor, respectively, the first digital activity (DA) sensor and the second digital activity (DA) sensor being configured to generate a first set of DA values ​​and a second set of DA values, respectively; and

[0106] processing circuitry configured to receive the first set of DA values ​​and the second set of DA values, and process the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds a DA threshold (TH) value, wherein upon determining that at least one of the DA values ​​exceeds the DA TH value, the processing circuitry is configured to reduce the digital activity of at least one processing stage of at least one of the first processing core and the second processing core, the at least one processing stage being associated with the DA value that exceeds the DA TH value.

[0107] 12. The system of clause 11, further comprising:

[0108] a first temperature sensor and a second temperature sensor, the first temperature sensor and the second temperature sensor being disposed in a first processing core and a second processing core of the multi-core processor, respectively, the first temperature sensor and the second temperature sensor being configured to generate a first set of temperature values ​​and a second set of temperature values, respectively; and

[0109] The processing circuitry is further configured to receive the first set of temperature values ​​and the second set of temperature values, and process the first set of temperatures and the second set of temperatures to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core.

[0110] 13. The system of clause 11 or 12, wherein the processing circuitry is configured to perform the processing of the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core by:

[0111] Prior to processing the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds the DA TH value:

[0112] comparing each temperature value with a first-order temperature TH value to determine whether any of the temperature values ​​exceeds the first-order temperature TH value; and

[0113] In a case where it is determined that at least one of the temperature values ​​in the first set of temperature values ​​exceeds the first-order temperature TH value, the clock frequency of the first processing core is reduced, and in a case where it is determined that at least one of the temperature values ​​in the second set of temperature values ​​exceeds the first-order temperature TH value, the clock frequency of the second processing core is reduced.

[0114] 14. The system of clause 13, wherein the processing circuitry is further configured to perform the processing of the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core by:

[0115] Prior to processing said first set of DA values ​​and said second set of DA values ​​to determine whether at least one of said DA values ​​exceeds a DA TH value:

[0116] When it is determined that a certain temperature value does not exceed the first-order temperature TH value compared with the first-order temperature TH value, the temperature value not exceeding the first-order temperature TH value is compared with a second-order temperature TH value smaller than the first-order temperature TH value.

[0117] 15. The system of clause 14, wherein the processing circuitry is further configured to perform the processing of the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds a DA TH value by:

[0118] aggregating the DA values ​​and determining a first maximum DA value in the first set of DA values ​​and a second maximum DA value in the second set of DA values, respectively;

[0119] comparing the first maximum DA value with the DA TH value if the temperature value belongs to the first set of temperature values ​​and exceeds the second-order temperature TH value compared to the second-order temperature TH value;

[0120] upon determining that the first maximum DA value exceeds the DA TH value, reducing digital activity of at least a first processing stage of the first processing core;

[0121] If the temperature value belongs to the second set of temperature values ​​and exceeds the second-order temperature TH value compared to the second-order temperature TH value, comparing the second maximum DA value with the DA TH value; and

[0122] Upon determining that the second maximum DA value exceeds the DA TH value, the digital activity of at least a second processing stage of the second processing core is reduced.

[0123] 16. A system according to clause 14 or 15, wherein the first processing stage of the first processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing the number of instructions per cycle (IPC) executed by the EU processing stage.

[0124] 17. A system according to any one of clauses 15 to 16, wherein the second processing stage of the second processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing the number of instructions per cycle (IPC) executed by the EU processing stage.

[0125] 18. The system according to any one of claims 15 to 17, wherein the processing circuit is further configured to:

[0126] Upon determining that the first maximum DA value does not exceed the DA TH value, a supply voltage / clock frequency (V / F) angle used by the first processing core is reduced.

[0127] 19. The system of any of clauses 15 to 18, wherein the processing circuit is further configured to:

[0128] Upon determining that the second maximum DA value does not exceed the DA TH value, a supply voltage / clock frequency (V / F) angle used by the second processing core is reduced.

[0129] 20. The system of any of clauses 11 to 19, wherein the multi-core processor is a multi-core processor of a system-on-chip (SoC) integrated circuit (IC) package of a portable computing device (PCD).

[0130] 21. A computer-readable medium comprising computer instructions, the computer instructions being executable by processing circuitry of a multi-core processor for performing thermal mitigation in the multi-core processor, the computer instructions comprising:

[0131] a first set of computer instructions for receiving at least a first set of digital activity (DA) values ​​and a second set of DA values ​​generated by a first digital activity (DA) sensor and a second digital activity (DA) sensor disposed in a first processing core and a second processing core, respectively, of the multi-core processor;

[0132] a second set of instructions for processing the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds a DA threshold (TH) value; and

[0133] a third set of computer instructions for execution by the processing circuitry upon determining that at least one of the DA values ​​exceeds the DA TH value, wherein execution by the third set of instructions reduces the digital activity of at least one processing stage of at least one of the first processing core and the second processing core, the at least one processing stage being associated with the at least one of the DA values ​​that exceeds the DA TH value.

[0134] 22. The computer-readable medium of clause 21, further comprising:

[0135] a fourth set of computer instructions for receiving a first set of temperature values ​​and a second set of temperature values ​​generated by a first temperature sensor and a second temperature sensor, respectively, disposed in a first processing core and a second processing core, respectively, of the multi-core processor; and

[0136] A fifth set of computer instructions for processing the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core.

[0137] 23. The computer-readable medium of clause 22, wherein the fifth set of computer instructions is executed before executing the third set of computer instructions and comprises:

[0138] computer instructions for comparing each temperature value to a first order temperature TH value to determine whether any of the temperature values ​​exceeds the first order temperature TH value;

[0139] computer instructions for reducing the clock frequency of the first processing core if it is determined that at least one of the temperature values ​​in the first set of temperature values ​​exceeds the first order temperature TH value; and

[0140] Computer instructions for reducing a clock frequency of the second processing core if it is determined that at least one of the temperature values ​​in the second set of temperature values ​​exceeds the first order temperature TH value.

[0141] 24. The computer-readable medium of clause 23, wherein the fifth set of computer instructions further comprises:

[0142] Computer instructions for comparing a temperature value not exceeding the first-order temperature TH value with a second-order temperature TH value less than the first-order temperature TH value.

[0143] 25. The computer-readable medium of clause 24, wherein the third set of computer instructions comprises:

[0144] computer instructions for aggregating the DA values ​​and determining a first maximum DA value in the first set of DA values ​​and a second maximum DA value in the second set of DA values, respectively;

[0145] computer instructions for comparing the first maximum DA value to a DA TH value if the temperature value belongs to the first set of temperature values ​​and exceeds the second order temperature TH value compared to the second order temperature TH value;

[0146] computer instructions for reducing digital activity of at least a first processing stage of the first processing core if it is determined that the first maximum DA value exceeds the DA TH value;

[0147] computer instructions for comparing the second maximum DA value to the DA TH value if the temperature value belongs to the second set of temperature values ​​compared to the second order temperature TH value and exceeds the second order temperature TH value; and

[0148] Computer instructions for reducing the digital activity of at least a second processing stage of the second processing core if it is determined that the second maximum DA value exceeds the DA TH value.

[0149] 26. A system for performing thermal mitigation in a multi-core processor, the system comprising:

[0150] means for receiving at least a first set of digital activity (DA) values ​​and a second set of DA values ​​generated by a first digital activity (DA) sensor and a second digital activity (DA) sensor disposed in a first processing core and a second processing core, respectively, of the multi-core processor;

[0151] means for processing said first set of DA values ​​and said second set of DA values ​​to determine whether at least one of said DA values ​​exceeds a DA threshold (TH) value; and

[0152] means for reducing the digital activity of at least one processing stage of at least one of the first processing core and the second processing core upon determining that at least one of the DA values ​​exceeds the DA TH value, the at least one processing stage being associated with the at least one of the DA values ​​that exceeds the DA TH value.

[0153] 27. The system according to clause 26, further comprising:

[0154] means for receiving a first set of temperature values ​​and a second set of temperature values ​​generated by a first temperature sensor and a second temperature sensor, respectively, disposed in a first processing core and a second processing core of the multi-core processor; and

[0155] Means for processing the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core.

[0156] 28. The system of clause 27, wherein the means for processing the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core comprises:

[0157] means for comparing each temperature value with a first-order temperature TH value to determine whether any of the temperature values ​​exceeds the first-order temperature TH value;

[0158] means for reducing the clock frequency of the first processing core if it is determined that at least one of the temperature values ​​of the first set of temperature values ​​exceeds the first order temperature TH value; and

[0159] Means for reducing the clock frequency of the second processing core if it is determined that at least one of the temperature values ​​in the second set of temperature values ​​exceeds the first order temperature TH value.

[0160] 29. The system of clause 28, wherein the means for processing the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core further comprises:

[0161] A component for comparing a temperature value not exceeding the first-order temperature TH value with a second-order temperature TH value less than the first-order temperature TH value.

[0162] 30. The system of any of clause 29, wherein the means for processing the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds a DA TH value and the means for reducing the digital activity of at least one processing stage of at least one of the first processing core and the second processing core comprises:

[0163] means for aggregating said DA values ​​and determining a first maximum DA value in said first set of DA values ​​and a second maximum DA value in said second set of DA values, respectively;

[0164] means for comparing the first maximum DA value with a DA TH value if the temperature value belongs to the first set of temperature values ​​and exceeds the second order temperature TH value compared to the second order temperature TH value;

[0165] component computer instructions for reducing digital activity of at least a first processing stage of the first processing core if it is determined that the first maximum DA value exceeds the DA TH value;

[0166] means for comparing the second maximum DA value with the DA TH value if the temperature value belongs to the second set of temperature values ​​and exceeds the second order temperature TH value compared to the second order temperature TH value; and

[0167] Means for reducing the digital activity of at least a second processing stage of the second processing core if it is determined that the second maximum DA value exceeds the DA TH value.

[0168] Alternative embodiments will become apparent to those skilled in the art.Thus, while selected aspects have been illustrated and described in detail, it should be understood that various substitutions and changes can be made therein.

Claims

1. A method for performing thermal mitigation in a multi-core processor, the method comprising: generating a first set of DA values ​​and a second set of DA values ​​using at least a first digital activity (DA) sensor and a second digital activity (DA) sensor disposed in a first processing core and a second processing core of the multi-core processor, respectively; as well as In the processing circuit, the first set of DA values ​​and the second set of DA values ​​are received and the first set of DA values ​​and the second set of DA values ​​are processed to determine whether at least one of the DA values ​​exceeds a DA threshold (TH) value, wherein upon determining that at least one of the DA values ​​exceeds the DA TH value, the digital activity of at least one processing stage of one of the first processing core and the second processing core is reduced, the at least one processing stage being associated with the DA value that exceeds the DA TH value.

2. The method according to claim 1, further comprising: generating a first set of temperature values ​​and a second set of temperature values, respectively, using a first temperature sensor and a second temperature sensor disposed in a first processing core and a second processing core of the multi-core processor, respectively; In the processing circuitry, the first set of temperature values ​​and the second set of temperature values ​​are received and the first set of temperatures and the second set of temperatures are processed to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core.

3. The method of claim 2 , wherein the processing of the first set of temperature values ​​and the second set of temperature values ​​in the processing circuit comprises: Prior to processing, in the processing circuitry, the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds the DA TH value: comparing each temperature value with a first-order temperature TH value to determine whether any of the temperature values ​​exceeds the first-order temperature TH value; as well as In a case where it is determined that at least one of the temperature values ​​in the first set of temperature values ​​exceeds the first-order temperature TH value, the clock frequency of the first processing core is reduced, and in a case where it is determined that at least one of the temperature values ​​in the second set of temperature values ​​exceeds the first-order temperature TH value, the clock frequency of the second processing core is reduced.

4. The method of claim 3 , wherein the processing of the first set of temperature values ​​and DA values ​​and the second set of temperature values ​​and DA values ​​in the processing circuit further comprises: Prior to processing said first set of DA values ​​and said second set of DA values ​​to determine whether at least one of said DA values ​​exceeds a DA TH value: When it is determined that a certain temperature value does not exceed the first-order temperature TH value compared with the first-order temperature TH value, the temperature value not exceeding the first-order temperature TH value is compared with a second-order temperature TH value smaller than the first-order temperature TH value.

5. The method of claim 4 , wherein the processing of the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds the DA TH value comprises: aggregating the DA values ​​and determining a first maximum DA value in the first set of DA values ​​and a second maximum DA value in the second set of DA values, respectively; comparing the first maximum DA value with the DA TH value if the temperature value belongs to the first set of temperature values ​​and exceeds the second-order temperature TH value compared to the second-order temperature TH value; upon determining that the first maximum DA value exceeds the DA TH value, reducing digital activity of at least a first processing stage of the first processing core; if the temperature value belongs to the second set of temperature values ​​and exceeds the second-order temperature TH value compared to the second-order temperature TH value, comparing the second maximum DA value with the DA TH value; as well as Upon determining that the second maximum DA value exceeds the DA TH value, the digital activity of at least a second processing stage of the second processing core is reduced.

6. The method of claim 5 , wherein the first processing stage of the first processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing a number of instructions per cycle (IPC) executed by the EU processing stage.

7. The method of claim 5 , wherein the second processing stage of the second processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing a number of instructions per cycle (IPC) executed by the EU processing stage.

8. The method according to claim 5, further comprising: Upon determining that the first maximum DA value does not exceed the DA TH value, a supply voltage / clock frequency (V / F) angle used by the first processing core is reduced.

9. The method according to claim 8, further comprising: Upon determining that the second maximum DA value does not exceed the DA TH value, a supply voltage / clock frequency (V / F) angle used by the second processing core is reduced.

10. The method of claim 1, wherein the multi-core processor is a multi-core processor of a system-on-chip (SoC) integrated circuit (IC) package of a portable computing device (PCD).

11. A system for performing thermal mitigation in a multi-core processor, the system comprising: a first digital activity (DA) sensor and a second digital activity (DA) sensor, the first digital activity (DA) sensor and the second digital activity (DA) sensor being disposed in a first processing core and a second processing core of the multi-core processor, respectively, the first digital activity (DA) sensor and the second digital activity (DA) sensor being configured to generate a first set of DA values ​​and a second set of DA values, respectively; and processing circuitry configured to receive the first set of DA values ​​and the second set of DA values, and process the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds a DA threshold (TH) value, wherein upon determining that at least one of the DA values ​​exceeds the DA TH value, the processing circuitry is configured to reduce the digital activity of at least one processing stage of at least one of the first processing core and the second processing core, the at least one processing stage being associated with the DA value that exceeds the DA TH value.

12. The system according to claim 11, further comprising: a first temperature sensor and a second temperature sensor, the first temperature sensor and the second temperature sensor being respectively disposed in the first processing core and the second processing core of the multi-core processor, the first temperature sensor and the second temperature sensor being configured to generate a first set of temperature values ​​and a second set of temperature values, respectively, and wherein the processing circuit is further configured to receive the first set of temperature values ​​and the second set of temperature values, and process the first set of temperatures and the second set of temperatures to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core.

13. The system of claim 12 , wherein the processing circuitry is configured to perform the processing of the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core by: Prior to processing the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds the DA TH value: comparing each temperature value with a first-order temperature TH value to determine whether any of the temperature values ​​exceeds the first-order temperature TH value; and In a case where it is determined that at least one of the temperature values ​​in the first set of temperature values ​​exceeds the first-order temperature TH value, the clock frequency of the first processing core is reduced, and in a case where it is determined that at least one of the temperature values ​​in the second set of temperature values ​​exceeds the first-order temperature TH value, the clock frequency of the second processing core is reduced.

14. The system of claim 13 , wherein the processing circuitry is further configured to perform the processing of the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core by: Prior to processing said first set of DA values ​​and said second set of DA values ​​to determine whether at least one of said DA values ​​exceeds a DA TH value: When it is determined that a certain temperature value does not exceed the first-order temperature TH value compared with the first-order temperature TH value, the temperature value not exceeding the first-order temperature TH value is compared with a second-order temperature TH value smaller than the first-order temperature TH value.

15. The system of claim 14 , wherein the processing circuit is further configured to perform the processing of the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds a DA TH value by: aggregating the DA values ​​and determining a first maximum DA value in the first set of DA values ​​and a second maximum DA value in the second set of DA values, respectively; comparing the first maximum DA value with the DA TH value if the temperature value belongs to the first set of temperature values ​​and exceeds the second-order temperature TH value compared to the second-order temperature TH value; upon determining that the first maximum DA value exceeds the DA TH value, reducing digital activity of at least a first processing stage of the first processing core; if the temperature value belongs to the second set of temperature values ​​and exceeds the second-order temperature TH value compared to the second-order temperature TH value, comparing the second maximum DA value with the DA TH value; as well as Upon determining that the second maximum DA value exceeds the DA TH value, the digital activity of at least a second processing stage of the second processing core is reduced.

16. The system of claim 15, wherein the first processing stage of the first processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing a number of instructions per cycle (IPC) executed by the EU processing stage.

17. The system of claim 15, wherein the second processing stage of the second processing core is an execution unit (EU) processing stage, and wherein the digital activity of the EU processing stage is reduced by reducing a number of instructions per cycle (IPC) executed by the EU processing stage.

18. The system of claim 15, wherein the processing circuit is further configured to: Upon determining that the first maximum DA value does not exceed the DA TH value, a supply voltage / clock frequency (V / F) angle used by the first processing core is reduced.

19. The system of claim 18, wherein the processing circuit is further configured to: Upon determining that the second maximum DA value does not exceed the DA TH value, a supply voltage / clock frequency (V / F) angle used by the second processing core is reduced.

20. The system of claim 11, wherein the multi-core processor is a multi-core processor of a system-on-chip (SoC) integrated circuit (IC) package of a portable computing device (PCD).

21. A non-transitory computer-readable medium comprising computer instructions, the computer instructions being executable by processing circuitry of a multi-core processor for performing thermal mitigation in the multi-core processor, the computer instructions comprising: a first set of computer instructions for receiving at least a first set of digital activity (DA) values ​​and a second set of DA values ​​generated by a first digital activity (DA) sensor and a second digital activity (DA) sensor disposed in a first processing core and a second processing core, respectively, of the multi-core processor; a second set of instructions for processing the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds a DA threshold (TH) value; and a third set of computer instructions for execution by the processing circuitry upon determining that at least one of the DA values ​​exceeds the DA TH value, wherein execution by the third set of instructions reduces the digital activity of at least one processing stage of at least one of the first processing core and the second processing core, the at least one processing stage being associated with the at least one of the DA values ​​that exceeds the DA TH value.

22. The computer-readable medium of claim 21 , further comprising: a fourth set of computer instructions for receiving a first set of temperature values ​​and a second set of temperature values ​​generated by a first temperature sensor and a second temperature sensor, respectively, disposed in the first processing core and the second processing core of the multi-core processor; and A fifth set of computer instructions for processing the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core.

23. The computer-readable medium of claim 22, wherein the fifth set of computer instructions is executed before executing the third set of computer instructions and comprises: computer instructions for comparing each temperature value to a first order temperature TH value to determine whether any of the temperature values ​​exceeds the first order temperature TH value; computer instructions for reducing a clock frequency of the first processing core if it is determined that at least one of the temperature values ​​in the first set of temperature values ​​exceeds the first order temperature TH value; and Computer instructions for reducing a clock frequency of the second processing core if it is determined that at least one of the temperature values ​​in the second set of temperature values ​​exceeds the first order temperature TH value.

24. The computer-readable medium of claim 23, wherein the fifth set of computer instructions further comprises: Computer instructions for comparing a temperature value not exceeding the first-order temperature TH value with a second-order temperature TH value less than the first-order temperature TH value.

25. The computer-readable medium of claim 24, wherein the third set of computer instructions comprises: computer instructions for aggregating the DA values ​​and determining a first maximum DA value in the first set of DA values ​​and a second maximum DA value in the second set of DA values, respectively; computer instructions for comparing the first maximum DA value to a DA TH value if the temperature value belongs to the first set of temperature values ​​and exceeds the second order temperature TH value compared to the second order temperature TH value; computer instructions for reducing digital activity of at least a first processing stage of the first processing core if it is determined that the first maximum DA value exceeds the DA TH value; computer instructions for comparing the second maximum DA value to the DA TH value if the temperature value belongs to the second set of temperature values ​​compared to the second order temperature TH value and exceeds the second order temperature TH value; and Computer instructions for reducing the digital activity of at least a second processing stage of the second processing core if it is determined that the second maximum DA value exceeds the DA TH value.

26. A system for performing thermal mitigation in a multi-core processor, the system comprising: means for receiving at least a first set of digital activity (DA) values ​​and a second set of DA values ​​generated by a first digital activity (DA) sensor and a second digital activity (DA) sensor disposed in a first processing core and a second processing core, respectively, of the multi-core processor; means for processing said first set of DA values ​​and said second set of DA values ​​to determine whether at least one of said DA values ​​exceeds a DA threshold (TH) value; and means for reducing the digital activity of at least one processing stage of at least one of the first processing core and the second processing core upon determining that at least one of the DA values ​​exceeds the DA TH value, the at least one processing stage being associated with the at least one of the DA values ​​that exceeds the DA TH value.

27. The system of claim 26, further comprising: means for receiving a first set of temperature values ​​and a second set of temperature values ​​generated by a first temperature sensor and a second temperature sensor, respectively, disposed in the first processing core and the second processing core of the multi-core processor; and Means for processing the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core.

28. The system of claim 27, wherein the means for processing the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core comprises: means for comparing each temperature value with a first-order temperature TH value to determine whether any of the temperature values ​​exceeds the first-order temperature TH value; means for reducing a clock frequency of the first processing core if it is determined that at least one of the temperature values ​​of the first set of temperature values ​​exceeds the first-order temperature TH value; and Means for reducing the clock frequency of the second processing core if it is determined that at least one of the temperature values ​​in the second set of temperature values ​​exceeds the first order temperature TH value.

29. The system of claim 28, wherein the means for processing the first set of temperature values ​​and the second set of temperature values ​​to determine whether one or more thermal mitigation steps need to be performed in at least one of the first processing core and the second processing core further comprises: A component for comparing a temperature value not exceeding the first-order temperature TH value with a second-order temperature TH value less than the first-order temperature TH value.

30. The system of claim 29, wherein the means for processing the first set of DA values ​​and the second set of DA values ​​to determine whether at least one of the DA values ​​exceeds the DA TH value and the means for reducing the digital activity of at least one processing stage of at least one of the first processing core and the second processing core comprises: means for aggregating said DA values ​​and determining a first maximum DA value in said first set of DA values ​​and a second maximum DA value in said second set of DA values, respectively; means for comparing the first maximum DA value with a DA TH value if the temperature value belongs to the first set of temperature values ​​and exceeds the second order temperature TH value compared to the second order temperature TH value; component computer instructions for reducing digital activity of at least a first processing stage of the first processing core if it is determined that the first maximum DA value exceeds the DA TH value; means for comparing the second maximum DA value with the DA TH value if the temperature value belongs to the second set of temperature values ​​and exceeds the second order temperature TH value compared to the second order temperature TH value; and Means for reducing the digital activity of at least a second processing stage of the second processing core if it is determined that the second maximum DA value exceeds the DA TH value.

Images