Resistance change type non-volatile memory device and method for driving resistance change type non-volatile memory element

Abstract

A resistance change type non-volatile memory device (10a) is provided with a memory cell (20) and a heater (30) thermally coupled to the memory cell (20), the memory cell (20) and the heater (30) being capable of operating independently. The memory cell (20) has a first electrode layer (21), a second electrode layer (22), and a variable resistance layer (23) sandwiched between the first electrode layer (21) and the second electrode layer (22). The heater (30) has a heating element (31), and a third terminal (32) and a fourth terminal (33) connected to the heating element (31).

Description

Technical Field

[0001] The present disclosure relates to a variable resistance nonvolatile memory device and a method for driving a variable resistance nonvolatile memory element, and in particular to a variable resistance nonvolatile memory device capable of suppressing degradation of retention. Background Art

[0002] Conventionally, a technology for improving the retention characteristics of a resistance variable nonvolatile memory device (hereinafter also referred to as "ReRAM (Resistive Random Access Memory)") has been proposed (see Patent Document 1).

[0003] In the technology of Patent Document 1, in the first write process, before applying a first write pulse to a variable resistance nonvolatile memory element (hereinafter also referred to as a "memory cell"), a first pulse of the same polarity and shorter pulse width as the first write pulse and a second pulse of the same polarity and opposite polarity to the first write pulse are sequentially applied. This ensures a memory window in the ReRAM and improves on-state retention characteristics.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-4579 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] However, in the technique of Patent Document 1, in addition to the original write pulse (i.e., the first write pulse), additional pulses (i.e., the first pulse and the second pulse) are applied to the memory cell during the first write process. This poses a problem of potentially degrading the endurance (i.e., rewrite resistance) characteristics. In other words, the endurance characteristics are sacrificed.

[0009] Therefore, an object of the present disclosure is to provide a variable resistance nonvolatile memory device and a method for driving a variable resistance nonvolatile memory element that can suppress degradation of retention without increasing the number of write operations.

[0010] Means for solving problems

[0011] In order to achieve the above-mentioned purpose, a resistance-variable non-volatile memory device of one embodiment of the present invention is characterized in that it comprises: a resistance-variable non-volatile memory element having a first electrode layer, a second electrode layer, a resistance-variable layer sandwiched by the first electrode layer and the second electrode layer, a first terminal connected to the first electrode layer, and a second terminal connected to the second electrode layer; and a heater having a heating element and a third terminal and a fourth terminal connected to the heating element; the resistance-variable non-volatile memory element and the heater are capable of operating independently and being thermally coupled.

[0012] In order to achieve the above-mentioned purpose, a driving method of a resistance-variable non-volatile memory element in one embodiment of the present invention is a driving method of a resistance-variable non-volatile memory element capable of obtaining a high resistance state and a low resistance state, including: a high resistance step of driving the resistance-variable non-volatile memory element so that the resistance-variable non-volatile memory element becomes a high resistance state; a low resistance step of driving the resistance-variable non-volatile memory element so that the resistance-variable non-volatile memory element becomes a low resistance state; and a heating step of driving a heater thermally coupled to the resistance-variable non-volatile memory element at any time selected for the resistance-variable non-volatile memory element for the high resistance step.

[0013] Effects of the Invention

[0014] According to the present disclosure, a variable resistance nonvolatile memory device and a method for driving a variable resistance nonvolatile memory element are provided, which are capable of suppressing degradation of retention without increasing the number of write operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A This is a schematic diagram showing a first structural example of a variable resistance nonvolatile memory device according to an embodiment.

[0016] Figure 1B This is a schematic diagram showing a second structural example of the resistance variable nonvolatile memory device according to the embodiment.

[0017] Figure 1C This is a schematic diagram showing a third structural example of the resistance variable nonvolatile memory device according to the embodiment.

[0018] Figure 2 A diagram showing a circuit configuration example of a variable resistance nonvolatile memory device according to an embodiment.

[0019] Figure 3 This is a timing chart showing a method for driving a memory cell according to an embodiment.

[0020] Figure 4AThis is a graph showing the retention characteristics of a memory cell after a cycle test was performed in which conventional writing to a high resistance state and writing to a low resistance state were repeated without performing “heat application” (wherein the writing current was 125 μA).

[0021] Figure 4B This is a graph showing the retention characteristics of a memory cell after a cycle test in which conventional writing to a high resistance state and writing to a low resistance state (wherein the writing current is 75 μA) without performing “heat application” are repeated.

[0022] Figure 4C 1 is a graph showing the retention characteristics of a memory cell after a cycle test was performed in which writing to a high resistance state and writing to a low resistance state (wherein the writing current was 75 μA) of an embodiment including “heat application” were repeated.

[0023] Figure 5 This is a diagram illustrating the features of the memory cell driving method according to the embodiment, in comparison with conventional methods.

[0024] Figure 6 This diagram explains a phenomenon that occurs when a cell current in a high-resistance state is reduced by a conventional method of increasing an applied voltage during an erase operation, by comparing the embodiment with the conventional method.

[0025] Figure 7 It is an explanation Figure 5 and Figure 6 Schematic diagram of the memory cell structure showing the mechanism of cell current transition.

[0026] Figure 8A This is a timing chart showing a method of driving a memory cell according to a first modification of the embodiment.

[0027] Figure 8B 1 is a timing chart showing a method of driving a memory cell according to a second modification of the embodiment. DETAILED DESCRIPTION

[0028] Hereinafter, the embodiments of the present disclosure will be described in detail using the accompanying drawings. In addition, the embodiments described below each represent a specific example of the present disclosure. The numerical values, shapes, materials, constituent elements, configuration positions of constituent elements, and connection methods, action timing, steps, order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. In addition, the figures are not necessarily strictly illustrated. In each figure, substantially the same structure is marked with the same figure mark, and repeated descriptions are omitted or simplified. In addition, "A and B are connected" means that A and B are electrically connected, including not only the case where A and B are directly connected, but also the case where A and B are indirectly connected in a state where other circuit elements are interposed between A and B. In addition, "up" and "down" are relative directions in the illustrated state, and do not represent the relationship with the vertical direction.

[0029] Figure 1A : is a schematic diagram showing a first structural example of a variable resistance nonvolatile memory device 10a according to an embodiment. More specifically, Figure 1A (a) is a cross-sectional view of the resistance variable nonvolatile memory device 10a. Figure 1A (b) is a top view of the resistance variable nonvolatile memory device 10a.

[0030] The variable resistance nonvolatile memory device 10a is a single-chip semiconductor ReRAM, characterized by including a memory cell 20 serving as a variable resistance nonvolatile memory element and a heater 30 thermally coupled to the memory cell 20, each capable of operating independently. The memory cell 20 includes a first electrode layer 21, a second electrode layer 22, and a variable resistance layer 23 sandwiched between the first and second electrode layers 21 and 22. The heater 30 includes a heating element 31 and third and fourth terminals 32 and 33 connected to the heating element 31. In this embodiment, the variable resistance nonvolatile memory device 10a further includes a thermal insulation structure 40 that prevents heat generated by the heater 30 from being transferred to the outside of the variable resistance nonvolatile memory device 10a. However, the thermal insulation structure 40 is not an essential component of the variable resistance nonvolatile memory device 10a.

[0031] Furthermore, the phrase "two circuit elements are independently operable" refers to a connection method that allows the operation of one circuit element to not affect the operation of the other. For example, this refers to the two circuit elements each having independent terminals for operation. Furthermore, the phrase "thermally coupled" refers to a relationship in which heat generated by one circuit element is transferred to the other circuit element. This includes not only direct contact between the two circuit elements but also indirect contact via another object.

[0032] In this structural example, the heater 30 is positioned parallel to the memory cell 20 (here, above the memory cell 20) in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23. Furthermore, the thermal insulation structure 40 surrounds the memory cell 20 and the heater 30 when viewed in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23. The "stacking direction" is also a direction perpendicular to the front or back surface of the wafer forming the variable resistance nonvolatile memory device 10a.

[0033] Hereinafter, each component of the resistance variable nonvolatile memory device 10 a will be described in detail.

[0034] The memory cell 20 is a non-volatile resistance change element that achieves a high resistance state and a low resistance state according to the voltage applied between the first electrode layer 21 and the second electrode layer 22. For example, when a positive voltage is applied to the second electrode layer 22 based on the voltage applied to the first electrode layer 21, the resistance is high, and when a negative voltage is applied to the second electrode layer 22 based on the voltage applied to the first electrode layer 21, the resistance is low.

[0035] The first electrode layer 21 is an electrode connected to the wiring 21a as an example of a first terminal, and is composed of, for example, a transition metal nitride such as tantalum nitride or titanium nitride, or a stack thereof. The second electrode layer 22 is an electrode connected to the wiring 22a as an example of a second terminal, and is composed of, for example, platinum, iridium, palladium, silver, nickel, tungsten or copper. The resistance variable layer 23 includes a tiny local area (i.e., a filament area composed of oxygen defect sites) in which the oxygen vacancy degree reversibly changes according to the polarity of the applied voltage. For example, a first resistance variable layer (a low-resistance tantalum oxide layer composed of oxygen-deficient Ta oxide) connected to the first electrode layer 21 and a second resistance variable layer (a high-resistance tantalum oxide layer) connected to the second electrode layer 22 are stacked.

[0036] The heating element 31 of the heater 30 exhibits relatively high resistance and is made of a material that generates a large amount of heat when current flows therethrough, such as titanium nitride, titanium aluminum nitride, titanium tungsten, tantalum nitride, tantalum silicon nitride, or tungsten nitride. A third terminal 32 is a terminal on one side of the heating element 31 to which a wiring 32a is connected, and a fourth terminal 33 is a terminal on the other side of the heating element 31 to which a wiring 33a is connected.

[0037] The heat-insulating structure 40 is a heat-insulating material with low thermal conductivity, and is made of, for example, silicon oxide, a low-dielectric-constant material, porous silicon oxide, aerogel, or xerogel.

[0038] In addition, if Figure 1AAs shown in FIG. 1 (b), the memory cell 20 and heater 30 have rectangular shapes when viewed from above, and the thermal insulation structure 40 has a rectangular ring shape. The thermal insulation structure may be a single block or divided into multiple pieces. The variable resistance nonvolatile memory device 10a, consisting of these components, is manufactured by repeatedly performing film formation and photolithography processes using a semiconductor substrate.

[0039] In addition, in this construction example, the heater 30 is arranged above the memory cell 20 as a position parallel to the memory cell 20 in the stacking direction of the first electrode layer 21, the second electrode layer 22 and the resistance change layer 23, but the position in the stacking direction is not limited to such an upper position. It can also be arranged below the memory cell 20 instead of such an upper position, or it can also be arranged below the memory cell 20 in addition to being arranged at such an upper position.

[0040] Figure 1B : is a schematic diagram showing a second structural example of the resistance variable nonvolatile memory device 10b according to the embodiment. More specifically, Figure 1B (a) is a cross-sectional view of the resistance variable nonvolatile memory device 10b. Figure 1B (b) is a top view of the resistance variable nonvolatile memory device 10b.

[0041] and Figure 1A The difference from the first structural example shown is that in this structural example, the heater 30 is arranged in a position parallel to the memory cell 20 in a direction perpendicular to the stacking direction of the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23. Even in this position, the heater 30 is thermally coupled to the memory cell 20. Furthermore, the "direction perpendicular to the stacking direction" is also a direction perpendicular to the cross section of the wafer forming the variable resistance nonvolatile memory device 10b.

[0042] In addition, in this construction example, the heater 30 is arranged at a position opposite to one of the four side surfaces of the memory cell 20 as a position parallel to the memory cell 20 in a direction perpendicular to the stacking direction of the first electrode layer 21, the second electrode layer 22 and the resistance change layer 23, but the position in the direction perpendicular to the stacking direction is not limited to this position, and it can also be arranged at a position opposite to two or more of the four side surfaces of the memory cell 20.

[0043] In addition to the heater 30 of this structural example, the heater 30 of the first structural example may be added. When heaters 30 are provided at multiple locations in one memory cell 20, these multiple heaters 30 are preferably electrically connected in series or in parallel.

[0044] Figure 1C: is a schematic diagram showing a third structural example of the resistance variable nonvolatile memory device 10c according to the embodiment. More specifically, Figure 1C (a) is a cross-sectional view of the resistance variable nonvolatile memory device 10c. Figure 1C (b) is a top view of the resistance variable nonvolatile memory device 10c.

[0045] In this construction example, Figure 1A The first structural example shown differs in that the heater 30 surrounds the memory cell 20 when viewed in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23. Even in this position, the heater 30 is thermally coupled to the memory cell 20. Furthermore, "viewed in the stacking direction" also means "viewed from the front or back side of the wafer forming the variable resistance nonvolatile memory device 10c."

[0046] In addition, in this construction example, when observed in the stacking direction of the first electrode layer 21, the second electrode layer 22 and the resistance change layer 23, the heater 30 surrounds the memory unit 20, but the position around the memory unit 20 is not limited to this. It can also be around the memory unit 20 when observed in a direction orthogonal to the stacking direction.

[0047] In addition to the heater 30 of this embodiment, the heater 30 of the first embodiment and / or the heater 30 of the second embodiment may be added. When heaters 30 are provided at multiple locations in one memory cell 20, these multiple heaters 30 are preferably electrically connected in series or in parallel.

[0048] In addition, Figures 1A to 1C In the illustrated structural examples, a pair of memory cell 20 and heater 30 is shown. While this pair represents one bit, multiple bits can be arranged two-dimensionally or three-dimensionally. In this case, the thermal insulation structure 40 is located at the boundary between each bit.

[0049] That is, in the above-mentioned construction example, when observed in the stacking direction of the first electrode layer 21, the second electrode layer 22 and the resistance change layer 23, the thermal insulation structure 40 surrounds the memory unit 20 and the heater 30, but the position around the memory unit 20 and the heater 30 is not limited to this, and it can also be that it surrounds the memory unit 20 and the heater 30 when observed in a direction orthogonal to the stacking direction.

[0050] Figure 2 This is a diagram showing a circuit configuration example of the resistance variable nonvolatile memory devices 10a to 10c according to the embodiment. Figures 1A to 1CThe memory cell 20 and the heater 30 shown are circuit configuration examples in which transistors 50 a and 50 b and a write control circuit 52 are added.

[0051] As shown in this figure, the memory cell 20 is connected in series with a transistor 50 a for driving the memory cell 20 , and the heater 30 is connected in series with a transistor 50 b for driving the heater 30 .

[0052] A word line WL is connected to the control terminals (i.e., gate terminals) of transistors 50a and 50b, a bit line BL is connected to a terminal on one side of the memory cell 20 (e.g., the first electrode layer 21), an input / output terminal on one side of the transistor 50a (e.g., one source / drain) is connected to a terminal on the other side of the memory cell 20 (e.g., the second electrode layer 22), a source line SL1 is connected to the input / output terminal on the other side of the transistor 50a (e.g., the other source / drain), a heater drive line HL is connected to a terminal on one side of the heater 30 (e.g., the third terminal 32), an input / output terminal on one side of the transistor 50b (e.g., one source / drain) is connected to a terminal on the other side of the heater 30 (e.g., the fourth terminal 33), and a source line SL2 is connected to the input / output terminal on the other side of the transistor 50b (e.g., the other source / drain).

[0053] The write control circuit 52 controls the word line WL, the bit line BL, the source line SL1, the heater drive line HL, and the source line SL2 by using Figure 3 By outputting various signals as described below, a high-resistance write operation (hereinafter also referred to as a "high-resistance step," "HR," or "erase operation") is performed to change the memory cell 20 to a high-resistance state, a heating operation (hereinafter also referred to as a "heating step," "heat application") is performed to heat the memory cell 20, and a low-resistance write operation (hereinafter also referred to as a "low-resistance step," "LR," or "write operation") is performed to change the memory cell 20 to a low-resistance state. To this end, the write control circuit 52 includes a selection circuit (not shown) that outputs a selection signal to a word line, a voltage source circuit (not shown) that supplies a voltage pulse or a constant voltage to the bit line BL, the source line SL1, the heater drive line HL, and the source line SL2, and a processor (not shown) that controls these selection circuits and voltage source circuits.

[0054] In the circuit configuration example of this figure, a pair of memory cell 20 and heater 30 is shown. However, when this pair is set as one bit, a plurality of bits may be arranged two-dimensionally or three-dimensionally.

[0055] Figure 3 1 is a timing diagram showing a method of driving the memory cell 20 according to the embodiment. Figure 3(a) to (e) represent Figure 2 Here, the signals of the word line WL, bit line BL, source line SL1, heater drive line HL, and source line SL2 in the circuit configuration example of FIG. Figure 2 According to the circuit configuration example shown, the memory cell 20 is driven in such a manner that writing to a high resistance state ("HR conversion" and "heat application") and writing to a low resistance state ("LR conversion") are sequentially performed.

[0056] While writing to a high-resistance state ("HR" and "heating") has traditionally only been performed, this embodiment features both "HR" and "heating." Specifically, the write control circuit 52 drives the word line WL to a select level (i.e., H level), thereby turning on transistors 50a and 50b. Then, while maintaining the source line SL1 at the reference potential, a "HR" voltage pulse (e.g., 1.7V) is applied to the bit line BL. Subsequently, while maintaining the source line SL2 at the reference potential, a "heating" voltage pulse (e.g., 3.0V) is applied to the heater drive line HL. The word line WL is then driven to a non-select level (i.e., L level). This allows the "HR" voltage pulse to be applied to the memory cell 20, followed by the "heating" voltage pulse applied to the heater 30, thereby performing writing to a high-resistance state that can suppress degradation of the memory cell 20's retention.

[0057] The subsequent writing to a low-resistance state ("LRing") is the same as in the conventional method. Specifically, the write control circuit 52 drives the word line WL to a select level (i.e., H level), thereby turning on transistors 50a and 50b. Then, while the bit line BL is maintained at the reference potential, a voltage pulse for "LRing" (e.g., 2.0V) is applied to the source line SL1. Subsequently, the word line WL is driven to a non-select level (i.e., L level). During writing to a low-resistance state, "heat application" is not performed.

[0058] Figures 4A to 4C 1 is a diagram for explaining the effect of the driving method of the memory cell 20 according to the embodiment. More specifically, Figure 4A The figure shows the retention characteristics of the memory cell after a cycle test in which conventional writing to a high resistance state and writing to a low resistance state (wherein the writing current is 125 μA) without performing “heat application” are repeated. Figure 4B The figure shows the retention characteristics of the memory cell after a cycle test in which conventional writing to a high resistance state and writing to a low resistance state (wherein the writing current is 75 μA) without performing “heat application” are repeated. Figure 4CThe figure shows the retention characteristics of the memory cell after a cycle test in which writing to a high resistance state and writing to a low resistance state (wherein the writing current is 75 μA) of the embodiment including “heat application” are repeated.

[0059] Retention characteristics are obtained by subjecting a certain number of memory cells with identical characteristics to a cycle test in which writing to a high-resistance state and writing to a low-resistance state are repeated 1000 times, followed by an accelerated life test. The normal expected value (expected value with standard deviation σ as the unit; Y-axis) of the current ("cell current") corresponding to the resistance value retained in the high-resistance state and the low-resistance state for each memory cell after 1 year and 10 years at 85°C is plotted. The horizontal axis represents "cell current."

[0060] exist Figures 4A to 4C In each figure, the connections between the black dots, black squares, and black triangles are the normal expected values ​​of the cell current in the low resistance state after the cycle test, after being placed at 85°C for 1 year, and after being placed at 85°C for 10 years, respectively. The connections between the white dots, white squares, and white triangles are the normal expected values ​​of the cell current in the high resistance state after the cycle test, after being placed at 85°C for 1 year, and after being placed at 85°C for 10 years, respectively.

[0061] from Figure 4A It can be seen that when conventional writing to a high-resistance state is performed without "heat application" at a relatively high write current (i.e., 125 μA), the window (specifically, the window of the normal expected value range of ±3.5σ (hereinafter also referred to as the "3.5σ-window")) between the minimum resistance value in the high-resistance state and the maximum resistance value in the low-resistance state maintained by each memory cell after 10 years at 85°C is approximately 17 μA. Note that σ is the standard deviation of the resistance distribution.

[0062] However, from Figure 4B It can be seen that when conventional writing to a high-resistance state is performed at a relatively low write current (i.e., 75 μA) without performing "heat application," the 3.5σ-window of each memory cell after 10 years at 85°C is extremely small, at approximately 2 μA, and the memory cell retention characteristics have significantly deteriorated. This is because the resistance value of the memory cell in the low-resistance state increases (i.e., the cell current decreases).

[0063] In contrast, from Figure 4C It can be seen that when writing to a high resistance state is performed using an implementation method including "heat application" with a relatively small write current (i.e., 75 μA), the 3.5σ-window becomes approximately 15 μA after being placed at 85°C for 10 years, and the degradation of the retention characteristics of the memory cell is greatly suppressed.

[0064] In recent years, with the miniaturization of semiconductors, high reliability in low power operation is required. Figure 4A and Figure 4B It can be seen that in the conventional memory cell driving method that does not include "heat application", if the write current is reduced, the retention degradation after the cycle becomes larger, and a sufficient memory window cannot be ensured, and high reliability cannot be guaranteed. Figure 4C It can be seen that, by implementing a "heat application" method for writing to a high-resistance state, even with a reduced write current, the amount of retention degradation after cycling can be suppressed. Therefore, implementing a "heat application" method for writing to a high-resistance state achieves highly reliable variable resistance nonvolatile memory devices 10a-10c while ensuring low-power operation.

[0065] Furthermore, according to the embodiment including “heat application”, the writing to the high resistance state does not sacrifice the durability characteristics of the memory cell 20 by increasing the number of writing times as in the conventional method, and the degradation of the retention of the memory cell 20 can be suppressed.

[0066] The following describes the characteristics of the memory cell driving method of this embodiment, along with comparison with the conventional method and the mechanism of the memory cell. Figures 5 to 7 Provide explanation.

[0067] Figure 5 1 is a diagram illustrating the characteristics of the driving method of the memory cell 20 of this embodiment while comparing it with the conventional method. More specifically, Figure 5 (a) shows the cell current transitions in the first conventional example where a normal erase voltage VH is applied to achieve a high resistance state, and in the present embodiment where a "hot application" is subsequently performed to reduce the cell current in the high resistance state. The horizontal axis represents the time series of the operation, and the vertical axis represents the cell current. Figure 5 (b) means Figure 5 "HR conversion", "heat application", "LR conversion" in (a) and the corresponding action timings thereafter. Figure 5 (c) shows that Figure 5 The meaning of each transition line type in (a).

[0068] like Figure 5As shown in (a), according to the driving method of the memory cell 20 of the present embodiment (the transition shown by the thin solid line and the thick solid line through the black dots, black squares, and black triangles), for the memory cell 20, by performing "heat application" after "HR treatment", the resistance change layer 23 of the memory cell 20 is oxidized, and the oxygen defects in the filament region formed in the resistance change layer 23 are reduced. That is, compared with the case where "heat application" is not performed (the transition shown by the thin dotted line and the thick dotted line), the cell current in the high resistance state becomes smaller. As a result, in the subsequent "LR treatment", a high voltage is applied to the memory cell 20 compared with the case where "heat application" is not performed, and the oxygen defects in the filament region increase. That is, compared with the case where no heat treatment is performed, the oxygen defects in the filament region increase, and the cell current in the low resistance state becomes larger. As a result, the reduction in cell current caused by the reduction (reoxidation) of oxygen defects over time is suppressed, and reliability is improved.

[0069] Figure 6 1 is a diagram illustrating the characteristics of the driving method of the memory cell 20 of this embodiment in comparison with the second conventional example. More specifically, Figure 6 In (a), as a method for reducing the cell current in the high-resistance state, the cell current transition after "LR conversion" is shown for the second conventional example in which the erase voltage VH is increased, and for the present embodiment in which "heat application" is performed after "HR conversion." The horizontal axis represents the time series of the operation, and the vertical axis represents the cell current. Figure 6 (b) shows the representation Figure 6 The meaning of each transition line type in (a).

[0070] like Figure 6 As shown in the transition of the second conventional example (transitions shown by the double and triple lines) in (a) of FIGURE 2 , in the second conventional example, the cell current in the high-resistance state is reduced by increasing the pulse voltage applied to the memory cell during the high-resistance transition. As a result, during the subsequent "LR transition," compared to the first conventional example in which the normal erase voltage VH is applied to the high-resistance state, the high voltage applied to the memory cell 20 increases oxygen vacancies in the filament region, increasing the cell current in the low-resistance state. However, as time passes, the cell current decreases, causing a problem of increased retention degradation.

[0071] In contrast, Figure 6As shown in the transition with "heat application" in (a) (the transition shown by the thin solid line and the thick solid line), in this embodiment, since "heat application" is performed after "HR conversion", the resistance variable layer 23 of the memory cell 20 is oxidized, and the oxygen vacancies formed in the filament region of the resistance variable layer 23 are reduced. As a result, during the subsequent "LR conversion", a high voltage is applied to the memory cell 20, the oxygen vacancies in the filament region increase, and the cell current in the low-resistance state increases. However, in the driving of this embodiment, the decrease in cell current over time is suppressed, and reliability is improved. Figure 7 It is an explanation Figure 6 Schematic diagram of the structure of the memory cell 20 showing the mechanism of the transition of the cell current.

[0072] Figure 7 (a) shows a schematic configuration of the memory cell 20 in a low resistance state ("LRS"). The resistance change layer 23 includes a first resistance change layer 23a containing oxygen ions and a second resistance change layer 23b having a filament 24 containing oxygen defects.

[0073] Figure 7 (b) shows the conventional driving method for Figure 7 The memory cell 20 in state (a) is schematically shown in the high-resistance state ("HRS") after being rendered high-resistance at a high erase voltage using a higher-than-normal write voltage ("HR voltage VH: High"). Oxygen ions within the first variable resistance layer 23a migrate toward the filament 24 within the second variable resistance layer 23b, combining with oxygen vacancies within the filament 24 to cause reoxidation. However, a large amount of oxygen ions that do not contribute to reoxidation remain within the filament.

[0074] Figure 7 (c) indicates Figure 7 Schematic structure of the memory cell 20 in the low resistance state ("LRS") after the memory cell 20 in state (b) is changed to a low resistance state by applying a write voltage to the low resistance state ("LR voltage application"). Oxygen ions within the filament 24 migrate toward the first variable resistance layer 23a, but a large amount of oxygen ions remain within the filament 24. As a result, if the memory cell 20 is maintained in this state for a long time, reoxidation of oxygen vacancies occurs within the filament 24, reducing the number of oxygen vacancies and decreasing the cell current in the low resistance state (i.e., retention degradation progresses).

[0075] on the other hand, Figure 7 (d) indicates that the driving method of this embodiment is used to Figure 7 The memory cell 20 in the state (a) is connected to the Figure 7Similarly, after the resistance is increased by using the normal erasing voltage ("HR voltage VH: normal") ( Figure 7 (d1)), and then further increase the resistance by applying heat ( Figure 7 Schematic structure of the memory cell 20 in the high resistance state ("HRS") of (d2). By "heat application", oxygen ions combine with oxygen vacancies in the filament 24 to cause reoxidation, and the oxygen vacancies are reduced.

[0076] Figure 7 (e) indicates Figure 7 Schematic structure of the memory cell 20 in the low resistance state ("LRS") after the memory cell 20 in state (d) is changed to a low resistance state by applying a write voltage to the low resistance state ("LR voltage application"). Although oxygen ions within the filament 24 migrate toward the first variable resistance layer 23a, the amount of oxygen ions within the filament 24 is small. As a result, even when the memory cell 20 is maintained in this state for a long time, reoxidation of oxygen vacancies is unlikely to occur, thereby suppressing degradation of retention.

[0077] In addition, in the present embodiment, in the erasing operation ("HR" and "heat application") for the memory cell 20 to the high resistance state, as shown in FIG. Figure 3 As shown, "heat application" is performed after "HR treatment", but it is not limited to this order. Figure 8A As shown in the timing diagram of the first modification example, after "heat application", "HR" can also be performed as shown in the timing diagram of the first modification example. Figure 8B As shown in the timing diagram of the second modified example, "HR" and "heat application" are performed in parallel. In short, the order of "HR" and "heat application" is not particularly limited, as long as any timing is selected for the high resistance step of the variable resistance nonvolatile memory element. The order of "HR" and "heat application," as well as the pulse width of "heat application," are appropriately determined based on the heat capacity of the memory cell 20, the heat generation of the heater 30, and the degree of thermal coupling between the memory cell 20 and the heater 30.

[0078] As described above, the variable resistance nonvolatile memory device 10a of this embodiment includes a memory cell 20 serving as a variable resistance nonvolatile memory element and a heater 30 thermally coupled to the memory cell 20, each capable of independent operation. The memory cell 20 includes a first electrode layer 21, a second electrode layer 22, and a variable resistance layer 23 sandwiched between the first and second electrode layers 21 and 22. The heater 30 includes a heating element 31 and third and fourth terminals 32 and 33 connected to the heating element 31.

[0079] As a result, when writing to a high-resistance state, the heater 30 can heat the memory cell 20, thereby reducing the cell current of the memory cell 20 after the resistance is increased and increasing the cell current of the memory cell 20 after the resistance is decreased. This prevents the durability of the memory cell 20 from being compromised by increasing the number of write cycles, as is conventional practice, and suppresses degradation in the retention of the memory cell 20. Consequently, a variable resistance nonvolatile memory device is achieved that suppresses degradation in retention even during low-current writing, ensuring high reliability in low-power operation.

[0080] Here, the heater 30 may be arranged in parallel with the memory cell 20 in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23. Alternatively, the heater 30 may be arranged in parallel with the memory cell 20 in a direction perpendicular to the stacking direction of the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23. Alternatively, the heater 30 may surround the memory cell 20 when viewed in the stacking direction, or surround the memory cell 20 when viewed in a direction perpendicular to the stacking direction. Thus, the memory cell 20 and the heater 30 can be thermally coupled to accommodate various structures.

[0081] Furthermore, the variable resistance nonvolatile memory device 10a or the like may include a heat insulating structure 40 that prevents heat generated by the heater 30 from being transferred to the outside of the variable resistance nonvolatile memory device 10a. This prevents heat generated by the heater 30 from being dissipated to the outside, thereby ensuring efficient heat application and minimizing thermal effects on other memory cells, etc., disposed adjacent to the memory cell 20.

[0082] In this case, the thermal insulation structure 40 may surround the memory cell 20 and the heater 30 when viewed in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23, or may surround the memory cell 20 and the heater 30 when viewed in a direction perpendicular to the stacking direction. This allows for more reliable heat application to the memory cell 20.

[0083] In addition, the driving method of the memory cell 20 of the present embodiment is a driving method of the memory cell 20 that can obtain a high resistance state and a low resistance state, including: a high resistance step, driving the memory cell 20 so that the memory cell 20 is in a high resistance state; a low resistance step, driving the memory cell 20 so that the memory cell 20 is in a low resistance state; and a heating step, driving the heater 30 thermally coupled to the memory cell 20 at any time when the memory cell 20 is selected for the high resistance step.

[0084] Thus, in order to write data to the memory cell 20 in a high-resistance state, a high-resistance step and a heating step are performed, thereby reducing the cell current of the memory cell 20 after the resistance is increased and increasing the cell current of the memory cell 20 after the resistance is decreased. Therefore, the durability of the memory cell 20 is not compromised by increasing the number of write cycles, as is conventional practice, and degradation of the memory cell 20's retention performance can be suppressed. Consequently, a resistance variable nonvolatile memory device is achieved that suppresses degradation of retention performance even during low-current writes, ensuring high reliability in low-power operation.

[0085] Here, the heater 30 may be driven during the heating step while the memory cell 20 is selected for the high resistance step, or the heater 30 may be driven after the memory cell 20 has been driven in the high resistance step. This ensures that the cell current of the memory cell 20 after the high resistance step is reduced and the cell current of the memory cell 20 after the low resistance step is increased.

[0086] While the above description of the variable resistance nonvolatile memory device and the method for driving a variable resistance nonvolatile memory element of the present disclosure is based on the embodiments and variations, the present disclosure is not limited to these embodiments and variations. Without departing from the scope of the present disclosure, various modifications of the embodiments and variations conceived by those skilled in the art, as well as other methods constructed by combining some of the components or processes in the embodiments and variations, are also included within the scope of the present disclosure.

[0087] For example, in the above embodiment, a Ta oxide layer is used as an example for the variable resistance layer 23 of the memory cell 20. However, the material is not limited to this. Alternatively, a metal oxide layer containing at least one of a transition metal such as hafnium, titanium, zirconium, niobium, tungsten, nickel, and iron, and aluminum as a parent metal may be used. The variable resistance layer 23 of the memory cell 20 is not limited to a stacked structure of two variable resistance layers; a single variable resistance layer may also be used.

[0088] Furthermore, in the circuit configuration example in the above embodiment, a 1T1R bit structure based on a series connection between the memory cell 20 and the transistor 50 a is shown, but a 1D1R bit structure based on a series connection between the memory cell 20 and a diode may also be used.

[0089] Industrial Applicability

[0090] The resistance variable nonvolatile memory device according to the embodiment of the present disclosure can be used as a ReRAM in which degradation of retention is suppressed, and in particular, as a ReRAM that ensures high reliability in low-power operation.

[0091] Description of Reference Numerals

[0092] 10a, 10b, 10c resistance variable nonvolatile memory devices (ReRAM)

[0093] 20 Resistance variable nonvolatile memory element (memory cell)

[0094] 21 first electrode layer

[0095] 21a, 22a, 32a, 33a wiring

[0096] 22 second electrode layer

[0097] 23 resistance variable layer

[0098] 23a First resistance variable layer

[0099] 23b second resistance variable layer

[0100] 24 filaments

[0101] 30 heaters

[0102] 31 heating element

[0103] 32 third terminal

[0104] 33 Fourth terminal

[0105] 40 thermal insulation structure

[0106] 50a, 50b transistors

[0107] 52 write control circuit

[0108] WL word line

[0109] BL bit line

[0110] SL1, SL2 source lines

[0111] HL heater drive line

Claims

1. A resistance variable nonvolatile memory device, characterized in that: have: A variable resistance nonvolatile memory element comprising a first electrode layer, a second electrode layer, a variable resistance layer sandwiched between the first electrode layer and the second electrode layer, a first terminal connected to the first electrode layer, and a second terminal connected to the second electrode layer; as well as The heater comprises a heating element and a third terminal and a fourth terminal connected to the heating element. The resistance variable nonvolatile memory element and the heater are independently operable and thermally coupled.

2. The resistance variable nonvolatile memory device according to claim 1, wherein: The heater is arranged at a position parallel to the variable resistance nonvolatile memory element in a stacking direction of the first electrode layer, the second electrode layer, and the variable resistance layer.

3. The resistance variable nonvolatile memory device according to claim 1 or 2, wherein: The heater is arranged at a position parallel to the variable resistance nonvolatile memory element in a direction perpendicular to a stacking direction of the first electrode layer, the second electrode layer, and the variable resistance layer.

4. The resistance variable nonvolatile memory device according to any one of claims 1 to 3, wherein: The heater surrounds the variable resistance nonvolatile memory element when viewed in a stacking direction of the first electrode layer, the second electrode layer, and the variable resistance layer. 5 . The resistance variable nonvolatile memory device according to claim 1 , wherein: The heater surrounds the variable resistance nonvolatile memory element when viewed in a direction perpendicular to a stacking direction of the first electrode layer, the second electrode layer, and the variable resistance layer. 6 . The resistance variable nonvolatile memory device according to claim 1 , wherein: A heat insulating structure is further provided. The heat insulating structure suppresses heat generated by the heater from being transferred to the outside of the variable resistance nonvolatile memory device.

7. The resistance variable nonvolatile memory device according to claim 6, wherein: The thermal insulation structure surrounds the variable resistance nonvolatile memory element and the heater when viewed in a stacking direction of the first electrode layer, the second electrode layer, and the variable resistance layer.

8. The resistance variable nonvolatile memory device according to claim 6 or 7, wherein: The thermal insulation structure surrounds the variable resistance nonvolatile memory element and the heater when viewed in a direction perpendicular to a stacking direction of the first electrode layer, the second electrode layer, and the variable resistance layer.

9. A method for driving a variable resistance nonvolatile memory element capable of taking a high resistance state and a low resistance state, characterized in that: include: a high resistance step of driving the variable resistance nonvolatile memory element to bring the variable resistance nonvolatile memory element into a high resistance state; a resistance lowering step of driving the variable resistance nonvolatile memory element to bring the variable resistance nonvolatile memory element into a low resistance state; and The heating step is to drive a heater thermally coupled to the variable resistance nonvolatile memory element at an arbitrary timing selected for the resistance increasing step.

10. The method for driving a variable resistance nonvolatile memory element according to claim 9, wherein: In the heating step, the resistance variable nonvolatile memory element is driven after the heater is driven in the resistance increasing step.

11. The method for driving a variable resistance nonvolatile memory element according to claim 9, wherein: In the heating step, the heater is driven after the resistance variable nonvolatile memory element is driven in the resistance increasing step.

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