Display device

Abstract

The embodiment of the invention provides display equipment. The display equipment comprises a display area and a peripheral area, a first thin film transistor disposed in the peripheral region and including a silicon semiconductor layer; a second thin film transistor disposed in the display area and including an oxide semiconductor layer disposed on a layer above the silicon semiconductor layer; and a semiconductor pattern disposed in the display area and disposed on the same layer as the silicon semiconductor layer of the first thin film transistor.

Description

Technical Field

[0001] Aspects of one or more embodiments of the present disclosure relate to pixels and display devices including the pixels. Background Art

[0002] Recently, display devices have been used for various purposes. In addition, as the thickness and weight of display devices are reduced, the application range of display devices has increased.

[0003] Since the display device is used in various ways, there may be various methods for designing the shape of the display device, and functions related to or associated with the display device have increased.

[0004] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the Invention Technical issues

[0005] One or more embodiments of the present disclosure relate to a display device with improved display quality. However, aspects and features of the present disclosure are not limited thereto. Solution to the problem

[0006] According to one or more embodiments of the present disclosure, a display device includes: a display area; a peripheral area; a first thin film transistor, in the peripheral area, and the first thin film transistor includes a silicon semiconductor layer; a second thin film transistor, in the display area, and the second thin film transistor includes an oxide semiconductor layer above the silicon semiconductor layer; and a semiconductor pattern, in the display area, and the semiconductor pattern is at the same layer as the silicon semiconductor layer of the first thin film transistor.

[0007] In an embodiment, the semiconductor pattern may include a silicon semiconductor.

[0008] In an embodiment, the semiconductor pattern may be configured to be in a floating state.

[0009] In an embodiment, the display device may further include: a conductive layer overlapping the semiconductor pattern; and a signal line electrically connected to opposite ends of the semiconductor pattern that do not overlap the conductive layer. The signal line may be electrically connected to the conductive layer.

[0010] In an embodiment, the conductive layer may be at the same layer as a gate electrode of the first thin film transistor.

[0011] In an embodiment, the oxide semiconductor layer of the second thin film transistor may overlap the semiconductor pattern.

[0012] In an embodiment, the display device may further include: a plurality of conductive electrodes overlapping the semiconductor pattern; and a signal line electrically connected to a portion of the semiconductor pattern between adjacent conductive electrodes among the plurality of conductive electrodes. The signal line may be electrically connected to the plurality of conductive electrodes.

[0013] In an embodiment, the plurality of conductive electrodes may be at the same layer as a gate electrode of the first thin film transistor.

[0014] In an embodiment, the oxide semiconductor layer of the second thin film transistor may overlap the semiconductor pattern.

[0015] In an embodiment, the display device may further include: an upper conductive layer overlapping the semiconductor pattern; a lower conductive layer overlapping the semiconductor pattern; and a signal line electrically connected to opposite ends of the semiconductor pattern that do not overlap with the upper conductive layer. The signal line may be electrically connected to the upper conductive layer and the lower conductive layer.

[0016] In an embodiment, the upper conductive layer may be at the same layer as the gate electrode of the first thin film transistor.

[0017] In an embodiment, the oxide semiconductor layer of the second thin film transistor may overlap the semiconductor pattern.

[0018] In an embodiment, the semiconductor pattern may include a plurality of semiconductor patterns spaced apart from each other in a row direction, and the display device may further include: a conductive layer overlapping the plurality of semiconductor patterns to cross the plurality of semiconductor patterns; a first signal line electrically connected to ends of the plurality of semiconductor patterns; and a second signal line electrically connected to other ends of the plurality of semiconductor patterns.

[0019] In an embodiment, the first and second signal lines may be configured to be applied with constant voltage signals, and the conductive layer may be configured to be applied with a signal including a voltage of a first voltage level and a voltage of a second voltage level lower than the first voltage level.

[0020] In an embodiment, the display device may further include: a second semiconductor pattern at the same layer as the plurality of semiconductor patterns, the second semiconductor pattern extending in the row direction; a second conductive layer overlapping the second semiconductor pattern; and a third signal line electrically connected to an opposite end of the second semiconductor pattern that does not overlap with the second conductive layer. The third signal line may be configured to be supplied with the same voltage as that supplied to the first and second signal lines.

[0021] In an embodiment, the display device may further include: a conductive layer overlapping the semiconductor pattern; and a signal line electrically connected to the conductive layer.

[0022] In an embodiment, the semiconductor pattern may be electrically connected to a conductive line configured to supply a constant voltage.

[0023] In an embodiment, the display device may further include a third thin film transistor in the display area and including an oxide semiconductor layer above the silicon semiconductor layer. The semiconductor pattern may be configured to electrically connect the oxide semiconductor layer of the second thin film transistor to the oxide semiconductor layer of the third thin film transistor.

[0024] In an embodiment, the display device may further include a third thin film transistor provided in the peripheral region and including the oxide semiconductor layer.

[0025] In an embodiment, the display device may further include: a fourth thin film transistor disposed in the display area and including the silicon semiconductor layer.

[0026] According to one or more embodiments of the present disclosure, a display device includes: a display area; a peripheral area; a semiconductor pattern in the display area; a conductive layer on the semiconductor pattern, and the conductive layer overlaps with the semiconductor pattern; a first electrode layer on the conductive layer, and the first electrode layer overlaps with the conductive layer; an oxide semiconductor layer on the first electrode layer; a second electrode layer on the oxide semiconductor layer; and a third electrode layer on the second electrode layer, and the third electrode layer overlaps with the second electrode layer.

[0027] In an embodiment, the semiconductor pattern may include a silicon semiconductor.

[0028] In an embodiment, the display device may further include a lower conductive layer in the display area, the lower conductive layer being between the substrate and the semiconductor pattern, and the semiconductor pattern may overlap with the lower conductive layer.

[0029] In an embodiment, the display device may further include: a silicon semiconductor layer in the peripheral region; and a fourth electrode layer on the silicon semiconductor layer, the fourth electrode layer overlapping the silicon semiconductor layer. The silicon semiconductor layer may be at the same layer as the semiconductor pattern, and the fourth electrode layer may be at the same layer as the conductive layer. Beneficial effects of the present invention

[0030] According to one or more embodiments of the present disclosure described above, a display device with improved display quality can be provided. However, the scope of the present disclosure is not limited thereto. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0032] Figure 1a and Figure 1b is a plan view schematically illustrating a display device according to one or more embodiments;

[0033] Figure 2 is a plan view schematically showing a display panel according to an embodiment;

[0034] Figures 3a to 3d is schematically shown along Figure 2 A cross-sectional view of the display panel taken along line II';

[0035] Figures 4a to 8b is a view schematically illustrating a semiconductor pattern of a display region according to one or more embodiments;

[0036] Figure 9a and Figure 9b is an equivalent circuit diagram showing a pixel according to the embodiment;

[0037] Figures 10 to 23 It is a schematic diagram showing the Figure 9a a view of an element of a layer of pixels;

[0038] Figure 24 is a view schematically illustrating an arrangement of emission regions of a plurality of pixels according to an embodiment;

[0039] Figure 25 It is along Figure 20 and Figure 23 A cross-sectional view taken along line VIII-VIII';

[0040] Figure 26 It is schematically shown Figure 9a A view of the transistors and capacitors of a pixel;

[0041] Figure 27 is a view schematically showing a conductive layer at an edge of a display area;

[0042] Figure 28 It is along Figure 27 A cross-sectional view taken along line XX';

[0043] Figure 29 is a schematic diagram showing a Figure 9a A view of the transistors and capacitors of a pixel;

[0044] Figures 30 to 36 It is a schematic diagram showing the Figure 29 A view of the components of the layer of the pixel circuit;

[0045] Figure 37 It shows Figure 29 Layout diagram of some components;

[0046] Figure 38 It is along Figure 29 A cross-sectional view taken along line XI-XI';

[0047] Figure 39 is a schematic diagram showing a Figure 9a A view of the transistors and capacitors of a pixel;

[0048] Figure 40 It is along Figure 39 A cross-sectional view taken along line XII-XII';

[0049] Figure 41 is a schematic diagram showing a Figure 9a A view of the transistors and capacitors of a pixel;

[0050] Figure 42 and Figure 43 It is schematically shown Figure 41 A view of some components of a pixel circuit;

[0051] Figure 44 It shows Figure 41 Layout diagram of some components;

[0052] Figure 45 It is along Figure 41 A cross-sectional view taken along line XIII-XIII';

[0053] Figure 46 is a schematic diagram showing a Figure 9a a view of the transistors and capacitors of a pixel; and

[0054] Figure 47 and Figure 48 It is schematically shown Figure 46 A view of some components of the pixel circuit. DETAILED DESCRIPTION

[0055] According to one or more embodiments of the present disclosure, a display device includes: a display area; a peripheral area; a first thin film transistor, which is in the peripheral area and includes a silicon semiconductor layer; a second thin film transistor, which is in the display area and includes an oxide semiconductor layer above the silicon semiconductor layer; and a semiconductor pattern, which is at the same layer as the silicon semiconductor layer of the first thin film transistor in the display area. Examples of the Invention

[0056] Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements from time to time. However, the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments shown in this article. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, throughout the drawings and written description, the same reference numerals refer to the same elements, and therefore, their redundant descriptions may not be repeated.

[0057] When a specific embodiment can be implemented differently, the specific process order may be different from the described order. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0058] In the accompanying drawings, for the sake of clarity, the relative sizes, thicknesses and proportions of elements, layers and regions may be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "under ... ", "below ... ", "below ", "below ... ", "above ... " and "on " may be used herein to describe the relationship between an element or feature and another element (multiple elements) or feature (multiple features) as shown in the drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, the element described as "under" or "below" or "below" other elements or features will subsequently be oriented as "above" other elements or features. Therefore, the example terms "under ... " and "below ... " can cover both above and below. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly.

[0059] In the drawings, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0060] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, the first element, first component, first area, first layer, or first part described below may be named as the second element, second component, second area, second layer, or second part without departing from the spirit and scope of the present disclosure.

[0061] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being “electrically connected to” another layer, region, or element, the layer, region, or element can be directly electrically connected to the other layer, region, or element and / or can be indirectly electrically connected with one or more intervening layers, regions, or elements interposed therebetween. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0062] As used herein, the term "on" used in association with a device state may refer to a state in which the device is activated, and the term "off" may refer to a state in which the device is disabled. The term "on" used in association with a signal received by a device may refer to a signal for activating the device, and the term "off" may refer to a signal for disabling the device. A device may be activated by a high level voltage or a low level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low level voltage, and an N-channel transistor (N-type transistor) is activated by a high level voltage. Therefore, it should be understood that the "on" voltages for P-type transistors and N-type transistors have opposite (e.g., high and low) voltage levels. Similarly, when any signal is applied, this may mean applying a turn-on voltage (e.g., a high level voltage), and when no signal is applied, this may mean applying a turn-off voltage (e.g., a low level voltage).

[0063] The terms used in this article are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in this article, unless the context clearly indicates otherwise, the singular forms "a" and "an (person / kind)" are also intended to include the plural forms. It will be further understood that when used in this specification, the terms "comprises, comprising", "includes, including" and "has, have, having" illustrate the presence of the stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups. As used in this article, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" refers to A, B or A and B. When following a list of elements, expressions such as "... at least one (person)" modify the entire list of elements without modifying the individual elements in the list. For example, the expressions "at least one of a, b, or c," "at least one of a, b, and c," and "at least one selected from the group consisting of a, b, and c" refer to only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0064] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation rather than terms of degree and are intended to account for the inherent variations in measurements or calculations that one of ordinary skill in the art would recognize. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their context in the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense.

[0066] According to one or more embodiments, the display device may be implemented as an electronic device such as a smart phone, a mobile phone, a smart watch, a navigation device, a game console, a television (TV), a vehicle head unit, a notebook computer, a laptop computer, a tablet computer, a personal media player (PMP), or a personal digital assistant (PDA). In addition, the electronic device may be a flexible device.

[0067] Figure 1a and Figure 1b is a plan view schematically illustrating a display device according to one or more embodiments. Figure 2 is a plan view schematically showing a display panel according to an embodiment.

[0068] refer to Figure 1a and Figure 1b , the display device 1 may include a display area DA in which an image is displayed and a peripheral area PA outside the display area DA. The display area DA may be completely surrounded by the peripheral area PA (eg, the peripheral area PA is around the periphery of the display area DA).

[0069] In a plan view, the display area DA may have a rectangular shape. In another embodiment, the display area DA may have a polygonal shape (e.g., a triangular shape, a pentagonal shape, and / or a hexagonal shape, etc.), a circular shape, an elliptical shape, or an irregular shape. The display area DA may have a shape including rounded corners. In an embodiment, as shown in FIG. Figure 1a As shown in , the display device 1 may include a display area DA having a shape in which the length in the x direction is greater than the length in the y direction. Figure 1b As shown in , the display device 1 may include a display area DA having a shape in which a length in the y direction is greater than a length in the x direction.

[0070] The display apparatus 1 may include a display panel 10 , and a cover window for protecting the display panel 10 may be located on the display panel 10 .

[0071] Various elements constituting the display panel 10 may be positioned on a substrate 100. The substrate 100 may include a display area DA and a peripheral area PA surrounding the display area DA (eg, around the periphery of the display area DA).

[0072] A plurality of pixels PX may be located in the display area DA. A plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX connected to the gate lines GL and the data lines DL may be located in the display area DA. The plurality of pixels PX may be arranged in a pattern such as a stripe pattern, an RGBG pattern (e.g., arrangement, is an officially registered trademark of Samsung Display Co., Ltd.), diamond arrangement or mosaic arrangement, and can be positioned in any of various suitable arrangements to display images. Each pixel PX may include an organic light emitting diode OLED as a display element (e.g., a light emitting element), and the organic light emitting diode OLED may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. Each pixel PX may emit light, such as red light, green light, blue light or white light, through a corresponding organic light emitting diode OLED. Each pixel PX may be connected to a corresponding gate line among a plurality of gate lines GL and a corresponding data line among a plurality of data lines DL.

[0073] Each of the gate lines GL may extend in the x-direction (e.g., the row direction) and may be connected to pixels PX located in the same row. The gate lines GL may transmit gate signals to pixels PX located in the same row. Each of the data lines DL may extend in the y-direction (e.g., the column direction) and may be connected to pixels PX located in the same column. The data lines DL may transmit data signals to each of the pixels PX located in the same column in synchronization with the gate signals. Each pixel PX may be connected to at least one of the plurality of drive voltage lines PL to receive a drive voltage ELVDD. Each of the drive voltage lines PL may extend in the y-direction (e.g., the column direction) and may be connected to pixels PX located in the same column.

[0074] Despite Figure 2 Pixel PX is shown as being connected to one gate line GL, but the present disclosure is not limited thereto. Pixel PX may be connected to one or more gate lines GL.

[0075] The pixel circuit for driving the pixel PX may be electrically connected to an external circuit located in the peripheral area PA. The first gate driving circuit DRV1, the second gate driving circuit DRV2, the terminal unit (e.g., terminal area) PAD, the driving voltage supply line 11, and the common voltage supply line 13 may be located in the peripheral area PA.

[0076] In one embodiment, the peripheral area PA may be a non-display area where pixels PX are not located. In another embodiment, a portion of the peripheral area PA may be implemented as the display area DA. For example, multiple pixels PX may overlap with external circuitry at at least one corner of the peripheral area PA. This can reduce unused area and expand the display area DA.

[0077] The first gate drive circuit DRV1 can be connected to multiple gate lines GL and can apply gate signals to pixel circuits for driving pixels PX through the gate lines GL. The gate signal can be a gate control signal for controlling the conduction or cutoff of a transistor having a gate connected to the gate line GL. The gate signal can be a square wave signal including a gate-on voltage for turning on the transistor and a gate-off voltage for turning off the transistor. The second gate drive circuit DRV2 can be positioned opposite the first gate drive circuit DRV1 relative to the display area DA and can be parallel or substantially parallel to the first gate drive circuit DRV1. In an embodiment, some of the pixel circuits of the pixels PX in the display area DA can be electrically connected to the first gate drive circuit DRV1, and other pixel circuits can be electrically connected to the second gate drive circuit DRV2. In another embodiment, the pixel circuits of the pixels PX in the display area DA can be electrically connected to the first gate drive circuit DRV1 and the second gate drive circuit DRV2. The second gate drive circuit DRV2 can be omitted as needed or desired.

[0078] The terminal unit PAD may be located on one side of the substrate 100 (eg, at an end of the substrate 100 ). The terminal unit PAD may be exposed without being covered by the insulating layer and may be connected to the display circuit board 30 . The display driver 32 may be located on the display circuit board 30 .

[0079] The display driver 32 may generate control signals that are transmitted to the first gate drive circuit DRV1 and the second gate drive circuit DRV2. The display driver 32 may include a data drive circuit. The data drive circuit may be connected to a plurality of data lines DL to generate data signals, and the generated data signals may be transmitted to the pixel circuits of the pixels PX via the fan-out lines FW and the data lines DL connected to the fan-out lines FW.

[0080] The display driver 32 may include a power supply circuit. The power supply circuit may supply a driving voltage ELVDD to the driving voltage supply line 11 and a common voltage ELVSS to the common voltage supply line 13. The driving voltage ELVDD may be applied to the pixel circuit of the pixel PX via the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS may be applied to the counter electrode of the display element via the common voltage supply line 13.

[0081] The driving voltage supply line 11 may be connected to the terminal unit PAD and may be located below the display area DA to extend in the x-direction. The common voltage supply line 13 may be connected to the terminal unit PAD and may have a ring shape with one side open to partially surround the display area DA (e.g., around the periphery of the display area DA).

[0082] Part or all of the first gate drive circuit DRV1 and the second gate drive circuit DRV2 may be formed in (e.g., directly formed in) the peripheral area PA of the substrate 100 during a process of forming a pixel circuit in the display area DA of the substrate 100. The display driver 32 may be formed as an integrated circuit chip and may be located on a display circuit board 30 electrically connected to a terminal unit PAD located on one side of the substrate 100. The display circuit board 30 may be a flexible printed circuit board (FPCB). In another embodiment, the display driver 32 may be directly positioned on the substrate using a chip-on-glass (COG) method or a chip-on-plastic (COP) method.

[0083] In an embodiment, the plurality of transistors included in the pixel circuits of the display area DA may be N-type oxide thin film transistors. The plurality of transistors included in the external circuits of the peripheral area PA (such as the first gate drive circuit DRV1 and the second gate drive circuit DRV2 as an example) may be P-type silicon thin film transistors.

[0084] In an embodiment, some of the multiple transistors included in the pixel circuit of the display area DA may be N-type oxide thin film transistors, and other transistors may be P-type silicon thin film transistors, and the multiple transistors included in the external circuit of the peripheral area PA may be P-type silicon thin film transistors.

[0085] In an embodiment, a plurality of transistors included in the pixel circuit of the display area DA may be N-type oxide thin film transistors, and some of a plurality of transistors included in the external circuit of the peripheral area PA may be N-type oxide thin film transistors, and the other transistors may be P-type silicon thin film transistors.

[0086] In an embodiment, some of the plurality of transistors included in the pixel circuit of the display area DA and the plurality of transistors included in the external circuit of the peripheral area PA may be N-type oxide thin film transistors, and the other transistors may be P-type silicon thin film transistors.

[0087] In an oxide thin film transistor, the semiconductor layer may include an oxide. The oxide semiconductor may include a Zn oxide-based material, such as Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. In some embodiments, the oxide semiconductor may be an In-Ga-Zn-O (IGZO) semiconductor containing a metal such as indium (In) or gallium (Ga) in ZnO. In an embodiment, the oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor. The silicon thin film transistor may be a low temperature polycrystalline silicon (LTPS) thin film transistor in which the semiconductor layer includes amorphous silicon or polycrystalline silicon.

[0088] Figures 3a to 3dis schematically shown along Figure 2 1-1' is a cross-sectional view of the display panel taken along line II'.

[0089] refer to Figures 3a to 3d , the pixel PX may be located in the display area DA of the substrate 100, and the driving circuit PCb may be located in the peripheral area PA. The driving circuit PCb may be Figure 2 Any one of the first gate driving circuit DRV1 and the second gate driving circuit DRV2.

[0090] The pixel PX may include a pixel circuit PCa and a light emitting element DE as a display element connected to the pixel circuit PCa. An insulating layer IL may be provided between the substrate 100 and the light emitting element DE. The insulating layer IL may include one or more inorganic insulating layers and / or one or more organic insulating layers.

[0091] In an embodiment, Figure 3a As shown in , the pixel circuit PCa may include at least one oxide thin film transistor TFTo, and the driving circuit PCb may include at least one silicon thin film transistor TFTs.

[0092] In an embodiment, Figure 3b As shown in , the pixel circuit PCa may include at least one oxide thin film transistor TFTo and at least one silicon thin film transistor TFTs, and the driving circuit PCb may include at least one silicon thin film transistor TFTs.

[0093] In an embodiment, Figure 3c As shown in , the pixel circuit PCa may include at least one oxide thin film transistor TFTo, and the driving circuit PCb may include at least one silicon thin film transistor TFTs and at least one oxide thin film transistor TFTo.

[0094] In an embodiment, Figure 3d As shown in , the pixel circuit PCa and the driving circuit PCb may include at least one oxide thin film transistor TFTo and at least one silicon thin film transistor TFTs.

[0095] The oxide thin film transistor TFTo may include a semiconductor layer containing an oxide (hereinafter referred to as an oxide semiconductor layer) OACT, a gate electrode GE1, a source electrode SE1, and a drain electrode DE1. The source electrode SE1 and the drain electrode DE1 may be electrically connected to the source region and the drain region of the oxide semiconductor layer OACT, respectively. The gate electrode GE1 may overlap with the channel region of the oxide semiconductor layer OACT. One of the source electrode SE1 and the drain electrode DE1 (for example, the source electrode SE1) may be electrically connected to the pixel electrode PE of the light-emitting element DE. The light-emitting element DE may include the pixel electrode PE, an emission layer EL, and a counter electrode CE.

[0096] The silicon thin film transistor TFTs may include a semiconductor layer containing silicon (hereinafter, silicon semiconductor layer) SACT, a gate electrode GE2, a source electrode SE2, and a drain electrode DE2. The source electrode SE2 and the drain electrode DE2 may be electrically connected to the source region and the drain region of the silicon semiconductor layer SACT, respectively. The gate electrode GE2 may overlap with the channel region of the silicon semiconductor layer SACT.

[0097] Since the oxide semiconductor layer OACT constituting the oxide thin film transistor TFTo is formed after the silicon semiconductor layer SACT constituting the silicon thin film transistor TFTs is formed, Figures 3a to 3d As shown in , the oxide semiconductor layer OACT may be formed over (eg, formed in a layer above) the silicon semiconductor layer SACT.

[0098] In an embodiment, the semiconductor pattern CP may be located around the pixel circuit PCa (e.g., adjacent to the pixel circuit PCa). The semiconductor pattern CP may include the same material as the silicon semiconductor layer SACT. For example, the semiconductor pattern CP may include a silicon semiconductor. The semiconductor pattern CP may be an LTPS pattern. The semiconductor pattern CP may be formed in the display area DA concurrently or simultaneously with the formation of the silicon semiconductor layer SACT of the silicon thin film transistors TFTs. The semiconductor pattern CP may function as a portion of an independent transistor or conductive line separated from the pixel circuit PCa in the display area DA.

[0099] Figures 4a to 8b is a view schematically illustrating a semiconductor pattern of a display region according to one or more embodiments.

[0100] refer to Figures 4a to 4d In an embodiment, the semiconductor pattern CP may be an element of a transistor in the display area DA. For example, the semiconductor pattern CP may be a semiconductor layer of a silicon thin film transistor TRs. The silicon thin film transistor TRs may be an LTPS thin film transistor.

[0101] The semiconductor pattern CP may extend in the x-direction and may be located in each row. The conductive layer DCL may extend in the x-direction on the semiconductor pattern CP and may be located in each row. In each row, the conductive layer DCL may be located above the semiconductor pattern CP so as to overlap with the semiconductor pattern CP. The two ends (e.g., opposite ends) of the semiconductor pattern CP at the edge of the display area DA may not overlap with the conductive layer DCL. The conductive layer DCL may include the same material as the gate electrode GE2 of the thin film transistor TFT2. The conductive layer DCL may be formed in the display area DA concurrently or simultaneously with the formation of the gate electrode GE2 of the thin film transistor TFT2 in the peripheral area PA.

[0102] In each row, the semiconductor pattern CP and the conductive layer DCL may correspond to the silicon semiconductor layer and the gate electrode of the silicon thin film transistor TRs, respectively. The two ends (e.g., opposite ends) of the semiconductor pattern CP that do not overlap with the conductive layer DCL may correspond to the source region (e.g., source electrode) and the drain region (e.g., drain electrode). The portion of the semiconductor pattern CP that overlaps with the conductive layer DCL may correspond to the channel region between the source region and the drain region. The length of the channel region of the silicon thin film transistor TRs and the length of the portion corresponding to the channel region of the semiconductor pattern CP may be or may substantially be the length of a row (e.g., pixel line) of the display area DA.

[0103] The semiconductor pattern CP and the conductive layer DCL may be electrically connected to a signal line SCL. The signal line SCL may extend in the y-direction. The signal line SCL may receive a DC voltage such as a driving voltage ELVDD, a first initialization voltage Vint, a second initialization voltage Vaint, or a reference voltage Vref. Thus, each of the gate electrode, the source region (e.g., the source electrode), and the drain region (e.g., the drain electrode) of the silicon thin film transistor TRs may receive the driving voltage ELVDD, the first initialization voltage Vint, the second initialization voltage Vaint, or the reference voltage Vref.

[0104] In an embodiment, the silicon thin film transistor TRs may be as follows Figure 4c The P-type LTPS thin film transistor shown in FIG, or may be as shown in FIG. Figure 4d N-type LTPS thin film transistor shown in. Figures 4a to 4d An example is shown in which the same voltage is applied to the gate electrode, the source region (eg, the source electrode), and the drain region (eg, the drain electrode) of the silicon thin film transistor TRs.

[0105] In another embodiment, the voltage applied to the gate electrode of the silicon thin film transistor TRs and the voltage applied to the source region (eg, source electrode) and the drain region (eg, drain electrode) may be different from each other. Figure 4e and Figure 4f As shown in , the conductive layer DCL may be electrically connected to the first signal line SCL1, and the semiconductor pattern CP may be electrically connected to the second signal line SCL2. Figure 4f As shown in , the first signal line SCL1 and the second signal line SCL2 may be located at the same layer as each other (e.g., located in the same layer or on the same layer as each other), or may be located at different layers from each other (e.g., located in different layers or on different layers from each other). The first signal line SCL1 may receive a driving voltage ELVDD, and the second signal line SCL2 may receive a DC voltage different from the driving voltage ELVDD, such as a first initialization voltage Vint, a second initialization voltage Vaint, or a reference voltage Vref, for example. Therefore, as Figure 4g As shown in , the gate electrode of the silicon thin film transistor TRs may receive the driving voltage ELVDD, and the source region (eg, source electrode) and the drain region (eg, drain electrode) may receive the first initialization voltage Vint, the second initialization voltage Vaint, or the reference voltage Vref.

[0106] Figures 4a to 4g The silicon thin film transistor TRs shown in FIG. 5 may be a non-operation transistor that does not participate in the operation of the pixel PX or the light emission of the pixel PX and may always be in an off state and thus not operate.

[0107] In another embodiment, the silicon thin film transistor TRs may be an operation transistor that does not participate in the operation of the pixel PX or the light emission of the pixel PX but may always operate in an on state (eg, may always be in an on state).

[0108] The silicon thin film transistor TRs that is always in the on state can be implemented by applying a voltage higher than the voltage applied to the gate electrode to the source region (e.g., source electrode) and drain region (e.g., drain electrode) of the P-type LTPS thin film transistor and / or by applying a voltage lower than the voltage applied to the gate electrode to the source region (e.g., source electrode) and drain region (e.g., drain electrode) of the N-type LTPS thin film transistor. For example, Figure 4e and Figure 4f As shown in , the conductive layer DCL may be electrically connected to the first signal line SCL1, and the semiconductor pattern CP may be electrically connected to the second signal line SCL2. Figure 4h As shown in , in the silicon thin film transistor TRs implemented as a P-type LTPS thin film transistor, the gate electrode can receive the first initialization voltage Vint, the second initialization voltage Vaint or the reference voltage Vref, and the source region (e.g., source electrode) and the drain region (e.g., drain electrode) can receive the driving voltage ELVDD. As another example, Figure 4iAs shown in , in the silicon thin film transistor TRs implemented as an N-type LTPS thin film transistor, the gate electrode can receive the driving voltage ELVDD, and the source region (e.g., the source electrode) and the drain region (e.g., the drain electrode) can receive the first initialization voltage Vint, the second initialization voltage Vaint or the reference voltage Vref.

[0109] Figures 4a to 4i 1 shows an example in which one silicon thin film transistor TRs is formed in each row. Figures 5a to 5c As shown in , a plurality of silicon thin film transistors TRs connected in series with each other may be formed in each row.

[0110] The semiconductor pattern CP may extend in the x-direction and may be located in each row. A plurality of conductive electrodes DCE, each having an island shape, may be located above the semiconductor pattern CP in each row. In each row, the conductive electrodes DCE may be located above the semiconductor pattern CP so as to be spaced apart from each other in the x-direction and may overlap with the semiconductor pattern CP. The conductive electrode DCE may include the same material as the gate electrode GE2 of the thin-film transistor TFT2. The conductive electrode DCE may be formed in the display area DA concurrently or simultaneously with the formation of the gate electrode GE2 of the thin-film transistor TFT2 in the peripheral area PA.

[0111] In each row, the semiconductor pattern CP and the conductive electrode DCE may correspond to the silicon semiconductor layer and gate electrode of the silicon thin film transistor TRs, respectively. The portion of the semiconductor pattern CP that does not overlap with the conductive electrode DCE may correspond to the source region (e.g., source electrode) and the drain region (e.g., drain electrode). The portion of the semiconductor pattern CP that overlaps with the conductive electrode DCE may correspond to the channel region between the source region and the drain region. The length of the channel region of the silicon thin film transistor TRs and the length of the portion corresponding to the channel region of the semiconductor pattern CP may be or may substantially be the length of the conductive electrode DCE in the x-direction.

[0112] The semiconductor pattern CP and the conductive electrode DCE can be electrically connected to the signal line SCL. The signal line SCL can extend in the y direction and can receive the driving voltage ELVDD. Therefore, each of the gate electrode, the source region (e.g., the source electrode), and the drain region (e.g., the drain electrode) of the silicon thin film transistor TRs can receive the driving voltage ELVDD. The intermediate node N between adjacent silicon thin film transistors TRs can be a portion of the semiconductor pattern CP that does not overlap with the conductive electrode DCE between adjacent conductive electrodes DCE. In the intermediate node N, the signal line SCL can contact the semiconductor pattern CP so that the signal line SCL and the semiconductor pattern CP are electrically connected to each other. Figure 5bAs shown in , each signal line SCL may be a source electrode or a drain electrode electrically connected to a gate electrode.

[0113] Similar to Figure 4c and Figure 4d In addition to the driving voltage ELVDD, each of the gate electrode, source region (e.g., source electrode), and drain region (e.g., drain electrode) of each of the silicon thin film transistors TRs may also receive a first initialization voltage Vint, a second initialization voltage Vaint, or a reference voltage Vref. The silicon thin film transistors TRs may be a P-type LTPS thin film transistor or an N-type LTPS thin film transistor.

[0114] In an embodiment, Figures 6a to 6c As shown in , the semiconductor pattern CP may be an element of the 4-terminal silicon thin film transistor TRs in the display area DA. For example, the semiconductor pattern CP may be a semiconductor layer of the silicon thin film transistor TRs.

[0115] The semiconductor pattern CP may extend in the x-direction and may be located in each row. The upper conductive layer DCLt may be located above the semiconductor pattern CP. The upper conductive layer DCLt may extend in the x-direction and may be located in each row. The upper conductive layer DCLt may overlap with the semiconductor pattern CP. The lower conductive layer DCLb may be located below the semiconductor pattern CP. The lower conductive layer DCLb may extend in the x-direction and may be located in each row. The semiconductor pattern CP may be located above the lower conductive layer DCLb so as to overlap with the lower conductive layer DCLb. Both ends (e.g., opposite ends) of the semiconductor pattern CP at the edge of the display area DA may not overlap with the upper conductive layer DCLt. The upper conductive layer DCLt may include the same material as the gate electrode GE2 of the thin film transistor TFT2. The upper conductive layer DCLt may be formed in the display area DA concurrently or simultaneously with the formation of the gate electrode GE2 of the thin film transistor TFT2 in the peripheral area PA.

[0116] In each row, the semiconductor pattern CP, the upper conductive layer DCLt, and the lower conductive layer DCLb may correspond to the silicon semiconductor layer, the top gate electrode, and the bottom gate electrode of the four-terminal silicon thin film transistor TRs, respectively. The two ends (e.g., opposite ends) of the semiconductor pattern CP that do not overlap with the upper conductive layer DCLt may correspond to the source region (e.g., source electrode) and the drain region (e.g., drain electrode). The portion of the semiconductor pattern CP that overlaps with the upper conductive layer DCLt may correspond to the channel region between the source region and the drain region. The length of the channel region of the four-terminal silicon thin film transistor TRs and the length of the portion corresponding to the channel region of the semiconductor pattern CP may be or may substantially be the length of the row of the display area DA.

[0117] The semiconductor pattern CP, the upper conductive layer DCLt, and the lower conductive layer DCLb may be electrically connected to a signal line SCL. The signal line SCL may extend in the y-direction and may receive a driving voltage ELVDD. Thus, each of the gate electrode, source region (e.g., source electrode), and drain region (e.g., drain electrode) of the silicon thin film transistor TRs may receive the driving voltage ELVDD.

[0118] Figures 6a to 6c An example of forming a 4-terminal silicon thin film transistor TRs in each row is shown. Figure 5a , a plurality of upper conductive layers DCLt each having an island shape may be spaced apart from each other in the x-direction to overlap the semiconductor pattern CP, thereby forming a plurality of 4-terminal silicon thin film transistors TRs connected in series to each other.

[0119] refer to Figures 7a to 7c In an embodiment, the semiconductor pattern CP may be an element of the silicon thin film transistor TRds in the display area DA. For example, the semiconductor pattern CP may be a semiconductor layer of the silicon thin film transistor TRds. The silicon thin film transistor TRds may be an operating transistor that does not participate in the operation of the pixel PX or the light emission of the pixel PX but operates based on a signal applied to a gate electrode. The silicon thin film transistor TRds may be an LTPS thin film transistor.

[0120] Multiple semiconductor patterns CP may be located in each row. In each row, the multiple semiconductor patterns CP may be spaced apart from each other in the x-direction. A conductive layer DCL may extend in the x-direction and may be located in each row. In each row, the conductive layer DCL may be located above the multiple semiconductor patterns CP, may cross the semiconductor patterns CP, and may partially overlap with the semiconductor patterns CP. The conductive layer DCL may include the same material as the gate electrode GE2 of the thin-film transistor TFT2. The conductive layer DCL may be formed in the display area DA concurrently or simultaneously with the formation of the gate electrode GE2 of the thin-film transistor TFT2 in the peripheral area PA.

[0121] Both ends (e.g., opposite ends) of the semiconductor pattern CP can be electrically connected to the signal line SCL to receive the driving voltage ELVDD. Both ends (e.g., opposite ends) of the conductive layer DCL can be connected to the first gate driving circuit DRV1 and / or the second gate driving circuit DRV2. The conductive layer DCL can receive the gate signal GS from the first gate driving circuit DRV1 and / or the second gate driving circuit DRV2.

[0122] The semiconductor pattern CP and the conductive layer DCL portions overlapping the semiconductor pattern CP may correspond to the silicon semiconductor layer and gate electrode of the silicon thin film transistor TRds, respectively. A plurality of silicon thin film transistors TRds connected in parallel to each other may be provided in each row. The two ends (e.g., opposite ends) of the semiconductor pattern CP that do not overlap with the conductive layer DCL may correspond to the source region (e.g., source electrode) and the drain region (e.g., drain electrode). The portion of the semiconductor pattern CP that overlaps with the conductive layer DCL may correspond to the channel region between the source region and the drain region. The length of the channel region of the silicon thin film transistor TRs and the length of the portion corresponding to the channel region of the semiconductor pattern CP may be or may substantially be the width of the conductive layer DCL in the y direction.

[0123] The semiconductor pattern CP may receive a driving voltage ELVDD from the signal line SCL, and the conductive layer DCL may receive a gate signal GS from the first gate driving circuit DRV1 and / or the second gate driving circuit DRV2 so that the silicon thin film transistor TRds operates in response to the gate signal GS.

[0124] refer to Figure 8a and Figure 8b In an embodiment, a semiconductor pattern CP in a floating state may be located in the display area DA, and a conductive layer DCL supplied with a constant voltage (e.g., a specific or predetermined constant voltage) may be located above the semiconductor pattern CP to overlap with the semiconductor pattern CP. The semiconductor pattern CP may extend in the x-direction and may be located in each row. The conductive layer DCL may extend in the x-direction and may be located in each row. The conductive layer DCL may be electrically connected to a signal line SCL. The signal line SCL may extend in the y-direction and may receive a driving voltage ELVDD. In another embodiment, the conductive layer DCL may be omitted. Figure 8a and Figure 8b The conductive layer DCL shown in FIG, and only the semiconductor patterns CP in a floating state may extend in the x-direction and may be located in each row.

[0125] In another embodiment, the semiconductor pattern CP can be designed in the display area DA to serve as a connecting line connecting elements constituting the pixel circuit PCa in the display area DA to each other, or as a constant voltage line supplying a voltage (e.g., a specific or predetermined voltage) to the pixel circuit PCa.

[0126] Figure 9a and Figure 9b is an equivalent circuit diagram showing a pixel according to the embodiment.

[0127] refer to Figure 9a and Figure 9b, the pixel PX may include an organic light emitting diode OLED as a display element and a pixel circuit PCa connected to the organic light emitting diode OLED.

[0128] The pixel PX may be connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GIL transmitting a second gate signal GI, a third gate line GRL transmitting a third gate signal GR, a fourth gate line EML transmitting a fourth gate signal EM, a fifth gate line EMBL transmitting a fifth gate signal EMB, and a data line DL transmitting a data signal Vdata. Because light emission of the pixel PX is controlled by the fourth gate signal EM and the fifth gate signal EMB, the fourth gate signal EM and the fifth gate signal EMB may be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL may be referred to as emission control lines.

[0129] The pixel PX may be connected to a driving voltage line PL transmitting a driving voltage ELVDD, a reference voltage line VRL transmitting a reference voltage Vref, a first initialization voltage line VL1 transmitting a first initialization voltage Vint, and a second initialization voltage line VL2 transmitting a second initialization voltage Vaint.

[0130] The voltage level of the driving voltage ELVDD may be higher than the voltage level of the common voltage ELVSS. The voltage level of the reference voltage Vref may be lower than the voltage level of the driving voltage ELVDD. The voltage level of the first initialization voltage Vint may be lower than the voltage level of the common voltage ELVSS. The voltage level of the second initialization voltage Vaint may be higher than the voltage level of the first initialization voltage Vint. The voltage level of the second initialization voltage Vaint may be equal to or higher than the voltage level of the common voltage ELVSS.

[0131] The pixel circuit PCa may include first to seventh transistors T1 to T7 and first to second capacitors C1 and C2. Figure 9a As shown in FIG, the first transistor T1 to the seventh transistor T7 may be N-type oxide thin film transistors. Figure 9b As shown in , among the first to seventh transistors T1 to T7 , the first to fourth transistors T1 to T4 and the seventh transistor T7 may be N-type oxide thin film transistors, and the fifth transistor T5 and the sixth transistor T6 may be P-type silicon thin film transistors.

[0132] The first transistor T1 may be a driving transistor that outputs a driving current corresponding to a data signal. The second transistor T2 to the seventh transistor T7 may be switching transistors that transmit a signal. The first terminal (e.g., a first electrode) and the second terminal (e.g., a second electrode) of each of the first transistor T1 to the seventh transistor T7 may be a source or a drain depending on the voltage of the first terminal and the second terminal. For example, depending on the voltage of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain.

[0133] A node connected to the first gate of the first transistor T1 may be defined as a first node N1. A node connected to the second terminal of the first transistor T1 may be defined as a second node N2.

[0134] The first transistor T1 may be connected between the driving voltage line PL and the organic light emitting diode OLED. The first transistor T1 may be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may include a gate, a first terminal, and a second terminal, the second terminal being connected to the second node N2. The gate of the first transistor T1 may include a first gate connected to the first node N1 and a second gate connected to the second node N2. The first gate and the second gate may be located at different layers from each other (for example, in different layers or on different layers) to face each other. For example, the first gate and the second gate of the first transistor T1 may face each other, with the semiconductor layer interposed between the first gate and the second gate of the first transistor T1.

[0135] The first gate of the first transistor T1 can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The second gate of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 can be connected to the driving voltage line PL via the fifth transistor T5, and the second terminal can be connected to the pixel electrode of the organic light emitting diode OLED via the sixth transistor T6. The second terminal of the first transistor T1 can be connected to the first terminal of the fourth transistor T4, the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 can receive the data signal Vdata according to the switching operation of the second transistor T2 and can control the amount of driving current flowing to the organic light emitting diode OLED.

[0136] The second transistor T2 (e.g., a write transistor) can be connected to the data line DL and the first gate of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 may be connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 may be turned on by a first gate signal GW transmitted via the first gate line GWL to electrically connect the data line DL to the first node N1 and transmit the data signal Vdata transmitted via the data line DL to the first node N1.

[0137] The third transistor T3 (e.g., a first initialization transistor) can be connected to the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 may be turned on by a third gate signal GR transmitted via the third gate line GRL to transmit the reference voltage Vref transmitted via the reference voltage line VRL to the first node N1.

[0138] The fourth transistor T4 (e.g., a second initialization transistor) can be connected to the first transistor T1 and the first initialization voltage line VL1. The fourth transistor T4 can include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1. The first terminal of the fourth transistor T4 can be connected to the second terminal of the first transistor T1, the first terminal of the sixth transistor T1, the first capacitor C1, and the second capacitor C2. The fourth transistor T4 can be turned on by the second gate signal GI transmitted via the second gate line GIL to transmit the first initialization voltage Vint transmitted via the first initialization voltage line VL1 to the second node N2.

[0139] A fifth transistor T5 (e.g., a first emission control transistor) may be connected to the driving voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to a fourth gate line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 may be turned on or off according to a fourth gate signal EM transmitted via the fourth gate line EML.

[0140] A sixth transistor T6 (e.g., a second light emission control transistor) may be connected to the first transistor T1 and the organic light emitting diode OLED. The sixth transistor T6 may be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 may be connected to the second terminal of the first transistor T1, the first terminal of the fourth transistor T4, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 may be connected to the first terminal of the seventh transistor T7 and the pixel electrode of the organic light emitting diode OLED. The sixth transistor T6 may be turned on or off according to a fifth gate signal EMB transmitted via the fifth gate line EMBL.

[0141] A seventh transistor T7 (e.g., a third initialization transistor or a reset transistor) may be connected between the organic light emitting diode OLED and the second initialization voltage line VL2. The seventh transistor T7 may be connected between the sixth transistor T6 and the second initialization voltage line VL2. The seventh transistor T7 may include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the second initialization voltage line VL2. The first terminal of the seventh transistor T7 may be connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED. The seventh transistor T7 may be turned on by a second gate signal GI transmitted via the second gate line GIL to transmit the second initialization voltage Vaint transmitted via the second initialization voltage line VL2 to the third node N3.

[0142] The first capacitor C1 may be connected between the first gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 may be connected to the first node N1, and the second electrode may be connected to the second node N2. The first electrode of the first capacitor C1 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 may be connected to the second terminal and the gate of the first transistor T1, the second electrode of the second capacitor C2, the first terminal of the fourth transistor T4, and the first terminal of the sixth transistor T6. The first capacitor C1 may be a storage capacitor for storing a voltage corresponding to the data signal Vdata and the threshold voltage of the first transistor T1.

[0143] The second capacitor C2 may be connected between the driving voltage line PL and the second node N2. A first electrode of the second capacitor C2 may be connected to the driving voltage line PL. A second electrode of the second capacitor C2 may be connected to the second terminal and the second gate of the first transistor T1, the second electrode of the first capacitor C1, the first terminal of the fourth transistor T4, and the first terminal of the sixth transistor T6. The capacitance of the first capacitor C1 may be greater than that of the second capacitor C2.

[0144] The organic light emitting diode OLED may be connected to the first transistor T1 via the sixth transistor T6. The organic light emitting diode OLED may include a pixel electrode (e.g., an anode) connected to the third node N3 and an opposite electrode (e.g., a cathode) facing the pixel electrode. The opposite electrode may receive a common voltage ELVSS. The opposite electrode may be a common electrode common to a plurality of pixels PX.

[0145] Figures 10 to 23 It is a schematic diagram showing the Figure 9a A view of an element of a layer of pixels. Figure 16 is a view showing elements of the first circuit area PCA1. Figure 21 is a diagram schematically illustrating a conductive layer at an edge of a display area according to an embodiment. Figure 22 It is along Figure 20 Line VII-VII' and Figure 21 A cross-sectional view taken along line IX-IX'. Figure 24 is a view schematically illustrating an arrangement of emission regions of a plurality of pixels according to an embodiment. Figure 25 It is along Figure 20 and Figure 23 A cross-sectional view taken along line VIII-VIII'.

[0146] The plurality of pixels PX located in the display area DA may include a first pixel PX1 for emitting light of a first color, a second pixel PX2 for emitting light of a second color, and a third pixel PX3 for emitting light of a third color. For example, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be repeatedly arranged along the x-direction and the y-direction according to a suitable pattern (e.g., a specific or predetermined pattern). Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a corresponding pixel circuit PCa and a corresponding organic light emitting diode OLED as a display element electrically connected to the pixel circuit PCa.

[0147] The display area DA defined on the substrate 100 may include a plurality of circuit areas where pixel circuits are located and where rows and columns intersect with each other. In an embodiment, a unit circuit area may be defined that includes two or more circuit areas adjacent to each other in the x-direction. For example, the unit circuit area PCAu may include three circuit areas adjacent to each other in the x-direction, such as a first circuit area PCA1, a second circuit area PCA2, and a third circuit area PCA3. The first circuit area PCA1 may be the area where the pixel circuit PCa of the first pixel PX1 is located. The second circuit area PCA2 may be the area where the pixel circuit PCa of the second pixel PX2 is located. The third circuit area PCA3 may be the area where the pixel circuit PCa of the third pixel PX3 is located.

[0148] The pixel circuits PCa located in the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3 can be electrically connected to display elements that emit light of different colors. The pixel circuits PCa located in the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3 can drive the display elements electrically connected thereto. For example, the display element electrically connected to the pixel circuit PCa located in the first circuit area PCA1 can emit red light. The display element electrically connected to the pixel circuit PCa located in the second circuit area PCA2 can emit green light. The display element electrically connected to the pixel circuit PCa located in the third circuit area PCA3 can emit blue light.

[0149] In an embodiment, by considering the light-emitting characteristics of the first pixel PX1, the second pixel PX2, and the third pixel PX3, different second initialization voltages Vaint may be supplied to the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, the pixel circuit PCa of the first pixel PX1 may be connected to the 2-1st initialization voltage line VL21. The pixel circuit PCa of the second pixel PX2 and the pixel circuit PCa of the third pixel PX3 may be connected to the 2-2nd initialization voltage line VL22. The second initialization voltage supplied to the 2-1st initialization voltage line VL21 and the second initialization voltage supplied to the 2-2nd initialization voltage line VL22 may be different from each other.

[0150] The same components may be located on each layer for the first, second, and third circuit areas PCA1, PCA2, and PCA3. For convenience, reference numerals may be assigned to components of the pixel circuit PCa located in the first circuit area PCA1, and the first circuit area PCA1 may be primarily described in more detail below. Thus, redundant descriptions of components in the second and third circuit areas PCA2 and PCA3 that are the same or substantially the same as those described in more detail below with respect to the first circuit area PCA1 may not be repeated. Figure 22 and Figure 25 The cross-sectional view is a cross-sectional view of the first circuit area PCA1.

[0151] Reference together Figures 10 to 26 ,like Figure 10 As shown in , the first conductive layer 210 may be located on the substrate 100. The substrate 100 may include a glass material, a ceramic material, a metal material or a flexible and / or bendable material. The substrate 100 may have a single-layer structure including an organic layer or a multi-layer structure including an organic layer and an inorganic layer. For example, the substrate 100 may have a stacked structure including a first base layer, a barrier layer and a second base layer. Each of the first base layer and the second base layer may be an organic layer including a polymer resin. Each of the first base layer and the second base layer may include a transparent polymer resin. The barrier layer may prevent or substantially prevent the penetration of external foreign matter and may have a material including a silicon nitride (SiN x ) or silicon oxide (SiO x In another embodiment, a barrier layer may be further located between the substrate 100 and the first conductive layer 210.

[0152] The first conductive layer 210 may extend in the x-direction and may cross the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3. The first conductive layer 210 may correspond to Figure 6a and Figure 6b The lower conductive layer DCLb.

[0153] The first insulating layer 111 may be located on the substrate 100 to cover the first conductive layer 210. A semiconductor pattern CP including a silicon semiconductor may be located on the first insulating layer 111, such as Figure 11 As shown in . The semiconductor pattern CP may extend in the x direction and may cross the first circuit area PCA1, the second circuit area PCA2 and the third circuit area PCA3. The semiconductor pattern CP may correspond to Figure 6a and Figure 6b semiconductor pattern CP.

[0154] The second insulating layer 112 may be located on the first insulating layer 111 to cover the semiconductor pattern CP, and the second conductive layer may be located on the second insulating layer 112. Figure 12 As shown in , the second conductive layer may include a first electrode layer 220, a driving voltage line PL, and a 2-2nd initialization voltage line VL22.

[0155] The drive voltage line PL and the 2-2 initialization voltage line VL22 may extend in the x-direction and may span the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3. The drive voltage line PL may include a protrusion PLa protruding in the +y direction from the main line PLm extending in the x-direction, and a protrusion PLb protruding in the -y direction. The protrusions PLa and PLb may be located in each circuit area. A portion of the drive voltage line PL may include the first electrode C21 of the second capacitor C2. The first electrode layer 220 may be provided in an island shape. The first electrode layer 220 may include the lower electrode G11b of the first gate electrode G11 of the first transistor T1 and the first electrode C11 of the first capacitor C1.

[0156] The third insulating layer 113 may be located on the second insulating layer 112 to cover the second conductive layer, and the third conductive layer may be located on the third insulating layer 113. Figure 13 As shown in , the third conductive layer may include a second electrode layer 230 , a reference voltage line VRL, and a first initialization voltage line VL1 .

[0157] The second electrode layer 230 may be provided in an island shape. The second electrode layer 230 may overlap the first electrode layer 220 and the main line PLm of the driving voltage line PL. The portion of the second electrode layer 230 overlapping the first electrode layer 220 may include the second electrode C12 of the first capacitor C1. The portion of the second electrode layer 230 overlapping the main line PLm of the driving voltage line PL may include the second gate electrode G12 of the first transistor T1 and the second electrode C22 of the second capacitor C2.

[0158] The reference voltage line VRL and the first initialization voltage line VL1 may extend in the x-direction and may cross the first, second, and third circuit areas PCA1, PCA2, and PCA3.

[0159] In an embodiment, the third conductive layer may further include a repair line RL. The repair line RL may extend in the x-direction and may cross the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3.

[0160] The fourth insulating layer 114 may be located on the third insulating layer 113 to cover the third conductive layer, and a semiconductor layer OACT including an oxide semiconductor may be located on the fourth insulating layer 114, as shown in FIG. Figure 14As shown in . The semiconductor layer OACT may include a first semiconductor layer OACT1, a second semiconductor layer OACT2, a third semiconductor layer OACT3, and a fourth semiconductor layer OACT4. The semiconductor layer OACT may include a channel region for each of the first transistor T1 to the seventh transistor T7 and a source region and a drain region on both sides (e.g., opposite sides) of the channel region. As needed or desired, the source region or the drain region may be interpreted as a source electrode or a drain electrode of the transistor.

[0161] refer to Figure 16 The first semiconductor layer OACT1 may include the source region S1 and drain region D1 of the first transistor T1, and the source region S5 and drain region D5 of the fifth transistor T5. The second semiconductor layer OACT2 may include the source region S2 and drain region D2 of the second transistor T2, and the source region S3 and drain region D3 of the third transistor T3. The third semiconductor layer OACT3 may include the source region S6 and drain region D6 of the sixth transistor T6, and the source region S7 and drain region D7 of the seventh transistor T7. The fourth semiconductor layer OACT4 may include the source region S4 and drain region D4 of the fourth transistor T4.

[0162] A fifth insulating layer 115 may be located on the fourth insulating layer 114 to cover the semiconductor layer OACT, and a fourth conductive layer may be located on the fifth insulating layer 115. Figure 15 and Figure 16 As shown in , the fourth conductive layer may include gate electrodes G1 to G7 of the first to seventh transistors T1 to T7. In addition, the fourth conductive layer may include first, second, third, fourth, and fifth gate lines GWL, GIL, GRL, EML, and EMBL, and a 2-1st initialization voltage line VL21.

[0163] The gate electrodes G1 to G7 of the first to seventh transistors T1 to T7 may overlap with the channel region of the semiconductor layer OACT.

[0164] refer to Figure 16The third electrode layer 240 may include an upper electrode G11t of the first gate electrode G11 of the first transistor T1. The upper electrode G11t of the first gate electrode G11 may overlap the first semiconductor layer OACT1. The fourth electrode layer 250 may be the gate electrode G2 of the second transistor T2. The fourth electrode layer 250 may overlap the second semiconductor layer OACT2. The third and fourth electrode layers 240 and 250 may be provided in an island shape. The gate electrode G3 of the third transistor T3 may be a portion of the third gate line GRL that overlaps the second semiconductor layer OACT2. The gate electrode G4 of the fourth transistor T4 may be a portion of the second gate line GIL that overlaps the fourth semiconductor layer OACT4. The gate electrode G5 of the fifth transistor T5 may be a portion of the fourth gate line EML that overlaps the first semiconductor layer OACT1. The gate electrode G6 of the sixth transistor T6 may be a portion of the fifth gate line EMBL that overlaps the third semiconductor layer OACT3. The gate electrode G7 of the seventh transistor T7 may be a portion of the second gate line GIL that overlaps the third semiconductor layer OACT3.

[0165] The sixth insulating layer 116 may be located on the fifth insulating layer 115 to cover the fourth conductive layer, and the fifth conductive layer may be located on the sixth insulating layer 116. Figure 17 As shown in , the fifth conductive layer may include the data lines DL and the connection electrodes 260 , 261 , 262 , 263 , 264 , 265 , 266 , 267 a , 267 b , and 268 .

[0166] The data line DL may extend in the y direction and may be located in each circuit region. The data line DL may be electrically connected to the drain region D2 of the second transistor T2 through a contact hole 37 passing through (eg, penetrating) the fifth insulating layer 115 and the sixth insulating layer 116 .

[0167] The connection electrode 260 may include a first region 260a overlapping the second and third electrode layers 230 and 240 and a second region 260b protruding in the -y direction from the first region 260a. The connection electrode 260 may electrically connect the source region S1 of the first transistor T1 to the fourth and sixth transistors T4 and T6.

[0168] The first region 260a of the connection electrode 260 can be electrically connected to the source region S1 of the first transistor T1 via a contact hole 31 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The first region 260a of the connection electrode 260 can be electrically connected to the second electrode layer 230 via a contact hole 32 passing through (e.g., penetrating) the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. Thus, the second electrode layer 230 can be a source electrode electrically connected to the source region S1 of the first transistor T1. The second region 260b of the connection electrode 260 can be electrically connected to the drain region D6 of the sixth transistor T6 via a contact hole 33 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The second region 260b of the connection electrode 260 can be electrically connected to the drain region D4 of the fourth transistor T4 via a contact hole 34 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116.

[0169] The connection electrode 261 may be electrically connected to the gate electrode G2 of the second transistor T2 via a contact hole 38 passing through (e.g., penetrating) the sixth insulating layer 116. The connection electrode 261 may be electrically connected to the first gate line GWL via a contact hole 39 passing through (e.g., penetrating) the sixth insulating layer 116.

[0170] The connection electrode 262 may be electrically connected to the source region S3 of the third transistor T3 via a contact hole 43 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The connection electrode 262 may be electrically connected to the reference voltage line VRL via a contact hole 44 passing through (e.g., penetrating) the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116.

[0171] The connection electrode 263 may be electrically connected to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 via a contact hole 40 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The connection electrode 263 may be electrically connected to the first electrode layer 220 via a contact hole 41 passing through (e.g., penetrating) the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116, and may be electrically connected to the lower electrode G11b of the first gate electrode G11 of the first transistor T1. The connection electrode 263 may be electrically connected to the third electrode layer 240 via a contact hole 42 passing through (e.g., penetrating) the sixth insulating layer 116, and may be electrically connected to the upper electrode G11t of the first gate electrode G11 of the first transistor T1.

[0172] The connection electrode 264 can be electrically connected to the protrusion PLb of the driving voltage line PL through a contact hole 35 passing through (e.g., penetrating) the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The connection electrode 264 can be electrically connected to the drain region D5 of the fifth transistor T5 through a contact hole 36 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. Therefore, the drain region D5 of the fifth transistor T5 can be electrically connected to the driving voltage line PL.

[0173] The connection electrode 265 may be electrically connected to the source region S6 of the sixth transistor T6 and the drain region D7 of the seventh transistor T7 through a contact hole 45 that passes through (e.g., penetrates) the fifth insulating layer 115 and the sixth insulating layer 116. The connection electrode 265 may overlap a portion of the repair line RL. The connection electrode 265 may be insulated from the repair line RL and may subsequently be electrically connected to the repair line RL if a defect occurs in a pixel circuit located in the corresponding circuit region.

[0174] The connection electrode 266 may be electrically connected to the source region S4 of the fourth transistor T4 through a contact hole 47 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The connection electrode 266 may be connected to the first initialization voltage line VL1 through a contact hole 46 passing through (e.g., penetrating) the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116.

[0175] The connection electrode 267a located in the first circuit area PCA1 can be electrically connected to the source region S7 of the seventh transistor T7 through a contact hole 48 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The connection electrode 267a can be connected to the 2-1st initialization voltage line VL21 through a contact hole 49 passing through (e.g., penetrating) the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The connection electrode 267b located in each of the second circuit area PCA2 and the third circuit area PCA3 can be electrically connected to the source region S7 of the corresponding seventh transistor T7 through a corresponding contact hole 48′ passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The connection electrode 267b can be electrically connected to the 2-2nd initialization voltage line VL22 through a contact hole 49′ passing through (e.g., penetrating) the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116.

[0176] The connection electrode 268 may be electrically connected to the 2-1st initialization voltage line VL21 through a contact hole 50 passing through (e.g., penetrating) the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The connection electrode 268 may be located in some of the second circuit areas PCA2.

[0177] The first gate line GWL, the second gate line GIL, the third gate line GRL, the fourth gate line EML, the fifth gate line EMBL, and the 2-1st initialization voltage line VL21 may extend in the x-direction and may be located in the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3. The 2-1st initialization voltage line VL21 may overlap the repair line RL.

[0178] like Figure 25 As shown in FIG, the main line PLm of the driving voltage line PL and the second electrode layer 230 overlapping the main line PLm can constitute a second capacitor C2. The third electrode layer 240 and the first region 260a of the connecting electrode 260 overlapping the third electrode layer 240 can constitute a 1-1 capacitor C1a. The first electrode layer 220 and the second electrode layer 230 overlapping the first electrode layer 220 can constitute a 1-2 capacitor C1b. Due to the parallel connection of the 1-1 capacitor C1a and the 1-2 capacitor C1b, the capacitance of the first capacitor C1 can be the sum of the capacitance of the 1-1 capacitor C1a and the capacitance of the 1-2 capacitor C1b. Because the 1-1 capacitor C1a and the 1-2 capacitor C1b vertically overlap each other, the capacitance can be increased (e.g., ensured) without increasing the area of ​​the first capacitor C1 in the x-direction.

[0179] The seventh insulating layer 117 may be located on the sixth insulating layer 116 to cover the fifth conductive layer, and the sixth conductive layer may be located on the seventh insulating layer 117. Figures 18a to 18d As shown in FIG, the sixth conductive layer may include a plurality of vertical conductive lines and a connecting electrode 270. For ease of illustration, Figures 18a to 18d Only the fifth conductive layer and some layers of the lower conductive layers are shown.

[0180] The connection electrode 270 may be electrically connected to the connection electrode 265 through a contact hole 61 passing through (eg, penetrating) the seventh insulating layer 117 , and may be electrically connected to the source region S6 of the sixth transistor T6 .

[0181] The vertical conductive lines may include a vertical driving voltage line PLv, a vertical initialization voltage line, a common voltage line EOL, and a vertical reference voltage line VRLv. The vertical initialization voltage lines may include a first vertical initialization voltage line VL1v, a 2-1st vertical initialization voltage line VL21v, and a 2-2nd vertical initialization voltage line VL22v. The vertical driving voltage line PLv, the vertical initialization voltage line, the common voltage line EOL, and the vertical reference voltage line VRLv may extend in the y-direction and may be spaced apart from each other along the x-direction in the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3.

[0182] like Figure 19 As shown in FIG, in each unit circuit area PCAu, the vertical driving voltage line PLv, the first vertical initialization voltage line VL1v, the 2-1st vertical initialization voltage line VL21v, the 2-2nd vertical initialization voltage line VL22v, the vertical reference voltage line VRLv, and the common voltage line EOL can be sequentially and repeatedly positioned along the x-direction. For example, in the x-direction, the vertical conductive lines can be arranged in the order of the vertical driving voltage line PLv, the first vertical initialization voltage line VL1v, the common voltage line EOL, the vertical driving voltage line PLv, the 2-1st vertical initialization voltage line VL21v, the common voltage line EOL, the vertical driving voltage line PLv, the vertical reference voltage line VRLv, the common voltage line EOL, the vertical driving voltage line PLv, the 2-2nd vertical initialization voltage line VL22v, and the common voltage line EOL. The vertical conductive lines can be electrically connected to the horizontal conductive lines extending in the x-direction. The horizontal conductive lines may include a driving voltage line PL, a first initialization voltage line VL1 , a 2-1st initialization voltage line VL21 , a 2-2nd initialization voltage line VL22 , and a reference voltage line VRL.

[0183] Figure 18a An example is shown in which the vertical driving voltage line PLv, the 2-1 th vertical initializing voltage line VL21v, and the common voltage line EOL are sequentially positioned in the unit circuit area PCAu along the x direction.

[0184] The vertical driving voltage line PLv may be located at the boundary between the third circuit area PCA3 and the first circuit area PCA1. The 2-1st vertical initialization voltage line VL21v may be located at the boundary between the first circuit area PCA1 and the second circuit area PCA2. The common voltage line EOL may be located at the boundary between the second circuit area PCA2 and the third circuit area PCA3.

[0185] The vertical driving voltage line PLv may overlap with the data line DL located in the first circuit area PCA1. The vertical driving voltage line PLv may include a protrusion PLvp that protrudes in the -x direction and overlaps with the third circuit area PCA3. The protrusion PLvp may be electrically connected to the connection electrode 264 located in the third circuit area PCA3 via a contact hole 62 that passes through (e.g., penetrates) the seventh insulating layer 117. Because the connection electrode 264 is electrically connected to the driving voltage line PL, the vertical driving voltage line PLv may be electrically connected to the driving voltage line PL, and the driving voltage line PL may have a mesh structure in the display area DA.

[0186] The 2-1st vertical initialization voltage line VL21v may overlap with the data line DL located in the second circuit area PCA2. The 2-1st vertical initialization voltage line VL21v may include a protrusion VL21vp that protrudes in the +x direction and overlaps with the second circuit area PCA2. The protrusion VL21vp may be electrically connected to the connection electrode 268 located in the second circuit area PCA2 via a contact hole 63 passing through (e.g., penetrating) the seventh insulating layer 117. Because the connection electrode 268 is electrically connected to the 2-1st initialization voltage line VL21, the 2-1st vertical initialization voltage line VL21v may be electrically connected to the 2-1st initialization voltage line VL21, and the 2-1st initialization voltage line VL21 may have a mesh structure in the display area DA.

[0187] The common voltage line EOL may overlap the data line DL located in the third circuit area PCA3. The common voltage line EOL may be electrically connected to the common voltage supply line 13 located in the peripheral area PA. In an embodiment, the counter electrode may be electrically connected to the common voltage line EOL at regular intervals in the display area DA.

[0188] Figure 18b An example is shown in which the vertical driving voltage line PLv, the first vertical initializing voltage line VL1v, and the common voltage line EOL are sequentially positioned in the unit circuit area PCAu along the x direction.

[0189] The first vertical initialization voltage line VL1v may overlap with the data line DL located in the second circuit area PCA2. The first vertical initialization voltage line VL1v may include a protrusion VL1vp that protrudes in the -x direction and overlaps with the first circuit area PCA1. The protrusion VL1vp may be electrically connected to the connection electrode 266 located in the first circuit area PCA1 through a contact hole 64 that passes through (e.g., penetrates) the seventh insulating layer 117. Because the connection electrode 266 is electrically connected to the first initialization voltage line VL1, the first vertical initialization voltage line VL1v may be electrically connected to the first initialization voltage line VL1, and the first initialization voltage line VL1 may have a mesh structure in the display area DA.

[0190] Figure 18c An example is shown in which the vertical driving voltage line PLv, the vertical reference voltage line VRLv, and the common voltage line EOL are sequentially positioned in the unit circuit area PCAu along the x direction.

[0191] The vertical reference voltage line VRLv may overlap with the data line DL located in the second circuit area PCA2. The vertical reference voltage line VRLv may include a protrusion VRLvp that protrudes in the +x direction and overlaps with the second circuit area PCA2. The protrusion VRLvp may be electrically connected to the connection electrode 262 located in the second circuit area PCA2 via a contact hole 65 that passes through (e.g., penetrates) the seventh insulating layer 117. Because the connection electrode 262 is electrically connected to the reference voltage line VRL, the vertical reference voltage line VRLv may be electrically connected to the reference voltage line VRL, and the reference voltage line VRL may have a mesh structure in the display area DA.

[0192] Figure 18d An example is shown in which the vertical driving voltage line PLv, the 2-2nd vertical initializing voltage line VL22v, and the common voltage line EOL are sequentially located in the unit circuit area PCAu along the x direction.

[0193] The 2-2nd vertical initialization voltage line VL22v may overlap with the data line DL located in the second circuit area PCA2. The 2-2nd vertical initialization voltage line VL22v may include a protrusion VL22vp that protrudes in the +x direction and overlaps with the second circuit area PCA2. The protrusion VL22vp may be electrically connected to the connection electrode 267b located in the second circuit area PCA2 via a contact hole 66 that passes through (e.g., penetrates) the seventh insulating layer 117. Because the connection electrode 267b is electrically connected to the 2-2nd vertical initialization voltage line VL22, the 2-2nd vertical initialization voltage line VL22v may be electrically connected to the 2-2nd initialization voltage line VL22, and the 2-2nd initialization voltage line VL22 may have a mesh structure in the display area DA.

[0194] In some embodiments, a voltage supply line electrically connected to the horizontal conductive line and / or the vertical conductive line may be further located in the peripheral area PA. The voltage supply line may be located on at least one of the upper side, lower side, left side, and / or right side of the display area PA.

[0195] The shapes and positions of the connection electrodes corresponding to the first circuit area PCA1 , the second circuit area PCA2 , and the third circuit area PCA3 may be variously modified according to the positions of the conductive lines located in the circuit areas.

[0196] Figure 20 Shown is located Figure 18a As the pixel circuits in the first circuit area PCA1, the second circuit area PCA2 and the third circuit area PCA3. Figure 6a An enlarged view of part A Figure 21 A pixel located at the edge of the display area DA and a conductive layer located around the pixel are shown.

[0197] As described above, in the display area DA, the semiconductor pattern CP may extend in the x-direction and may be located in each row, and the main line PLm of the driving voltage line PL may extend in the x-direction and may be located in each row to overlap the semiconductor pattern CP. Figure 21 and Figure 22 As shown in the figure, at the edge of the display area DA, the end of the first conductive layer 210, the end of the semiconductor pattern CP, the end of the main line PLm of the driving voltage line PL, and the protrusion PLvp of the vertical driving voltage line PLv can overlap each other sequentially in the z direction and can be electrically connected to each other through the connecting electrode 269.

[0198] The connection electrode 269 may be located at a layer between the end of the main line PLm of the driving voltage line PL and the semiconductor pattern CP (e.g., located in a layer between the end of the main line PLm of the driving voltage line PL and the semiconductor pattern CP or located on a layer between the end of the main line PLm of the driving voltage line PL and the semiconductor pattern CP). For example, the connection electrode 269 may be located between the sixth insulating layer 116 and the seventh insulating layer 117. The protrusion PLvp of the vertical driving voltage line PLv may be electrically connected to the connection electrode 269 via a contact hole 81 passing through (e.g., penetrating) the seventh insulating layer 117. The connection electrode 269 may be electrically connected to the end of the main line PLm of the driving voltage line PL via a contact hole 82 passing through (e.g., penetrating) the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The connection electrode 269 may be electrically connected to the end portion of the semiconductor pattern CP through a contact hole 83 passing through (e.g., penetrating) the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The connection electrode 269 may be electrically connected to the end portion of the first conductive layer 210 through a contact hole 84 passing through (e.g., penetrating) the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116.

[0199] The above about Figure 21 The description of the embodiment may be applied to the pixel located in the last column and the conductive layer located around the pixel, and therefore, a redundant description thereof may not be repeated.

[0200] The semiconductor pattern CP, the main line PLm of the driving voltage line PL, and the first conductive layer 210 may correspond to the above reference numerals. Figures 6a to 6c The semiconductor layer (e.g., semiconductor pattern CP), top gate electrode (e.g., upper conductive layer DCLt), and bottom gate electrode (e.g., lower conductive layer DCLb) of the 4-terminal silicon thin film transistor TRs located in each row are described. The vertical driving voltage line PLv may correspond to the semiconductor layer (e.g., semiconductor pattern CP), top gate electrode (e.g., upper conductive layer DCLt), and bottom gate electrode (e.g., lower conductive layer DCLb) described above. Figures 6a to 6c The signal line SCL for receiving the driving voltage ELVDD is described.

[0201] In an embodiment, the semiconductor pattern CP may be located in the display area DA to overlap a portion of the pixel circuit PCa, and a 4-terminal silicon thin film transistor TRs including the semiconductor pattern CP may be provided in each row to overlap a portion of the pixel circuit PCa. Figure 20 and Figure 25 As shown in FIG, the 4-terminal silicon thin film transistor TRs may overlap with the first transistor T1, the first capacitor C1, and the second capacitor C2 of the pixel circuit PCa.

[0202] The eighth insulating layer 118 may be located on the seventh insulating layer 117 to cover the sixth conductive layer, and an organic light emitting diode OLED may be located on the eighth insulating layer 118 as a display element. The organic light emitting diode OLED may include a pixel electrode 311, an opposite electrode 315, and an intermediate layer between the pixel electrode 311 and the opposite electrode 315.

[0203] The pixel electrode 311 may be electrically connected to the connection electrode 270 as the lower conductive pattern through the contact hole 71 of the eighth insulating layer 118 and may be connected to the first transistor T1. Figure 23 As shown in FIG, the pixel electrode 311 of the pixel circuit connected to the first pixel PX1 can be electrically connected to the connection electrode 270 located in the first circuit area PCA1 and can be connected to the first transistor T1. The pixel electrode 311 of the pixel circuit connected to the second pixel PX2 can be electrically connected to the connection electrode 270 located in the second circuit area PCA2 and can be connected to the first transistor T1. The pixel electrode 311 of the pixel circuit connected to the third pixel PX3 can be electrically connected to the connection electrode 270 located in the third circuit area PCA3 and can be connected to the first transistor T1.

[0204] like Figure 25 As shown in FIG, a ninth insulating layer 119 as a pixel defining layer covering an edge of the pixel electrode 311 may be located on the pixel electrode 311. An opening 119OP may be defined in the ninth insulating layer 119, through which a portion of the pixel electrode 311 is exposed and an emission region is defined. The ninth insulating layer 119 may have a single-layer structure or a multi-layer structure including an organic insulating layer and / or an inorganic insulating layer.

[0205] The intermediate layer may include an emission layer 313 and a first functional layer above the emission layer 313 and / or a second functional layer below the emission layer 313. The first functional layer may be a hole transport layer (HTL). As another example, the first functional layer may include a hole injection layer (HIL) and an HTL. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer and the second functional layer may each be integrally formed to correspond to the plurality of organic light emitting diodes OLED included in the display area DA. The first functional layer or the second functional layer may be omitted as needed or desired. Figure 23 Shown are an emission layer 313a of the organic light emitting diode OLED electrically connected to the pixel circuit located in the first circuit area PCA1, an emission layer 313b of the organic light emitting diode OLED electrically connected to the pixel circuit located in the second circuit area PCA2, and an emission layer 313c of the organic light emitting diode OLED electrically connected to the pixel circuit located in the third circuit area PCA3.

[0206] Figure 24 The pixel electrode 311 and the emission area EA of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 are shown. The emission area EA is the area where the emission layer 313 of the organic light emitting diode OLED is located. The emission area EA can be defined by the opening 119OP of the ninth insulating layer 119. Because the emission layer 313 is located on the pixel electrode 311, Figure 24 The arrangement of the emission areas EA may be an arrangement of pixel electrodes or an arrangement of pixels.

[0207] The emission area EA may have a polygonal shape (such as a quadrilateral shape or an octagonal shape), a circular shape, or an elliptical shape. The polygonal shape may include a shape having rounded corners (eg, rounded vertices).

[0208] like Figure 24 As shown in FIG, the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 can be positioned adjacent to each other in the y direction. The emission area EA of the third pixel PX3 can be positioned adjacent to the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 in the x direction. Therefore, the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 can be alternately positioned along the y direction along the virtual straight line ISL1, and the emission area EA of the third pixel PX3 can be repeatedly positioned along the y direction along the virtual straight line ISL2.

[0209] The lengths of the emission area EA of the first pixel PX1, the emission area EA of the second pixel PX2, and the emission area EA of the third pixel PX3 in the x-direction and the y-direction may be the same or substantially the same as each other, or may be different from each other. For example, the emission area EA of the first pixel PX1 may have a square shape, and the emission area EA of the second pixel PX2 and the emission area EA of the third pixel PX3 may have a rectangular shape with a long side extending in the y-direction. The length of the emission area EA of the third pixel PX3 in the y-direction may be equal to or greater than the sum of the length of the emission area EA of the first pixel PX1 and the length of the emission area EA of the second pixel PX2 in the y-direction.

[0210] The first emission area EA of the first pixel PX1, the second emission area EA of the second pixel PX2, and the third emission area EA of the third pixel PX3 may have different areas (e.g., sizes) from each other. In an embodiment, the emission area EA of the third pixel PX3 may have an area larger than the area of ​​the emission area EA of the first pixel PX1. The emission area EA of the third pixel PX3 may have an area larger than the area of ​​the emission area EA of the second pixel PX2. The emission area EA of the second pixel PX2 may have an area larger than the area of ​​the emission area EA of the first pixel PX1.

[0211] The opposing electrode 315 may be integrally formed to correspond to a plurality of organic light emitting diodes OLED included in the display area DA.

[0212] Figure 26 It is schematically shown Figure 9a A view of the pixel's transistors and capacitors. Figure 27 is a view schematically showing a conductive layer at an edge of a display area. Figure 28 It is along Figure 27 A cross-sectional view taken along line XX'. Figure 27 yes Figure 6a An enlarged view of part A of FIG.

[0213] exist Figures 26 to 28 In the above reference Figures 10 to 25 Elements that are identical or substantially identical to the elements described herein are denoted by the same reference numerals, and thus, redundant descriptions thereof may not be repeated. Figure 26 In the above reference, you can omit Figures 10 to 25 The reference numerals of some of the elements described are identical or substantially identical to the elements described. Figures 10 to 25 In addition to the first conductive layer 210 in the display device described above, Figure 26 and Figure 27 The display device is the same as the above reference Figure 20 and Figure 21The display device described above is the same or substantially the same (or similar). Figures 10 to 25 The differences between the described embodiments.

[0214] like Figure 26 and Figure 28 As shown in FIG, in the display area DA, the semiconductor pattern CP may extend in the x direction and may be located in each row. The main line PLm of the driving voltage line PL may extend in the x direction and may be located in each row to overlap with the semiconductor pattern CP. Figure 27 and Figure 28 As shown in the figure, around the pixels of the first column and the last column located at the edge of the display area DA, the end of the semiconductor pattern CP, the end of the main line PLm of the driving voltage line PL, and the protrusion PLvp of the vertical driving voltage line PLv can overlap each other sequentially in the z direction and can be electrically connected to each other through the connecting electrode 269.

[0215] The protrusion PLvp of the vertical driving voltage line PLv can be electrically connected to the connection electrode 269 through a contact hole 81 passing through (e.g., penetrating) the seventh insulating layer 117. The connection electrode 269 can be electrically connected to the end of the main line PLm of the driving voltage line PL through a contact hole 82 passing through (e.g., penetrating) the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The connection electrode 269 can be electrically connected to the end of the semiconductor pattern CP through a contact hole 83 passing through (e.g., penetrating) the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116.

[0216] The semiconductor pattern CP and the main line PLm of the driving voltage line PL may correspond to the above referenced Figures 4a to 4c The semiconductor layer (eg, semiconductor pattern CP) and gate electrode (eg, conductive layer DCL) of the 3-terminal silicon thin film transistor TRs provided in each row are described. The vertical driving voltage line PLv may correspond to the above reference Figures 4a to 4c The signal line SCL for receiving the driving voltage ELVDD is described.

[0217] In an embodiment, the semiconductor pattern CP and the 3-terminal silicon thin film transistor TRs including the semiconductor pattern CP may be provided in each row to overlap a portion of the pixel circuit PCa. Figure 26 As shown in FIG, the 3-terminal silicon thin film transistor TRs may overlap with the first transistor T1, the first capacitor C1, and the second capacitor C2 of the pixel circuit PCa.

[0218] Figure 29 is a schematic diagram showing a Figure 9aA view of the pixel's transistors and capacitors. Figures 30 to 36 It is a schematic diagram showing the Figure 29 A view of the components of the pixel circuit layer. Figure 37 It shows Figure 29 Layout diagram of some components. Figure 38 It is along Figure 29 A cross-sectional view taken along line XI-XI'. Figure 38 is a cross-sectional view showing some elements located in the second circuit area PCA2.

[0219] exist Figures 29 to 38 In the above reference Figures 10 to 25 Elements that are identical or substantially identical to the elements described herein are denoted by the same reference numerals, and thus, redundant descriptions thereof may not be repeated. Figure 29 In the above reference, you can omit Figures 10 to 25 Reference numerals of some of the elements that are the same or substantially the same as those described herein are used. Except that the first conductive layer 210 is omitted and the semiconductor pattern CP and the driving voltage line PL are modified, Figure 29 The components of the display device are the same as those referenced above Figure 20 The elements of the display device described above are the same or substantially the same (or similar). Figures 10 to 25 The differences between the described embodiments.

[0220] The first insulating layer 111 may be located on the substrate 100 and may be formed as shown in FIG. Figure 30 As shown in FIG, a semiconductor pattern CP including a silicon semiconductor may be located on the first insulating layer 111. The semiconductor pattern CP may extend in the x-direction and may cross the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3. The semiconductor pattern CP may correspond to the above reference Figure 5a and Figure 5b The semiconductor pattern CP may include a protrusion CPp protruding in the −y direction in each circuit region.

[0221] The second insulating layer 112 may be located on the first insulating layer 111 to cover the semiconductor pattern CP, and the second conductive layer may be located on the second insulating layer 112. Figure 31 As shown in , the second conductive layer may include a first electrode layer 220, a driving voltage line PL, and a 2-2nd initialization voltage line VL22.

[0222] The driving voltage line PL and the 2-2 th initialization voltage line VL22 may extend in the x direction and may cross the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3. Figure 31As shown in part B of , the driving voltage line PL may include a plurality of sub-lines spaced apart (e.g., separated) from each other at suitable intervals (e.g., specific or predetermined intervals) in the x-direction. In an embodiment, the driving voltage line PL may be separated between the second circuit area PCA2 and the third circuit area PCA3, so that part B may be located between the second circuit area PCA2 and the third circuit area PCA3. Each sub-line of the driving voltage line PL may include a main line PLm extending in the x-direction and a protrusion PLc protruding from the main line PLm in the -y direction. The protrusion PLc may be located in each circuit area. The plurality of sub-lines may correspond to the above reference Figure 5a and Figure 5b The plurality of conductive electrodes DCE described above may include the first electrode layer 220 which may be provided in an island shape.

[0223] The third insulating layer 113 may be located on the second insulating layer 112 to cover the second conductive layer, and the third conductive layer may be located on the third insulating layer 113. Figure 32 As shown in FIG, the third conductive layer may include a second electrode layer 230, a reference voltage line VRL, and a first initialization voltage line VL1. The third conductive layer may further include a repair line RL.

[0224] The fourth insulating layer 114 may be located on the third insulating layer 113 to cover the third conductive layer, and a semiconductor layer OACT including an oxide semiconductor may be located on the fourth insulating layer 114, as shown in FIG. Figure 33 The semiconductor layer OACT may include a first semiconductor layer OACT1, a second semiconductor layer OACT2, a third semiconductor layer OACT3 and a fourth semiconductor layer OACT4.

[0225] A fifth insulating layer 115 may be located on the fourth insulating layer 114 to cover the semiconductor layer OACT, and a fourth conductive layer may be located on the fifth insulating layer 115. Figure 34 and Figure 16 As shown in FIG, the fourth conductive layer may include a third electrode layer 240, a fourth electrode layer 250, a first gate line GWL, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, and a 2-1st initialization voltage line VL21. Some of the third electrode layer 240, the fourth electrode layer 250, the first gate line GWL, the second gate line GIL, the third gate line GRL, the fourth gate line EML, and the fifth gate line EMBL may include gate electrodes G1 of the first transistor T1 to the gate electrode G7 of the seventh transistor T7.

[0226] The sixth insulating layer 116 may be located on the fifth insulating layer 115 to cover the fourth conductive layer, and the fifth conductive layer may be located on the sixth insulating layer 116. Figure 35As shown in , the fifth conductive layer may include the data lines DL and the connection electrodes 260 , 261 , 262 , 263 , 264 , 265 , 266 , 267 a , 267 b , and 268 .

[0227] The seventh insulating layer 117 may be located on the sixth insulating layer 116 to cover the fifth conductive layer, and the sixth conductive layer may be located on the seventh insulating layer 117. Figure 36 As shown in FIG, the sixth conductive layer may include a plurality of vertical conductive lines and a connecting electrode 270. The plurality of vertical conductive lines may include a vertical driving voltage line PLv, a vertical initialization voltage line, a common voltage line EOL, and a vertical reference voltage line VRLv. The vertical initialization voltage lines may include a first vertical initialization voltage line VL1v, a 2-1st vertical initialization voltage line VL21v, and a 2-2nd vertical initialization voltage line VL22v. Figure 36 A vertical driving voltage line PLv, a 2-1st vertical initializing voltage line VL21v, and a common voltage line EOL are shown.

[0228] An eighth insulating layer 118 may be located on the seventh insulating layer 117 to cover the sixth conductive layer, and an organic light emitting diode OLED may be located on the eighth insulating layer 118 as a display element.

[0229] like Figure 37 and Figure 38 As shown in , the connection electrode 264 can be electrically connected to the protrusion CPp of the semiconductor pattern CP by passing through (e.g., penetrating) the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115 and the sixth insulating layer 116. The connection electrode 264 can be electrically connected to the drain region D5 of the fifth transistor T5 as part of the first semiconductor layer OACT1 by passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The connection electrode 264 can be electrically connected to the protrusion PLc of the driving voltage line PL by passing through (e.g., penetrating) the contact hole 54 of the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115 and the sixth insulating layer 116. The protrusion PLvp of the vertical driving voltage line PLv can be electrically connected to the connection electrode 264 of the third circuit area PCA3 by passing through (e.g., penetrating) the contact hole 62 of the seventh insulating layer 117. As shown in Figure 27 As shown in FIG, around the first and last columns of pixels located at the edge of the display area DA, the end of the semiconductor pattern CP and the protrusion PLvp of the vertical driving voltage line PLv can be electrically connected to each other. Therefore, the semiconductor pattern CP and the plurality of sub-lines of the driving voltage line PL can receive the driving voltage ELVDD.

[0230] In an embodiment, the semiconductor pattern CP and the sub-lines of the driving voltage line PL may correspond to the above referenced Figures 5a to 5c The semiconductor layer (eg, semiconductor pattern CP) and gate electrode (eg, conductive electrode DCE) of each of the plurality of silicon thin film transistors TRs connected in series in each row are provided as described above. The vertical driving voltage line PLv may correspond to the semiconductor layer (eg, semiconductor pattern CP) and gate electrode (eg, conductive electrode DCE) of each of the plurality of silicon thin film transistors TRs connected in series in each row. Figures 5a to 5c The signal line SCL for receiving the driving voltage ELVDD is described. Figure 37 The portion B between the sub-lines of the driving voltage line PL may correspond to the portion B between the sub-lines of the driving voltage line PL Figure 5b and Figure 5c The node N described.

[0231] Figure 39 is a schematic diagram showing a Figure 9a A view of the pixel's transistors and capacitors. Figure 40 It is along Figure 39 A cross-sectional view taken along line XII-XII'.

[0232] exist Figure 39 In the above reference Figures 10 to 25 Elements that are identical or substantially identical to the elements described herein are denoted by the same reference numerals, and thus, redundant descriptions thereof may not be repeated. Figure 39 In the above reference, you can omit Figures 10 to 25 The reference numerals of some of the elements that are the same or substantially the same as those described above are used except that the first conductive layer 210 is omitted and the elements in part C are added. Figure 39 The components of the display device are the same as those referenced above Figure 20 The elements of the display device described above are the same or substantially the same (or similar). Figures 10 to 25 The differences between the described embodiments.

[0233] In an embodiment, a second semiconductor pattern CP2 as an additional semiconductor pattern may be further provided between adjacent rows of the display area DA. Figure 39 As shown in FIG, the second semiconductor pattern CP2 may be located in a portion C between the 2-1 initialization voltage line VL21 of any row and the first gate line GWL of the next row.

[0234] In the portion C, a plurality of second semiconductor patterns CP2 , a pair of first and second signal lines SCL1 and SCL2 , and a conductive layer DCL may be positioned.

[0235] The plurality of second semiconductor patterns CP2 may be spaced apart from each other in the x-direction on the substrate 100. A conductive layer DCL extending in the x-direction across the plurality of second semiconductor patterns CP2 may be located on the second insulating layer 112. The conductive layer DCL may be located above the plurality of second semiconductor patterns CP2 so as to overlap with the second semiconductor patterns CP2. A pair of first and second signal lines SCL1 and SCL2 may extend in the x-direction and may be located on the third insulating layer 113. The first signal line SCL1 may overlap with an end portion of the plurality of second semiconductor patterns CP2. The second signal line SCL2 may overlap with the other end portions of the plurality of second semiconductor patterns CP2. Connecting electrodes 281 and 282 may be located on the sixth insulating layer 116.

[0236] like Figure 40 As shown in FIG, the connection electrode 281 may be electrically connected to the end portion of the second semiconductor pattern CP2 through a contact hole 61 passing through (e.g., penetrating) the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The connection electrode 281 may be electrically connected to the first signal line SCL1 through a contact hole 62 passing through (e.g., penetrating) the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116.

[0237] The connection electrode 282 may be electrically connected to the other end portion of the second semiconductor pattern CP2 through a contact hole 64 passing through (e.g., penetrating) the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The connection electrode 282 may be electrically connected to the second signal line SCL2 through a contact hole 63 passing through (e.g., penetrating) the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116.

[0238] When forming the semiconductor pattern CP in the circuit region, the second semiconductor pattern CP2 may be formed concurrently or substantially simultaneously from the same material as the semiconductor pattern CP. When forming the second conductive layer in the circuit region, the conductive layer DCL may be formed concurrently or substantially simultaneously from the same material as the second conductive layer. When forming the third conductive layer in the circuit region, the first signal line SCL1 and the second signal line SCL2 may be formed concurrently or substantially simultaneously from the same material as the third conductive layer. When forming the fifth conductive layer in the circuit region, the connection electrodes 281 and 282 may be formed concurrently or substantially simultaneously from the same material as the fifth conductive layer.

[0239] Both ends (e.g., opposite ends) of the conductive layer DCL may be connected to the first gate driving circuit DRV1 and the second gate driving circuit DRV2 to receive a gate signal GS from the first gate driving circuit DRV1 and the second gate driving circuit DRV2. The gate signal GS may be the same as, substantially the same as, or different from the gate signal applied to the pixel circuit.

[0240] The first and second signal lines SCL1 and SCL2 may be electrically connected to the vertical driving voltage line PLv at the edge of the display area DA or may be electrically connected to the driving voltage supply line 11 of the peripheral area PA. Therefore, the second semiconductor pattern CP2 may receive the driving voltage ELVDD.

[0241] The second semiconductor pattern CP2 and the conductive layer DCL may correspond to the above referenced Figures 7a to 7c The semiconductor layer (eg, semiconductor pattern CP) and gate electrode (eg, conductive layer DCL) of each of the plurality of silicon thin film transistors TRds connected in parallel in each row are provided as described above. The vertical driving voltage line PLv may correspond to the semiconductor layer (eg, semiconductor pattern CP) and gate electrode (eg, conductive layer DCL) of the plurality of silicon thin film transistors TRds connected in parallel in each row. Figures 7a to 7c The signal line SCL for receiving the driving voltage ELVDD is described.

[0242] In an embodiment, in the display area DA, the display device 1 may include a semiconductor pattern CP as an element of a non-operating silicon thin film transistor TRs located in the circuit area and a second semiconductor pattern CP2 as an element of an operating silicon thin film transistor TRds located around the circuit area.

[0243] although Figure 39 The display device 1 has a portion C attached to Figure 25 For example, in the display device 1, part C may be added to Figure 29 The pixel circuit may be configured as follows, or the semiconductor pattern CP may be omitted in the circuit region, the non-operational silicon thin film transistor TRs may not be formed, and the operation silicon thin film transistor TRds including the second semiconductor pattern CP2 as an element may be formed only in portion C.

[0244] Figure 41 is a schematic diagram showing a Figure 9a A view of the pixel's transistors and capacitors. Figure 42 and Figure 43 It is schematically shown Figure 41 A view of some components of the pixel circuit. Figure 44 It shows Figure 41 Layout diagram of some components. Figure 45 It is along Figure 41 A cross-sectional view taken along line XIII-XIII'. Figure 45 is a cross-sectional view showing some elements located in the third circuit area PCA3.

[0245] exist Figure 41 In the above reference Figures 10 to 25 Elements that are identical or substantially identical to the elements described herein are denoted by the same reference numerals, and thus, redundant descriptions thereof may not be repeated. Figure 41 In the above reference, you can omit Figures 10 to 25 The reference numerals of some of the elements that are the same or substantially the same as those described above are used. Except that the first conductive layer 210 is omitted and some elements are modified, Figure 41 The components of the display device are the same as those referenced above Figure 20 The elements of the display device described above are the same or substantially the same (or similar). Figures 10 to 25 The differences between the described embodiments.

[0246] A first insulating layer 111 may be located on the substrate 100, and a semiconductor pattern CP including a silicon semiconductor may be located on the first insulating layer 111, as shown in FIG. Figure 42 As shown in . The semiconductor pattern CP may extend in the x direction and may cross the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3. The semiconductor pattern CP may include a protrusion CPpa protruding in the +y direction and a protrusion CPpb protruding in the -y direction in each circuit area.

[0247] The second insulating layer 112 may be located on the first insulating layer 111 to cover the semiconductor pattern CP, and the second conductive layer may be located on the second insulating layer. Figure 43 As shown in , the second conductive layer may include a first electrode layer 220, a fifth electrode layer 225, and a 2-2nd initialization voltage line VL22.

[0248] Each of the first electrode layer 220 and the fifth electrode layer 225 may be provided in an island shape. The 2-2 initialization voltage line VL22 may extend in the x-direction and may cross the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3. The fifth electrode layer 225 may include a protrusion 225p protruding from the main body in the -y direction. The protrusion 225p may be located in each circuit area.

[0249] The third insulating layer 113 may be located on the second insulating layer 112 to cover the second conductive layer, and the third conductive layer may be located on the third insulating layer 113. Figure 13 As shown in FIG, the third conductive layer may include a second electrode layer 230, a reference voltage line VRL, and a first initialization voltage line VL1. The third conductive layer may further include a repair line RL.

[0250] The fourth insulating layer 114 may be located on the third insulating layer 113 to cover the third conductive layer, and a semiconductor layer OACT including an oxide semiconductor may be located on the fourth insulating layer 114, as shown in FIG. Figure 14 The semiconductor layer OACT may include a first semiconductor layer OACT1, a second semiconductor layer OACT2, a third semiconductor layer OACT3 and a fourth semiconductor layer OACT4.

[0251] A fifth insulating layer 115 may be located on the fourth insulating layer 114 to cover the semiconductor layer OACT, and a fourth conductive layer may be located on the fifth insulating layer 115. Figure 15 and Figure 16 As shown in FIG, the fourth conductive layer may include a third electrode layer 240, a fourth electrode layer 250, a first gate line GWL, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, and a 2-1st initialization voltage line VL21. Some of the third electrode layer 240, the fourth electrode layer 250, the first gate line GWL, the second gate line GIL, the third gate line GRL, the fourth gate line EML, and the fifth gate line EMBL may include gate electrodes G1 of the first transistor T1 to the gate electrode G7 of the seventh transistor T7.

[0252] The sixth insulating layer 116 may be located on the fifth insulating layer 115 to cover the fourth conductive layer, and the fifth conductive layer may be located on the sixth insulating layer 116. Figure 17 As shown in , the fifth conductive layer may include the data lines DL and the connection electrodes 260 , 261 , 262 , 263 , 264 , 265 , 266 , 267 a , 267 b , and 268 .

[0253] The seventh insulating layer 117 may be located on the sixth insulating layer 116 to cover the fifth conductive layer, and the sixth conductive layer may be located on the seventh insulating layer 117. Figures 18a to 18d As shown in , the sixth conductive layer may include a plurality of vertical conductive lines and a connecting electrode 270 .

[0254] The eighth insulating layer 118 may be located on the seventh insulating layer 117 to cover the sixth conductive layer, and the organic light emitting diode OLED may be located as a display element on the eighth insulating layer 118. The plurality of vertical conductive lines may include a vertical driving voltage line PLv, a vertical initialization voltage line, a common voltage line EOL, and a vertical reference voltage line VRLv, as shown in FIG. Figures 18a to 18d The vertical initialization voltage lines may include a first vertical initialization voltage line VL1v, a 2-1st vertical initialization voltage line VL21v, and a 2-2nd vertical initialization voltage line VL22v.

[0255] like Figure 44 and Figure 45 As shown in FIG, the connection electrode 264 can be electrically connected to the protrusion CPpb of the semiconductor pattern CP through a contact hole 52 passing through (e.g., penetrating) the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The connection electrode 264 can be electrically connected to the drain region D5 of the fifth transistor T5, which is part of the first semiconductor layer OACT1, through a contact hole 53 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The connection electrode 264 can be electrically connected to the protrusion 225p of the fifth electrode layer 225 through a contact hole 54 passing through (e.g., penetrating) the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The protrusion PLvp of the vertical driving voltage line PLv can be electrically connected to the connection electrode 264 of the third circuit area PCA3 through a contact hole 62 passing through (e.g., penetrating) the seventh insulating layer 117.

[0256] like Figure 21 and Figure 27 As shown in FIG, around the first and last columns of pixels located at the edge of the display area DA, the end portion of the semiconductor pattern CP and the protrusion PLvp of the vertical driving voltage line PLv may be electrically connected to each other. Therefore, the semiconductor pattern CP may function together with the vertical driving voltage line PLv as a horizontal wiring having a mesh structure for supplying the driving voltage ELVDD in the display area DA.

[0257] In an embodiment, the semiconductor pattern CP is implemented as a constant voltage line that supplies the driving voltage ELVDD to the pixel circuit PCa in the display area DA.

[0258] Figure 46 is a schematic diagram showing a Figure 9a A view of the pixel's transistors and capacitors. Figure 47 and Figure 48 It is schematically shown Figure 46 A view of some components of the pixel circuit.

[0259] exist Figure 46 In the above reference Figures 10 to 25 Elements that are identical or substantially identical to the elements described herein are denoted by the same reference numerals, and thus, redundant descriptions thereof may not be repeated. Figure 46 In the above reference, you can omit Figures 10 to 25 The reference numerals of some of the elements that are the same or substantially the same as those described above are used. Except that the first conductive layer 210 is omitted and some elements are modified, Figure 46 The components of the display device can be compared with the above reference Figure 20The elements of the display device described above are the same or substantially the same (or similar). Figures 10 to 25 The differences between the described embodiments.

[0260] A first insulating layer 111 may be located on the substrate 100, and a semiconductor pattern CP including a silicon semiconductor may be located on the first insulating layer 111, as shown in FIG. Figure 47 As shown in . The semiconductor pattern CP may include a first semiconductor pattern CP1 and a second semiconductor pattern CP2. The first semiconductor pattern CP1 may extend in the x-direction and may span the first circuit area PCA1, the second circuit area PCA2, and the third circuit area PCA3. The second semiconductor pattern CP2 may be provided in an island shape in each circuit area.

[0261] The second insulating layer 112 may be located on the first insulating layer 111 to cover the semiconductor pattern CP, and the second conductive layer may be located on the second insulating layer 112. Figure 12 As shown in , the second conductive layer may include a first electrode layer 220, a driving voltage line PL, and a 2-2nd initialization voltage line VL22.

[0262] The third insulating layer 113 may be located on the second insulating layer 112 to cover the second conductive layer, and the third conductive layer may be located on the third insulating layer 113. Figure 13 As shown in FIG, the third conductive layer may include a second electrode layer 230, a reference voltage line VRL, and a first initialization voltage line VL1. The third conductive layer may further include a repair line RL.

[0263] The fourth insulating layer 114 may be located on the third insulating layer 113 to cover the third conductive layer, and a semiconductor layer OACT including an oxide semiconductor may be located on the fourth insulating layer 114, as shown in FIG. Figure 14 As shown in .

[0264] A fifth insulating layer 115 may be located on the fourth insulating layer 114 to cover the semiconductor layer OACT, and a fourth conductive layer may be located on the fifth insulating layer 115. Figure 15 and Figure 16 As shown in FIG, the fourth conductive layer may include a third electrode layer 240, a fourth electrode layer 250, a first gate line GWL, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, and a 2-1st initialization voltage line VL21. Some of the third electrode layer 240, the fourth electrode layer 250, the first gate line GWL, the second gate line GIL, the third gate line GRL, the fourth gate line EML, and the fifth gate line EMBL may include gate electrodes G1 of the first transistor T1 to the gate electrode G7 of the seventh transistor T7.

[0265] The sixth insulating layer 116 may be located on the fifth insulating layer 115 to cover the fourth conductive layer, and the fifth conductive layer may be located on the sixth insulating layer 116. Figure 48 As shown in FIG, the fifth conductive layer may include the data lines DL and the connection electrodes 260 , 261 , 262 , 263 , 264 , 265 , 266 , 267 a , 267 b , 268 , and 290 .

[0266] The first region 260a of the connection electrode 260 may be electrically connected to the source region S1 of the first transistor T1 via a contact hole 31 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The first region 260a of the connection electrode 260 may be electrically connected to the second electrode layer 230 via a contact hole 32 passing through (e.g., penetrating) the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116. The second region 260b of the connection electrode 260 may be electrically connected to the drain region D6 of the sixth transistor T6 via a contact hole 71 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The second region 260b of the connection electrode 260 may be electrically connected to the end portion of the second semiconductor pattern CP2 via a contact hole 72 passing through (e.g., penetrating) the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116.

[0267] The connection electrode 290 may be electrically connected to the drain region D4 of the fourth transistor T4 through a contact hole 74 passing through (e.g., penetrating) the fifth insulating layer 115 and the sixth insulating layer 116. The connection electrode 290 may be electrically connected to the other end portion of the second semiconductor pattern CP2 through a contact hole 73 passing through (e.g., penetrating) the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, and the sixth insulating layer 116.

[0268] The seventh insulating layer 117 may be located on the sixth insulating layer 116 to cover the fifth conductive layer, and the sixth conductive layer may be located on the seventh insulating layer 117. Figures 18a to 18d As shown in , the sixth conductive layer may include a plurality of vertical conductive lines and a connecting electrode 270 .

[0269] An eighth insulating layer 118 may be located on the seventh insulating layer 117 to cover the sixth conductive layer, and an organic light emitting diode OLED may be located on the eighth insulating layer 118 as a display element.

[0270] In an embodiment, in the display area DA, the display device 1 may include a first semiconductor pattern CP1 as an element of a non-operating silicon thin film transistor TRs in a circuit region and a second semiconductor pattern CP2 as a connection electrode for connecting a node in the pixel circuit PCa.

[0271] although Figure 46 The display device 1 has a second semiconductor pattern CP2 attached to Figure 26 For example, in the display device 1, the second semiconductor pattern CP2 may be attached to the pixel circuit of the display device 1. Figure 20 or Figure 29 The pixel circuit described herein may omit the first semiconductor pattern CP1 in the circuit region, may not form the non-operational silicon thin film transistor TRs, and may include only the second semiconductor pattern CP2.

[0272] Although the reference Figures 10 to 48 Describes how the pixel circuit is Figure 9a The example of the N-type oxide transistor shown in FIG, but even when the pixel circuit includes Figure 9b When the N-type oxide transistor and P-type silicon transistor are shown in Figures 10 to 48 The semiconductor pattern shown in FIG can also be applied to pixel circuits. For example, during the process of forming silicon transistors of pixel circuits and / or external circuits, a semiconductor pattern can be formed in the display area. The semiconductor pattern can be used as a transistor and / or a conductive line.

[0273] When there is a LTPS density difference between the peripheral area PA and the display area DA, pattern critical dimension (CD) distribution may occur. According to embodiments, since the semiconductor pattern CP including silicon is formed in the display area DA when forming the silicon thin film transistor, the pattern CD distribution between the peripheral area PA and the display area DA can be minimized or reduced.

[0274] According to one or more embodiments of the present disclosure described above, a display device with improved display quality can be provided. However, the present disclosure is not limited thereto.

[0275] The foregoing is an illustration of some embodiments of the present disclosure and should not be construed as limiting thereof. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, it will be apparent to those of ordinary skill in the art that, unless otherwise specifically noted, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other example embodiments are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device comprising a display area and a peripheral area, the display device comprising: a first thin film transistor in the peripheral region, wherein the first thin film transistor includes a silicon semiconductor layer; a second thin film transistor in the display area, wherein the second thin film transistor includes an oxide semiconductor layer above the silicon semiconductor layer; as well as A semiconductor pattern is in the display area, and the semiconductor pattern is at the same layer as the silicon semiconductor layer of the first thin film transistor.

2. The display device according to claim 1, wherein The semiconductor pattern includes a silicon semiconductor.

3. The display device according to claim 2, wherein The semiconductor pattern is configured to be in a floating state.

4. The display device according to claim 1, further comprising: a conductive layer overlapping the semiconductor pattern; as well as a signal line electrically connected to opposite ends of the semiconductor pattern that do not overlap with the conductive layer, Wherein, the signal line is electrically connected to the conductive layer.

5. The display device according to claim 4, wherein The conductive layer is at the same layer as the gate electrode of the first thin film transistor. The display device according to claim 4 , wherein: The oxide semiconductor layer of the second thin film transistor overlaps with the semiconductor pattern.

7. The display device according to claim 1, further comprising: a plurality of conductive electrodes overlapping the semiconductor pattern; as well as a signal line electrically connected to a portion of the semiconductor pattern between adjacent conductive electrodes among the plurality of conductive electrodes, Wherein, the signal line is electrically connected to the plurality of conductive electrodes.

8. The display device according to claim 7, wherein The plurality of conductive electrodes are at the same layer as the gate electrode of the first thin film transistor.

9. The display device according to claim 7, wherein The oxide semiconductor layer of the second thin film transistor overlaps with the semiconductor pattern.

10. The display device according to claim 1, further comprising: an upper conductive layer overlapping the semiconductor pattern; a lower conductive layer overlapping the semiconductor pattern; as well as a signal line electrically connected to opposite ends of the semiconductor pattern that do not overlap with the upper conductive layer, Wherein, the signal line is electrically connected to the upper conductive layer and the lower conductive layer.

11. The display device according to claim 10, wherein The upper conductive layer is at the same layer as the gate electrode of the first thin film transistor.

12. The display device according to claim 10, wherein The oxide semiconductor layer of the second thin film transistor overlaps with the semiconductor pattern.

13. The display device according to claim 1, wherein The semiconductor pattern includes a plurality of semiconductor patterns spaced apart from each other in a row direction, and Wherein, the display device further includes: a conductive layer overlapping the plurality of semiconductor patterns to cross the plurality of semiconductor patterns; a first signal line electrically connected to end portions of the plurality of semiconductor patterns; and The second signal line is electrically connected to the other ends of the plurality of semiconductor patterns.

14. The display device according to claim 13, wherein The first signal line and the second signal line are configured to be applied with a constant voltage signal, and The conductive layer is configured to be applied with a signal including a voltage of a first voltage level and a voltage of a second voltage level lower than the first voltage level.

15. The display device according to claim 13, further comprising: a second semiconductor pattern at the same layer as the plurality of semiconductor patterns, the second semiconductor pattern extending in the row direction; a second conductive layer overlapping the second semiconductor pattern; as well as a third signal line electrically connected to an opposite end portion of the second semiconductor pattern that does not overlap with the second conductive layer, The third signal line is configured to be applied with the same voltage as that supplied to the first signal line and the second signal line.

16. The display device according to claim 1, further comprising: a conductive layer overlapping the semiconductor pattern; as well as A signal line is electrically connected to the conductive layer.

17. The display device according to claim 1, wherein The semiconductor pattern is electrically connected to a conductive line configured to supply a constant voltage.

18. The display device according to claim 1 , further comprising a third thin film transistor in the display area and comprising an oxide semiconductor layer over the silicon semiconductor layer, in, The semiconductor pattern is configured to electrically connect the oxide semiconductor layer of the second thin film transistor to the oxide semiconductor layer of the third thin film transistor. 19 . The display device according to claim 1 , further comprising a third thin film transistor provided in the peripheral region and including the oxide semiconductor layer. 20 . The display device according to claim 1 , further comprising a fourth thin film transistor provided in the display region and including the silicon semiconductor layer.

21. A display device comprising a display area and a peripheral area, the display device comprising: A semiconductor pattern in the display area; a conductive layer on the semiconductor pattern, wherein the conductive layer overlaps the semiconductor pattern; a first electrode layer on the conductive layer, wherein the first electrode layer overlaps the conductive layer; an oxide semiconductor layer on the first electrode layer; a second electrode layer on the oxide semiconductor layer; as well as The third electrode layer is on the second electrode layer, and the third electrode layer overlaps with the second electrode layer.

22. The display device according to claim 21, wherein The semiconductor pattern includes a silicon semiconductor.

23. The display device according to claim 21, further comprising a lower conductive layer in the display area, the lower conductive layer being between the substrate and the semiconductor pattern, in, The semiconductor pattern overlaps the lower conductive layer.

24. The display device according to claim 21, further comprising: a silicon semiconductor layer in the peripheral region; as well as a fourth electrode layer on the silicon semiconductor layer, wherein the fourth electrode layer overlaps the silicon semiconductor layer; wherein the silicon semiconductor layer and the semiconductor pattern are at the same layer, and The fourth electrode layer and the conductive layer are at the same layer.

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