Apparatus and method for high speed input output

Abstract

The invention relates to the technical field of data processing and provides a device and a method for high-speed input and output. In one embodiment, an apparatus includes a cross-clock-domain transmission logic to periodically receive N beats of input data of single N bits according to a write clock signal, and to individually write the input data bitwise to the cross-clock-domain transmission logic according to a value of each bit in the N-bit write enable control signal, and to transmit the input data to the cross-clock-domain transmission logic according to a value of each bit in the N-bit write enable control signal. Reading as output data according to a read enable control signal; and the cross-clock-domain sending control logic is used for writing a write enable control signal into the cross-clock-domain sending control logic, reading as a gating signal according to the read clock signal, and gating the read clock signal according to the gating signal to obtain a read enable control signal, and the frequency ratio of the read clock signal to the write clock signal is N. Therefore, cross-clock-domain interaction of the read-write pointers is avoided, the logic depth and the chip complexity are reduced, and the speed can be increased and the power consumption can be reduced.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a device and method for high-speed input and output. Background Art

[0002] In high-performance memory applications, such as the fourth- and fifth-generation specifications for Double Data Rate Synchronous Dynamic Random Access Memory (DDR SRAM), also known as DDR4 and DDR5, the design of the memory's physical layer (PHY) requires the transmission of multiple signals from the PHY to the dynamic random access memory (DRAM) while ensuring signal quality. These signals can have extremely high frequencies, and the challenges of cross-clock domain transmission and latency variations between different traces on the circuit board must be considered. For example, according to the DDR5 specification, while the data (DQ) signal transmission rate is 6400 bits per second (bps), the command / address (CA) signal transmission rate can reach up to 3200 megabits per second (Mbps), which means the CA signal frequency is extremely high. In addition to the CA signal, there are also chip select (CS) signals, command and address parity (PAR) signals, activation command (ACT) signals, bank address (BA) signals, and bank group (BG) signals. To meet the high-frequency and high-quality transmission requirements of multiple signals, existing technologies rely on advanced manufacturing processes and complex control logic circuits to precisely control the transmission of data and signals. For example, Chinese patent application number CN113615088B discloses a cross-clock domain synchronization circuit that samples a write enable signal to obtain multiple sampling results and selects one of the multiple sampling results as the read enable signal based on the clock phase difference between the write clock signal and the read clock signal. For another example, a Chinese patent application with publication number CN116541333A discloses a data synchronization method from a slow clock domain to a fast clock domain, in which a slow clock signal is sampled sequentially from the first clock cycle to the Mth clock cycle of the fast clock signal, and recorded as the first sampling signal to the Mth sampling signal respectively. Based on the first sampling signal to the Mth sampling signal, it is determined whether the transition edge of the slow clock signal is triggered within any clock cycle from the first clock cycle to the Mth clock cycle.Therefore, the technical solutions for cross-clock domain transmission in the existing technology require complex control logic circuits to implement signal sampling and edge judgment. In the application of high-frequency signals, they rely on high-performance devices provided by advanced manufacturing processes. Therefore, it is difficult to meet the requirements of increasingly higher transmission rates, and it is not conducive to reducing chip complexity and control costs.

[0003] To this end, the present application proposes a device and method for high-speed input and output to address the technical difficulties in the prior art. Summary of the Invention

[0004] In a first aspect, the present application provides a device for high-speed input and output. The device includes: cross-clock domain transmission transmission logic, which is used to periodically receive N-bit single-beat input data according to a write clock signal in a write clock domain, and write the N-bit input data bit by bit to a first first-in-first-out memory in the cross-clock domain transmission transmission logic according to the value of each bit in an N-bit write enable control signal, and read the first first-in-first-out memory as output data according to a read enable control signal; cross-clock domain transmission control logic, which is used to write the write enable control signal to a second first-in-first-out memory in the cross-clock domain transmission control logic, and read the second first-in-first-out memory as a gating signal according to a read clock signal in a read clock domain, and gate the read clock signal according to the gating signal to obtain the read enable control signal, wherein the frequency of the read clock signal is N times the frequency of the write clock signal, and N is a positive integer greater than 1 and equal to 1.

[0005] Through the first aspect of the present application, the interaction between read and write pointers across clock domains is avoided, the loss of clock signal edge judgment and transition edge triggering is avoided, and the loss of frequent measurement and determination of clock phase differences is avoided, ensuring the correctness of data transmission control from a low-speed clock domain to a high-speed clock domain, and also ensuring the correctness of the parallel-to-serial logic, effectively reducing the logic depth and chip complexity, helping to achieve higher speeds and reduce overall power consumption, which is conducive to meeting increasingly higher transmission rate requirements and cost control requirements.

[0006] In a possible implementation of the first aspect of the present application, the input data includes parallel port data to be transmitted and parallel port enable to be transmitted, and the output data includes serial port send data corresponding to the parallel port data to be transmitted and serial port send enable corresponding to the parallel port enable to be transmitted.

[0007] In a possible implementation of the first aspect of the present application, the read enable control signal and the write enable control signal are used together to establish read and write pipeline control of the cross-clock domain transmission transmission logic.

[0008] In a possible implementation of the first aspect of the present application, the cross-clock domain transmission control logic is used to implement control signal conversion from the write clock domain to the read clock domain to achieve cycle-level timing control.

[0009] In a possible implementation of the first aspect of the present application, the cross-clock domain transmission logic is used to write the N beats of input data into the first first-in-first-out memory in the cross-clock domain transmission logic bit by bit according to the value of each bit in the N-bit write enable control signal, including: writing the data on the bit corresponding to the position of the bit with a value of 1 in the N bits of the write enable control signal in the input data of each beat of the N beats of input data according to the position of the bit with a value of 1 in the N bits of the write enable control signal.

[0010] In a possible implementation of the first aspect of the present application, the cross-clock domain transmission logic is used to write the N beats of input data into the first first-in-first-out memory in the cross-clock domain transmission logic bit by bit according to the value of each bit in the N-bit write enable control signal, including: writing the data on the bit corresponding to the position of the bit with a value of 0 in the N bits of the write enable control signal in the input data of each beat of the N beats of input data according to the position of the bit with a value of 0 in the N bits of the write enable control signal.

[0011] In a possible implementation of the first aspect of the present application, the cross-clock domain transmission control logic further includes a gating module, which is configured to gate the read clock signal according to the gating signal to obtain the read enable control signal.

[0012] In a possible implementation of the first aspect of the present application, the device also includes a digital delay chain, which is used to adjust the delay of the read enable control signal being received by the cross-clock domain transmission logic according to a delay control signal, so as to adjust the delay of the output data provided by the cross-clock domain transmission logic.

[0013] In a possible implementation of the first aspect of the present application, the delay control signal is used to adjust the delay of the output data so that the middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal.

[0014] In a possible implementation of the first aspect of the present application, the device also includes a self-test module and a single-ended output module, the single-ended output module is used to selectively send data externally or send loopback data to the self-test module after receiving the output data, and the self-test module is used to provide a data self-test function based on the input data and the loopback data.

[0015] In a possible implementation of the first aspect of the present application, the delay control signal is used to adjust the delay of the output data so as to cooperate with the self-test module to implement a data eye diagram scanning function.

[0016] In a possible implementation manner of the first aspect of the present application, the cross-clock domain transmission control logic is further used to receive a control signal set, wherein the control signal set includes a power control signal and a terminal resistance control signal.

[0017] In a possible implementation of the first aspect of the present application, the device is applied to a high-speed input and output application scenario of serial in / out, and the high-speed input and output application scenario includes one or more of the following: a transmitting end of a serializer and deserializer, a double data rate synchronous dynamic random access memory, a low-power fifth-generation double data rate memory, a high-bandwidth memory, a die-to-die interconnection, an automotive-grade chip interconnection, an internal interconnection of a data center, and an internal interconnection of an artificial intelligence platform.

[0018] In a second aspect, the present application provides a method for high-speed input and output. The method includes: periodically receiving N-bit single-beat N-bit input data according to a write clock signal in a write clock domain through a cross-clock domain transmission transmission logic, and writing the N-bit input data bit by bit to a first first-in-first-out memory in the cross-clock domain transmission transmission logic according to the value of each bit in the N-bit write enable control signal, and reading the first first-in-first-out memory as output data according to a read enable control signal; writing the write enable control signal to a second first-in-first-out memory in the cross-clock domain transmission control logic through a cross-clock domain transmission control logic, and reading the second first-in-first-out memory as a gating signal according to a read clock signal in a read clock domain, and gating the read clock signal according to the gating signal to obtain the read enable control signal, wherein the frequency of the read clock signal is N times the frequency of the write clock signal, and N is a positive integer greater than 1 and equal to 1.

[0019] Through the second aspect of the present application, the interaction between the read and write pointers across clock domains is avoided, the loss of clock signal edge judgment and transition edge triggering is avoided, and the loss of frequent measurement and determination of clock phase differences is avoided, ensuring the correctness of data transmission control from the low-speed clock domain to the high-speed clock domain, and also ensuring the correctness of the parallel-to-serial logic, effectively reducing the logic depth and chip complexity, helping to achieve higher speeds and reduce overall power consumption, which is conducive to meeting the requirements of increasingly higher transmission rates and cost control requirements.

[0020] In a possible implementation of the second aspect of the present application, the method further includes: adjusting, through a digital delay chain, the delay of the read enable control signal being received by the cross-clock domain transmission logic according to a delay control signal, so as to adjust the delay of the output data provided by the cross-clock domain transmission logic.

[0021] In a possible implementation of the second aspect of the present application, the delay control signal is used to adjust the delay of the output data so that the middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 A schematic diagram of a device for high-speed input and output according to a first embodiment of the present application; Figure 2 A schematic diagram of a device for high-speed input and output according to a second embodiment of the present application; Figure 3 A schematic diagram of the timing control function of sending control logic across clock domains provided in an embodiment of the present application; Figure 4 A schematic diagram of the delay adjustment function of the digital delay chain provided in an embodiment of the present application; Figure 5 A schematic diagram of adjusting the delay of multiple traces using the delay adjustment function of a digital delay chain according to an embodiment of the present application; Figure 6 A schematic diagram of performing data eye diagram scanning using the data self-test function of the self-test module and the delay adjustment function of the digital delay chain provided in an embodiment of the present application; Figure 7A flowchart of a method for high-speed input and output provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

[0025] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality" means two or more. In addition, unless otherwise specified, the terms "first" and "second" are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or order.

[0026] Figure 1 This is a schematic diagram of a device for high-speed input and output according to the first embodiment of the present application. Figure 1 As shown, the device A100 for high-speed input and output includes cross-clock domain transmission transmission logic A130 and cross-clock domain transmission control logic A140. The cross-clock domain transmission transmission logic A130 is configured to periodically receive N-bit single-beat input data A110 according to a write clock signal A114 in a write clock domain, and to write the N-bit input data A110 bit by bit to a first first-in-first-out memory A132 in the cross-clock domain transmission transmission logic A130 according to the value of each bit in an N-bit write enable control signal A120, and to read the first first-in-first-out memory A132 as output data A112 according to a read enable control signal A122. The cross-clock domain transmission control logic A140 is configured to write the write enable control signal A120 to a second first-in-first-out memory A142 within the cross-clock domain transmission control logic A140, read the second first-in-first-out memory A142 as a gating signal based on a read clock signal A116 in the read clock domain, and gate the read clock signal A116 based on the gating signal to obtain the read enable control signal A122. The frequency of the read clock signal A116 is N times the frequency of the write clock signal A114, where N is a positive integer greater than 1 and equal to 1.

[0027] Figure 1The device A100 for high-speed input and output shown can be applied to application scenarios of high-performance memory and high-speed data transmission, such as the fourth-generation and fifth-generation technical specifications of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SRAM), that is, the relevant technical specifications of DDR4 and DDR5; it can be used to meet the data transmission requirements from the physical layer (PHY) of high-performance memory to dynamic random access memory (DRAM), including the transmission of various signals such as command / address (CA) signal, chip select (CS) signal, command and address parity (PAR) signal, activation command (ACT) signal, bank address (BA) signal, bank group (BG) signal, etc. In addition, Figure 1 The high-speed input and output device A100 shown can be used to ensure data conversion from a low-speed clock domain to a high-speed clock domain, ensuring correct control of input / output (IO) status to implement transmission logic, and can also implement functions such as controlling output data delay, detecting input and output working status, and eye pattern scanning by adding additional functional modules. In addition, Figure 1 The device A100 for high-speed input and output shown can meet the parallel-to-serial conversion requirements in high-speed input and output applications, such as implementing an 8-to-1 data conversion operation on the physical layer side, and greatly simplifies the control complexity of data transmission and the difficulty of implementing parallel-to-serial conversion logic, which is conducive to controlling the demand for advanced manufacturing processes and helping to reduce chip complexity and control costs. Figure 1 The device A100 for high-speed input and output shown can be applied to high-speed input and output application scenarios with serial input and output, including but not limited to: the transmitting end of the serializer / deserializer (SERDES), double data rate synchronous dynamic random access memory, low power fifth generation double data rate (LPDDR5) memory, high bandwidth memory (HBM), die-to-die (D2D) interconnection, automotive-grade chip interconnection, internal interconnection of data centers, and internal interconnection of artificial intelligence platforms.

[0028] See Figure 1The device A100 for high-speed input and output includes cross-clock domain transmission logic A130 and cross-clock domain transmission control logic A140. The cross-clock domain transmission logic A130 includes a built-in first-in-first-out memory A132, which acts as a data entry for storing written data, such as the write enable and the data to be transmitted. The first FIFO A132 implements cross-clock domain data transmission logic and can be considered a transmit first-in-first-out memory (TXFIFO). The write clock signal A114 in the write clock domain can correspond to the local low-speed clock (i_dfi_phy_clk) of the physical layer, while the read clock signal A116 in the read clock domain is the high-speed clock (txclk) used for data transmission. Therefore, from the write clock domain to the read clock domain, various challenges associated with cross-clock domain interaction and cross-clock domain data transmission must be considered, including frequency and phase differences between different clock signals, and the need to ensure high-frequency and high-speed signal transmission. The cross-clock domain transmission control logic A140 is used to control the cross-clock domain transmission of signals. The cross-clock domain transmission control logic A140 includes a built-in second FIFO memory A142, which is used to implement cross-clock domain conversion and cycle-level timing control of the high-speed clock. Therefore, it can be considered a clock data control FIFO (CDCFIFO). The cross-clock domain transmission control logic A140 generates a converted control signal, which can be used to control the fast clock of the cross-clock domain transmission transmission logic A130. Furthermore, the converted clock signal provided by the cross-clock domain transmission control logic A140 can be provided according to the number of cycles required by the cross-clock domain transmission transmission logic A130. This, together with the slow clock control of the cross-clock domain transmission transmission logic A130, achieves pipeline control for reading and writing. This design reduces ineffective clock signal toggling in the cross-clock domain transmission transmission logic A130, which helps reduce power consumption. In addition, the cross-clock domain sending control logic A140 is used to assist the cross-clock domain sending transmission logic A130 in establishing the pipeline control of reading and writing of the cross-clock domain sending transmission logic A130. There is no need for the interaction between the read and write pointers across the clock domains, which reduces the depth of the logic and can achieve a higher rate while maintaining the process level.The device A100 for high-speed input and output utilizes the collaboration between the optimized cross-clock domain transmission transmission logic A130 and the cross-clock domain transmission control logic A140, thereby saving the cross-clock domain interaction of the read and write pointers. In contrast, the technical solutions for cross-clock domain transmission in the prior art require complex control logic circuits to implement signal sampling and edge judgment. For example, the write enable signal is sampled to obtain multiple sampling results and then one sampling result is selected from the multiple sampling results as the read enable signal based on the clock phase difference between the write clock signal and the read clock signal. Therefore, it is difficult to avoid the cross-clock domain interaction of the read and write pointers. This means that using the same manufacturing process level, that is, under the same process, through the optimized design of the device A100 for high-speed input and output, compared with the technical solutions for cross-clock domain transmission in the prior art, a higher rate can be achieved and overall power consumption can be reduced.

[0029] Continue reading Figure 1The cross-clock domain transmission logic A130 is configured to periodically receive N beats of single-beat N-bit input data A110 based on a write clock signal A114 in the write clock domain. Based on the values ​​of each bit in the N-bit write enable control signal A120, the logic writes the N beats of input data A110 bit by bit into a first FIFO memory A132 within the cross-clock domain transmission logic A130. Furthermore, the logic reads the first FIFO memory A132 as output data A112 based on a read enable control signal A122. In this manner, multiple valid data written in parallel are transmitted serially, achieving a parallel-to-serial operation. Specifically, N beats of input data A110 (each beat consisting of N bits) are written in parallel to the first FIFO memory A132 and then transmitted serially. For example, if the memory's physical layer interface protocol specifies an 8-to-1 operation, N can be set to 8, thus performing a parallel-to-serial operation on the 8 beats of input data A110. In some embodiments, the data to be transmitted (TXDATA) and the transmission enable (TXOE) can be written together. The N-bit write enable control signal A120 is a write enable control signal (WREN) with a specific data length. Write enable control signal A120 is used to control bit-by-bit writing. That is, each beat of the input data A110 written writes the corresponding data based on the values ​​of each bit in the N-bit write enable control signal A120. For example, assuming that N is equal to 8, this means that the write enable control signal A120 is 8 bits in length, and the input data A110 is 8-bit data with a single beat of 8 bits; further assuming that the values ​​of each bit in the write enable control signal A120 are "00011111", this means that the values ​​of the highest 3 bits in the write enable control signal A120 are 0, and the values ​​of the lowest 5 bits are 1. This can be used to control bit-by-bit writing, so that the data on the lowest 5 bits in each beat of the input data A110 are written into the first first-in-first-out memory A132 in the cross-clock domain transmission logic A130.In some embodiments, if the value of each bit in the write enable control signal A120 is 1, it means that the data at the bit at the corresponding position in each shot of the input data A110 is written into the first first-in-first-out memory A132. For example, the 8-bit write enable control signal A120 is "00011111", which means that the data at the lowest 5 bits in each shot of the input data A110 is written into the first first-in-first-out memory A132. In other embodiments, depending on actual needs, it can also be set that when the value of each bit in the write enable control signal A120 is 0, it means that the data at the bit at the corresponding position in each shot of the input data A110 is written into the first first-in-first-out memory A132. For example, the 8-bit write enable control signal A120 is "00011111", which means that the data at the highest 3 bits in each shot of the input data A110 is written into the first first-in-first-out memory A132. Therefore, according to the value of each bit in the N-bit write enable control signal A120, the N-beat input data A110 are written bit by bit to the first first-in-first-out memory A132 in the cross-clock domain transmission logic A130. The bit with a value of 1 in the write enable control signal A120 can be used as an indication of valid writing, or the bit with a value of 0 in the write enable control signal A120 can be used as an indication of valid writing, which provides more flexibility at the control level.

[0030] Continue reading Figure 1The pipeline control for writing to the cross-clock domain transmission transmission logic A130 is based on the N-bit write enable control signal A120. For example, each write cycle writes N bits of parallel port data per beat according to the values ​​of each bit in the write enable control signal A120. The write clock signal A114 in the write clock domain is used to coordinate when to receive the input data A110 for writing. In addition, the pipeline control for reading from the cross-clock domain transmission transmission logic A130 is based on the read enable control signal A122. That is, the first first-in-first-out memory A132 is read as the output data A112 according to the read enable control signal A122. The cross-clock domain transmission control logic A140 is used to generate the read enable control signal A122 to establish the pipeline control for reading from the cross-clock domain transmission transmission logic A130. Cross-clock domain transmission control logic A140 is configured to write the write enable control signal A120 to a second FIFO memory A142 within the cross-clock domain transmission control logic A140, read the second FIFO memory A142 based on a read clock signal A116 in the read clock domain as a gating signal, and gate the read clock signal A116 based on the gating signal to obtain the read enable control signal A122. Therefore, to ensure correct write and read timing, the read clock signal A116 is used to coordinate when to read the gating signal, and the gating signal also gates the read clock signal A116 to obtain the read enable control signal A122. The read enable control signal A122 is used to control the read timing of the transmission transmission logic, thereby ensuring correct write and read timing. In this way, the write clock signal A114 in the write clock domain is used to coordinate the cross-clock domain transmission transmission logic A130 to determine when to receive the input data A110 for writing, that is, the cross-clock domain transmission transmission logic A130 periodically receives N beats of single-beat N-bit input data A110 according to the write clock signal A114 in the write clock domain; the read clock signal A116 in the read clock domain is used to generate the read enable control signal A122, that is: the cross-clock domain transmission control logic A140 reads the second first-in-first-out memory A142 as a gating signal according to the read clock signal A116 in the read clock domain, and, according to the gating signal, gates the read clock signal A116 to obtain the read enable control signal A122. It can be seen that the interaction between the read and write pointers across clock domains is avoided, there is no need to perform edge judgment on the write clock signal A114, and there is no need to frequently determine the clock phase difference between the write clock signal A114 and the read clock signal A116, which effectively reduces the logic depth and circuit complexity.In order to ensure that data is converted from the low-speed clock domain to the high-speed clock domain, and to ensure the correctness of the parallel-to-serial logic, the transmission logic A130 is sent across the clock domain, and the N-bit write enable control signal A120 is used to control the bit-by-bit write operation to write the N-bit input data A110 of a single beat. Here, the write clock signal A114 in the write clock domain is used to coordinate the transmission logic A130 sent across the clock domain to periodically receive the input data A110; the control logic A140 is sent across the clock domain, and the write enable control signal A120 is written to the second first-in-first-out memory A142. Here, the read clock signal A116 in the read clock domain is used to coordinate the cross-clock domain transmission control logic A140 to read the second first-in-first-out memory A142 to obtain a gating signal, and the read clock signal A116 is gated according to the gating signal to obtain the read enable control signal A122. In this way, there's no need for cross-clock domain interaction between read and write pointers. In the write clock domain, the data and enable to be transmitted are written according to the enable function of the write enable control signal A120. In the read clock domain, the first FIFO memory A132 is read according to the read enable control signal A122 as output data A112, such as the data sequence (txdata serial) and the enable sequence (txoe serial) for transmission. It should be understood that the data length of the write enable control signal A120 is N bits. Here, N, as a parameter, is consistent with the parameter N in the single-beat N-bit N-beat input data A110, and also consistent with the frequency of the read clock signal A116 being N times the frequency of the write clock signal A114. Therefore, N can be understood as the ratio of the high-speed to low-speed clock frequencies, or the ratio of the fast clock frequency to the slow clock frequency. For example, N can be set to 8, that is, the data length of the write enable control signal A120 is 8 bits, which means that the input data A110 is 8-bit data with a single beat of 8 bits, and the high-speed and low-speed clock frequency ratio is 8 to 1. For another example, N can be set to 6, that is, the data length of the write enable control signal A120 is 6 bits, which means that the input data A110 is 6-bit data with a single beat of 6 bits, and the high-speed and low-speed clock frequency ratio is 6 to 1. Therefore, the parameter N is the high-speed and low-speed clock frequency ratio, or in other words, the ratio of the frequency of the read clock signal A116 to the frequency of the write clock signal A114, which determines how to divide the input data A110, that is, divide it into N beats with a data length of N bits as a single beat, and the writing of each beat is bit-by-bit writing according to the binary value of the bit in the write enable control signal A120.

[0031] Continue reading Figure 1To overcome the problem of data transmission across clock domains and address the frequency and phase differences between the clock signals of two different clock domains, in the cross-clock domain transmission logic A130, the local low-speed clock, i.e., the write clock signal A114 in the write clock domain, is used to control the periodic reception of data to be written, and the high-speed clock, i.e., the read clock signal A116 in the read clock domain, is used to control the output of read data. To ensure that the written data can be read correctly, it must be ensured that the data can be read only after it has been written and stabilized. In order to avoid interaction between the write and read pointers and reduce logic complexity, Figure 1The illustrated device A100 for high-speed input and output utilizes an optimized design of cross-clock domain transmission control logic A140 and design constraints around parameter N to achieve correct data reading and writing by controlling the time at which the high-speed clock reaches the cross-clock domain transmission transmission logic A130. Specifically, the write enable control signal A120 is converted to the high-speed clock domain using the generation mechanism of the read enable control signal A122 of the cross-clock domain transmission control logic A140. Furthermore, the read clock signal A116 is gated to obtain the read enable control signal A122 by using the gating signal converted to the high-speed clock domain by the cross-clock domain transmission control logic A140. This allows the read enable control signal A122 to be used to address cross-clock domain alignment requirements by controlling the time at which the enable signal in the high-speed clock domain reaches the cross-clock domain transmission transmission logic A130. From another perspective, the generation mechanism of the read enable control signal A122 by the cross-clock domain transmission control logic A140 is as follows: the second FIFO memory A142 is read as a gating signal based on the read clock signal A116 in the read clock domain, and the read clock signal A116 is gated based on the gating signal to generate the read enable control signal A122. Thus, the already written write enable control signal A120 read from the second FIFO memory A142 is used as the read enable signal, which is used as the gating signal to gate the read clock signal A116. This is used to sample the high-speed original clock signal in the high-speed clock domain, namely the read clock signal A116 (the frequency of the read clock signal A116 is N times the frequency of the write clock signal A114), to generate the gated clock signal. This is the read enable control signal A122, which is also the control signal provided by the cross-clock domain transmission control logic A140 for pipeline control of data reading. In addition, the above design constraints around parameter N also include the implementation of parallel-to-serial logic. Taking parameter N as 8 as an example, in order to convert the write enable control signal A120 to the high-speed clock domain, for example, from the low-speed clock domain of 1 gigahertz (GHz) to the high-speed clock domain of 8 GHz, the related parallel-to-serial operation includes converting 8 beats of parallel data with a single beat of 8 bits into serial data, that is, converting 8 beats of parallel data into 1 beat of serial data; conversely, if the high-speed to low-speed frequency ratio is 6 to 1, the related parallel-to-serial operation includes converting 6 beats of parallel data into 1 beat of serial data. In addition, in addition to receiving the write enable control signal A120, the cross-clock domain sending control logic A140 can also receive a series of control signals, including power control signals and terminal resistance control signals, etc., to provide flexibility at the control level. As long as the cross-clock domain sending control logic A140 receives the write enable control signal A120 and performs cross-clock domain conversion, it provides the read enable control signal A122 for constructing the cycle-level timing control of data reading of the cross-clock domain sending transmission logic A130.

[0032] In short, Figure 1 The device A100 for high-speed input and output shown in the figure introduces parameter N as a global parameter. Based on the high-speed and low-speed clock frequency ratio (the frequency of the read clock signal A116 is N times the frequency of the write clock signal A114), design constraints are set for the data format of the input data A110, the data format of the write enable control signal A120, and the specific method of writing the input data A110 into the first first-in-first-out memory A132 in the cross-clock domain transmission transmission logic A130. Specifically, these design constraints are set: single-shot N-bit N-shot Input data A110, N-bit write enable control signal A120, and write the N-beat input data A110 bit by bit according to the value of each bit in the N-bit write enable control signal A120; based on the constraints of the established design, the write clock signal A114 in the write clock domain is used to coordinate when to receive the input data A110 for writing, thereby constructing a pipeline control for writing the transmission logic A130 across clock domains and realizing the cycle-level timing control of writing; based on the constraints of the established design, the read clock signal A114 in the write clock domain is used to coordinate when to receive the input data A110 for writing. The read clock signal A116 of the cross-clock domain is used to coordinate when to read the gating signal, and then the gating signal is used to gate the read clock signal to obtain the read enable control signal A122, thereby constructing the pipeline control of the reading of the cross-clock domain transmission transmission logic A130, and realizing the cycle-level timing control of the reading; combined with the data format of the input data A110, the data format of the write enable control signal A120, and the design constraints made on the specific method of writing the input data A110 into the first first-in-first-out memory A132 in the cross-clock domain transmission transmission logic A130, the cross-clock domain transmission transmission logic A130 is used to transmit the data to the first first-in-first-out memory A132. The generation mechanism of the read enable control signal A122 of the clock domain sending control logic A140 avoids the interaction between the read and write pointers across clock domains, avoids the loss of clock signal edge judgment and jump edge triggering, and avoids the loss of frequent measurement and determination of clock phase difference, ensuring the correctness of data transmission control from the low-speed clock domain to the high-speed clock domain, and also ensures the correctness of the parallel-to-serial logic, effectively reducing the logic depth and chip complexity, helping to achieve higher speeds and reduce overall power consumption, which is conducive to meeting the requirements of increasingly higher transmission rates and cost control requirements.

[0033] Figure 2 This is a schematic diagram of a device for high-speed input and output according to a second embodiment of the present application. Figure 2As shown, the device B200 for high-speed input and output includes cross-clock domain transmission transmission logic B230 and cross-clock domain transmission control logic B240. The cross-clock domain transmission transmission logic B230 is used to periodically receive N-bit single-beat input data B210 according to the write clock signal B214 in the write clock domain, and write the N-bit input data B210 bit by bit to the first first-in-first-out memory B232 in the cross-clock domain transmission transmission logic B230 according to the value of each bit in the N-bit write enable control signal B220, and read the first first-in-first-out memory B232 as output data B212 according to the read enable control signal B222. The cross-clock domain sending control logic B240 is used to write the write enable control signal B220 to the second first-in-first-out memory B242 in the cross-clock domain sending control logic B240, and read the second first-in-first-out memory B242 as the gating signal B246 according to the read clock signal B216 in the read clock domain, and gate the read clock signal B216 according to the gating signal B246 to obtain the read enable control signal B222. The frequency of the read clock signal B216 is N times the frequency of the write clock signal B214, and N is a positive integer greater than 1 and equal to 1. The cross-clock domain sending control logic B240 also includes a gating module B244. The gating module B244 is used to gate the read clock signal B216 according to the gating signal B246 to obtain the read enable control signal B222. It should be understood that Figure 2 The cross-clock domain transmission control logic B240 shown implements a gating operation through a gating module B244 to support the generation mechanism of the read enable control signal B222. As long as the generation mechanism of the read enable control signal B222 is satisfied, Figure 2 The cross-clock domain transmission control logic B240 shown may also be implemented by other hardware, circuits, firmware, software, etc. having gating operation characteristics.

[0034] See Figure 2The device B200 for high-speed input and output utilizes cross-clock domain transmission transmission logic B230 and cross-clock domain transmission control logic B240 to ensure that data is converted from a low-speed clock domain to a high-speed clock domain, ensuring the correct control of the input and output states to implement the transmission logic. The device B200 for high-speed input and output can also implement functions such as controlling the delay of output data, detecting the working status of input and output, and eye diagram scanning through additional functional modules. Among them, for the function of controlling the delay of output data, the device B200 for high-speed input and output also includes a digital delay chain B250. The digital delay chain B250 is used to adjust the delay of the read enable control signal B222 received by the cross-clock domain transmission transmission logic B230 according to the delay control signal, so as to adjust the delay of the output data B212 provided by the cross-clock domain transmission transmission logic B230. In some embodiments, the delay control signal is used to adjust the delay of the output data B212 so that the middle of the data signal associated with the output data B212 is aligned with the sampling clock edge of the data clock signal associated with the data signal. For the function of detecting the working status of input and output, the device B200 for high-speed input and output also includes a self-test module B260 and a single-ended output module B262. The single-ended output module B262 is used to selectively send data to the outside or send loopback data B270 to the self-test module B260 after receiving the output data B212. The self-test module B260 is used to provide a data self-test function based on the input data B210 and the loopback data B270. For the eye scan function, in some embodiments, the delay control signal is used to adjust the delay of the output data B212 so as to cooperate with the self-test module B260 to achieve the data eye scan function. It should be understood that in Figure 2 In the embodiment, the digital delay chain B250 is deployed outside the cross-clock domain sending control logic B240 and the cross-clock domain sending transmission logic B230. In some embodiments, the digital delay chain B250 can also be a part of the cross-clock domain sending control logic B240, or the digital delay chain B250 can also be a part of the cross-clock domain sending transmission logic B230.

[0035] In short, Figure 2The high-speed input and output device B200 shown in the figure introduces parameter N as a global parameter. Based on the high-speed and low-speed clock frequency ratio (the frequency of the read clock signal B216 is N times the frequency of the write clock signal B214), design constraints are set for the data format of the input data B210, the data format of the write enable control signal B220, and the specific method of writing the input data B210 into the first first-in-first-out memory B232 in the cross-clock domain transmission transmission logic B230. Specifically, these design constraints are set: single-shot N-bit N-shot Input data B210, N-bit write enable control signal B220, and write the N-beat input data B210 bit by bit according to the value of each bit in the N-bit write enable control signal B220; Based on the constraints of the established design, the write clock signal B214 in the write clock domain is used to coordinate when to receive the input data B210 for writing, thereby constructing a pipeline control for writing the transmission logic B230 across the clock domain, and realizing the cycle-level timing control of writing; Based on the constraints of the established design, the read clock signal B214 in the write clock domain is used to coordinate when to receive the input data B210 for writing. The read clock signal B216 of the domain is used to coordinate when to read the gating signal, and then the gating signal is used to gate the read clock signal to obtain the read enable control signal B222, thereby constructing the pipeline control of the reading of the cross-clock domain transmission transmission logic B230, and realizing the cycle-level timing control of the reading; combined with the data format of the input data B210, the data format of the write enable control signal B220, and the design constraints made on the specific method of writing the input data B210 into the first first-in-first-out memory B232 in the cross-clock domain transmission transmission logic B230, the cross-clock domain transmission transmission logic B230 is used to transmit the data to the first first-in-first-out memory B232. The generation mechanism of the read enable control signal B222 of the clock domain transmission control logic B240 avoids the interaction between the read and write pointers across clock domains, avoids the loss of clock signal edge judgment and transition edge triggering, and avoids the loss of frequent measurement and determination of clock phase differences, ensuring the correctness of data transmission control from the low-speed clock domain to the high-speed clock domain, and also ensures the correctness of the parallel-to-serial logic, effectively reducing the logic depth and chip complexity, helping to achieve higher speeds and reduce overall power consumption, which is conducive to meeting the requirements of increasingly higher transmission rates and cost control. In addition, Figure 2The device B200 for high-speed input and output shown in the figure implements additional control features by deploying functional modules. Specifically, the delay of the read enable control signal B222 being received by the cross-clock domain transmission logic B230 is adjusted through the digital delay chain B250, so as to adjust the delay of the output data B212 provided by the cross-clock domain transmission logic B230. This implements the delay adjustment logic, which can indirectly adjust the data delay through the clock delay, thereby achieving data and clock alignment on the DRAM side. In addition, the self-test module B260 and the single-ended output module B262 provide a loopback function to support the path test of the serial link, etc.

[0036] See Figure 1 and Figure 2 In one possible implementation, the input data includes parallel port data to be transmitted and a parallel port enable to be transmitted, and the output data includes serial port transmit data corresponding to the parallel port data to be transmitted and a serial port transmit enable corresponding to the parallel port enable to be transmitted. In this way, a parallel-to-serial conversion operation is achieved, and the interaction between read and write pointers across clock domains is avoided, the loss of clock signal edge judgment and transition edge triggering is avoided, and the loss of frequent measurement and determination of clock phase differences is avoided, ensuring the correctness of data transmission control when switching from a low-speed clock domain to a high-speed clock domain, effectively reducing logic depth and chip complexity, helping to achieve higher speeds and reduce overall power consumption, and helping to meet increasingly higher transmission rate requirements and cost control requirements.

[0037] In one possible implementation, the read enable control signal and the write enable control signal are used together to establish read and write pipeline control for the cross-clock domain transmission transmission logic. Thus, parameter N is introduced as a global parameter. Based on the high-speed / low-speed clock frequency ratio (the read clock signal frequency is N times the write clock signal frequency), design constraints are imposed on the data format of the input data, the data format of the write enable control signal, and the specific method of writing the input data to the first first-in-first-out memory in the cross-clock domain transmission transmission logic A130. Based on these established design constraints, the write clock signal in the write clock domain is used to coordinate when input data is received for writing, thereby establishing pipeline control for writing in the cross-clock domain transmission transmission logic and achieving cycle-level timing control for writing. Based on these established design constraints, the read clock signal in the read clock domain is used to coordinate when a gating signal is read, and the gating signal is then used to gate the read clock signal to obtain a read enable control signal, thereby establishing pipeline control for reading in the cross-clock domain transmission transmission logic and achieving cycle-level timing control for reading. The interaction between the read and write pointers across clock domains is avoided, and there is no need to perform edge judgment on the write clock signal or frequently determine the clock phase difference between the write clock signal and the read clock signal, which effectively reduces the logic depth and circuit complexity.

[0038] In one possible implementation, the cross-clock domain sending control logic is used to implement the control signal conversion from the write clock domain to the read clock domain in order to achieve cycle-level timing control. In this way, in order to ensure that the written data can be read correctly, it must be ensured that the data can be read after it is written and stabilized. In order to avoid the interaction between the write and read pointers in order to reduce the logic complexity, the optimized design of the cross-clock domain sending control logic and the design constraints around the parameter N are utilized to control the early or late arrival of the high-speed clock at the cross-clock domain sending transmission logic to achieve correct reading and writing of data. The generation mechanism of the read enable control signal of the cross-clock domain sending control logic is utilized to convert the write enable control signal to the high-speed clock domain, and the read clock signal is gated to obtain the read enable control signal by converting the cross-clock domain sending control logic to the gating signal of the high-speed clock domain. In this way, the read enable control signal can be used to control the time when the enable signal under the high-speed clock domain arrives at the cross-clock domain sending transmission logic to meet the cross-clock domain alignment requirements.

[0039] In one possible embodiment, the cross-clock domain transmission transmission logic is configured to write the N beats of input data into the first first-in-first-out memory in the cross-clock domain transmission transmission logic bit by bit based on the value of each bit in the N-bit write enable control signal, including: writing data at bits corresponding to the positions of the N bits of the write enable control signal that are 1 in each beat of the input data of the N beats of input data. Thus, with N as a global parameter, the data length of the write enable control signal is N bits, which is consistent with the parameter N in the N-bit single-beat input data of N beats, and also consistent with the frequency of the read clock signal being N times the frequency of the write clock signal. Based on the parameter N, design constraints are imposed on the specific method of writing input data into the first first-in-first-out memory in the cross-clock domain transmission logic, thereby realizing parallel-to-serial logic and avoiding the cross-clock domain interaction between the read and write pointers. There is no need to perform edge judgment on the write clock signal, nor is there a need to frequently determine the clock phase difference between the write clock signal and the read clock signal, thus effectively reducing the logic depth and circuit complexity.

[0040] In one possible embodiment, the cross-clock domain transmission transmission logic is configured to write the N beats of input data into the first first-in-first-out memory in the cross-clock domain transmission transmission logic bit by bit based on the value of each bit in the N-bit write enable control signal, including: writing data at bits corresponding to the positions of the N bits of the write enable control signal having a value of 0 in each beat of the input data of the N beats of input data. Thus, with N as a global parameter, the data length of the write enable control signal is N bits, which is consistent with the parameter N in the N-bit single-beat input data of N beats, and also consistent with the frequency of the read clock signal being N times the frequency of the write clock signal. Based on the parameter N, design constraints are imposed on the specific method of writing input data into the first first-in-first-out memory in the cross-clock domain transmission logic, thereby realizing parallel-to-serial logic and avoiding the cross-clock domain interaction between the read and write pointers. There is no need to perform edge judgment on the write clock signal, nor is there a need to frequently determine the clock phase difference between the write clock signal and the read clock signal, thus effectively reducing the logic depth and circuit complexity.

[0041] In a possible embodiment, the cross-clock domain sending control logic also includes a gating module, and the gating module is used to gate the read clock signal according to the gating signal to obtain the read enable control signal. In this way, the gating operation is realized by the gating module, and the optimized design of the cross-clock domain sending control logic and the design constraints around the parameter N are utilized to control the early or late arrival of the high-speed clock at the cross-clock domain sending transmission logic to achieve correct reading and writing of data. In other words, the generation mechanism of the read enable control signal of the cross-clock domain sending control logic is utilized to convert the write enable control signal to the high-speed clock domain, and the read clock signal is gated to obtain the read enable control signal by converting the cross-clock domain sending control logic to the gating signal of the high-speed clock domain. In this way, the read enable control signal can be used to control the time when the enable signal under the high-speed clock domain arrives at the cross-clock domain sending transmission logic to meet the cross-clock domain alignment requirements.

[0042] In one possible embodiment, the device further includes a digital delay chain, which is configured to adjust the delay of the read enable control signal received by the cross-clock domain transmission transmission logic based on a delay control signal, thereby adjusting the delay of the output data provided by the cross-clock domain transmission transmission logic. Thus, the digital delay chain provides an additional delay adjustment function, which can adjust the delay of the read enable control signal received by the cross-clock domain transmission transmission logic based on the delay control signal. This helps adjust the transmission delay logic to ensure correct data transmission. The delay adjustment function provided by the digital delay chain can effectively address the problem of delay differences between different traces on a circuit board. Specifically, there are multiple traces on a circuit board, with each input and output port corresponding to a separate trace. The delays between different traces may be different. This makes it difficult to sample correct data when sampling data signals transmitted through multiple traces using the same clock signal at a receiving end, such as a DRAM, due to the differences in trace delays. To this end, the delay adjustment function and delay adjustment logic provided by the digital delay chain can indirectly adjust the data delay by adjusting the clock delay, thereby achieving data-clock alignment on the DRAM side. The digital delay chain is used to correctly sample data on the DRAM side by adjusting the delay of data sent across clock domains to the transmission logic. By sending the high-speed clock after the gating operation of the control logic across clock domains, the data sent through the delayed clock of the digital delay chain can ensure that the correct data is sampled on the DRAM side. If the correct data is not sampled, the relationship between the data signal and the data clock signal can be adjusted by adjusting the delay, so that the center of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal. In some embodiments, the delay control signal is used to adjust the delay of the output data so that the center of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal. In this way, data-clock alignment is achieved, helping to ensure that the written data can be correctly sampled and read for output. The delay adjustment function aligns the middle of the data signal associated with the output data with the sampling clock edge of the data clock signal associated with the data signal, thereby improving the accuracy of the reading side and meeting the writing and reading requirements across clock domains.

[0043] In some embodiments, the device further includes a self-test module and a single-ended output module, wherein the single-ended output module is configured to selectively send data outward or send loopback data to the self-test module after receiving the output data, and the self-test module is configured to provide a data self-test function based on the input data and the loopback data. In this way, a data self-test function is provided by the self-test module and the single-ended output module. In this way, the device is used for high-speed input and output design and can be used to test the availability of the input and output functions of the chip during testing with automated test equipment. Specifically, data is sent through the transmission logic across the clock domain, and loopback data is provided to the self-test module after passing through the single-ended output module, that is, it returns to the receiving direction. Then, adaptive testing of the sampled data is implemented through a self-test module, such as a pseudo-random binary sequence (PRBS) test module. Then, combined with the delay adjustment function provided by the digital delay chain, data path connectivity testing can be implemented, and an eye diagram scanning function can be implemented. Generally, because the clock delay of the PRBS test module is fixed, data can be sampled from the right edge to the left edge of the data after the delay, thereby improving the test efficiency. In this way, data sent by the cross-clock domain transmission logic is looped back to the receiving direction (RX) self-test module, such as the PRBS verification module. This allows the cross-clock domain transmission control logic to control the clock of the cross-clock domain transmission transmission logic and thus control data reading. This ensures the correctness of the data looped back to the receiving direction and can verify the correctness of the data in the receiving direction. In addition, the delay of the high-speed clock is adjusted through the digital delay chain, thereby achieving data delay. This allows the entire data area to be scanned, thereby achieving the purpose of scanning the data eye diagram.

[0044] In some examples, the delay control signal is used to adjust the delay of the output data so as to cooperate with the self-test module to realize the data eye diagram scanning function. In this way, through the self-test module such as the PRBS check module, from output to input, the clock of the self-test module is not delayed, and the clock of the transmission logic sent across the clock domain is delayed by the digital delay chain. Therefore, an eye diagram scan can be performed. The eye diagram result indicates the quality of the input and output. In addition, the control code of the digital delay chain, that is, the delay control signal, can come from the outside and be generated by external logic in some embodiments. Using the data eye diagram scanning function, the quality of input and output can be conveniently judged, providing more flexibility at the control level.

[0045] In one possible implementation, the cross-clock domain transmission control logic is further configured to receive a set of control signals, wherein the set of control signals includes a power control signal and a terminal resistance control signal. Thus, the cross-clock domain transmission control logic is utilized to receive a series of control signals, including power control signals and terminal resistance control signals, to provide flexibility at the control level. As long as the cross-clock domain transmission control logic receives a write enable control signal and performs cross-clock domain conversion, it can provide a read enable control signal to establish cycle-level timing control for data reading in the cross-clock domain transmission transmission logic.

[0046] In one possible embodiment, the device is applied to high-speed input / output applications involving parallel-input and serial-output, including one or more of the following: the transmitter end of a serializer / deserializer, double-data-rate synchronous dynamic random access memory (SDRAM), low-power fifth-generation double-data-rate memory (DBR), high-bandwidth memory, die-to-die interconnection, automotive-grade chip interconnection, data center internal interconnection, and artificial intelligence platform internal interconnection. Thus, the device can be applied to high-speed input / output applications involving parallel-input and serial-output, meeting the parallel-to-serial conversion requirements of high-speed input / output applications, such as implementing an 8-to-1 data conversion operation on the physical layer side. It also significantly simplifies the control complexity of data transmission and the difficulty of implementing parallel-to-serial conversion logic, facilitating the control of advanced manufacturing processes and helping to reduce chip complexity and control costs.

[0047] Figure 3 A schematic diagram of the timing control function of sending control logic across clock domains provided in an embodiment of the present application. Figure 3 3 , an original clock signal 310 , an enable signal 320 , and a gated clock signal 330 are shown. Figure 3 The timing control function of sending control logic across clock domains shown corresponds to Figure 1 and Figure 2The generation mechanism of the read enable control signal of the cross-clock domain transmission control logic in the embodiment of the present invention is as follows. In this way, the written write enable control signal read from the second first-in-first-out memory is used as the read enable signal 320, which is used as a gating signal to gate the read clock signal, that is, to sample the original clock signal 310 in the high-speed clock domain, that is, the read clock signal (the frequency of the read clock signal is N times the frequency of the write clock signal), and obtain the gated clock signal 330, which is the read enable control signal and also the control signal for the pipeline control of data reading provided by the cross-clock domain transmission control logic. In this way, the read clock signal in the read clock domain is used to coordinate when to read the gate signal, and then the gate signal is used to gate the read clock signal to obtain the read enable control signal, thereby constructing the pipeline control of the read of the cross-clock domain transmission transmission logic, realizing the cycle-level timing control of the read, and also overcoming the problem of data transmission across clock domains and coping with the frequency difference and phase difference between the clock signals of two different clock domains. Furthermore, combined with the design constraints on the data format of the input data, the data format of the write enable control signal, and the specific method of writing the input data into the first first-in-first-out memory in the cross-clock domain transmission transmission logic, the generation mechanism of the read enable control signal of the cross-clock domain transmission control logic is utilized to avoid the interaction between the read and write pointers across clock domains, avoid the loss of clock signal edge judgment and transition edge triggering, and avoid the loss of frequent measurement and determination of clock phase differences, ensure the correctness of data transmission control from the low-speed clock domain to the high-speed clock domain, and ensure the correctness of the parallel-to-serial logic, effectively reduce the logic depth and chip complexity, help to achieve higher speeds and reduce overall power consumption, and help meet the requirements of increasingly higher transmission rates and cost control.

[0048] Figure 4 A schematic diagram of the delay adjustment function of the digital delay chain provided in an embodiment of the present application. Figure 4 4 shows a clock A401 before delay adjustment, data A403 before delay adjustment, a clock B411 after delay adjustment, and data B413 after delay adjustment. Figure 1 and Figure 2The device for high-speed input and output shown may include a digital delay chain, which is used to adjust the delay of the read enable control signal received by the cross-clock domain transmission transmission logic according to a delay control signal, so as to adjust the delay of the output data provided by the cross-clock domain transmission transmission logic. In some embodiments, the delay control signal is used to adjust the delay of the output data so that the middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal. In this way, an additional delay adjustment function is provided by the digital delay chain, and the delay of the read enable control signal received by the cross-clock domain transmission transmission logic can be adjusted according to the delay control signal, which helps to adjust the logic of the transmission delay to ensure the correct transmission of data. The delay adjustment function provided by the digital delay chain can effectively deal with the problem of delay differences between different traces on the circuit board. Specifically, there are multiple traces on a circuit board, with each input and output port corresponding to a separate trace. The delays between different traces can vary. This makes it difficult to sample the correct data at the receiving end, such as a DRAM, when using the same clock signal to sample data signals transmitted through multiple traces due to the differences in trace delays. To address this issue, the delay adjustment function and delay adjustment logic provided by the digital delay chain indirectly adjust the data delay by adjusting the clock delay, thereby achieving data and clock alignment on the DRAM side. Figure 4 As shown in FIG, the delay adjustment function and delay adjustment logic of the digital delay chain are used to achieve alignment of data and clock, which is helpful in overcoming problems such as routing delay differences.

[0049] Figure 5 This is a schematic diagram of using the delay adjustment function of the digital delay chain to adjust the delay of multiple lines according to the embodiment of the present application. Figure 5As shown, the situation before adjustment is A501, the reference clock before adjustment is A503, the data before adjustment is A505, and the data before adjustment is A507. It can be seen that there are multiple traces on the circuit board, and each input and output port corresponds to a separate trace. The delays between different traces may be different. This makes it difficult to sample the correct data when the same clock signal is used to sample the data signals transmitted through multiple traces at the receiving end, such as the DRAM side, due to the differences in trace delays. To this end, the delay adjustment function and delay adjustment logic provided by the digital delay chain can be used to indirectly adjust the data delay by adjusting the clock delay, thereby achieving the function of aligning data with the clock on the DRAM side. Using the digital delay chain, the correct sampling of data on the DRAM side is achieved by adjusting the delay of the data transmitted through the transmission logic across the clock domain. By sending the high-speed clock after the gating operation of the control logic across clock domains, the data sent through the delayed clock of the digital delay chain can ensure that the correct data is sampled on the DRAM side. Moreover, if the correct data cannot be sampled, the relationship between the data signal and the data clock signal can be adjusted by adjusting the delay, so that the middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal. The situation after adjustment is the adjusted reference clock B511, the adjusted data of routing A B513, the adjusted data of routing B B515, and the adjusted data of routing C B517. In this way, the alignment of data and clock is achieved, which helps to ensure that the written data can be correctly sampled and read for output. The delay adjustment function aligns the middle of the data signal associated with the output data with the sampling clock edge of the data clock signal associated with the data signal, thereby improving the accuracy of the reading side and helping to meet the writing and reading requirements across clock domains.

[0050] Figure 6 A schematic diagram of an embodiment of the present application providing a method for performing data eye diagram scanning using the data self-test function of the self-test module and the delay adjustment function of the digital delay chain. Figure 6The figure shows the clock 601, delayed data A 603, delayed data B 605, and delayed data C 607 of the self-test module. Here, the device for high-speed input and output also includes a self-test module and a single-ended output module. The single-ended output module is configured to selectively transmit data externally or send loopback data to the self-test module after receiving the output data. The self-test module is configured to provide a data self-test function based on the input data and the loopback data. The delay control signal is used to adjust the delay of the output data so as to cooperate with the self-test module to implement a data eye scan function. Thus, the self-test module and the single-ended output module provide a data self-test function. This device is used in high-speed input and output designs and can be used to test the availability of a chip's input and output functions during automated testing equipment. Specifically, data is transmitted through transmission logic across clock domains. After passing through the single-ended output module, loopback data is provided to the self-test module, returning the data to the receiving direction. Then, the self-test module, such as a pseudo-random binary sequence verification module, performs adaptive verification of the sampled data. Combined with the delay adjustment function provided by the digital delay chain, data path connectivity testing and eye diagram scanning can be performed. Generally, because the clock delay of the PRBS verification module is fixed, data can be sampled from the right edge to the left edge after the delay, improving verification efficiency. In this way, data sent by the cross-clock domain transmission logic is looped back to the receive (RX) self-test module, such as the PRBS verification module. This allows the cross-clock domain transmission control logic to control the clock of the cross-clock domain transmission logic, thereby controlling data reading. This ensures the accuracy of the looped-back data and allows data accuracy verification in the receive direction. Furthermore, by adjusting the high-speed clock delay through the digital delay chain, data delay is achieved, allowing the entire data region to be scanned, achieving the goal of scanning the data eye diagram. From the output to the input of a self-test module, such as the PRBS verification module, the self-test module clock is not delayed, while the cross-clock domain transmission logic clock is delayed by the digital delay chain, enabling eye diagram scanning. The eye diagram results indicate the quality of the input and output. Furthermore, in some embodiments, the control code for the digital delay chain, i.e., the delay control signal, can be externally generated by external logic. The data eye scan function facilitates the determination of input and output quality, providing greater control flexibility.

[0051] Figure 7 This is a flow chart of a method for high-speed input and output provided in an embodiment of the present application. Figure 7 As shown, the method includes the following steps.

[0052] Step S701: Through the cross-clock domain transmission logic, N beats of input data of a single beat of N bits are periodically received according to the write clock signal in the write clock domain, and, according to the value of each bit in the N-bit write enable control signal, the N beats of input data are written bit by bit to the first first-in-first-out memory in the cross-clock domain transmission logic, and the first first-in-first-out memory is read as output data according to the read enable control signal.

[0053] Step S703: Write the write enable control signal to the second first-in-first-out memory in the cross-clock domain sending control logic through the cross-clock domain sending control logic, and read the second first-in-first-out memory as a gating signal according to the read clock signal in the read clock domain, and gate the read clock signal according to the gating signal to obtain the read enable control signal, wherein the frequency of the read clock signal is N times the frequency of the write clock signal, and N is a positive integer greater than 1 and equal to 1.

[0054] Figure 7The method for high-speed input and output shown introduces parameter N as a global parameter. Based on the high-speed and low-speed clock frequency ratio (the frequency of the read clock signal is N times the frequency of the write clock signal), design constraints are imposed on the data format of the input data, the data format of the write enable control signal, and the specific method of writing the input data into the first first-in-first-out memory in the cross-clock domain transmission transmission logic. These design constraints are specifically formulated: single-beat N-bit input data of N beats, N-bit write enable control signal, and writing the N beats of input data bit by bit according to the value of each bit in the N-bit write enable control signal; based on the formulated design constraints, the write clock signal in the write clock domain is used to coordinate when to receive the input data for writing, thereby constructing the pipeline control of the write of the cross-clock domain transmission transmission logic and realizing the cycle-level timing control of the write; based on the formulated design constraints, the read clock signal in the read clock domain is used to coordinate When the gating signal is read, the gating signal is used to gate the read clock signal to obtain the read enable control signal, thereby constructing the pipeline control of the reading of the cross-clock domain transmission transmission logic and realizing the cycle-level timing control of the reading; combined with the design constraints on the data format of the input data, the data format of the write enable control signal, and the specific method of writing the input data to the first first-in-first-out memory in the cross-clock domain transmission transmission logic, the generation mechanism of the read enable control signal of the cross-clock domain transmission control logic is used to avoid the interaction between the read and write pointers across clock domains, avoid the loss of clock signal edge judgment and jump edge triggering, and avoid the loss of frequent measurement and determination of clock phase difference, ensure the correctness of data transmission control from the low-speed clock domain to the high-speed clock domain, and ensure the correctness of the parallel-to-serial logic, effectively reduce the logic depth and chip complexity, help to achieve higher speeds and reduce overall power consumption, and help meet the requirements of increasingly higher transmission rates and cost control.

[0055] See Figure 7In one possible embodiment, the method further includes: adjusting, via a digital delay chain, the delay of the read enable control signal received by the cross-clock domain transmission logic according to a delay control signal, thereby adjusting the delay of the output data provided by the cross-clock domain transmission logic. In this way, the digital delay chain provides an additional delay adjustment function, allowing the delay of the read enable control signal received by the cross-clock domain transmission logic to be adjusted according to the delay control signal. This helps adjust the transmission delay logic to ensure correct data transmission. The delay adjustment function provided by the digital delay chain can effectively address the problem of delay differences between different traces on a circuit board. Specifically, there are multiple traces on a circuit board, with each input and output port corresponding to a separate trace. The delays between different traces may vary. This makes it difficult to sample correct data at a receiving end, such as a DRAM, when sampling data signals transmitted through multiple traces using the same clock signal due to the differences in trace delays. To this end, the delay adjustment function and delay adjustment logic provided by the digital delay chain can indirectly adjust the data delay by adjusting the clock delay, thereby achieving data-clock alignment on the DRAM side. The digital delay chain is used to correctly sample data on the DRAM side by adjusting the delay of data sent across clock domains to the transmission logic. By sending the high-speed clock after the gating operation of the control logic across clock domains, the data sent through the delayed clock of the digital delay chain can ensure that the correct data is sampled on the DRAM side. If the correct data is not sampled, the relationship between the data signal and the data clock signal can be adjusted by adjusting the delay, so that the center of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal. In some embodiments, the delay control signal is used to adjust the delay of the output data so that the center of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal. In this way, data-clock alignment is achieved, helping to ensure that the written data can be correctly sampled and read for output. The delay adjustment function aligns the middle of the data signal associated with the output data with the sampling clock edge of the data clock signal associated with the data signal, thereby improving the accuracy of the reading side and meeting the writing and reading requirements across clock domains.

[0056] The methods and devices provided in the embodiments of the present application are based on the same inventive concept. Since the principles of the methods and devices for solving problems are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0057] The present application also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed on a computer device (e.g., one or more processors), the method steps described in the above method embodiments can be implemented. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be further described here.

[0058] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part via software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part as a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. The computer program product comprises one or more computer instructions. When loaded or executed on a computer, the computer program instructions fully or partially perform the processes or functions described in the embodiments of the present application. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that contains a collection of one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, or magnetic tape), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable storage medium.

[0059] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including the instruction device, which implements the function specified in the process. Figure 1a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0060] In the above embodiments, the descriptions of each embodiment have different emphases. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in sequence, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A device for high-speed input and output, characterized in that: The device comprises: Cross-clock domain transmission transmission logic is used to periodically receive N beats of single-beat N-bit input data according to a write clock signal in a write clock domain, and write the N beats of input data bit by bit to a first first-in-first-out memory in the cross-clock domain transmission transmission logic according to the value of each bit in an N-bit write enable control signal, and read the first first-in-first-out memory as output data according to a read enable control signal; The cross-clock domain sending control logic is used to write the write enable control signal to the second first-in-first-out memory in the cross-clock domain sending control logic, and read the second first-in-first-out memory as a gating signal according to the read clock signal in the read clock domain, and gate the read clock signal according to the gating signal to obtain the read enable control signal, wherein the frequency of the read clock signal is N times the frequency of the write clock signal, and N is a positive integer greater than 1 and equal to 1.

2. The device according to claim 1, characterized in that The input data includes parallel port data to be transmitted and a parallel port enable to be transmitted, and the output data includes serial port send data corresponding to the parallel port data to be transmitted and a serial port send enable corresponding to the parallel port enable to be transmitted.

3. The device according to claim 1, characterized in that The read enable control signal and the write enable control signal are used together to establish the read and write pipeline control of the cross-clock domain transmission transmission logic.

4. The device according to claim 1, characterized in that The cross-clock domain transmission control logic is used to implement control signal conversion from the write clock domain to the read clock domain so as to achieve cycle-level timing control.

5. The device according to claim 1, characterized in that The cross-clock domain transmission transmission logic is configured to write the N beats of input data into the first first-in-first-out memory in the cross-clock domain transmission transmission logic bit by bit according to the value of each bit in the N-bit write enable control signal, including: According to the position of the bit with a value of 1 in the N bits of the write enable control signal, the data on the bit corresponding to the position of the bit with a value of 1 in the N bits of the write enable control signal in each beat of the input data of the N beats is written.

6. The device according to claim 1, characterized in that The cross-clock domain transmission transmission logic is configured to write the N beats of input data into the first first-in-first-out memory in the cross-clock domain transmission transmission logic bit by bit according to the value of each bit in the N-bit write enable control signal, including: According to the position of the bit with a value of 0 in the N bits of the write enable control signal, data on the bit corresponding to the position of the bit with a value of 0 in the N bits of the write enable control signal in the input data of each beat of the N beats of input data is written.

7. The device according to claim 1, characterized in that The cross-clock domain transmission control logic further includes a gating module, which is configured to gate the read clock signal according to the gating signal to obtain the read enable control signal.

8. The device according to claim 1, characterized in that The device also includes a digital delay chain, which is used to adjust the delay of the read enable control signal being received by the cross-clock domain transmission transmission logic according to a delay control signal, so as to adjust the delay of the output data provided by the cross-clock domain transmission transmission logic.

9. The device according to claim 8, characterized in that The delay control signal is used to adjust the delay of the output data so that the middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal.

10. The device according to claim 8, characterized in that The device also includes a self-test module and a single-ended output module. The single-ended output module is used to selectively send data externally or send loopback data to the self-test module after receiving the output data. The self-test module is used to provide a data self-test function based on the input data and the loopback data.

11. The device according to claim 10, characterized in that The delay control signal is used to adjust the delay of the output data so as to cooperate with the self-test module to realize the data eye diagram scanning function.

12. The device according to claim 1, characterized in that The cross-clock domain transmission control logic is further configured to receive a control signal set, wherein the control signal set includes a power control signal and a terminal resistance control signal.

13. The device according to claim 1, characterized in that The device is applied to high-speed input and output application scenarios of serial in / out, and the high-speed input and output application scenarios include one or more of the following: the transmitting end of the serializer / deserializer, double data rate synchronous dynamic random access memory, low-power fifth-generation double data rate memory, high-bandwidth memory, die-to-die interconnection, automotive-grade chip interconnection, internal interconnection of data centers, and internal interconnection of artificial intelligence platforms.

14. A method for high-speed input and output, characterized in that: The method comprises: Periodically receiving N beats of input data of N bits in a single beat according to a write clock signal in a write clock domain through a cross-clock domain transmission transmission logic, and writing the N beats of input data bit by bit to a first first-in-first-out memory in the cross-clock domain transmission transmission logic according to the value of each bit in an N-bit write enable control signal, and reading the first first-in-first-out memory as output data according to a read enable control signal; The write enable control signal is written to the second first-in-first-out memory in the cross-clock domain sending control logic by sending the control logic across the clock domain, and the second first-in-first-out memory is read as a gating signal according to the read clock signal in the read clock domain, and the read clock signal is gated according to the gating signal to obtain the read enable control signal, wherein the frequency of the read clock signal is N times the frequency of the write clock signal, and N is a positive integer greater than 1 and equal to 1.

15. The method according to claim 14, characterized in that The method further includes adjusting, by a digital delay chain, a delay of the read enable control signal being received by the cross-clock domain transmission transmission logic according to a delay control signal, so as to adjust a delay of the output data provided by the cross-clock domain transmission transmission logic.

16. The method according to claim 15, characterized in that The delay control signal is used to adjust the delay of the output data so that the middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal.

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