Frame buffer storage controller, frame buffer storage control method and display equipment

Abstract

The invention discloses a frame buffer storage controller, a frame buffer storage control method and a display device, in the frame buffer storage controller, a frame buffer storage unit comprises a first buffer area and a second buffer area, the storage space of the first buffer area is larger than the storage space of the second buffer area, and if a read-write conflict occurs, the first buffer area and the second buffer area are connected in parallel. The frame buffer control unit changes the first address information into second address information according to the buffer allocation correspondence, and generates a second write request signal based on the second address information; and the frame buffer storage unit writes the updated frame data into a storage area indicated by the second address information in the second buffer area according to the second write request signal. The storage space of the second buffer area is set to be smaller than the storage space of the first buffer area, so that the storage structure is optimized, and the space resource utilization rate is improved; the read-write behavior of the frame data is controlled through the frame buffer control unit, efficient data updating and display control are achieved, normal display of the display device is guaranteed, and the overall stability of the system is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a frame buffer storage controller, a frame buffer storage control method and a display device. Background Art

[0002] With the rapid development of display technology, power consumption and cost, as product performance indicators, have become increasingly important in the R&D and design of display products. To reduce the power consumption of display products, Panel Self Refresh (PSR) technology has been proposed.

[0003] In PSR technology, when the display system's screen display content update is inactive or the display system is in a static screen display state, the overall power consumption of the display system is saved by temporarily disconnecting the main transmission link (Main-LinkOff) for transmitting frame data and storing the current frame data used for image display in the remote frame buffer (RFB) unit.

[0004] Therefore, when the display system enters PSR mode, frame data needs to be written to the RFB unit for storage, and the display system reads the frame data from the RFB unit for image display. This requires that the size of the RFB unit is at least larger than the size of the storage space corresponding to the frame data of one frame of image.

[0005] Existing RFB units often use a double-frame buffer configuration. This means the RFB unit includes two frame buffers, each storing the data for a single frame. While the display system reads frame data from one frame buffer to display the current image, the other receives and writes updated frame data. Using two frame buffers allows for separate read and write operations for frame data.

[0006] However, in the aforementioned Double-Frame Buffer RFB unit, when image frame data is not being updated, only the frame buffer memory used for the current image display is active, while the other frame buffer memory used for receiving updated frame data is completely idle. This results in a significant waste of storage space resources corresponding to the frame data for an entire image frame. Summary of the Invention

[0007] The present invention provides a frame buffer memory controller, a frame buffer memory control method and a display device, which are used to solve the problem of waste of storage space resources in the existing RFB unit.

[0008] In a first aspect, an embodiment of the present invention provides a frame buffer memory controller, comprising a frame buffer control unit and a frame buffer memory unit, wherein the frame buffer memory unit comprises a first buffer zone for display cache and a second buffer zone for backup cache, wherein the storage space of the first buffer zone is larger than the storage space of the second buffer zone, wherein:

[0009] the frame buffer control unit being configured to determine whether a read-write conflict occurs based on the read request signal and the first write request signal, and when a read-write conflict occurs, change first address information determined based on the first write request signal to second address information based on the buffer allocation correspondence, and generate a second write request signal based on the second address information;

[0010] the frame buffer storage unit being configured to write updated frame data into a storage area indicated by the second address information in the second buffer according to the second write request signal, and to read frame data from the first buffer according to the read request signal;

[0011] Among them, the read request signal is generated after receiving the PSR status indication, the first write request signal is generated after receiving the updated frame data, and the buffer allocation correspondence is used to characterize the correspondence between the address information in the frame buffer storage unit and the buffer ownership information.

[0012] In the frame buffer storage controller provided by an embodiment of the present invention, since the storage space of the second buffer is smaller than the storage space of the first buffer, the total storage space of the frame buffer storage unit is smaller than the storage space required for the frame data included in two image frames, thereby optimizing the frame buffer storage structure, reducing redundancy in the data storage process, improving the space resource utilization of the frame buffer storage controller, and achieving cost savings; in addition, the frame buffer control unit controls the read and write behavior logic of the frame data, adaptively avoiding the read and write conflict problem in the PSR mode, achieving efficient data update control and data display control, ensuring the normal display of the display device, and providing overall stability of the display system.

[0013] In an optional embodiment, the frame buffer control unit is specifically configured to:

[0014] generating the read request signal based on a first timing signal, and generating the first write request signal based on the update frame data and a second timing signal, wherein the first timing signal is generated after receiving the PSR status indication, and the second timing signal and the update frame data are provided by an image output device;

[0015] parsing the read request signal to obtain third address information, and parsing the first write request signal to obtain the first address information;

[0016] It is determined whether a read-write conflict occurs according to the first address information and the third address information.

[0017] The above-mentioned frame buffer storage controller judges the read-write conflict through the third address information corresponding to the read request signal and the first address information corresponding to the first write request signal, thereby improving the accuracy of the judgment result, so as to ensure that the frame buffer control unit can adaptively avoid the read-write conflict problem in the PSR mode, realize efficient data update control and data display control, and ensure the normal display of the display device.

[0018] In an optional embodiment, the frame buffer control unit is specifically configured to:

[0019] If a row position corresponding to the first data in the image frame is greater than or equal to a row position corresponding to the second data in the image frame, a read-write conflict occurs, wherein the first data is data stored in the storage area indicated by the first address information, and the second data is data stored in the storage area indicated by the third address information;

[0020] If the row position corresponding to the first data in the image frame is smaller than the row position corresponding to the second data in the image frame, no read-write conflict occurs.

[0021] The above-mentioned frame buffer storage controller determines whether a read-write conflict occurs by determining the relationship between the row position in the image frame corresponding to the data to be read by the read request signal and the row position in the image frame corresponding to the data stored in the address to be written by the first write request signal, thereby ensuring that the frame buffer control unit can adaptively avoid the read-write conflict problem in the PSR mode, realize efficient data update control and data display control, and ensure normal display of the display device.

[0022] In an optional embodiment, the frame buffer control unit is further configured to:

[0023] When no read-write conflict occurs, outputting the first write request signal;

[0024] The frame buffer storage unit is further used for:

[0025] The updated frame data is written into a storage area indicated by the first address information in the first buffer according to the first write request signal.

[0026] The above-mentioned frame buffer storage controller directly sends the first write request signal to the frame buffer storage unit when the frame buffer control unit determines that no read-write conflict occurs, so that the frame buffer storage unit stores the updated frame data in the storage area indicated by the first write request signal, thereby realizing the image update operation.

[0027] In an optional embodiment, the frame buffer control unit is further configured to:

[0028] After reading frame data from the first buffer, the buffer affiliation information corresponding to the first address information is changed to the second buffer, and the buffer affiliation information corresponding to the second address information is changed to the first buffer, so as to update the buffer allocation correspondence.

[0029] In an optional embodiment, the frame buffer control unit is further configured to:

[0030] determining fourth address information corresponding to a storage area for storing third data, wherein a row position corresponding to the third data in the image frame is adjacent to a row position corresponding to fourth data in the image frame, and the fourth data is data stored in the storage area indicated by the second address information;

[0031] A read sequence connection is established for the fourth address information and the second address information according to a row position in the image frame corresponding to the third data and a row position in the image frame corresponding to the fourth data.

[0032] The above-mentioned frame buffer storage controller updates the buffer allocation correspondence after the frame data corresponding to the current image frame is read, and establishes a new read sequence connection for the updated address information, so that in the next display cycle, the frame data stored in the storage area belonging to the first buffer zone is read according to the new read sequence connection, thereby allowing the display device to display the updated image frame.

[0033] In an optional embodiment, the frame buffer control unit is further configured to:

[0034] The read request signal and the second write request signal are output alternately in a time-division multiplexing manner.

[0035] The frame buffer memory controller, when the frame buffer memory unit is a single-port communication memory unit, alternately outputs a read request signal and a second write request signal in a time-division multiplexing manner, so that the frame buffer memory unit can achieve an effect equivalent to parallel reading and writing, thereby improving data access efficiency.

[0036] In an optional embodiment, the frame buffer control unit is further configured to:

[0037] The read request signal and the first write request signal are buffered so that the first timing signal included in the read request signal is synchronized with the second timing signal included in the first write request signal.

[0038] The frame buffer storage controller and the frame buffer control unit buffer the read request signal and the first write request signal to ensure that the first timing signal and the second timing signal are in the same clock domain, thereby eliminating potential asynchronous problems and ensuring efficient read and write operations.

[0039] In a second aspect, an embodiment of the present invention provides a frame buffer storage control method, which is applied to the frame buffer storage controller according to any one of the embodiments of the first aspect above, the method comprising:

[0040] Determining whether a read-write conflict occurs based on a read request signal and a first write request signal, wherein the read request signal is generated after receiving a PSR status indication, and the first write request signal is generated after receiving update frame data;

[0041] When a read-write conflict occurs, changing the first address information determined according to the first write request signal to second address information according to the buffer allocation correspondence, and generating a second write request signal based on the second address information;

[0042] writing the updated frame data into a storage area indicated by the second address information in the second buffer according to the second write request signal, and reading the frame data from the first buffer according to the read request signal;

[0043] Among them, the first buffer is used for display cache, the second buffer is used for backup cache, the storage space of the first buffer is larger than the storage space of the second buffer, and the buffer allocation correspondence is used to characterize the correspondence between the address information in the frame buffer storage unit and the buffer ownership information.

[0044] In an optional embodiment, determining whether a read-write conflict occurs based on the read request signal and the first write request signal includes:

[0045] generating the read request signal based on a first timing signal, and generating the first write request signal based on the update frame data and a second timing signal, wherein the first timing signal is generated after receiving the PSR status indication, and the second timing signal and the update frame data are provided by an image output device;

[0046] parsing the read request signal to obtain third address information, and parsing the first write request signal to obtain the first address information;

[0047] Whether a read-write conflict occurs is determined according to the first address information and the third address information.

[0048] In an optional embodiment, determining whether a read-write conflict occurs according to the first address information and the third address information includes:

[0049] If a row position corresponding to the first data in the image frame is greater than or equal to a row position corresponding to the second data in the image frame, a read-write conflict occurs, wherein the first data is data stored in the storage area indicated by the first address information, and the second data is data stored in the storage area indicated by the third address information;

[0050] If the row position corresponding to the first data in the image frame is smaller than the row position corresponding to the second data in the image frame, no read-write conflict occurs.

[0051] In an optional embodiment, after determining whether a read-write conflict occurs, the method further includes:

[0052] When no read-write conflict occurs, outputting the first write request signal;

[0053] The updated frame data is written into a storage area indicated by the first address information in the first buffer according to the first write request signal.

[0054] In an optional embodiment, after reading the frame data from the first buffer is completed, the method further includes:

[0055] The buffer zone affiliation information corresponding to the first address information is changed to the second buffer zone, and the buffer zone affiliation information corresponding to the second address information is changed to the first buffer zone, so as to update the buffer allocation correspondence.

[0056] In an optional embodiment, after updating the buffer allocation correspondence, the method further includes:

[0057] determining fourth address information corresponding to a storage area for storing third data, wherein a row position corresponding to the third data in the image frame is adjacent to a row position corresponding to fourth data in the image frame, and the fourth data is data stored in the storage area indicated by the second address information;

[0058] A read sequence connection is established for the fourth address information and the second address information according to a row position in the image frame corresponding to the third data and a row position in the image frame corresponding to the fourth data.

[0059] In an optional embodiment, after generating the second write request signal, the method further includes:

[0060] The read request signal and the second write request signal are output alternately in a time-division multiplexing manner.

[0061] In an optional embodiment, after generating the read request signal and the first write request signal, the method further includes:

[0062] The read request signal and the first write request signal are buffered so that the first timing signal included in the read request signal is synchronized with the second timing signal included in the first write request signal.

[0063] In a third aspect, an embodiment of the present invention provides a display device, comprising a display module and a frame buffer memory controller as described in any one of the embodiments of the first aspect, wherein:

[0064] The display module is used to display image frames according to the read frame data.

[0065] For the technical effects that may be achieved by the frame buffer storage control method disclosed in the second aspect and the display device disclosed in the third aspect, please refer to the above description of the technical effects that can be achieved by the first aspect or various possible solutions in the first aspect, and no further details will be given here.

[0066] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0068] Figure 1 A schematic diagram of an application scenario of a frame buffer memory controller provided by an embodiment of the present invention;

[0069] Figure 2 A schematic diagram of the module structure of a display system provided by an embodiment of the present invention;

[0070] Figure 3 A schematic diagram of the module structure of a frame buffer memory controller provided by an embodiment of the present invention;

[0071] Figure 4 A schematic diagram of the internal structure of a frame buffer storage unit provided by an embodiment of the present invention;

[0072] Figure 5A schematic diagram of the internal structure of another frame buffer storage unit provided by an embodiment of the present invention;

[0073] Figure 6 A schematic diagram of the internal structure of a frame buffer control unit provided by an embodiment of the present invention;

[0074] Figure 7 A schematic diagram of the internal structure of a read-write behavior control subunit provided by an embodiment of the present invention;

[0075] Figure 8 A schematic diagram of the internal structure of a frame buffer management subunit provided by an embodiment of the present invention;

[0076] Figure 9 A schematic diagram of the internal structure of a frame buffer memory controller provided by an embodiment of the present invention;

[0077] Figure 10 A schematic diagram of a complete workflow based on a frame buffer memory controller provided by an embodiment of the present invention;

[0078] Figure 11 A schematic diagram of the workflow of a frame buffer storage control method provided by an embodiment of the present invention;

[0079] Figure 12 A schematic diagram of a mode structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0080] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only some, not all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0081] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of apparatus and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0082] As mentioned earlier, PSR technology is used to reduce the power consumption of display products. Its implementation requires the cooperation of both the source and receiver. The source is typically a product with image output capabilities, such as a host computer, while the receiver is a product with image display capabilities, such as a monitor.

[0083] Specifically, when the display system's screen display content is not actively updated or the display system is in a static screen display state, the source sends a status indication and current frame data to the receiver. The receiver caches the current frame data in the RFB unit for use in the static screen display of the display system and enters PSR mode based on the status indication, temporarily disconnecting the main transmission link (Main-Link Off) between the receiver and the source to stop frame data transmission, thereby achieving energy conservation and reducing system power consumption. Only when the image frame is updated will the source send the status indication and updated frame data to the receiver again to update the displayed image.

[0084] When the display system is in PSR mode, it stores the received frame data in the RFB unit and reads the frame data from the RFB unit to display the image. Therefore, the size of the RFB unit must be at least larger than the storage space corresponding to the frame data of one frame of image.

[0085] Existing RFB units often use a double-frame buffer configuration. This means the RFB unit includes two frame buffers, each storing the data for a single frame. The two frame buffers operate alternately: while the display system reads frame data from one frame buffer to display the current image, the other receives and writes updated frame data.

[0086] The above RFB unit can realize the read and write separation of frame data by using two frame buffer memories, thus avoiding the occurrence of read and write conflicts. However, the following problems may occur:

[0087] 1. Waste of storage space: When image frame data is not updated, only the frame buffer memory used for the current image display is active, while the other frame buffer memory used for receiving updated frame data is completely idle. As a result, the storage space resources corresponding to the frame data of an entire image are wasted.

[0088] 2. There are defects in the compatibility of PSR functions: When local frame data is updated, targeted design is required to address the compatibility issues of data migration in the unupdated area. There is a lack of adaptive compatibility, and there will be multiple read and write situations in this process, which will generate additional power consumption.

[0089] Based on this, an embodiment of the present invention provides a frame buffer storage controller, a frame buffer storage control method and a display device to optimize the spatial resource structure of the RFB unit, improve the utilization rate of the storage space resources of the RFB unit, and design the read-write control logic of the optimized RFB unit to solve the problem that the existing read-write separation control logic is not suitable for the optimized RFB unit.

[0090] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to illustrate the present invention and are not intended to limit the present invention.

[0091] The following describes the application scenarios of the frame buffer memory controller provided by the present invention with reference to the accompanying drawings:

[0092] The frame buffer memory controller provided by the embodiment of the present invention can be applied in the application scenario of the display system. Figure 1 A schematic diagram showing an application scenario of a frame buffer memory controller provided by an embodiment of the present invention is shown. Figure 1 As shown, the display 10 and the server 20 are communicatively connected via the Internet, a frame buffer memory controller is provided in the display 10 , and an image output device, such as a GPU (Graphic Processing Unit), is provided in the server 20 .

[0093] In a specific implementation, when the screen display content update of the display 10 is not active or the display 10 is in a static screen display state, the image output device in the server 20 will send a PSR status indication and frame data corresponding to an image frame to the display 10. Under the control of the PSR status indication, the display 10 enters the PSR mode and stores the received frame data in the frame buffer storage controller of the display 10. The display 10 reads the frame data stored in the frame buffer storage controller to realize the display of the image frame.

[0094] When the display 10 is in PSR mode, when the frame data is updated, the updated frame data is written into the frame buffer storage controller and the frame data is read from the frame buffer storage controller in accordance with the method provided in the embodiment of the present invention to avoid read-write conflicts and ensure that the display 10 displays the image frame normally.

[0095] Of course, the device provided in the embodiment of the present invention is not limited to Figure 1 The application scenarios shown can also be used in other possible application scenarios, such as televisions, laptops, etc., and the embodiments of the present invention are not limited thereto. Figure 1 The functions that can be achieved by each part of the application scenario shown will be described in subsequent embodiments and will not be described in detail here.

[0096] After introducing the application scenarios of the embodiments of the present invention, the preferred implementation methods of the present invention are further described in detail with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other if there is no conflict.

[0097] The overall working logic of the frame buffer memory controller provided by the present invention is specifically described below with reference to the accompanying drawings:

[0098] In one or more embodiments, Figure 2 As shown, the image output device 210 and the display device 220 are communicatively connected via eDP (Embedded DisplayPort), wherein the display device 220 is provided with a PSR state controller 2201, a PSR timing controller 2202, a frame buffer storage controller 2203 and a display module 2204.

[0099] In a specific implementation, when the image output device 210 detects that the screen display content update is inactive or is currently in a static screen display state, it sends a PSR state indication and frame data included in an image frame to the PSR state controller 2201 in the display device 220 via eDP, and temporarily disconnects the data transmission link between the display device 220 and the image output device 210.

[0100] After receiving the PSR status indication and frame data, the PSR state controller 2201 controls the display device 220 to enter the PSR mode, outputs a PSR status control signal to the PSR timing controller 2202, and sends the frame data to the frame buffer memory controller 2203 for storage;

[0101] After receiving the PSR status control signal, the PSR timing controller 2202 generates a first timing signal to control the reading of frame data in the frame buffer storage controller 2203; the frame buffer storage controller 2203 transmits the read frame data to the display module 2204 under the control of the first timing signal, and the display module 2204 displays the image frame according to the received frame data.

[0102] When the display image frame needs to be updated, the image output device 210 will resend the PSR status indication and the updated frame data included in the updated image frame to the PSR status controller 2201; the PSR status controller 2201 sends the updated frame data to the frame buffer storage controller 2203, and the frame buffer storage controller 2203 writes the updated frame data into the frame buffer storage unit of the frame buffer storage controller 2203 in accordance with the method provided in the above embodiment to realize the update of the display image frame, thereby enabling the display module 2204 to realize self-refresh display of the display panel.

[0103] The frame buffer memory controller provided by the present invention is specifically described below with reference to the accompanying drawings:

[0104] Figure 2 A schematic diagram of the unit structure of a frame buffer memory controller is shown in FIG. Figure 3 As shown, the frame buffer memory controller 2203 includes a frame buffer control unit 310 and a frame buffer memory unit 320, wherein:

[0105] The frame buffer storage unit 320 includes a first buffer zone for display buffering and a second buffer zone for standby buffering, wherein the storage space of the first buffer zone is larger than the storage space of the second buffer zone;

[0106] a frame buffer control unit 310 configured to determine whether a read-write conflict occurs based on the read request signal and the first write request signal, and when a read-write conflict occurs, change first address information determined based on the first write request signal to second address information based on the buffer allocation correspondence, and generate a second write request signal based on the second address information;

[0107] The read request signal is generated after receiving the PSR status indication, the first write request signal is generated after receiving the update frame data, and the buffer allocation correspondence is used to represent the correspondence between the address information in the frame buffer storage unit and the buffer ownership information;

[0108] The frame buffer storage unit 320 is configured to write updated frame data into a storage area indicated by the second address information in the second buffer according to the second write request signal, and to read frame data from the first buffer according to the read request signal.

[0109] It should be noted that the image output device in the embodiment of the present invention may be a GPU, a graphics card, or other devices with image data output function, which is not shown in the embodiment of the present invention.

[0110] In one or more embodiments, the frame buffer storage unit 320 may be an RFB unit.

[0111] In the frame buffer storage controller provided by an embodiment of the present invention, since the storage space of the second buffer is smaller than the storage space of the first buffer, the total storage space of the frame buffer storage unit is smaller than the storage space required for the frame data included in two image frames, thereby optimizing the frame buffer storage structure, reducing redundancy in the data storage process, improving the space resource utilization of the frame buffer storage controller, and achieving cost savings; in addition, the frame buffer control unit controls the read and write behavior logic of the frame data, adaptively avoiding the read and write conflict problem in the PSR mode, achieving efficient data update control and data display control, ensuring the normal display of the display device, and providing overall stability of the display system.

[0112] The following is a detailed description of the frame buffer memory unit 320 in the frame buffer memory controller 2203 provided in an embodiment of the present invention:

[0113] In one or more embodiments, the frame buffer storage unit 320 adopts a "One-Frame Buffer + ExtraBuffer" type buffer storage structure, that is, the storage space of the frame buffer storage unit 320 is between the storage space corresponding to the frame data included in 1 to 2 image frames.

[0114] It should be noted that, in an embodiment of the present invention, the storage space of the frame buffer storage unit 320 can be any value between greater than the storage space required for the frame data included in one image frame and less than the storage space required for the frame data included in two image frames. It can be flexibly set according to actual business needs, and the embodiment of the present invention does not impose any restrictions on this.

[0115] Optionally, the storage space of the frame buffer storage unit 320 can be the storage space required for the frame data included in 1.5 image frames, the storage space required for the frame data included in 1.2 image frames, the storage space required for the frame data included in 1 image frame + the storage space of 1 row storage specification, etc.

[0116] Figure 4 FIG. 3 shows a schematic structural diagram of a frame buffer storage unit 320 provided by an embodiment of the present invention. Figure 4 As shown, the frame buffer storage unit 320 includes multiple storage areas (Buffer Sub-unit 0 to Buffer Sub-unit k), each of which is a row storage specification area, that is, each storage area can store a group of row pixel data in the frame data, and a group of row pixel data is pixel data corresponding to a row of pixels in the image frame.

[0117] Since the frame data of an image frame is composed of multiple pixel data, the number of pixel data included in the frame data is related to the resolution of the image frame. For example, an image frame with a resolution of 1920×1080 includes 1920 rows of pixels, so the frame data of the image frame includes 1920 groups of pixel data rows.

[0118] Optionally, the storage area used to store the frame data included in a complete image frame is used as a first buffer, and the remaining storage area is used as a second buffer. The frame data stored in the first buffer is read and displayed to ensure normal display of the current image frame; the storage space in the second buffer is used as a backup cache area to store updated frame data in the event of a read-write conflict, ensuring that the updated frame data is not lost, thereby ensuring the normal update of the next image frame.

[0119] For example, assuming that the frame buffer storage unit 320 includes 10 storage areas, namely Buffer Sub-unit 0 to Buffer Sub-unit 9, if the frame data included in a frame image requires 7 storage areas, 3101 to Buffer Sub-unit 6 are used as the first buffer zone; and the remaining Buffer Sub-unit 7 to Buffer Sub-unit 9 are used as the second buffer zone.

[0120] The frame buffer storage unit provided by the embodiment of the present invention not only ensures the feasibility of storage space streamlining and optimization, but also adapts to frame buffer designs of various storage space specifications within a reasonable range.

[0121] In one or more embodiments, Figure 5 As shown, the frame buffer storage unit 320 further includes a storage management module 3201, wherein:

[0122] The storage management module 3201 is used to receive a second write request signal sent by the frame buffer control unit 310, so as to write the updated frame data into the storage area indicated by the second address information in the second buffer according to the second write request signal, or to receive a read request signal sent by the frame buffer control unit 310, so as to read the number of frames from the first buffer according to the read request signal, and send the read frame data to the subsequent display module 2204 for displaying the image frame.

[0123] After introducing the frame buffer storage unit 320, the frame buffer control unit 310 in the frame buffer storage controller 2203 provided by the embodiment of the present invention is described in detail below:

[0124] In one or more embodiments, Figure 6 A schematic diagram of the module structure of the frame buffer control unit 310 is shown. Figure 6As shown, the frame buffer control unit 310 includes a read / write behavior control subunit 3101 and a frame buffer management subunit 3102, wherein:

[0125] The read / write behavior control subunit 3101 is configured to generate a read request signal based on the first timing signal, and to generate a first write request signal based on the update frame data and the second timing signal.

[0126] The first timing signal is generated by the PSR timing controller 2202 after receiving the PSR status indication, and the second timing signal and the updated frame data are provided by the image output device 210 .

[0127] The frame buffer management subunit 3102 is used to determine whether a read-write conflict occurs based on the read request signal and the first write request signal, and when a read-write conflict occurs, change the first address information determined according to the first write request signal to second address information according to the buffer allocation correspondence, and generate a second write request signal based on the second address information.

[0128] In one or more embodiments, Figure 7 A schematic diagram of the module structure of a read-write behavior control subunit 3101 is shown, as shown in FIG. Figure 7 As shown, the read / write behavior control subunit 3101 includes a write control module 710, a read / write buffer pool 720, and a read control module 730, wherein:

[0129] The write control module 710 is configured to receive the update frame data and the second timing signal from the PSR state controller 2201 , generate a first write request signal according to the update frame data and the second timing signal, and send the first write request signal to the read-write buffer pool 720 .

[0130] The second timing signal is used to provide write timing control for writing the updated frame data into the frame buffer storage unit 320 .

[0131] The read control module 730 is configured to receive a first timing signal from the PSR timing controller 2202 , generate a read request signal according to the first timing signal, and send the read request signal to the read / write buffer pool 720 .

[0132] The first timing signal is used to provide read timing control for reading frame data from the frame buffer storage unit 320 , and the read frame data is used for image frame display.

[0133] The read / write buffer pool 720 is configured to receive a read request signal and a first write request signal, and perform buffering on the received read request signal and the first write request signal so as to synchronize a first timing signal included in the read request signal with a second timing signal included in the first write request signal.

[0134] In the above manner, by buffering the read request signal and the first write request signal, the first timing signal and the second timing signal are ensured to be in the same clock domain, thereby eliminating potential asynchronous problems and ensuring efficient read and write operations.

[0135] In one or more embodiments, Figure 8 A schematic diagram of the module structure of the frame buffer management subunit 3102 is shown, as shown in FIG. Figure 8 As shown, the frame buffer management subunit 3102 includes a read / write parsing module 810, a frame buffer monitoring module 820, a buffer mapping management module 830, and a read / write data stream reorganization module 840, wherein:

[0136] The read-write parsing module 810 is used to receive the read request signal and the first write request signal output by the read-write buffer pool 720, parse the read request signal to obtain the third address information, and parse the first write request signal to obtain the first address information; and send the first address information and the third address information to the frame buffer monitoring module 820.

[0137] Optionally, the read / write parsing module 810 may analyze the first timing signal included in the read request signal, for example, by counting rising edges of the first timing signal, to determine third address information, wherein the storage area indicated by the third address information is an area storing the frame data to be read.

[0138] Optionally, the read / write parsing module 810 may analyze the second timing signal and the update frame data included in the first write request signal, for example, by counting rising edges of the second timing signal to determine the first address information, wherein the storage area indicated by the first address information is the area to which the update frame data is to be written.

[0139] For example, assuming that the storage areas Buffer Sub-unit 0 to Buffer Sub-unit 6 respectively store the 0th group of row pixel data to the 6th group of row pixel data in the frame data, and the read request signal wants to request to read the 2nd row of pixel data in the image frame, and the first write request signal wants to use the updated frame data to overwrite the 5th row of pixel data in the image frame, then the storage area indicated by the third address information is Buffer Sub-unit 1, and the storage area indicated by the first address information is Buffer Sub-unit 4.

[0140] It should be noted that the read-write parsing module 810 in the embodiment of the present invention can also obtain other information indicating the area to be read and other information indicating the area to be written after parsing the read request signal and the first write request signal. The embodiment of the present invention does not impose any restrictions on this.

[0141] In one embodiment, the read / write parsing module 810 parses the read request signal to obtain read pointer information, and parses the first write request signal to obtain write pointer information; and sends the read pointer information and the write pointer information to the frame buffer monitoring module 820 .

[0142] The frame buffer monitoring module 820 is configured to determine whether a read-write conflict occurs based on the first address information and the third address information.

[0143] In one or more embodiments, whether a read-write conflict occurs may be determined by:

[0144] If the row position corresponding to the first data in the image frame is greater than or equal to the row position corresponding to the second data in the image frame, a read-write conflict occurs, wherein the first data is data stored in the storage area indicated by the first address information, and the second data is data stored in the storage area indicated by the third address information;

[0145] If the row position corresponding to the first data in the image frame is smaller than the row position corresponding to the second data in the image frame, no read-write conflict occurs.

[0146] In a specific implementation, the first data stored in the storage area indicated by the first address information is determined to correspond to row position i in the image frame. Row position i is used to indicate that the i-th row of data in the image frame needs to be updated using the update frame data. The second data stored in the storage area indicated by the third address information is determined to correspond to row position j in the image frame. Row position j is used to indicate that the j-th row of data in the image frame needs to be read for displaying the image frame.

[0147] Based on the size relationship between row position i and row position j, it is determined whether a read-write conflict occurs. If i ≥ j, it means that in the current image frame, the position to be written is located after the position to be read, or the position to be written overlaps with the position to be read. If the updated frame data is directly written to the storage area indicated by the first address information, then in the frame data read during the current frame display cycle, part of the frame data belongs to the current image frame, and part of the frame data belongs to the updated image frame, resulting in discontinuity or tearing of the image frame displayed by the display module 2204. That is, when i ≥ j, a read-write conflict occurs.

[0148] If i < j, it means that in the current image frame, the location to be written is located before the location to be read. Since the frame data at the location to be written has already been read during the current frame display period, the updated frame data is directly written to the storage area indicated by the first address information, overwriting the data stored in the storage area indicated by the first address information. This does not affect the display of the current image frame. That is, when i < j, no read-write conflict occurs.

[0149] In one or more embodiments, whether a read-write conflict occurs may also be determined in the following manner:

[0150] calculating an absolute difference between the first address information and the third address information;

[0151] If the absolute difference is within the preset safety threshold, no read-write conflict occurs;

[0152] If the absolute difference is outside the preset safety threshold, a read-write conflict occurs.

[0153] It should be noted that the security threshold range in the embodiment of the present invention is an empirical threshold range, which can be flexibly set according to actual business needs, and the embodiment of the present invention does not impose any restrictions on this.

[0154] The above-mentioned frame buffer storage controller determines whether a read-write conflict occurs by determining the relationship between the row position in the image frame corresponding to the data to be read by the read request signal and the row position in the image frame corresponding to the data stored in the address to be written by the first write request signal, thereby improving the accuracy of the judgment result, ensuring that the frame buffer control unit can adaptively avoid the read-write conflict problem in the PSR mode, realizing efficient data update control and data display control, and ensuring the normal display of the display device.

[0155] The buffer mapping management module 830 is configured to, if a read / write conflict occurs, change the first address information determined based on the first write request signal to second address information based on the buffer allocation correspondence; generate a second write request signal based on the second address information; and transmit the second write request signal and the read request signal to the read / write data stream reorganization module 840;

[0156] If no read-write conflict occurs, the first write request signal and the read request signal sent by the read-write parsing module 810 are directly transmitted to the read-write data stream reorganization module 840 .

[0157] In a specific implementation, when the frame buffer monitoring module 820 does not detect a read / write conflict, the control buffer mapping management module 830 directly sends the first write request signal and the read request signal received from the read / write parsing module 810 to the read / write data stream reorganization module 840. In other words, the normal read / write operation process is performed on the frame data, and the read / write behavior of the frame data is not interfered with.

[0158] When the frame buffer monitoring module 820 detects a read-write conflict, the control buffer mapping management module 830 starts the read-write arbitration management mechanism to ensure the continuity of frame data reading, that is, to ensure that the current image frame is displayed normally, and at the same time ensure that the updated frame data is not lost, that is, to ensure that the next image frame is refreshed normally.

[0159] In one or more embodiments, the buffer mapping management module 830 generates a buffer allocation correspondence based on the specific storage space structure of the frame buffer storage unit 320 . The buffer allocation correspondence is used to represent the correspondence between address information in the frame buffer storage unit and buffer ownership information.

[0160] For example, assuming that the frame buffer storage unit 320 includes multiple storage areas (Buffer Sub-unit 0 to Buffer Sub-unit k), and the address information corresponding to Buffer Sub-unit 0 is set to 0x00 to 0x05, the address information corresponding to Buffer Sub-unit 1 is set to 0x06 to 0x0a, the address information corresponding to Buffer Sub-unit 2 is set to 0x0b to 0x0f, and so on. The buffer allocation correspondence can be shown in Table 1:

[0161] Address information Storage Area Buffer ownership information 0x00~0x05 BufferSub-unit0 First buffer zone 0x06~0x0a BufferSub-unit1 First buffer zone 0x0b~0x0f BufferSub-unit2 First buffer zone 0x10~0x15 BufferSub-unit3 First buffer zone 0x16~0x1a BufferSub-unit4 Second buffer zone 0x1b~0x1f BufferSub-unit5 Second buffer zone …… …… ……

[0162] Table 1

[0163] Optionally, as shown in Table 1, the buffer allocation correspondence may also be used to represent the correspondence between the storage area in the frame buffer storage unit and the buffer zone ownership information, and the embodiment of the present invention does not impose any limitation on this.

[0164] In one or more embodiments, based on the buffer allocation correspondence shown in Table 1, the read-write arbitration management mechanism of the buffer mapping management module 830 may specifically be:

[0165] When the frame buffer monitoring module 820 monitors a read-write conflict, it can inform the buffer mapping management module 830 in the form of conflict indication information; the buffer mapping management module 830 changes the first address information to the second address information according to the buffer allocation correspondence, and generates a second write request signal based on the second address information, and sends the generated second write request signal to the subsequent read-write data stream reorganization module 840 to complete the write operation of the updated frame input.

[0166] The first address information belongs to the first buffer zone, and the second address information belongs to the second buffer zone.

[0167] For example, assuming that the first address information is 0x0b, the first address information 0x0b is changed to the second address information 0x16 according to the buffer allocation correspondence shown in Table 1, so that when a read-write conflict occurs, the updated frame data is written to the second buffer as a backup cache, thereby achieving the purpose of not affecting the display of the current image frame.

[0168] In one or more embodiments, after reading the frame data from the first buffer is completed, the buffer mapping management module 830 is further configured to:

[0169] The buffer zone affiliation information corresponding to the first address information is changed to the second buffer zone, and the buffer zone affiliation information corresponding to the second address information is changed to the first buffer zone, so as to update the buffer allocation correspondence.

[0170] Based on the above example, assuming that the first address information is 0x0b and the second address information is 0x16. After completing the reading of the frame data included in the current image frame, the buffer ownership information corresponding to the first address information 0x0b is changed from the first buffer to the second buffer, and the buffer ownership information corresponding to the second address information 0x16 is changed from the second buffer to the first buffer, thereby updating the buffer allocation correspondence. The updated buffer allocation correspondence can be shown in Table 2:

[0171] Address information Storage Area Buffer ownership information 0x00~0x05 BufferSub-unit0 First buffer zone 0x06~0x0a BufferSub-unit1 First buffer zone 0x0b~0x0f BufferSub-unit2 Second buffer zone 0x10~0x15 BufferSub-unit3 First buffer zone 0x16~0x1a BufferSub-unit4 First buffer zone 0x1b~0x1f BufferSub-unit5 Second buffer zone …… …… ……

[0172] Table 2

[0173] In one or more embodiments, after completing the buffer ownership update of the address information, the buffer mapping management module 830 is further configured to:

[0174] determining fourth address information corresponding to a storage area for storing third data, wherein a row position corresponding to the third data in the image frame is adjacent to a row position corresponding to the fourth data in the image frame, and the fourth data is data stored in the storage area indicated by the second address information;

[0175] A read sequence connection is established for the fourth address information and the second address information based on a row position in the image frame corresponding to the third data and a row position in the image frame corresponding to the fourth data.

[0176] In a specific implementation, first, based on the second address information, the row position m in the updated image frame corresponding to the fourth data stored in the storage area indicated by the second address information is determined. The row position m is used to indicate that the m-th row of data in the image frame has been updated, resulting in an updated image frame. Then, the row position adjacent to row position m, i.e., row position m+1, is determined, and the fourth address information corresponding to the storage area containing the third data included in row position m+1 is determined. Finally, a read sequence connection of "fourth address information → second address information" is established so that within the frame display period, the storage management module 3201 reads the data in the storage area indicated by the fourth address information according to the read request signal, and then reads the data in the storage area indicated by the second address information, thereby allowing the updated image frame to be displayed normally and smoothly.

[0177] Through the buffer mapping management module 830, after the frame data corresponding to the current image frame is read, the buffer allocation correspondence is updated, and a new read sequence connection is established for the updated address information, so that in the next display cycle, the frame data stored in the storage area belonging to the first buffer zone is read according to the new read sequence connection, thereby allowing the display device to display the updated image frame.

[0178] The read / write data stream reorganization module 840 is configured to alternately output the read request signal and the second write request signal in a time-division multiplexing manner, or alternately output the read request signal and the first write request signal in a time-division multiplexing manner.

[0179] In a specific implementation, when no read / write conflict occurs, the read / write data stream reorganization module 840 alternately outputs the read request signal and the first write request signal in a time-division multiplexing manner, so that the storage management module 3201 alternately performs read and write operations on the storage area according to the received read request signal and the first write request signal.

[0180] When a read-write conflict occurs, the read-write data stream reorganization module 840 will alternately output the read request signal and the second write request signal in a time-division multiplexing manner, so that the storage management module 3201 can perform read and write operations on the storage area alternately according to the received read request signal and the second write request signal.

[0181] The above-mentioned frame buffer memory controller, when the frame buffer memory unit is a single-port communication memory unit, alternately outputs the read request signal and the second write request signal, or alternately outputs the read request signal and the first write request signal in a time-division multiplexing manner, so that the frame buffer memory unit can achieve an effect equivalent to parallel reading and writing, thereby improving data access efficiency.

[0182] Figure 9 The structure diagram of the display device 220 including the frame buffer memory controller 2203 is shown. Figure 9 The display device 220 shown in FIG. 2 is used to specifically introduce the overall working process of the display device 220 :

[0183] When the image output device 210 detects that the screen display content is not being updated or is currently in a static screen display state, it controls the display device 220 to enter the PSR mode by sending a PSR state indication. In the PSR mode, the image output device 210 sends the updated frame data and the second timing signal to the write control module 710 via the PSR state controller 2201, and the PSR timing controller 2202 sends the first timing signal to the read control module 730.

[0184] The write control module 710 generates a first write request signal based on the update frame data and the second timing signal, and sends the first write request signal to the read-write buffer pool 720. The read control module 730 generates a read request signal based on the first timing signal, and sends the read request signal to the read-write buffer pool 720. The read-write buffer pool 720 buffers the read request signal and the first write request signal and outputs the buffer signal to the read-write parsing module 810.

[0185] The read / write parsing module 810 parses the read request signal to obtain the third address information, and parses the first write request signal to obtain the first address information; sends the first address information and the third address information to the frame buffer monitoring module 820, and sends the read request signal and the first write request signal to the buffer mapping management module 830; the frame buffer monitoring module 820 monitors the first address information and the third address information to determine whether a read / write conflict occurs, specifically including the following two situations:

[0186] Scenario 1:

[0187] When a read / write conflict occurs, the buffer mapping management module 830 changes the first address information determined according to the first write request signal to the second address information according to the buffer allocation correspondence; generates a second write request signal based on the second address information, and transmits the second write request signal and the read request signal to the read / write data stream reorganization module 840; the read / write data stream reorganization module 840 alternately outputs the read request signal and the second write request signal to the storage management module 3201 in a time-division multiplexing manner;

[0188] The storage management module 3201 writes the updated frame data into the storage area indicated by the second address information in the second buffer according to the received second write request signal, and reads the frame number from the first buffer according to the received read request signal, and sends the read frame data to the subsequent display module 2204 for displaying the image frame.

[0189] Scenario 2:

[0190] When no read-write conflict occurs, the buffer mapping management module 830 directly transmits the first write request signal and the read request signal to the read-write data stream reorganization module 840; the read-write data stream reorganization module 840 alternately outputs the read request signal and the first write request signal to the storage management module 3201 in a time-division multiplexing manner;

[0191] The storage management module 3201 writes the updated frame data into the storage area indicated by the first address information in the first buffer according to the received first write request signal, and reads the frame number from the first buffer according to the received read request signal, and sends the read frame data to the subsequent display module 2204 for displaying the image frame.

[0192] By designing the storage structure of the frame buffer storage unit 320 as a "One-Frame Buffer + ExtraBuffer" structure, the frame buffer memory controller 2203 can implement the storage function of the conventional "Double-Frame Buffer" RFB unit with less storage space, thereby optimizing the storage resource structure, improving the effective utilization of storage resources, and achieving the goals of reducing power consumption and costs.

[0193] In addition, the frame buffer control unit 310 can solve the potential read-write conflict problem in the PSR state. That is, when a read-write conflict is detected, the buffer mapping management module 830 is used to efficiently control the read-write behavior and adaptively avoid the occurrence of read-write conflicts, thereby reducing the probability of display screen tearing problems. While ensuring the normal display of the current image frame, it also ensures the normal update of the next image frame, thereby ensuring the overall stability and reliability of the display system.

[0194] Furthermore, the frame buffer memory controller 2203 is composed of a frame buffer control unit 310 and a frame buffer memory unit 320 , and has a clear structure and layout, clear unit functions, and is easy to integrate and maintain.

[0195] like Figure 10 As shown, based on Figure 9 The complete workflow of the display device 220 shown may include the following steps:

[0196] Step S1001 , the image output device 210 sends a PSR status indication, updated frame data, and a second timing signal to the PSR status controller 2201 ;

[0197] Step S1002, the PSR state controller 2201 sends the updated frame data and the second timing signal to the write control module 710, and generates a PSR state control signal to the PSR timing controller 2202 according to the PSR state indication;

[0198] Step S1003 , the PSR timing controller 2202 sends a first timing signal to the read control module 730 ;

[0199] Step S1004 , the write control module 710 generates a first write request signal according to the update frame data and the second timing signal, and sends the first write request signal to the read-write buffer pool 720 ;

[0200] Step S1005 , the read control module 730 generates a read request signal according to the first timing signal, and sends the read request signal to the read / write buffer pool 720 ;

[0201] Step S1006: the read / write buffer pool 720 buffers the read request signal and the first write request signal and outputs the buffered signals to the read / write parsing module 810;

[0202] Step S1007: The read / write parsing module 810 parses the read request signal to obtain third address information, and parses the first write request signal to obtain first address information; sends the first address information and the third address information to the frame buffer monitoring module 820, and sends the read request signal and the first write request signal to the buffer mapping management module 830;

[0203] Step S1008: The frame buffer monitoring module 820 monitors the first address information and the third address information to determine whether a read / write conflict occurs. If so, step S1009 is executed; otherwise, step S1013 is executed.

[0204] Step S1009: the buffer mapping management module 830 changes the first address information determined according to the first write request signal to second address information according to the buffer allocation correspondence;

[0205] Step S1010: The buffer mapping management module 830 generates a second write request signal based on the second address information, and transmits the second write request signal and the read request signal to the read / write data stream reorganization module 840;

[0206] Step S1011: the read / write data stream reorganization module 840 alternately outputs a read request signal and a second write request signal to the storage management module 3201 in a time-division multiplexing manner;

[0207] In step S1012, the storage management module 3201 writes the updated frame data into the storage area indicated by the second address information in the second buffer in response to the received second write request signal, and reads the frame data from the first buffer in response to the received read request signal, and sends the read frame data to the display module 2204.

[0208] Step S1013: The buffer mapping management module 830 directly transmits the first write request signal and the read request signal to the read / write data stream reorganization module 840;

[0209] Step S1014: the read / write data stream reorganization module 840 alternately outputs the read request signal and the first write request signal to the storage management module 3201 in a time-division multiplexing manner;

[0210] In step S1015, the storage management module 3201 writes the updated frame data into the storage area indicated by the first address information in the first buffer according to the received first write request signal, and reads the frame data from the first buffer according to the received read request signal, and sends the read frame data to the display module 2204.

[0211] In step S1016 , the display module 2204 displays the image frame according to the read frame data.

[0212] Based on the same concept, an embodiment of the present invention further provides a frame buffer storage control method, which is applied to the frame buffer storage controller provided in any of the above embodiments. Since this method is the method executed by the frame buffer storage controller in the embodiment of the present invention, and the principle of solving the problem by this method is similar to that of the frame buffer storage controller, the implementation of this method can refer to the implementation of the frame buffer storage controller, and the repeated parts will not be repeated.

[0213] like Figure 11 As shown, the method includes the following steps:

[0214] Step S1101, determining whether a read-write conflict occurs based on a read request signal and a first write request signal;

[0215] Wherein, the read request signal is generated after receiving the PSR status indication, and the first write request signal is generated after receiving the update frame data;

[0216] Step S1102 , when a read-write conflict occurs, changing the first address information determined according to the first write request signal to second address information according to the buffer allocation correspondence, and generating a second write request signal based on the second address information;

[0217] The buffer allocation correspondence is used to represent the correspondence between the address information in the frame buffer storage unit and the buffer zone ownership information;

[0218] Step S1103, writing the updated frame data into the storage area indicated by the second address information in the second buffer according to the second write request signal, and reading the frame data from the first buffer according to the read request signal;

[0219] The first buffer is used for display buffering, and the second buffer is used for standby buffering. The storage space of the first buffer is larger than that of the second buffer.

[0220] In an optional embodiment, determining whether a read-write conflict occurs based on the read request signal and the first write request signal includes:

[0221] generating a read request signal based on a first timing signal, and generating a first write request signal based on the updated frame data and a second timing signal, wherein the first timing signal is generated after receiving a PSR status indication, and the second timing signal and the updated frame data are provided by the image output device;

[0222] parsing the read request signal to obtain third address information, and parsing the first write request signal to obtain first address information;

[0223] Whether a read-write conflict occurs is determined according to the first address information and the third address information.

[0224] In an optional embodiment, determining whether a read-write conflict occurs according to the first address information and the third address information includes:

[0225] If the row position corresponding to the first data in the image frame is greater than or equal to the row position corresponding to the second data in the image frame, a read-write conflict occurs, wherein the first data is data stored in the storage area indicated by the first address information, and the second data is data stored in the storage area indicated by the third address information;

[0226] If the row position corresponding to the first data in the image frame is smaller than the row position corresponding to the second data in the image frame, no read-write conflict occurs.

[0227] In an optional embodiment, after determining whether a read-write conflict occurs, the method further includes:

[0228] When no read-write conflict occurs, outputting a first write request signal;

[0229] According to the first write request signal, the updated frame data is written into the storage area indicated by the first address information in the first buffer.

[0230] In an optional embodiment, after reading the frame data from the first buffer is completed, the method further includes:

[0231] The buffer zone affiliation information corresponding to the first address information is changed to the second buffer zone, and the buffer zone affiliation information corresponding to the second address information is changed to the first buffer zone, so as to update the buffer allocation correspondence.

[0232] In an optional embodiment, after updating the buffer allocation correspondence, the method further includes:

[0233] determining fourth address information corresponding to a storage area for storing third data, wherein a row position corresponding to the third data in the image frame is adjacent to a row position corresponding to the fourth data in the image frame, and the fourth data is data stored in the storage area indicated by the second address information;

[0234] A read sequence connection is established for the fourth address information and the second address information based on a row position in the image frame corresponding to the third data and a row position in the image frame corresponding to the fourth data.

[0235] In an optional embodiment, after generating the second write request signal, the method further includes:

[0236] The read request signal and the second write request signal are output alternately in a time-division multiplexing manner.

[0237] In an optional embodiment, after generating the read request signal and the first write request signal, the method further includes:

[0238] The read request signal and the first write request signal are buffered so that a first timing signal included in the read request signal is synchronized with a second timing signal included in the first write request signal.

[0239] Based on the same concept, Figure 12 As shown, an embodiment of the present invention further provides a display device 1200, including a display module 2204 and a frame buffer memory controller 2203 provided in any of the above embodiments, wherein:

[0240] The frame buffer memory controller 2203 is configured to perform the following operations:

[0241] Determining whether a read-write conflict occurs based on a read request signal and a first write request signal, wherein the read request signal is generated after receiving a PSR status indication, and the first write request signal is generated after receiving update frame data;

[0242] When a read-write conflict occurs, the first address information determined according to the first write request signal is changed to second address information according to the buffer allocation correspondence, and a second write request signal is generated based on the second address information;

[0243] writing the updated frame data into the storage area indicated by the second address information in the second buffer according to the second write request signal, and reading the frame data from the first buffer according to the read request signal;

[0244] The first buffer is used for display buffering, the second buffer is used for backup buffering, the storage space of the first buffer is larger than the storage space of the second buffer, and the buffer allocation correspondence is used to represent the correspondence between the address information in the frame buffer storage unit and the buffer ownership information;

[0245] The display module 2204 is used to display image frames according to the read frame data.

[0246] The principle of solving the problem by the display device is similar to that of the aforementioned frame buffer memory controller. Therefore, the implementation of the display device can refer to the implementation of the aforementioned frame buffer memory controller, and the repeated parts will be omitted.

[0247] In specific implementation, in the embodiments of the present invention, the display device may be a television, a personal computer, etc. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limiting the present invention.

[0248] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A frame buffer memory controller, characterized in that: The system comprises a frame buffer control unit and a frame buffer storage unit, wherein the frame buffer storage unit comprises a first buffer zone for display buffering and a second buffer zone for standby buffering, wherein the storage space of the first buffer zone is larger than the storage space of the second buffer zone, wherein: the frame buffer control unit being configured to determine whether a read-write conflict occurs based on the read request signal and the first write request signal, and when a read-write conflict occurs, change first address information determined based on the first write request signal to second address information based on the buffer allocation correspondence, and generate a second write request signal based on the second address information; the frame buffer storage unit being configured to write updated frame data into a storage area indicated by the second address information in the second buffer according to the second write request signal, and to read frame data from the first buffer according to the read request signal; Among them, the read request signal is generated after receiving the panel self-refresh PSR status indication, the first write request signal is generated after receiving the update frame data, and the buffer allocation correspondence is used to characterize the correspondence between the address information in the frame buffer storage unit and the buffer ownership information.

2. The frame buffer memory controller according to claim 1, wherein: The frame buffer control unit is specifically used for: generating the read request signal based on a first timing signal, and generating the first write request signal based on the update frame data and a second timing signal, wherein the first timing signal is generated after receiving the PSR status indication, and the second timing signal and the update frame data are provided by an image output device; parsing the read request signal to obtain third address information, and parsing the first write request signal to obtain the first address information; It is determined whether a read-write conflict occurs according to the first address information and the third address information.

3. The frame buffer memory controller according to claim 2, wherein: The frame buffer control unit is specifically used for: If a row position corresponding to the first data in the image frame is greater than or equal to a row position corresponding to the second data in the image frame, a read-write conflict occurs, wherein the first data is data stored in the storage area indicated by the first address information, and the second data is data stored in the storage area indicated by the third address information; If the row position corresponding to the first data in the image frame is smaller than the row position corresponding to the second data in the image frame, no read-write conflict occurs.

4. The frame buffer memory controller according to claim 3, wherein: The frame buffer control unit is further configured to: When no read-write conflict occurs, outputting the first write request signal; The frame buffer storage unit is further used for: The updated frame data is written into a storage area indicated by the first address information in the first buffer according to the first write request signal.

5. The frame buffer memory controller according to claim 1, wherein: The frame buffer control unit is further configured to: After reading frame data from the first buffer, the buffer affiliation information corresponding to the first address information is changed to the second buffer, and the buffer affiliation information corresponding to the second address information is changed to the first buffer, so as to update the buffer allocation correspondence.

6. The frame buffer memory controller according to claim 5, wherein: The frame buffer control unit is further configured to: determining fourth address information corresponding to a storage area for storing third data, wherein a row position corresponding to the third data in the image frame is adjacent to a row position corresponding to fourth data in the image frame, and the fourth data is data stored in the storage area indicated by the second address information; A read sequence connection is established for the fourth address information and the second address information according to a row position in the image frame corresponding to the third data and a row position in the image frame corresponding to the fourth data.

7. The frame buffer memory controller according to claim 1, wherein: The frame buffer control unit is further configured to: The read request signal and the second write request signal are output alternately in a time-division multiplexing manner.

8. The frame buffer memory controller according to any one of claims 1 to 7, wherein: The frame buffer control unit is further configured to: The read request signal and the first write request signal are buffered so that the first timing signal included in the read request signal is synchronized with the second timing signal included in the first write request signal.

9. A frame buffer storage control method, characterized in that: Applied to the frame buffer memory controller according to any one of claims 1 to 8, the method comprises: Determining whether a read-write conflict occurs based on a read request signal and a first write request signal, wherein the read request signal is generated after receiving a panel self-refresh PSR status indication, and the first write request signal is generated after receiving update frame data; When a read-write conflict occurs, changing the first address information determined according to the first write request signal to second address information according to the buffer allocation correspondence, and generating a second write request signal based on the second address information; writing the updated frame data into a storage area indicated by the second address information in the second buffer according to the second write request signal, and reading the frame data from the first buffer according to the read request signal; The first buffer is used for display cache, the second buffer is used for backup cache, the storage space of the first buffer is larger than the storage space of the second buffer, and the buffer allocation correspondence is used to characterize the correspondence between the address information in the frame buffer storage unit and the buffer ownership information.

10. A display device, characterized in that: The device comprises a display module and a frame buffer memory controller according to any one of claims 1 to 8, wherein: The display module is used to display image frames according to the read frame data.

Images