High-energy-efficiency digital storage and calculation integrated RS (Reed-Solomon) coding and decoding accelerator supporting variable code length

Abstract

The invention discloses a high-energy-efficiency digital storage and calculation integrated RS (Reed-Solomon) coding and decoding accelerator supporting variable code length, which relates to the technical field of storage and calculation integrated accelerators and comprises a main controller, an RS coding and decoding module, a global buffer region, a buffer region 1 and a buffer region 2, the main controller is used for adjusting the RS coding and decoding module to a coding or decoding mode; the global buffer area is used for storing tape information to be coded and decoded; the RS encoding and decoding module is used for encoding or decoding tape information to be encoded and decoded; the cache region 1 is used for caching tape information; the cache region 2 is used for caching coding or decoding results; according to the RS coding and decoding accelerator, the Galois field operation is deeply embedded into the storage unit, and the bit width self-adaptive data flow path is constructed, so that breakthrough in two aspects of calculation energy efficiency and multi-calculation format compatibility is realized, and an error correction solution with ultrahigh energy efficiency and cross-generation compatibility is provided for PB-level tape storage.

Description

Technical Field

[0001] The present invention relates to the technical field of storage-computing integrated accelerators, and in particular to a high-energy-efficiency digital storage-computing integrated RS codec accelerator supporting variable code length. Background Art

[0002] (1) Digital storage and computing integration; In 1965, Gordon Moore summarized the principle of transistor development—"Moore's Law," which has become a key metric for measuring technological progress, product iteration, and business development in the integrated circuit field. Its core principle states that, assuming the price remains constant, the number of transistors that can be accommodated on an integrated circuit will double every 18 to 24 months, and performance will also double. For sixty years, this law has continuously driven technological progress in the industry. However, as semiconductor processing approaches its physical limits, the pace of Moore's Law has significantly slowed, and the development of integrated circuits has entered the post-Moore era. The industry urgently needs major changes to achieve breakthroughs in computing power, hence the emergence of integrated storage and computing technology.

[0003] Storage and computing integration is essentially an innovation at the architectural level, which is different from the classic von Neumann architecture (hereinafter referred to as the von Neumann architecture). Figure 7 In the traditional Feng architecture, the storage unit and the computing unit are separated, and the data between the two is transmitted by the bus. This architecture of separation of "storage" and "computing" makes practitioners focus on improving the computing speed when designing the processor and on improving the capacity when designing the memory. Now in the post-Moore era, there is a performance mismatch between "storage" and "computing", such as Figure 8 As mentioned above, this leads to problems such as "storage wall", "power consumption wall" and "bandwidth wall". Figure 8 From Gholami, Z. Yao, S. Kim, C. Hooper, MW Mahoney and K. Keutzer, "AI and Memory Wall," in IEEE Micro, vol. 44, no. 3, pp. 33-39, May-June 2024, doi: 10.1109 / MM.2024.3373763.

[0004] The integrated storage and computing architecture can solve the above-mentioned "three-wall problem". Its core is to fully integrate storage and computing, overcome the bottleneck of the Phong architecture, and combine advanced packaging, new storage devices and other technologies in the post-Moore era to achieve an order of magnitude increase in computing power and energy efficiency. Based on the distinction between volatility and non-volatility, SRAM, DRAM, RRAM, MRAM and other storage units can be used as storage media. Therefore, the integration of storage and computing is essentially to use the physical properties of different storage media to redesign the storage circuit so that it has both storage and computing capabilities. Since the academic community mainly focuses on the narrow sense of storage and computing integration, the industry also divides the broad sense of storage and computing integration into near-memory computing, in-memory processing, in-memory computing, etc. To avoid ambiguity, the storage and computing integration mentioned in this article refers to the narrow sense of storage and computing integration, that is, in-memory computing.

[0005] At the categorization level, integrated memory and computing chips can be divided into two main categories: analog memory and computing and digital memory and computing. Analog memory and computing are primarily based on the laws of physics (such as Ohm's law and Kirchhoff's laws), performing multiplication and accumulation operations on a memory and computing array. Their storage media typically uses non-volatile memory devices (such as RRAM, MRAM, and PCM). The main advantages of analog memory and computing are low power consumption, small area, and low cost.

[0006] Digital computing primarily integrates logic and computational circuits within a storage array, giving it both storage and computational capabilities. Its storage media typically uses volatile memory devices (SRAM, DRAM, etc.). The main advantages of digital computing lie in high computational accuracy, high energy efficiency, and high reliability. Because digital computing typically uses SRAM as its storage medium, it combines the advantages of advanced technology and performance with greater compatibility.

[0007] (2) Bit-width reconfigurable architecture; In order to simultaneously meet the performance, energy efficiency, and flexibility requirements of variable code length encoding and decoding accelerators, researchers have proposed various reconfigurable AI chips in the past few years. These chips are based on FPGA or CGRA (reconfigurable computing) platforms, have domain-specific reconfigurability, and can customize computing units and data paths for different neural network training and inference tasks without the need to re-produce chips.

[0008] For integrated storage and computing chips, implementing a reconfigurable design can better adapt to different neural network models (DNN, CNN, BNN, etc.), enabling a "one-chip, multiple-use" multi-model design. For example, ISSCC 2022:15.1 successfully deployed neural network models such as CNN, RNN, and MLP on a reconfigurable chip. Building on this, we designed a reconfigurable digital storage and computing chip, rather than an analog one, to achieve both improved accuracy and energy efficiency while maintaining flexibility, achieving a balanced all-in-one solution.

[0009] The reconfigurable digital storage and computing integrated chip was first proposed by Hyunjoon Kim of Nanyang Technological University in 2019. The digital storage and computing core designed with reconfigurable data bit width and unit function can perform multiplication and accumulation operations on 1 to 16-bit data. The implementation of reconfigurable storage and computing technology usually has three technical routes: reconfigurable computing unit precision, reconfigurable computing logic, and reconfigurable data flow.

[0010] In the technological evolution of reconfigurable bit-width architectures, the academic community continues to push the boundaries of computational efficiency through paths such as precision reconfiguration, logic reconfiguration, and data flow reconfiguration. The precision adaptation mechanism proposed by H. Kim's team provides theoretical support for dynamic symbol bit-width switching, while the scalable computational logic design of B. Yan's team verifies the feasibility of multi-mode encoding and decoding hardware. The dynamic data flow path configuration scheme pioneered by Naveen Verma's team demonstrates unique advantages in addressing the data flow characteristics of polynomial calculation and check bit generation in RS encoding scenarios, significantly improving array utilization by eliminating redundant data transfer.

[0011] (3) RS coding; Since its introduction in the 1960s, Reed-Solomon (RS) coding has become the cornerstone of data reliability in tape storage systems due to its efficient correction capabilities for sudden errors and hardware-friendly features. Its mathematical core lies in the construction of Galois Field (GF) polynomials - by mapping the original data symbols into polynomial coefficients, redundant check symbols are generated, and the arithmetic properties of finite fields are used to achieve error location and repair. In modern tape formats (such as LTO-9), RS coding uses a two-dimensional interleaved structure (RS(240,224) + RS(64,58)), which enables a single 45TB tape to achieve 10 -19 The unrecoverable bit error rate is orders of magnitude lower, making it a perfect match for scenarios where local data corruption occurs due to magnetic powder shedding and mechanical wear on tape media.

[0012] As storage density moves toward the petabyte level, RS coding faces three disruptive challenges: First, the inhomogeneity of nanoscale magnetic particles causes the error pattern to shift from local burst errors to wide-area random distribution, making it difficult for traditional fixed-parameter RS ​​codes to dynamically adapt to complex error characteristics; second, multiple generations of tape formats have put forward conflicting requirements for symbol bit width. The DDS-320 format relies on 4-bit low-precision head signal processing, while HAMR technology requires 16-bit high-precision check support, forcing the hardware to compromise between accuracy and energy efficiency; finally, the inherent defects of the von Neumann architecture cause matrix operations in the encoding and decoding process to fall into the "storage wall" dilemma. The data transportation energy consumption in key links such as syndrome calculation and key equation solution accounts for as much as 78%, seriously restricting energy efficiency improvement.

[0013] To address these challenges, the industry has tried ASIC fixed acceleration and FPGA dynamic reconfiguration solutions. However, the former cannot adapt to bit width switching requirements due to its rigid architecture, while the latter cannot meet real-time requirements due to reconfiguration delays (>15 minutes) and uncontrolled power consumption (>28W).

[0014] There are four solutions in the prior art: (1) General processor solution; Software implementations based on general-purpose CPUs (such as the x86 / ARM architecture) are the foundation of RS encoding. Typical examples include the open-source library libfec and early IBM tape drives (such as the TS1140). This approach uses software algorithms to implement Galois field operations and supports dynamic adjustment of code length and sign width. While its flexibility is significant for low-density tapes (such as the DDS-4 format), it struggles to meet real-time requirements for RS (240,224) encoding on modern tapes like LTO-9 due to the serial computing nature of the processor.

[0015] (2) Fixed-function ASIC solution; The IBM TS1160 tape controller is a representative example, which uses a customized ASIC to implement RS encoding hardware acceleration. Its core design is based on a parallel multiplier array (128 GF(2 8 ) unit), optimizing the data path for fixed code lengths (such as RS(255,223)) to achieve 0.3 TOPS / W energy efficiency in LTO-9. This approach offers excellent performance for a single format, but cannot adapt to the varying symbol widths required across multiple tape generations.

[0016] (3) FPGA programmable solution; Referring to patents such as CN117240306A and CN118611677B, the use of FPGA programmable solutions to implement Huffman coding and TDC coding has become a common practice in the field of coding and decoding. RS coding and decoding can utilize the characteristics of the Van der Waals matrix or the Cauchy matrix to implement error correction codes, that is, mapping them into matrix operations. Utilizing FPGA programmability for RS coding and decoding is also very mature, and there is a lot of open source code available online: (4) Storage and computing integrated solution; Referring to patents CN118740186A, CN116566400A, etc., the use of integrated storage and computing arrays for LDPC coding calculations has become a common method. LDPC encoding and decoding and RS encoding and decoding are both error-correcting codes, and a large number of matrix operations are involved in the encoding and decoding processes. Using integrated storage and computing technology to accelerate matrix operations has become a common operation in the encoding and decoding field.

[0017] The existing technology has the following shortcomings: (1) Poor computing energy efficiency: The RS codec general-purpose processor using the traditional Feng architecture and the FPGA-based programmable accelerator solution have limited computing energy efficiency. The power consumption overhead caused by large amounts of data transfer restricts the development of this type of codec processor.

[0018] (2) Poor compatibility (versatility): The RS codec accelerator implemented using an ASIC solution has the characteristics of high computing energy efficiency, but it generally only supports fixed bit width calculations and cannot adapt to codec calculations under different tape formats and multiple bit widths. Summary of the Invention

[0019] Based on the technical problems existing in the background technology, the present invention proposes a high-efficiency digital storage and computing integrated RS codec accelerator that supports variable code length, achieving breakthroughs in computing energy efficiency and compatibility with multiple computing formats, and providing PB-level tape storage with an error correction solution that has both ultra-high energy efficiency and cross-generation compatibility.

[0020] The present invention proposes a high-efficiency digital storage and computing integrated RS codec accelerator supporting variable code length, comprising a main controller, an RS codec module, a global buffer, a cache area 1 and a cache area 2; The main controller is used to adjust the RS codec module to the encoding or decoding mode; The global buffer is used to store tape information to be encoded and decoded; The RS encoding and decoding module is used to encode or decode the tape information to be encoded or decoded; Cache area 1 is used to cache tape information; Buffer 2 is used to cache encoding or decoding results.

[0021] Furthermore, the RS encoding and decoding module includes a bus, four reconfigurable sub-units and a slave controller; The RS codec module is connected to the main controller via a bus; The slave controller is used to switch the encoding or decoding mode inside the RS codec module; The reconfigurable subunit is used to encode or decode the tape information.

[0022] Furthermore, the reconfigurable subunit includes four digital storage and computing cores and a reconfigurable cross network; The reconfigurable cross network separates the four digital storage and computing cores, and each digital storage and computing core is designed to support only 4-bit computing mode.

[0023] Furthermore, the reconfigurable cross network is provided with a shifter, an accumulator and an output storage; Adjacent digital storage and calculation cores are connected through shifters and accumulators. The output of the accumulator is fed back to another accumulator, and the accumulated result is output through the output storage.

[0024] Furthermore, in 4-bit mode, each digital storage and computing core performs independent calculations, and the RS encoding and decoding module is in 4-bit calculation mode.

[0025] Furthermore, in 8-bit calculation mode, The four digital storage and computing cores in the reconfigurable subunit are divided into two groups, each group contains two adjacent digital storage and computing cores. In each group, each digital storage and computing core still performs 4-bit / 4-bit calculations; In one group, the digital storage and calculation core calculates with the high-order 4-bits of the 8-bit data, and in the other group, the digital storage and calculation core calculates with the low-order 4-bits of the 8-bit data; The high-order calculation result is shifted left by four bits through the shifter and then added to the low-order result to obtain an 8-bit / 8-bit calculation result.

[0026] Furthermore, in 16-bit computing mode, Between the four reconfigurable subunits, 16-bit / 16-bit is split into four 4-bit calculations, with each reconfigurable subunit responsible for one 4-bit / 16-bit calculation; In each reconfigurable subunit, 4-bit / 16-bit calculations are split into four 4-bit / 4-bit calculations according to the high-level status, and are respectively set in four digital storage and calculation cores for calculation, and the 4-bit / 16-bit calculation results are obtained through the accumulator respectively; The output results of the four reconfigurable sub-units are added together to obtain a 16-bit / 16-bit calculation result.

[0027] Furthermore, when performing encoding operations, The main controller is used to adjust the RS codec module to the encoding mode; In the RS encoding and decoding module, the tape information to be encoded and decoded is calculated with the RS encoding matrix, and the encoding result is stored in the buffer area 2; The main controller controls the encoding result to be written from the buffer area 2 to the magnetic head.

[0028] Furthermore, when performing the decoding operation, The main controller is used to adjust the RS codec module to the decoding mode; In the RS encoding and decoding module, the tape information to be encoded and decoded is calculated with the RS decoding matrix, and the decoding result is stored in the buffer area 2; The main controller controls the decoding result to be stored from the buffer area 2 back to the global buffer.

[0029] Furthermore, the RS encoding and decoding module supports 4 / 8 / 16-bit encoding or decoding operations, and is controlled by the slave controller.

[0030] The advantages of the high-energy-efficiency digital storage and computing integrated RS codec accelerator supporting variable code length provided by the present invention are: proposing a multi-bit reconfigurable storage and computing integrated architecture, deeply embedding Galois field operations into storage units, and constructing a bit-width adaptive data flow path, achieving breakthroughs in computing energy efficiency and compatibility with multiple computing formats, and providing an error correction solution with both ultra-high energy efficiency and cross-generation compatibility for PB-level tape storage; its core advantages are reflected in three aspects: first, by embedding Galois field operations into SRAM storage units to construct an in-memory computing paradigm, the data movement of the traditional von Neumann architecture is completely eliminated. Secondly, it adopts a dynamic combination mechanism of reconfigurable cross network and 4-bit basic storage and computing core to realize seamless switching of 4 / 8 / 16-bit sign bit width, which not only meets the 4-bit head signal processing requirements of DDS-320 format, but also adapts to the 8-bit operation of LTO standard and the 16-bit high-precision verification required by HAMR technology; thirdly, it optimizes hardware resources through fine-grained data flow reconfiguration technology, dynamically schedules multi-dimensional data paths between storage and computing cores, and significantly improves the reuse rate of computing units while breaking through the area limitations of traditional solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a structural schematic diagram of the present invention; Figure 2 This is a schematic diagram of the accelerator process; Figure 3 It is a structural diagram of RS codec; Figure 4 This is a structural diagram of the RS codec in 4-bit calculation mode; Figure 5 This is a structural diagram of the RS codec in 8-bit calculation mode; Figure 6 This is a structural diagram of the RS codec in 16-bit calculation mode; Figure 7 This is a diagram of the von Neumann architecture; Figure 8 Schematic diagram of the performance scissors gap of existing storage computing; DETAILED DESCRIPTION The technical solutions of the present invention are described in detail below through specific embodiments. Numerous specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0032] This embodiment is based on the development of digital storage and computing integration in (1) the background technology. As the density of tape storage moves towards the PB level, RS coding has put forward unprecedented stringent requirements on the accuracy, compatibility and reliability of storage and computing chips. With its unique architectural advantages, the digital storage and computing integration chip has demonstrated irreplaceable value in dealing with challenges such as high-precision Galois field operations, dynamic symbol bit width switching and long-term data stability. Its digital logic characteristics based on SRAM not only support seamless reconstruction of multi-level bit widths from 4-bit to 16-bit, but can also be directly embedded in the tape controller chip through mature process integration, while eliminating the data handling bottleneck of the traditional architecture, significantly improving the anti-interference ability and long-term operation stability of the encoding and decoding system. This technical feature is highly consistent with the error correction requirements of ultra-high-density tape storage, making the digital storage and computing integration architecture a core solution to break through the energy efficiency and compatibility barriers of RS coding. Therefore, this embodiment adopts this technical route to realize the innovative design of variable code length encoding and decoding accelerator.

[0033] This embodiment integrates the technical context of the previous technology and adopts a data stream reconfigurable storage and computing integrated architecture to meet the RS encoding and decoding requirements of tape storage systems. By reconfiguring the multi-dimensional scheduling strategy between storage and computing cores and the mode switching mechanism across the array data path, it achieves adaptive processing of 4 / 8 / 16-bit sign bit widths. This solution enables the Galois field operation unit to dynamically adapt to the differentiated requirements of tape formats such as DDS, LTO, and HAMR, while ensuring ultra-high energy efficiency while breaking the fixed bit width bottleneck of traditional architectures.

[0034] The core solutions of this embodiment are as follows: (1) Based on a digital storage and computing integrated architecture, RS polynomial operations are mapped to in-memory matrix operations, eliminating data transfer energy consumption and improving the chip encoding and decoding computing energy efficiency; (2) A data flow reconfigurable architecture is designed to support 4 / 8 / 16-bit bit width processing modes and be compatible with computing requirements under different bit width formats.

[0035] like Figures 1 to 6 As shown, the high-efficiency digital storage and computing integrated RS codec accelerator supporting variable code length proposed by the present invention includes a main controller, an RS codec module, a global buffer, a cache area 1 and a cache area 2; The main controller is used to adjust the RS codec module to the encoding or decoding mode; The global buffer is used to store tape information to be encoded and decoded; The RS encoding and decoding module is used to encode or decode the tape information to be encoded or decoded; Cache area 1 is used to cache tape information; Buffer 2 is used to cache encoding or decoding results.

[0036] In this embodiment, Figure 2 As shown, specifically: 1) the data to be encoded and decoded in the tape information is pre-stored in the global buffer, waiting for the RISC-V main controller to control; 2) the RISC-V main controller adjusts the RS encoding and decoding module to the encoding or decoding mode; 3) in the encoding mode, the slave controller first adjusts the RS encoding and decoding module to the 4 / 8 / 16-bit calculation mode, and then controls the data to be encoded and the RS encoding matrix to perform encoding calculation, and the encoding result is stored in the cache area 2, waiting for the RISC-V main controller to control the write head; 4) in the decoding mode, the slave controller first adjusts the RS encoding and decoding module to the 4 / 8 / 16-bit calculation mode, and then controls the data to be decoded and the RS decoding matrix to perform decoding calculation, and the decoding result is stored in the cache area 2, waiting for the RISC-V main controller to control the write back to the global buffer.

[0037] The accelerator architecture set up in this embodiment combines the high energy efficiency of ASIC with the flexibility of FPGA. It not only enhances the anti-interference ability of RS encoding, but also achieves compatibility support across generations of tape formats, providing an innovative solution for ultra-high-density storage systems to break through the rigid bottleneck of encoding and decoding hardware.

[0038] In one embodiment, Figure 3 As shown, the RS encoding and decoding module is a variable code length RS encoding and decoding module, which includes a bus, four reconfigurable sub-units and a slave controller; the reconfigurable sub-unit contains four digital storage and computing cores and a reconfigurable cross network, and the reconfigurable cross network is provided with a shifter, an accumulator and an output storage, etc.

[0039] The variable code length RS codec module can support 4 / 8 / 16-bit bit width encoding or decoding operations. For 4-bit calculation mode, see Figure 4 , 8-bit calculation mode see Figure 5 , 16-bit calculation mode see Figure 6 .

[0040] The variable code length RS codec module has four reconfigurable subunits, and each reconfigurable subunit has four digital storage and calculation cores. The digital storage and calculation core of this embodiment is designed to support only 4-bit calculation mode. Therefore, in 4-bit mode, Figure 4 As shown in the figure, each storage and computing core performs independent calculations, and the RS encoding and decoding module is in 4-bit calculation mode.

[0041] It should be noted that the storage and computing core is the smallest computing unit, and the calculation of a storage and computing core itself is 4-bit / 4-bit. Fine-grained data flow reconfiguration is achieved by rearranging / combining the smallest computing units.

[0042] In one embodiment, Figure 5 As shown, based on the above accelerator architecture, 8-bit computing mode can be achieved: In the 8-bit calculation mode, inside the reconfigurable subunit, the four digital storage and calculation cores in the reconfigurable subunit are divided into two groups, each group containing two adjacent digital storage and calculation cores. In each group, each digital storage and calculation core still performs 4-bit / 4-bit calculations; in one group, the digital storage and calculation core calculates with the high-order 4-bits of the 8-bit data, and in the other group, the digital storage and calculation core calculates with the low-order 4-bits of the 8-bit data; the high-order calculation result is shifted left by four bits through the shifter and then added to the low-order result to obtain the 8-bit / 8-bit calculation result, that is, the 8-bit calculation mode.

[0043] Specifically: the four digital storage and computing cores in the reconfigurable sub-unit are 1, 2, 3, and 4, respectively. Storage and computing core 1 and storage and computing core 2 are group 1, used to process the high-order 4-bits in 8-bit data, and storage and computing core 3 and storage and computing core 4 are group 2, used to process the low-order 4-bits in 8-bit data. It can be understood that the two groups can exchange the calculation of the high and low bits of 8-bit data.

[0044] The two 8-bit input operands A and B need to be split into 4-bit segments: the allocation rules (taking multiplication as an example) are detailed in Table 1: Table 1

[0045] Each digital storage core performs 4-bit basic operations, generates intermediate results, and shifts and aligns them. Specifically, the result of storage core 1 is shifted left by 8 bits → aligned to the upper 16 bits (if it is multiplication), the results of storage core 2 and storage core 3 are shifted left by 4 bits → aligned to the middle 8 bits, and the result of storage core 4 is not shifted → aligned to the lower 8 bits.

[0046] The partial products are merged through a multi-stage adder network. That is, the carry of storage core 1 is passed to storage core 2, and the carry of storage core 3 is passed to storage core 4. Finally, the carry chain is merged: First level addition: Storage and calculation core 1 (high 8 bits) + storage and calculation core 2 (middle high 4 bits) → intermediate result 1 (12-bit).

[0047] Storage and calculation core 3 (lower 4 bits) + storage and calculation core 4 (lower 8 bits) → intermediate result 2 (12-bit).

[0048] Second level addition: Intermediate result 1 + intermediate result 2 → final 8-bit / 8-bit mode calculation result.

[0049] This embodiment uses four 4-bit storage and computing cores to collaboratively complete 8-bit operations under hardware reconstruction control, achieving: resource reuse: the same hardware supports RS encoding and decoding of multiple code lengths; performance improvement: parallel calculation of partial products, with efficiency close to that of native 8-bit units.

[0050] In one embodiment, Figure 6 As shown, based on the above accelerator architecture, a 16-bit computing mode can be achieved, specifically: Across the four reconfigurable subunits, 16-bit / 16-bit operations are split into four 4-bit calculations. The four digital storage and computation cores within the four reconfigurable subunits are 1, 2, 3, and 4, respectively. Each reconfigurable subunit is responsible for a 4-bit / 16-bit calculation. Specifically, each reconfigurable subunit processes the upper 4 bits, mid-upper 4 bits, mid-lower 4 bits, or lower 4 bits of a 16-bit operand (corresponding to the four 4-bit segments after the split). The reconfigurable subunits are connected via a global adder network and crossbar switches, supporting cross-unit accumulation of partial products.

[0051] Split the two 16-bit operands A and B into four 4-bit segments, A = A3 || A2 || A1 || A0 (A3 is the most significant 4 bits, A0 is the least significant 4 bits), B = B3 || B2 || B1 || B0, and assign each segment to four reconfigurable sub-units. The reconfigurable sub-unit assignment rules (taking multiplication as an example) are detailed in Table 2: Table 2

[0052] Each reconfigurable subunit needs to complete a 4-bit × 16-bit operation. The specific steps are as follows: Secondary splitting of B: Split the 16-bit B into B3, B2, B1, and B0 (4-bit segments). The allocation and calculation of the digital storage and computing cores in the reconfigurable subunits are shown in Table 3. Taking subunit 1 as an example: Table 3

[0053] The calculation results of the four digital storage cores in the reconfigurable sub-unit are added through the adder to obtain the intermediate result of A3×B (occupying 12–31 bits) The above four reconfigurable sub-units are bit-aligned and accumulated. The output shift alignment of the reconfigurable sub-units is detailed in Table 4: Table 4

[0054] Through a multi-stage adder network: In the first stage, the results of subunits 1 and 2 are combined through an adder. In the second stage, the results of subunits 3 and 4 are combined through another adder. The intermediate results of the two stages are output through the final adder in 16-bit calculation mode.

[0055] This embodiment uses 4-bit × 16-bit calculation decomposition within the reconfigurable sub-unit and cross-sub-unit collaborative accumulation. The system completes 16-bit / 16-bit operations with four reconfigurable sub-units, achieving: Hardware reuse: 4-bit memory and computing core design is used to avoid dedicated high-bit-width units; Parallel acceleration: 16 memory and computing cores calculate 16 partial products in parallel, achieving efficiency close to that of native 16-bit units. Flexible reconfiguration: Seamlessly switch between 4 / 8 / 16-bit modes through dynamic data path and shift control.

[0056] This embodiment proposes a multi-bit reconfigurable storage and computing integrated architecture. By deeply embedding Galois field operations into storage units and constructing bit-width adaptive data flow paths, it achieves breakthroughs in computing energy efficiency and compatibility with multiple computing formats, providing PB-level tape storage with an error correction solution that combines ultra-high energy efficiency and cross-generation compatibility.

[0057] This embodiment achieves multiple breakthroughs in the field of RS encoding and decoding through the deep integration of a digital storage and computing architecture and data stream reconfiguration technology. Its core advantages are reflected in three aspects: First, by embedding Galois field operations into SRAM storage cells to construct an in-memory computing paradigm, the data transfer energy consumption of the traditional von Neumann architecture is completely eliminated, significantly improving computing energy efficiency; second, a dynamic combination mechanism of a reconfigurable cross network and a 4-bit basic storage and computing core is adopted to achieve seamless switching of 4 / 8 / 16-bit sign bit widths, meeting the 4-bit head signal processing requirements of the DDS-320 format, while adapting to the 8-bit operations of the LTO standard and the 16-bit high-precision verification required by HAMR technology; third, through fine-grained data stream reconfiguration technology, hardware resources are optimized and multi-dimensional data paths between storage and computing cores are dynamically scheduled, significantly improving the reuse rate of computing units while breaking through the area limitations of traditional solutions.

[0058] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. High-efficiency digital storage and computing integrated RS codec accelerator supporting variable code length, characterized by: It includes a main controller, an RS codec module, a global buffer, a buffer area 1 and a buffer area 2; The main controller is used to adjust the RS codec module to the encoding or decoding mode; The global buffer is used to store tape information to be encoded and decoded; The RS encoding and decoding module is used to encode or decode the tape information to be encoded or decoded; Cache area 1 is used to cache tape information; Buffer 2 is used to cache encoding or decoding results.

2. The RS codec accelerator according to claim 1, wherein: The RS codec module includes a bus, four reconfigurable subunits and a slave controller; The RS codec module is connected to the main controller via a bus; The slave controller is used to switch the encoding or decoding mode inside the RS codec module; The reconfigurable subunit is used to encode or decode the tape information.

3. The RS codec accelerator according to claim 2, wherein: The reconfigurable subunit contains four digital storage and computing cores and a reconfigurable cross network; The reconfigurable cross network separates the four digital storage and computing cores, and each digital storage and computing core is designed to support only 4-bit computing mode.

4. The RS codec accelerator according to claim 3, wherein: The reconfigurable cross network is provided with a shifter, an accumulator and an output storage; Adjacent digital storage and calculation cores are connected through shifters and accumulators. The output of the accumulator is fed back to another accumulator, and the accumulated result is output through the output storage.

5. The RS codec accelerator according to claim 4, wherein: In 4-bit mode, each digital storage and computing core performs independent calculations, and the RS encoding and decoding module is in 4-bit calculation mode.

6. The RS codec accelerator according to claim 4, wherein: In 8-bit calculation mode, The four digital storage and computing cores in the reconfigurable subunit are divided into two groups, each group contains two adjacent digital storage and computing cores. In each group, each digital storage and computing core still performs 4-bit / 4-bit calculations; In one group, the digital storage and calculation core calculates with the high-order 4-bits of the 8-bit data, and in the other group, the digital storage and calculation core calculates with the low-order 4-bits of the 8-bit data; The high-order calculation result is shifted left by four bits through the shifter and then added to the low-order result to obtain an 8-bit / 8-bit calculation result.

7. The RS codec accelerator according to claim 4, wherein: In 16-bit calculation mode, Between the four reconfigurable subunits, 16-bit / 16-bit is split into four 4-bit calculations, with each reconfigurable subunit responsible for one 4-bit / 16-bit calculation; In each reconfigurable subunit, 4-bit / 16-bit calculations are split into four 4-bit / 4-bit calculations according to the high-level status, and are respectively set in four digital storage and calculation cores for calculation, and the 4-bit / 16-bit calculation results are obtained through the accumulator respectively; The output results of the four reconfigurable sub-units are added together to obtain a 16-bit / 16-bit calculation result.

8. The RS codec accelerator according to claim 1, wherein: When encoding, The main controller is used to adjust the RS codec module to the encoding mode; In the RS encoding and decoding module, the tape information to be encoded and decoded is calculated with the RS encoding matrix, and the encoding result is stored in the buffer area 2; The main controller controls the encoding result to be written from the buffer area 2 to the magnetic head.

9. The RS codec accelerator according to claim 1, wherein: During the decoding operation, The main controller is used to adjust the RS codec module to the decoding mode; In the RS encoding and decoding module, the tape information to be encoded and decoded is calculated with the RS decoding matrix, and the decoding result is stored in the buffer area 2; The main controller controls the decoding result to be stored from the buffer area 2 back to the global buffer.

10. The RS codec accelerator according to claim 2, wherein: In 4-bit mode, the RS codec module supports 4 / 8 / 16-bit encoding or decoding operations and is controlled by the slave controller.

Images