Hardware assisted checkpoint for enabling recovery from hardware failure

Abstract

The invention relates to hardware-assisted checkpoints for enabling recovery from hardware failures. Techniques are described herein that enable hardware-driven checkpoint settings within an accelerator device without requiring significant host software intervention to generate checkpoints. One embodiment provides an accelerator device comprising a memory interconnect, a plurality of accelerator cores, and a scheduler coupled with the plurality of accelerator cores. The scheduler is configured to receive a checkpoint creation job such that a compressed checkpoint for a training operation performed via the plurality of accelerator cores is generated, atomically create the compressed checkpoint for at least a portion of the training operation, and store the compressed checkpoint to a checkpoint storage associated with the accelerator device.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. Provisional Application No. 63 / 564,859, filed on March 13, 2024, which is hereby incorporated by reference herein. Technical Field

[0003] The present disclosure relates to hardware-assisted checkpointing for enabling recovery from hardware failures. Background Art

[0004] AI training models are large and growing rapidly, and these models are trained on massive datasets and run in a distributed manner. Therefore, even when trained on highly optimized GPU clusters, training recommendation models at production scale can take days. Summary of the Invention

[0005] According to an embodiment of the present disclosure, an accelerator device is provided, comprising: a memory interconnect; a plurality of accelerator cores; and a scheduler coupled to the plurality of accelerator cores, the scheduler being configured to: receive a checkpoint creation job to generate a compressed checkpoint for a training operation, the training operation being performed via the plurality of accelerator cores; atomically create a compressed checkpoint for at least a portion of the training operation; and store the compressed checkpoint in a checkpoint storage device associated with the accelerator device.

[0006] According to an embodiment of the present disclosure, a method for creating a hardware-assisted checkpoint is provided, the method comprising: executing a training operation for a neural network via one or more accelerator devices; submitting a checkpoint creation job to an accelerator device among the one or more accelerator devices in response to a checkpoint creation marker within a training workload; executing the checkpoint creation job at a scheduler of the accelerator device; atomically creating a compressed checkpoint for at least a portion of the training operation executed at the accelerator device; and storing the compressed checkpoint in a checkpoint storage device associated with the accelerator device.

[0007] According to an embodiment of the present disclosure, a data processing system is provided, comprising: a general-purpose processor; and an accelerator device coupled to the general-purpose processor, the accelerator device comprising a plurality of accelerator cores and a scheduler coupled to the plurality of accelerator cores, the scheduler being configured to: receive a checkpoint creation job to generate a compressed checkpoint for a training operation, the training operation being executed by the general-purpose processor via the plurality of accelerator cores; atomically create a compressed checkpoint for at least a portion of the training operation; and store the compressed checkpoint in a checkpoint storage device associated with the accelerator device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments described herein are illustrated by way of example and not limitation in the accompanying drawings in which like numerals indicate similar elements, and in which:

[0009] Figure 1 The block diagram illustrates a computer system configured to implement one or more aspects of the embodiments described herein;

[0010] Figures 2A-2E illustrates parallel processor components, including a graphics multiprocessor;

[0011] Figure 3 illustrates a graphics processing unit that includes a collection of specialized graphics processing resources arranged into multi-core groups;

[0012] Figures 4A-4E An exemplary architecture is illustrated in which multiple GPUs are communicatively coupled with multiple multi-core processors;

[0013] Figure 5 The graphics processing pipeline is illustrated;

[0014] Figure 6 Diagram showing the machine learning software stack;

[0015] Figure 7 A general purpose graphics processing unit is illustrated;

[0016] Figure 8 The diagram shows a multi-GPU computing system;

[0017] Figures 9A-9B illustrates the layers of an exemplary deep neural network;

[0018] Figures 10A-10B An exemplary language model is illustrated;

[0019] Figure 11 Illustrate the training and deployment of deep neural networks;

[0020] Figure 12A The block diagram illustrates distributed learning;

[0021] Figure 12B The block diagram illustrates a programmable network interface and a data processing unit;

[0022] Figure 13 An exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model is illustrated;

[0023] Figure 14 It is a block diagram of the processing system;

[0024] Figures 15A-15CA diagram illustrates a computing system and a graphics processor;

[0025] Figure 16 is a block diagram of a graphics processor, which may be a discrete or integrated graphics processing unit;

[0026] Figures 17A-17B illustrates a block diagram of an add-on graphics processor and computing accelerator architecture;

[0027] Figures 18A-18C illustrates thread execution logic comprising an array of processing elements employed in a graphics processor core;

[0028] Figure 19 illustrates a tile of a multi-tile processor according to an embodiment;

[0029] Figure 20 The block diagram illustrates the graphics processor instruction format;

[0030] Figure 21 is a block diagram of an additional graphics processor architecture;

[0031] Figures 22A-22B The graphic shows the graphics processor command format and command sequence;

[0032] Figure 23 illustrates an exemplary graphical software architecture for a data processing system;

[0033] Figure 24 The block diagram illustrates the IP core development system;

[0034] Figure 25A illustrates a cross-sectional side view of an integrated circuit package assembly including a plurality of hardware logic core units connected to a substrate (e.g., base die);

[0035] Figure 25B A package assembly including interchangeable die is illustrated;

[0036] Figure 26 The block diagram illustrates a system-on-chip integrated circuit;

[0037] Figures 27A-27B Graph showing training failure rate and CPU-based checkpointing.

[0038] Figures 28A-28C illustrates a system 2800 for implementing hardware-assisted checkpointing during neural network training, according to an embodiment;

[0039] Figure 29 Illustrated are components of a HW scheduler that implement the creation of compressed checkpoint data according to an embodiment;

[0040] Figure 30 is a block diagram of a portion of a data center including computing assets configurable to perform distributed training operations;

[0041] Figure 31 A system for implementing scheduling of other jobs while a checkpoint operation is in progress is illustrated;

[0042] Figures 32A-32B illustrates methods for saving and restoring checkpoint data during training operations; and

[0043] Figure 33 is a block diagram of a computing device including a graphics processor, according to an embodiment. DETAILED DESCRIPTION

[0044] To improve performance, graphics processors often implement processing techniques such as pipelining, which attempts to process as much graphics data as possible in parallel across different parts of the graphics pipeline. Parallel graphics processors with a single instruction, multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing within the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to improve processing efficiency.

[0045] A graphics processing unit (GPU) is communicatively coupled to a host / processor core to, for example, accelerate graphics operations, machine learning operations, pattern analysis operations, and / or various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). Alternatively, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0046] Although the techniques described herein are primarily discussed in the context of GPUs, these techniques may also be implemented in other types of processors, including but not limited to general-purpose processors and accelerator devices such as artificial intelligence accelerators, vision processors, and neural processing units.

[0047] In the following description, many specific details are described to provide a more thorough understanding. However, it will be clear to those skilled in the art that the embodiments described herein can be implemented without one or more of these specific details. In other cases, well-known features are not described to avoid obscuring the details of these embodiments.

[0048] System Overview

[0049] Figure 1 The block diagram of FIG. 1 illustrates a computing system 100 configured to implement one or more aspects of the embodiments described herein. Computing system 100 includes a processing subsystem 101 having one or more processors 102 and system memory 104, which communicate via an interconnect path that may include a memory hub 105. Memory hub 105 may be a separate component within a chipset assembly or may be integrated within one or more processors 102. Memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. I / O subsystem 111 includes an I / O hub 107, which enables computing system 100 to receive input from one or more input devices 108. Additionally, I / O hub 107 may enable a display controller included in one or more processors 102 to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to I / O hub 107 may include local, internal, or embedded display devices.

[0050] For example, the processing subsystem 101 includes one or more parallel processors 112 that are coupled to the memory hub 105 via a communication link 113, such as a bus or fabric. The communication link 113 can be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication architecture. The one or more parallel processors 112 can form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many-integrated core (MIC) processor. For example, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0051] Within the I / O subsystem 111, a system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components (e.g., a network adapter 118 and / or a wireless network adapter 119 that can be integrated into the platform) and various other devices that can be added via one or more additional devices 120. The additional device(s) 120 can also include, for example, one or more external graphics processor devices, graphics cards, and / or computing accelerators. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0052] Computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 107 . Figure 1 The communication paths interconnecting the various components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express), or any (one or more) other bus or point-to-point communication interface and / or protocol, such as NVLink high-speed interconnect, Compute Express Link, or the like. TM (Compute Express Link TM , CXL TM) (e.g., CXL.mem), Infinity Fabric (IF), Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Ultra Ethernet Transport (UET), Ultra Accelerator Link (UALink), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omni-Path, HyperTransport, Advanced Microcontroller Bus Architecture (AMDCA), Intel FPGA IPsec (Intel FPGA IPsec), Intel FPGA IPsec (Intel FPGA IPsec), Intel FPGA IPsec (Intel FPGA IPsec), Intel FPGA IPsec (Intel FPGA IPsec), Intel FPGA IPsec (Intel FPGA IPsec), Intel FPGA IPsec (Intel FPGA IPsec), Intel FPGA IPsec (Intel FPGA IPsec), Intel FPGA IPsec (Intel FPGA IPsec), Intel FPGA IPsec Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variants thereof, or wired or wireless interconnect protocols known in the art. In some examples, data can be copied or stored to the virtualized storage node using a protocol such as non-volatile memory express (NVMe) over Fabrics (NVMe-oF) or NVMe.

[0053] One or more parallel processors 112 may include circuits optimized for graphics and video processing, such as video output circuits, and constitute a graphics processing unit (GPU). Alternatively or additionally, one or more parallel processors 112 may include circuits optimized for general-purpose processing while retaining the underlying computing architecture described in more detail herein. The components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, the memory hub 105, (one or more) processors 102, and the I / O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0054] In some configurations, in addition to the processor(s) 102 and the parallel processor(s) 112, the computing system 100 also includes one or more accelerator devices 130 coupled to the memory hub 105. The accelerator device(s) 130 are configured to perform domain-specific acceleration of workloads to address computationally intensive or high-throughput tasks. The accelerator device(s) 130 can reduce the burden placed on the processor(s) 102 and / or the parallel processor(s) 112 of the computing system 100. The accelerator device(s) 130 may include, but are not limited to, intelligent network interface cards, data processing units, cryptographic accelerators, storage accelerators, artificial intelligence (AI) accelerators, neural processing units (NPUs), storage accelerators, and / or video transcoding accelerators. It will be understood that the computing system 100 shown herein is illustrative only and is subject to variation and modification. The connection topology (including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112) can be modified as needed. For example, system memory 104 can be connected directly to processor(s) 102 rather than through a bridge, while other devices communicate with system memory 104 via memory hub 105 and processor(s) 102. In other alternative topologies, parallel processor(s) 112 are connected to I / O hub 107 or directly to one of the processor(s) 102 rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 can be integrated into a single chip. Two or more sets of processors 102 can also be attached via multiple sockets, which can be coupled to two or more instances of parallel processor(s) 112.

[0055] Some specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of add-in cards or peripherals may be supported, or some components may be eliminated. Additionally, some architectures may have different requirements for the Figure 1 Similar components are shown in FIG. 1 using different terminology. For example, in some architectures, memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0056] Figure 2AThe diagram shows a parallel processor 200. The parallel processor 200 may be a GPU, a GPGPU, or the like as described herein. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The parallel processor 200 may be Figure 1 One or more of the parallel processor(s) 112 shown in .

[0057] The parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices (including other instances of the parallel processing unit 202). The I / O unit 204 can be directly connected to other devices. For example, the I / O unit 204 is connected to other devices by using a hub or switch interface (e.g., a memory hub 105). The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, wherein the host interface 206 receives commands for executing processing operations, and the memory crossbar 216 receives commands for executing memory operations. In one embodiment, the I / O unit 204 is configured to implement secure I / O operations via a Trusted Execution Environment (TEE)-I / O support. TEE-IO implements trusted I / O virtualization, where a trust relationship can be directly established between a secure virtual environment (eg, a trusted virtual machine) and a parallel processor 200 or a secure partition of a parallel processor.

[0058] When host interface 206 receives command buffers via I / O unit 204, it can direct the work of executing these commands to front-end 208. In one embodiment, front-end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. Before tasks are distributed to processing clusters within processing cluster array 212, scheduler 210 ensures that processing cluster array 212 is properly configured and in a valid state. Scheduler 210 can be implemented via firmware logic executed on a microcontroller. A microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling rapid preemption and context switching of threads executing on processing cluster array 212. Preferably, host software can authenticate workloads for scheduling on processing cluster array 212 via one of multiple graphics processing doorbells. In other examples, polling for new workloads or interrupts can be used to identify or indicate the availability of work to be executed. The scheduler 210 logic within the scheduler microcontroller may then automatically distribute the workload across the processing cluster array 212 .

[0059] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, through cluster 214N). Each cluster 214A-214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to assign work to the clusters 214A-214N of the processing cluster array 212, which may vary depending on the workload occurring for each type of program or computation. Scheduling may be handled dynamically by the scheduler 210, or may be partially assisted by compiler logic during the compilation of program logic configured for execution by the processing cluster array 212. Optionally, different clusters 214A-214N of the processing cluster array 212 may be assigned to process different types of programs or perform different types of computations.

[0060] Processing cluster array 212 may be configured to perform various types of parallel processing operations. For example, processing cluster array 212 may be configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations (including physics operations), and performing data transformations.

[0061] Processing cluster array 212 is configured to perform parallel graphics processing operations. In such embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0062] In embodiments where parallel processing unit 202 is used to perform graphics processing, scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 214A-214N of processing cluster array 212. In some of these embodiments, portions of processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N may be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0063] During operation, processing cluster array 212 may receive processing tasks to be executed via scheduler 210, which receives commands defining the processing tasks from front-end 208. For graphics processing operations, a processing task may include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program to execute). Scheduler 210 may be configured to retrieve an index corresponding to a task, or may receive an index from front-end 208. Front-end 208 may be configured to ensure that processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0064] Each of the one or more instances of parallel processing unit 202 can be coupled to parallel processor memory 222. Parallel processor memory 222 can be accessed via memory crossbar 216, which can receive memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar 216 can access parallel processor memory 222 via memory interface 218. Memory interface 218 can include multiple partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N), each of which can be coupled to a portion of parallel processor memory 222 (e.g., memory cells). The number of partition units 220A-220N can be configured to be equal to the number of memory cells, such that each partition unit 220A-220N has a corresponding memory cell 224A-224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory cells.

[0065] Memory units 224A-224N may include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random-access memory, such as synchronous graphics random-access memory (SGRAM), including graphics double data rate (GDDR) memory. Optionally, memory units 224A-224N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory units 224A-224N may vary and may be selected from a variety of conventional designs. Render targets (e.g., frame buffers or texture atlases) may be stored across memory units 224A-224N, allowing partition units 220A-220N to write portions of each render target in parallel, efficiently utilizing the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may not be included, and a unified memory design utilizing system memory in combination with local cache memory may be employed.

[0066] Optionally, any of the clusters 214A-214N in the processing cluster array 212 can process data to be written to any memory unit 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transmit the output of each cluster 214A-214N to any partition unit 220A-220N or to another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with a memory interface 218 via the memory crossbar 216 to read from or write to various external memory devices. In one embodiment having a memory crossbar 216, the memory crossbar 216 has connections to the memory interface 218 for communicating with the I / O unit 204, as well as connections to local instances of the parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. Generally speaking, the memory crossbar 216 may be capable of separating traffic flows between the clusters 214A-214N and the partition units 220A-220N, for example, using virtual channels.

[0067] Although a single instance of PPU 202 is illustrated within PPU 200, any number of instances of PPU 202 may be included. For example, multiple instances of PPU 202 may be provided on a single add-in card, or multiple add-in cards may be interconnected. For example, PPU 202 may be a processor that is configured to handle multiple processors. Figure 1 The additional device included in the (one or more) additional devices 120 can be a graphics card, such as a discrete graphics card including one or more GPUs, one or more memory devices, and a device-to-device or network or architecture interface. Different instances of the parallel processing unit 202 can be configured to interoperate, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. Optionally, some instances of the parallel processing unit 202 may include floating point units with higher precision relative to other instances. Systems including one or more instances of the parallel processing unit 202 or parallel processor 200 can be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems. The coordinator can utilize one or more of the following to form a composite node for workload execution: decomposed processor resources, cache resources, memory resources, storage resources, and networking resources.

[0068] In one embodiment, parallel processing unit 202 can be partitioned into multiple instances. These multiple instances can be configured to execute workloads associated with different clients in an isolated manner, thereby enabling a predetermined quality of service to be provided to each client. For example, each cluster 214A-214N can be separated and isolated from the other clusters, allowing the processing cluster array 212 to be divided into multiple compute partitions or instances. In this configuration, workloads executed on isolated partitions can be protected from failures or errors associated with different workloads executed on different partitions. Partition units 220A-220N can be configured to implement dedicated and / or isolated paths to memory for clusters 214A-214N associated with each compute partition. This data path isolation enables computing resources within a partition to communicate with one or more assigned memory units 224A-224N without being interfered with by the activities of other partitions. In one embodiment, data path isolation can be enhanced by encrypting data in the memory of each partition using encryption keys unique to the associated partition, thereby ensuring partition-based security for data both at rest and in transit.

[0069] Figure 2B is a block diagram of the partition unit 220. The partition unit 220 may be Figure 2A 220N。 As shown in the figure, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225 and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache that is configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read misses and urgent write back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer for processing via the frame buffer interface 225. In one embodiment, the frame buffer interface 225 is connected to the frame buffer interface 225. Figure 2A The partition unit 220 interfaces with a memory unit 224 of the memory units 224A-224N in the parallel processor memory 222. The partition unit 220 may additionally or alternatively interface with one of the memory units in the parallel processor memory via a memory controller (not shown).

[0070] In graphics applications, ROP 226 is a processing unit that performs raster operations (e.g., stenciling, z-testing, blending, etc.). ROP 226 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes or is coupled to a codec 227, which includes compression logic to compress depth or color data written to memory or L2 cache 221 and decompress depth or color data read from memory or L2 cache 221. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by codec 227 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, incremental color compression is performed on depth and color data on a per-tile basis. In one embodiment, codec 227 includes compression and decompression logic that can compress and decompress computational data associated with machine learning operations. For example, codec 227 can compress sparse matrix data used for sparse machine learning operations. The codec 227 can also compress sparse matrix data encoded in a sparse matrix format (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compressed sparse column (CSC), etc.) to generate compressed and encoded sparse matrix data. The compressed and encoded sparse matrix data can be decompressed and / or decoded before being processed by the processing element, or the processing element can be configured to consume compressed, encoded, or compressed and encoded data for processing. In one embodiment, the codec 227 can be configured as a general-purpose data compression engine for GPU database acceleration and large-volume data analysis.

[0071] ROP 226 may be included in each processing cluster (e.g., Figure 2A 214A-214N) rather than within partition unit 220. In such an embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted through memory crossbar 216. The processed graphics data may be displayed on a display device, such as a Figure 1 One of the one or more display devices 110A-110B is routed to be further processed by the processor(s) 102, or is routed to be further processed by the processor(s) 102. Figure 2A One of the processing entities within the parallel processor 200 further processes.

[0072] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit. For example, processing cluster 214 represents Figure 2AAn instance of one of the processing clusters 214A-214N. The processing cluster 214 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific input data set. Alternatively, a single instruction multiple data (SIMD) instruction issuance technology can be used to support the parallel execution of a large number of threads without providing multiple independent instruction units. Alternatively, a single-instruction, multiple-thread (SIMT) technology can be used to support the parallel execution of a large number of generally synchronized threads, wherein a common instruction unit is used that is configured to issue instructions to a group of processing engines within each processing cluster. Unlike the SIMD execution mechanism (in which all processing engines typically execute the same instructions), SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0073] The operation of the processing cluster 214 may be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. Figure 2A Scheduler 210 receives instructions and manages the execution of these instructions via graphics multiprocessor 234 and / or texture unit 236. Graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures may be included within processing cluster 214. One or more instances of graphics multiprocessor 234 may be included within processing cluster 214. Graphics multiprocessor 234 may also be referred to as a streaming multiprocessor (SM) and is capable of executing a large number of execution threads simultaneously.

[0074] The graphics multiprocessor 234 can process data, and the data crossbar 240 can be used to distribute the processed data to one of multiple possible destinations, including instances of the graphics multiprocessor 234 within the processing cluster 214. The pipeline manager 232 can facilitate the distribution of processed data by specifying destinations for the processed data to be distributed via the data crossbar 240. Each graphics multiprocessor 234 within the processing cluster 214 may include an identical set of function execution logic (e.g., an arithmetic logic unit, a load-store unit, etc.). The function execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions are completed. The function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and the calculation of various algebraic functions. The same functional unit hardware can be used to perform different operations, and any combination of functional units can be present.

[0075] Instructions transmitted to processing cluster 214 constitute threads. A group of threads executing on a set of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. The number of threads included in a thread group can be less than the number of processing engines within graphics multiprocessor 234. When the number of threads included in a thread group is less than the number of processing engines within graphics multiprocessor 234, one or more of the processing engines may be idle during the cycle in which the thread group is being processed. The number of threads included in a thread group can also be greater than the number of processing engines within graphics multiprocessor 234. When the number of threads included in a thread group is greater than the number of processing engines within graphics multiprocessor 234, processing can be performed in consecutive clock cycles. Optionally, multiple thread groups can be executed simultaneously on graphics multiprocessor 234.

[0076] The graphics multiprocessors 234 may include internal cache memory to perform load and store operations. Alternatively, the graphics multiprocessors 234 may forgo internal cache memory and use cache memory within the processing cluster 214 (e.g., level 1 (L1) cache 248). Each graphics multiprocessor 234 may also have access to partition units (e.g., Figure 2A 20N) are shared between all instances of processing cluster 214 and can be used to transfer data between threads. Graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data, which can be stored in L1 cache 248.

[0077] Each processing cluster 214 may include an MMU 245 (memory management unit) that is configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 may reside in Figure 2AThe MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and, optionally, to cache line indices. The MMU 245 may include a translation lookaside buffer (TLB) or cache that may reside within the L1 cache 248 of the graphics multiprocessor 234 or processing cluster 214. Physical addresses are processed to distribute surface data access locations to allow efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0078] In graphics and compute applications, the processing clusters 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 that is used to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown), or in some embodiments, from an L1 cache within the graphics multiprocessor 234, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct the data to a ROP unit that may interface with a partition unit (e.g., a partition unit) as described herein. Figure 2A The preROP 242 unit may perform color blending optimizations, organize pixel color data, and perform address translation.

[0079] It will be appreciated that the core architecture described herein is illustrative only and is subject to variation and modification. Any number of processing units may be included within processing cluster 214, e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc. The parallel processing units described herein may include any number of instances of processing cluster 214. Optionally, each processing cluster 214 may be configured to operate independently of other instances of processing cluster 214, e.g., using separate and distinct processing units, L1 caches, and L2 caches to facilitate data and fault isolation.

[0080] Figure 2DAn example of a graphics multiprocessor 234 is shown, where the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit cores (GPGPU cores 262), and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268. The graphics multiprocessor 234 may also include a ray tracing core 263 (including hardware logic to accelerate ray tracing operations) and a tensor core 264 (including hardware logic to accelerate tensor (e.g., matrix) operations). The instruction cache 252 may receive a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as groups of threads (e.g., warps), with each thread of the thread group being assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to translate addresses in the unified address space into different memory addresses accessible by the load / store unit 266.

[0081] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 234. The register file 258 provides temporary storage for operands in the data paths of the functional units connected to the graphics multiprocessor 234 (e.g., the GPGPU core 262, the load / store unit 266). The register file 258 can be divided among each functional unit so that each functional unit can be allocated a dedicated portion of the register file 258. For example, the register file 258 can be divided among different warps executed by the graphics multiprocessor 234.

[0082] The GPGPU cores 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions for the graphics multiprocessor 234. In some implementations, the GPGPU cores 262 may include hardware logic that might otherwise reside within the tensor core 264 and / or the ray tracing core 263. The GPGPU cores 262 may be architecturally similar or architecturally different. For example, in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. Optionally, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In one embodiment, a single-precision FPU or a set of separate FPUs may be configured to perform operations on 16-bit floating-point operands, such as operands in half-precision format or bfloat16 format (e.g., brain floating point), which is a 16-bit floating-point format with one sign bit, eight exponent bits, and eight significand bits, seven of which are explicitly stored. The FPUs within one or more GPGPU cores 262 may also support one or more 8-bit floating-point formats. Supported 8-bit floating-point formats include the E4M3 format with a 4-bit exponent and a 3-bit mantissa and the E5M2 format with a 5-bit exponent and a 2-bit mantissa. The graphics multiprocessor 234 may also include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. One or more GPGPU cores may also include fixed-function or special-function logic.

[0083] The GPGPU core 262 may include SIMD logic capable of executing a single instruction on multiple sets of data. Optionally, the GPGPU core 262 may physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions of the GPGPU core may be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operation may be executed in parallel as SIMD8 instructions. In one embodiment, a warp of 32 SIMT threads may be executed as a single SIMD32 instruction. Warp divergence may be handled via multiple SIMD instructions.

[0084] The memory and cache interconnect 268 is an interconnect network that connects each functional unit of the graphics multiprocessor 234 to the register file 258 and shared memory 270. For example, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, resulting in very low latency data transfers between the GPGPU core 262 and the register file 258. Shared memory 270 can be used to facilitate communication between threads executing on the functional units within the graphics multiprocessor 234. Shared memory 270 can also serve as a program-managed cache. Cache memory 272 can be used, for example, as an automatically managed data cache for caching texture data communicated between the functional units and the texture unit 236. Shared memory 270 and cache memory 272 can be coupled to the data crossbar 240 to facilitate communication with other components of the processing cluster, thereby facilitating coordinated execution of cluster workgroups across multiple graphics multiprocessors within the processing cluster. In addition to automatically cached data stored in cache memory 272, threads executing on GPGPU core 262 can also programmatically store data in shared memory. In one embodiment, shared memory 270 and cache memory 272 can be combined into a single configurable memory unit that can be selectively configured as either cache memory 272 or shared memory 270.

[0085] Figure 2E The diagram shows the Figure 2D The graphics multiprocessor 234 has an alternative configuration of the graphics multiprocessor 235. Any features disclosed in conjunction with the graphics multiprocessor 235 described herein are also disclosed with Figure 2D The corresponding combination of the graphics multiprocessor 234 is provided, but is not limited to this. Figure 2E The graphics multiprocessor 235 includes relative Figure 2DThe graphics multiprocessor 235 may include multiple additional instances of execution resources 286A-286D of the graphics multiprocessor 234. For example, the graphics multiprocessor 235 may include multiple instruction units 254A-254D, register files 258A-258D, and texture units 280A-280D. The graphics multiprocessor 235 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 262A-262D, ray tracing cores 263A-263D, and tensor cores 264A-264D) and multiple sets of load / store units 266A-266D. The execution resources 286A-286D work in conjunction with the texture unit(s) 280A-280D for texture operations while sharing the instruction cache 252, shared memory 270, and cache memories 272A-272B. In one embodiment, the execution resources 286A-286D also include a multi-function unit (MUFU) and / or a special-function unit (SFU) (e.g., MFUs 267A-267D) for performing special mathematical operations (e.g., transcendental operations including exponential, logarithmic, and trigonometric functions).

[0086] Various components can communicate via interconnect fabric 290. Interconnect fabric 290 may include one or more crossbar switches to enable communication between various components of graphics multiprocessor 235. GPGPU cores 262A-262D, ray tracing cores 263A-263B, and tensor cores 264A-264D can each communicate with shared memory 270 via interconnect fabric 290. Interconnect fabric 290 can arbitrate communications within graphics multiprocessor 235 to ensure fair bandwidth allocation between components. In one embodiment, interconnect fabric 290 can be a separate high-speed network fabric layer upon which each component of graphics multiprocessor 235 is stacked. Components of graphics multiprocessor 235 can also communicate with remote components via interconnect fabric 290.

[0087] In one embodiment, the graphics multiprocessor 235 includes a tensor transfer engine 292, which is a copy engine configurable to accelerate the movement of tensor data into and out of the graphics multiprocessor 235. The tensor transfer engine 292 can accelerate tensor memory operations by asynchronously performing address generation and data movement operations for N-dimensional tensor data blocks, thereby offloading operations that would otherwise be performed manually by program code executed by the graphics multiprocessor 235. The tensor transfer engine 292 can be configured to copy data between, for example, the shared memory 270 and / or cache memories 272A-272B of the graphics multiprocessor 235 and memory external to the graphics multiprocessor 235 (e.g., graphics processor global memory, such as parallel processor memory 222). In one embodiment, data transfers performed by the tensor transfer engine 292 can be configured to selectively bypass various intermediate data storage levels between source and destination memory. For example, transfers between global memory and shared memory 270 can bypass register files 258A-258D. In one embodiment, threads can synchronize on asynchronous tensor transfers via a non-blocking barrier synchronization mechanism.

[0088] In various embodiments, the graphics multiprocessor 235 can be customized for specific use cases by including or excluding certain components, thereby allowing for various implementations of the graphics multiprocessor 235 tailored to target power, performance, and area characteristics. For example, a compute-oriented variant of the graphics multiprocessor 235 that does not perform graphics operations can exclude ray tracing cores 263A-263D. A fully graphics-oriented variant can exclude the tensor transfer engine 292, while a graphics-oriented variant that is additionally configured to accelerate neural network inference can include at least one version of the tensor transfer engine 292.

[0089] Those skilled in the art will understand that Figure 1 and Figures 2A-2E The architecture described in the present disclosure is illustrative only and does not limit the scope of the present embodiments. Thus, the techniques described herein may be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (e.g., Figure 2A parallel processing unit 202), and one or more graphics processors or special purpose processing units without departing from the scope of the embodiments described herein.

[0090] A parallel processor or GPGPU as described herein can be communicatively coupled with a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPUs.

[0091] (GPGPU) functionality. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe, NVLink, or other known, standardized, or proprietary protocols). In other embodiments, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0092] Figure 3 A graphics processing unit (GPU 380) is shown that includes a collection of specialized graphics processing resources arranged into multi-core groups 365A-365N. Figure 2D Graphics multiprocessor 234 or Figure 2E 2. The graphics multiprocessor 235 of FIG. 2 corresponds to FIG. 2. Although details are provided for a single example of a multi-core group 365A-365N (e.g., multi-core group 365A), it will be appreciated that other multi-core groups 365B-365N may be equipped with the same or similar sets of graphics processing resources. Details described herein for multi-core groups 365A-365N may also be applied to the graphics multiprocessor 234 or graphics multiprocessor 235 as described herein.

[0093] As shown, multi-core group 365A may include a graphics core 370, a tensor core 371, and a ray tracing core 372. Graphics core 370 is similar to GPGPU cores 262A-262D and can be configured to execute instructions to perform graphics and / or general computing operations. Scheduler / dispatcher 368 is responsible for scheduling and dispatching graphics threads for execution on various cores within multi-core group 365A. Register files 369 are included, which store the operand values ​​used by the core when performing graphics or general computing operations for the executed threads. These register files 369 may include, for example, registers that can be configured to store integer values ​​or floating-point values, including vector registers for storing packed integer and / or floating-point data elements and tile registers for storing tensor / matrix values. Tile registers can be implemented as multidimensional registers including a combined set of vector registers.

[0094] One or more combined level 1 (L1) cache and shared memory units 373 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc. locally within each multi-core group 365A. One or more texture units 374 can also be used to perform texture rendering operations, such as texture mapping and sampling. A level 2 (L2) cache 375 shared by all or a subset of the multi-core groups 365A-365N stores graphics data and / or instructions for multiple concurrent graphics threads. As shown, the L2 cache 375 can be shared among multiple multi-core groups 365A-365N. One or more memory controllers 367 couple the GPU 380 to memory 366, which can be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0095] Input / output circuitry (I / O circuitry 363) couples GPU 380 to one or more I / O devices 362, such as a digital signal processor (DSP), a network controller, or a user input device. On-chip interconnects may be used to couple I / O devices 362 to GPU 380 and memory 366. At least one I / O memory management unit (IOMMU 364) of I / O circuitry 363 couples I / O devices 362 directly to memory 366. Optionally, IOMMU 364 manages multiple sets of page tables to map virtual addresses to physical addresses in memory 366. I / O devices 362, CPU(s) 361, and GPU 380 can thus share the same virtual address space.

[0096] In one implementation of IOMMU 364, IOMMU 364 supports virtualization. In this case, it can manage a first set of page tables to map guest / graphics virtual addresses to guest / graphics physical addresses, and a second set of page tables to map guest / graphics physical addresses to system / host physical addresses (e.g., within memory 366). The base address of each of the first and second sets of page tables can be stored in a control register and swapped out upon context switch (e.g., to enable the new context to access the associated set of page tables). Although in Figure 3 Not shown, each core within the multi-core group 365A-365N may include a translation lookaside buffer (TLB) to cache guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

[0097] (One or more) CPUs 361, GPU 380, and I / O devices 362 may be integrated on a single semiconductor chip and / or chip package. Memory 366 may be integrated on the same chip or may be coupled to one or more memory controllers 367 via an off-chip interface. In one implementation, memory 366 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, but the underlying principles described herein are not limited to this particular implementation.

[0098] Tensor Core 371 may include multiple execution units specifically designed to perform matrix operations, which are fundamental computational operations used to perform deep learning operations. For example, synchronized matrix multiplication operations can be used for neural network training and inference. Tensor Core 371 can perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half bytes (4 bits). For example, a neural network implementation extracts features from each rendered scene, potentially combining details from multiple frames to construct a high-quality final image.

[0099] In deep learning implementations, parallel matrix multiplication work can be scheduled for execution on the Tensor Core 371. Neural network training, in particular, requires a large number of matrix dot product operations. To process the inner product formula for N x N x N matrix multiplication, the Tensor Core 371 may include at least N dot product processing elements. Before the matrix multiplication begins, a complete matrix is ​​loaded into the tile register, and at least one column of the second matrix is ​​loaded each cycle for N cycles. In each cycle, N dot products are processed.

[0100] Matrix elements can be stored with different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT4), depending on the specific implementation. Different precision modes can be specified for the tensor core 371 to ensure that the most efficient precision is used for different workloads (e.g., inference workloads, which can tolerate quantization to bytes and nibbles). Supported formats also include 64-bit floating point (FP64) and non-IEEE floating point formats, such as bfloat16 format. One embodiment includes support for a reduced-precision tensor-floating point (TF32) mode that performs calculations using the range of FP32 (8 bits) and the precision of FP16 (10 bits). Reduced-precision TF32 operations can be performed on FP32 inputs and produce FP32 outputs with higher performance relative to FP32 and higher precision relative to FP16. In one embodiment, one or more 8-bit floating point (FP8), 6-bit floating point (FP6), and 4-bit floating point (FP4) formats are supported, including floating point formats represented as microscaling (MX) formats.

[0101] In one embodiment, the tensor core 371 supports a sparse mode of operation on matrices where the vast majority of values ​​are zero. The tensor core 371 includes support for encoding a matrix represented as a sparse matrix (e.g., a list of coordinates).

[0102] The Tensor Core 371 also includes support for compressed sparse matrix representations, such as compressed sparse row (COO), compressed sparse row (CSR), compressed sparse column (CSC), and the like. Where the sparse matrix representation can be further compressed, the Tensor Core 371 also includes support for compressed sparse matrix representations. Compressed, encoded, and / or compressed and encoded matrix data, along with associated compression and / or encoding metadata, can be read by the Tensor Core 371, and non-zero values ​​can be extracted. For example, for a given input matrix A, non-zero values ​​can be loaded from a compressed and / or encoded representation of at least a portion of matrix A. Based on the position of the non-zero value in matrix A (which can be determined based on index or coordinate metadata associated with the non-zero value), the corresponding value from input matrix B can be loaded. Depending on the operation to be performed (e.g., multiplication), if the corresponding value is zero, the operation to load the value from input matrix B can be bypassed. In one embodiment, the value pairs for certain operations (e.g., multiplication operations) can be pre-scanned by scheduler logic, and only operations between non-zero inputs are scheduled. Depending on the size of matrices A and B and the operation to be performed, the output matrix C can be dense or sparse. In the case where the output matrix C is sparse, the output matrix C can be output in a compressed format, sparse coding, or compressed sparse coding, depending on the configuration of the tensor core 371.

[0103] The ray tracing core 372 can accelerate ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. Specifically, the ray tracing core 372 may include ray traversal / intersection circuitry for performing ray traversals using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. The ray tracing core 372 may also include circuitry for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing core 372 performs traversal and intersection operations in conjunction with the image denoising techniques described herein, at least a portion of which can be executed on the tensor core 371. For example, the tensor core 371 may implement a deep learning neural network to perform denoising on frames generated by the ray tracing core 372. However, the CPU(s) 361, the graphics core 370, and / or the ray tracing core 372 may also implement all or part of the denoising and / or deep learning algorithms.

[0104] Furthermore, as described above, a distributed denoising scheme can be employed, wherein GPU 380 is located in a computing device coupled to other computing devices via a network or high-speed interconnect. In such a distributed scheme, the interconnected computing devices can share neural network learning / training data to increase the speed at which the entire system learns to perform denoising for different types of image frames and / or different graphics applications.

[0105] The ray tracing cores 372 can handle all BVH traversals and / or ray primitive intersections so that the graphics core 370 is not overloaded with thousands of instructions per ray. For example, each ray tracing core 372 includes a first set of dedicated circuits for performing bounding box tests (e.g., for traversal operations) and / or a second set of dedicated circuits for performing ray-triangle intersection tests (e.g., traversed intersecting rays). Thus, for example, multi-core group 365A can simply launch a ray probe, and the ray tracing cores 372 independently perform ray traversals and intersections and return hit data (e.g., hits, misses, multiple hits, etc.) to the thread context. While the ray tracing cores 372 perform traversals and intersection operations, the graphics core 370 and tensor cores 371 are freed up to perform other graphics or computational work. Optionally, each ray tracing core 372 can include a traversal unit that performs BVH test operations and / or an intersection unit that performs ray-primitive intersection tests. The intersection unit generates a "hit," "miss," or "multiple hits" response and provides it to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 370 and tensor core 371) are freed up to perform other forms of graphics work. In an optional embodiment described below, a hybrid rasterization / ray tracing scheme is used in which rendering operations are distributed between graphics core 370 and ray tracing core 372.

[0106] The ray tracing core 372 may include hardware support for a ray tracing instruction set, such as Microsoft's DirectX Ray Tracing (DXR), which includes the DispatchRays command, as well as ray generation, nearest hit, any hit, and miss shaders, which enable the assignment of a unique set of shaders and textures to each object. Another ray tracing platform that the ray tracing core 372, graphics core 370, and tensor core 371 can support is the Vulkan API (e.g., version 1.1.85 and later of Vulkan). However, it should be noted that the underlying principles described herein are not limited to any particular ray tracing ISA. In general, the ray tracing core 372, tensor core 371, and graphics core 370 can support a ray tracing instruction set that includes instructions / functions for one or more of ray generation, nearest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exception. More specifically, a preferred embodiment includes ray tracing instructions for performing one or more of the following functions:

[0107] Light Generation —Ray generation instructions can be executed for each pixel, sample, or other user-defined work assignment.

[0108] Recent Hits —A nearest hit instruction may be executed to locate the closest intersection point of a ray with a primitive within the scene.

[0109] Random Hit —Any hit instruction identifies multiple intersections of a ray with primitives within the scene, potentially identifying a new closest intersection point.

[0110] Intersection — The intersection instructions perform ray-primitive intersection tests and output the results.

[0111] Per-primitive bounding box construction —This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

[0112] Missed —Indicates that the ray missed all geometry within the scene or within a specified area of ​​the scene.

[0113] Visit —Indicates the subvolume that the ray will traverse.

[0114] abnormal —Includes various types of exception handlers (e.g., called for various error conditions).

[0115] In one embodiment, the ray tracing core 372 may be adapted to accelerate general computational operations using computational techniques similar to ray intersection testing. A computational framework may be provided that enables shader programs to be compiled into low-level instructions and / or primitives that perform general computational operations via the ray tracing core. Typical computational problems that may benefit from computational operations performed on the ray tracing core 372 include computations involving the propagation of beams, waves, rays, or particles within a coordinate space. Interactions associated with such propagation may be computed relative to geometry or meshes within the coordinate space. For example, computations associated with the propagation of an electromagnetic signal through an environment may be accelerated using instructions or primitives performed via the ray tracing core. Diffraction and reflection of the signal by objects in the environment may be computed as an analogy to direct ray tracing.

[0116] The ray tracing core 372 can also be used to perform calculations that are not directly similar to ray tracing. For example, the ray tracing core 372 can be used to accelerate mesh projection, mesh refinement, and volume sampling calculations. General coordinate space calculations, such as nearest neighbor calculations, can also be performed. For example, by defining a bounding box in the coordinate space around a given point, the set of points near that point can be found. The BVH and ray detection logic within the ray tracing core 372 can then be used to determine the set of intersections within the bounding box. These intersections constitute the origin and the nearest neighbors of the origin. The calculations performed using the ray tracing core 372 can be performed in parallel with the calculations performed on the graphics core 370 and the tensor core 371. The shader compiler can be configured to compile compute shaders or other general graphics processing programs into low-level primitives that can be processed in parallel on the graphics core 370, the tensor core 371, and the ray tracing core 372.

[0117] Technologies for GPU to host processor interconnect

[0118] Figure 4A An exemplary architecture is illustrated in which multiple GPUs 410-413 (e.g., Figure 2A ) is communicatively coupled to a plurality of multi-core processors 405-406 via high-speed links 440A-440D (e.g., a bus, a point-to-point interconnect, etc.). The high-speed links 440A-440D may support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0, PCIe 5.0, PCIe 6.0, and various NVLink and NVLink-C2C (chip-to-chip) interconnect protocols (e.g., NVLink v5). However, the underlying principles described herein are not limited to any particular communication protocol or throughput.

[0119] Two or more of the GPUs 410-413 may be interconnected via high-speed links 442A-442B, which may be implemented using the same or different protocols / links as those used for high-speed links 440A-440D. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 443, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or lower or higher speeds. Alternatively, Figure 4A All communications between the various system components shown in can be implemented using the same protocol / links (e.g., through a common interconnect architecture). However, as previously stated, the underlying principles described herein are not limited to any particular type of interconnect technology.

[0120] Each of multi-core processors 405 and 406 can be communicatively coupled to processor memories 401-402 via memory interconnects 430A-430B, respectively, while each of GPUs 410-413 can be communicatively coupled to GPU memories 420-423, respectively, via GPU memory interconnects 450A-450D. Memory interconnects 430A-430B and 450A-450D can utilize the same or different memory access technologies. By way of example, and not limitation, processor memories 401-402 and GPU memories 420-423 can be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memories, such as 3D XPoint / Optane or Nano-Ram. For example, a portion of the memory may be volatile memory, while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy). The memory subsystem described herein may be compatible with several memory technologies, such as the double data rate version published by the Joint Electronic Device Engineering Council (JEDEC).

[0121] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific processor memories 401-402 and GPU memories 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, while the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0122] Figure 4BThe diagram illustrates additional optional details of the interconnection between processor 407 and graphics accelerator 446. Graphics accelerator 446 may include one or more GPU chips integrated on a line card coupled to processor 407 via high-speed link 440. Alternatively, graphics accelerator 446 may be integrated into the same package or chip as processor 407. Processor 407 includes multiple cores 460A-460D, each having a translation lookaside buffer 461A-461D and one or more caches 462A-462D. These cores may include various other components for executing instructions and processing data, which are not shown to avoid obscuring the underlying principles of the components described herein (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.). Caches 462A-462D may include first-level (L1) and second-level (L2) caches. In addition, one or more shared caches 456 may be included in the cache hierarchy and shared by the set of cores 460A-460D. For example, one embodiment of processor 407 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. Processor 407 is connected to system memory 441, which may include processor memories 401-402.

[0123] Coherence is maintained for data and instructions stored in the various caches 462A-462D, the shared cache(s) 456, and the system memory 441 via inter-core communication over the coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well known to those skilled in the art and are not described in detail herein to avoid obscuring the underlying principles described herein. Proxy circuitry 425 may be provided that communicatively couples the graphics accelerator 446 to the coherence bus 464, thereby allowing the graphics accelerator 446 to participate in the cache coherence protocol as a peer of the core. Specifically, an interface 435 provides connectivity to the proxy circuitry 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and an interface 437 connects the graphics accelerator 446 to the high-speed link 440.

[0124] In one implementation, interface 437 is coupled to accelerator integrated circuit 436, which provides cache management, memory access, context management, and interrupt management services on behalf of graphics processing engines 431, 432, ..., N of graphics accelerator 446. Graphics processing engines 431, 432, ..., N may each comprise a separate graphics processing unit (GPU). Alternatively, graphics processing engines 431, 432, ..., N may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a block image transfer (BLIT) engine. In other words, the graphics accelerator may comprise graphics processing engines 431-432, ..., N of a single GPU, or graphics processing engines 431-432, ..., N may be associated with multiple GPUs integrated on a common package, circuit card, or chip. Graphics processing engines 431-432, ..., N may be configured with any graphics processor or computing accelerator architecture described herein. The work to be performed by the graphics processing engines 431 , 432 may be specified via a work descriptor, which provides an indication to the graphics accelerator 446 of the work to be done.

[0125] The accelerator integrated circuit 436 may include a memory management unit (MMU 439) for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431, 432, ..., N. Data stored in cache 438 and graphics memories 433-434, ..., M may be kept consistent with core caches 462A-462D, shared cache(s) 456, and system memory 441. As previously described, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and graphics memories 433-434, ..., M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 462A-462D, shared cache(s) 456 to cache 438, and receiving updates from cache 438).

[0126] Registers 445 store context data for threads executed by graphics processing engines 431-432, ..., N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 can perform save and restore operations during context switching to save and restore the contexts of various threads (e.g., save a first thread and restore a second thread so that the graphics processing engine can execute the second thread). For example, upon context switching, context management circuitry 448 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer). When returning to the context, it can then restore the register values. Interrupt management circuitry 447 can, for example, receive and process interrupts received from system devices.

[0127] In one implementation, the virtual / effective address from the graphics processing engine is translated by the MMU 439 into a real / physical address in the system memory 441. Optionally, the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerators 446 and / or other accelerator devices. The graphics accelerator 446 can be dedicated to a single application executed on the processor 407, or can be shared between multiple applications. Optionally, a virtualized graphics execution environment is provided in which the resources of the graphics processing engines 431-432, ..., N are shared with multiple applications, virtual machines (VMs), or containers. Resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications, or based on a predetermined partition profile of the graphics accelerator 446. VM and container can be used interchangeably in this article.

[0128] A virtual machine (VM) can be software that runs an operating system and one or more applications. A VM can be defined by specifications, configuration files, virtual disk files, non-volatile random-access memory (NVRAM) setting files, and log files, and is supported by the physical resources of the host computing platform. A VM may include an operating system (OA) or application environment installed on software that simulates dedicated hardware. The end user's experience on a virtual machine is the same as their experience on dedicated hardware. Specialized software called a hypervisor completely simulates the CPU, memory, hard disk, network, and other hardware resources of a PC client or server, allowing virtual machines to share these resources. A hypervisor can simulate multiple isolated virtual hardware platforms, allowing virtual machines to run on the same underlying physical host. Server, VMware ESXi, and other operating systems.

[0129] A container is a software package consisting of an application, configuration, and dependencies so that the application can run reliably from one computing environment to another. Containers can share the operating system installed on a server platform and run as isolated processes. A container is a software package that contains everything the software needs to run, such as system tools, libraries, and settings. Containers are not installed like traditional software programs, which allows them to be isolated from other software and the operating system itself. The isolated nature of containers provides several benefits. First, the software in the container will run the same in different environments. For example, a container containing PHP and MySQL can be installed on Computers and Second, containers provide additional security because the software cannot affect the host operating system. While installed applications can change system settings and modify resources such as the Windows Registry, containers can only modify settings within the container.

[0130] Thus, the accelerator integrated circuit 436 acts as a bridge to the system for the graphics accelerator 446 and provides address translation and system memory caching services. In one embodiment, to facilitate the bridging function, the accelerator integrated circuit 436 may also include shared I / O 497 (e.g., PCIe, USB, or other) and hardware to implement system control of voltage, clocking, performance, cooling, and security. The shared I / O 497 may utilize a separate physical connection or may traverse the high-speed link 440. In addition, the accelerator integrated circuit 436 may provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0131] Because the hardware resources of graphics processing engines 431-432, ..., N are explicitly mapped to the real address space seen by processor 407, any host processor can directly address these resources using valid address values. An optional feature of accelerator integrated circuit 436 is the physical separation of graphics processing engines 431-432, ..., N so that they appear to the system as independent units. In one embodiment, accelerator integrated circuit 436 includes security circuitry 444 that enables configurable cryptographic isolation of data associated with each slice of resources. Different slices can be associated with different security domains, so that data associated with various security domains can be encrypted using different cryptographic keys. In one embodiment, the security domains of graphics accelerator 446 can be integrated into a trusted execution environment supported by processor 407. In one embodiment, secure I / O capabilities can be enabled, which allow each security domain to be presented as a separate trusted I / O device, thereby supporting trusted DMA and MMIO operations.

[0132] One or more graphics memories 433-434, ..., M may be respectively coupled to each of the graphics processing engines 431-432, ..., N. The graphics memories 433-434, ..., M store instructions and data being processed by each of the graphics processing engines 431-432, ..., N. The graphics memories 433-434, ..., M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint / Optane, Samsung Z-NAND, or Nano-Ram.

[0133] To reduce data traffic on high-speed link 440, biasing techniques can be used to ensure that the data stored in graphics memories 433-434, ..., M is the data that will be used most frequently by graphics processing engines 431-432, ..., N, and preferably is not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 431-432, ..., N) in caches 462A-462D, shared cache(s) 456, and system memory 441.

[0134] In an alternative variation, accelerator integrated circuit 436 is integrated within processor 407, and graphics processing engines 431-432, ..., N communicate with accelerator integrated circuit 436 via high-speed link 440 via interface 437 and interface 435 (again, any form of bus, architecture, or interface protocol may be utilized). In this variation, the operations performed by accelerator integrated circuit 436 are the same as those described above.

[0135] The described embodiments may support different programming models, including a dedicated process programming model (without graphics accelerator virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics accelerator 446. In the dedicated process model embodiment, graphics processing engines 431, 432, ..., N may be dedicated to a single application or process under a single operating system. A single application may route other application requests to graphics processing engines 431, 432, ..., N, thereby providing virtualization within a VM / partition. In the dedicated process programming model, graphics processing engines 431, 432, ..., N may be shared by multiple VMs / application partitions. The shared model requires the system hypervisor to virtualize graphics processing engines 431-432, ..., N to allow access by each operating system. For a single-partition system without a hypervisor, graphics processing engines 431-432, ..., N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, ..., N to provide access to each process or application. For the shared programming model, graphics accelerator 446 or individual graphics processing engines 431-432, ..., N use a process handle to select a process element. Process elements can be stored in system memory 441 and addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, ..., N. This can be performed by the host process by calling system software to add the process element to the process element linked list. The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0136] Figure 4C An accelerator integrated slice 490 is illustrated. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 436. An application stores process elements 483 in an address space 482 within system memory 441. Process elements 483 may be stored in response to a GPU call 481 from an application 480 executing on a processor 407. Process elements 483 contain the process state of the application 480. The work descriptor (WD 484) contained in the process element 483 may be a single job requested by the application, or may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application's address space 482.

[0137] Graphics accelerator 446 and / or individual graphics processing engines 431-432, ..., N can be shared by all processes in the system or a subset of processes. For example, the techniques described herein may include infrastructure for setting process state and sending WD 484 to graphics accelerator 446 to start a job in a virtualized environment.

[0138] In one implementation, a dedicated process programming model is implementation-specific. In this model, a single process owns graphics accelerator 446 or an individual graphics processing engine (e.g., graphics processing engine 431). Because graphics accelerator 446 is owned by a single process, when graphics accelerator 446 is assigned, the hypervisor initializes accelerator integrated circuit 436 for the owning partition, and the operating system initializes accelerator integrated circuit 436 for the owning process.

[0139] In operation, a fetch unit 491 in the accelerator integrated slice 490 fetches a WD 484 to be processed. WD 484 includes instructions for work to be performed by one or more graphics processing engines of the graphics accelerator 446. Data from WD 484 may be stored in registers 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 448, as shown. For example, the MMU 439 may include segment / page routing circuitry for accessing segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 may process interrupt events 492 received from the graphics accelerator 446. When executing graphics operations, effective addresses 493 generated by the graphics processing engines 431-432, ..., N are translated into real addresses by the MMU 439.

[0140] Registers 445 may be replicated for each graphics processing engine 431-432, ..., N and / or graphics accelerator 446 and may be initialized by a hypervisor or operating system. Each of these replicated registers may be included in an accelerator integration slice 490. In one embodiment, each graphics processing engine 431-432, ..., N may be presented to a hypervisor 496 as a distinct graphics processor device. Quality of Service (QoS) settings may be configured for clients of a particular graphics processing engine 431-432, ..., N. Cryptographic and physical data isolation between clients of each engine may be achieved via isolated memory access paths and automatic data encryption for each client. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0141] Table 1 - Supervisor Initialization Registers

[0142] 1 Slice Control Register 2 Real address (RA) dispatch process area pointer 3 Permission Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Utilizing Record Pointers 9 Storage Description Register

[0143] Exemplary registers that may be initialized by the operating system are shown in Table 2.

[0144] Table 2 - Operating System Initialization Registers

[0145]

[0146]

[0147] Each WD 484 may be specific to a particular graphics accelerator 446 and / or graphics processing engine 431-432, ..., N. It contains all the information required by the graphics processing engine to do its work, or it may be a pointer to a memory location where the application has set up a command queue for work to be done.

[0148] Figure 4D The diagram shows additional optional details of the sharing model. It includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes the graphics processing engine for the operating system 495.

[0149] The shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics accelerator 446. There are two programming models where the graphics accelerator 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graph-directed sharing.

[0150] In this model, hypervisor 496 owns graphics accelerator 446 and provides its functionality to all operating systems 495. In order for graphics accelerator 446 to support hypervisor 496 virtualization, graphics accelerator 446 must adhere to the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or graphics accelerator 446 must provide a context save and restore mechanism. 2) Graphics accelerator 446 guarantees that application job requests are completed within a specified amount of time, including any translation errors, or graphics accelerator 446 provides the ability to preempt job processing. 3) When operating in a directed-sharing programming model, graphics accelerator 446 must be guaranteed fairness between processes.

[0151] For the directed sharing model, application 480 may be required to make an operating system 495 system call with a graphics accelerator 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). The graphics accelerator 446 type describes the targeted acceleration function of the system call. The graphics accelerator 446 type can be a system-specific value. The WD is formatted specifically for the graphics accelerator 446 and can take the form of a graphics accelerator 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing the work to be performed by the graphics accelerator 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 436 and graphics accelerator 446 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Before placing the AMR into the process element 483, the hypervisor 496 may optionally choose to apply the current Authority Mask Override Register (AMOR) value. CSRP may be one of the registers 445 that contains the effective address of an area in the application's address space 482 where the graphics accelerator 446 saves and restores context state. This pointer is optional if state preservation between jobs is not required, or when a job is preempted. The context save / restore area may be fixed in system memory.

[0152] Upon receiving the system call, the operating system 495 can verify that the application 480 has been registered and has been given permission to use the graphics accelerator 446. The operating system 495 then calls the hypervisor 496 using the information shown in Table 3.

[0153] Table 3 - OS to Hypervisor Call Parameters

[0154] 1 Work Descriptor (WD) 2 The value of the permission mask register (AMR) (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0155] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and been granted permission to use the graphics accelerator 446. The hypervisor 496 then places the process element 483 into a linked list of process elements of the corresponding graphics accelerator 446 type. The process element may include the information shown in Table 4.

[0156] Table 4 - Process Element Information

[0157] 1 Work Descriptor (WD) 2 The permission mask register (AMR) value (may be masked). 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, derived from the supervisor call parameters. 9 Status register (SR) value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilizing Record Pointers 12 Storage Descriptor Register (SDR)

[0158] The hypervisor may initialize the registers 445 of the accelerator integrated slice 490 .

[0159] like Figure 4E As shown in , in an optional implementation, a unified memory is employed that is addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. A first portion of the virtual / effective address space may be allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on and so forth. The entire virtual / effective memory space (sometimes referred to as the effective address space) may thus be distributed across each of processor memories 401-402 and GPU memories 420-423, thereby allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0160] Bias / coherency management circuitry 494A-494E within one or more of the MMUs 439A-439E may be provided that ensures cache coherency between the caches of the host processor (e.g., multi-core processor 405) and the GPUs 410-413 and implements biasing techniques that indicate where specific types of data should be stored. Figure 4E Multiple instances of bias / coherence management circuits 494A-494E are illustrated in , but the bias / coherence circuits may be implemented within an MMU of one or more host processors and / or within the accelerator integrated circuit 436.

[0161] GPU-attached memory 420-423 can be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memory 420-423 as system memory without the burdensome cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead is critical to the execution time of offloaded computations. For example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setup, result access, and GPU computation all play a role in determining the effectiveness of GPU offloading.

[0162] The selection between GPU bias and host processor bias can be driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure (i.e., controlled at the granularity of a memory page), comprising 1 or 2 bits for each GPU-attached memory page. The bias table can be implemented in the stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., to cache frequently used / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0163] In one implementation, the bias table entry associated with each access to the GPU attached memory 420-423 is accessed before the GPU memory is actually accessed, resulting in the following operations. First, local requests from the GPU 410-413 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPU whose pages are found in the host bias are forwarded to the processor (e.g., via a high-speed link as described above). Optionally, requests from the host processor that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests directed to the GPU bias page can be forwarded to the GPU 410-413. The GPU can then convert the page to the host processor bias if it is not currently using the page. The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, by a purely hardware-based mechanism. One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU instructing it to change the bias state and, for some transitions, perform a cache flush in the host. A cache flush is required for transitions from host processor bias to GPU bias, but not for the reverse.

[0164] Cache coherency can be maintained by temporarily making GPU-biased pages uncacheable by the host processor. To access these pages, the host processor can request access from GPU 410, which may or may not immediately grant access, depending on the implementation. Thus, to reduce communication between the host processor and GPU 410, it is beneficial to ensure that GPU-biased pages are requested by the GPU, not the host processor, and vice versa.

[0165] Graphics processing pipeline

[0166] Figure 5 5. A graphics processing pipeline 500 is shown. A graphics multiprocessor, such as Figure 2D Graphics multiprocessor 234 or Figure 2E The graphics multiprocessor 235 can implement the graphics processing pipeline 500. The graphics multiprocessor can be included in a parallel processing subsystem as described herein, such as Figure 2A The parallel processor 200 can be used with Figure 1 The various parallel processing systems may be implemented via one or more instances of parallel processing units as described herein (e.g., Figure 2AThe parallel processing units 202 of FIG. 5 implement the graphics processing pipeline 500. For example, the shader units (e.g., Figure 2C The graphics multiprocessor 234 of the processing cluster may be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines within the processing cluster (e.g., Figure 2A processing cluster 214) and corresponding partition units (e.g., Figure 2A The graphics processing pipeline 500 may also be implemented using one or more dedicated processing units. One or more portions of the graphics processing pipeline 500 may also be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). Optionally, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., a CPU) via a memory interface 528. Figure 2A The parallel processor memory 222 in the memory interface can be Figure 2A The graphics processing pipeline 500 can also be connected to the memory interface 218 via Figure 3 Multi-core cluster 365A implementation in.

[0167] The data assembler 502 is a processing unit that can collect vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data (including vertex attributes) to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, lighting, and transforms vertex data as specified by the vertex shader programs. The vertex processing unit 504 reads data stored in cache, local, or system memory to process vertex data and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0168] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., which are supported by various graphics processing application programming interfaces (APIs).

[0169] The tessellation control processing unit 508 treats input vertices as control points for a geometric patch. The control points are transformed from an input representation of the patch (e.g., the basis of the patch) into a representation suitable for surface estimation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patch. The tessellation factor applies to a single edge and quantifies the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0170] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. The geometry processing unit 516 can be programmed to subdivide the graphics primitive into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0171] The geometry processing unit 516 may be capable of adding or removing elements from the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory to process the geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0172] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs these fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. The fragment / pixel processing unit 524 transforms fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels, which are output to the raster operation unit 526. The fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity, depending on the sampling rate configured for the processing unit.

[0173] Raster operations unit 526 is a processing unit that performs raster operations, including but not limited to stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., Figure 2A Parallel processor memory 222 in, and / or Figure 1 The raster operation unit 526 may be configured to compress z or color data written to memory and decompress z or color data read from memory.

[0174] Machine Learning Overview

[0175] The above architecture can be applied to perform training and reasoning operations using machine learning models. Machine learning has been successful in solving many types of tasks. The calculations generated when training and using machine learning algorithms (e.g., neural networks) are naturally suitable for efficient parallel implementation. Therefore, parallel processors such as general-purpose graphics processing units (GPGPUs) have played an important role in the actual implementation of deep neural networks. Parallel graphics processors with single instruction, multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads try to execute program instructions together synchronously as frequently as possible to improve processing efficiency. The efficiency provided by parallel machine learning algorithm implementations allows the use of high-capacity networks and enables these networks to be trained on larger data sets.

[0176] Machine learning algorithms are algorithms that can learn based on a collection of data. For example, machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output a numerical value given an input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0177] An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged into layers. Typically, a feedforward network topology includes an input layer and an output layer, which are separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating output in the output layer. The network nodes are fully connected to the nodes in the adjacent layers via edges, but there are no edges between nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes in each successive layer of the network based on coefficients ("weights") associated with each edge connecting the layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

[0178] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a set of training data representing the problem being modeled by the network, and adjusting weights until the network model has performance with minimal error for all instances of the training data set. For example, during the supervised learning training process of a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the "correct" labeled output is calculated, and the weights associated with the connections are adjusted to minimize the error as the error signal is backpropagated through the layers of the network. The network is considered "trained" when the error for each output generated from an instance of the training data set is minimized.

[0179] The accuracy of a machine learning algorithm can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can require a significant amount of time on traditional general-purpose processors. Consequently, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are inherently well-suited for parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to exploit the parallel processing hardware within general-purpose graphics processing devices.

[0180] Figure 6 is a generalized diagram of a machine learning software stack 600. A machine learning application 602 is any logic that can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 602 may include training and inference functionality for the neural network and / or specialized software that can be used to train the neural network prior to deployment. The machine learning application 602 may implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation. Example machine learning applications 602 include but are not limited to voice-based virtual assistants, image or facial recognition algorithms, autonomous navigation, and software tools for training machine learning models used by the machine learning application 602.

[0181] Hardware acceleration for machine learning applications 602 can be implemented via a machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations commonly performed by machine learning algorithms. Without the machine learning framework 604, developers of machine learning algorithms would need to create and optimize the main computational logic associated with the machine learning algorithm, and then reoptimize the computational logic as new parallel processors are developed. Instead, machine learning applications can be configured to perform computations using primitives provided by the machine learning framework 604. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning framework 604 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations. Examples of machine learning frameworks 604 include, but are not limited to, TensorFlow, TensorRT, PyTorch, MXNet, Caffe, and other high-level machine learning frameworks.

[0182] The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate input to the compute framework 606. The compute framework 606 can abstract the underlying instructions provided to the GPGPU driver 608 to enable the machine learning framework 604 to utilize hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to have detailed knowledge of the architecture of the GPGPU hardware 610. In addition, the compute framework 606 can implement hardware acceleration for the machine learning framework 604 on various types and generations of GPGPU hardware 610. In one example, the compute framework 606 can include the CUDA compute framework and associated machine learning libraries, such as the CUDA Deep Neural Network (cuDNN) library. The machine learning software stack 600 can also include communication libraries or frameworks to facilitate multi-GPU and multi-node computations.

[0183] GPGPU machine learning acceleration

[0184] Figure 7 A general purpose graphics processing unit (GPGPU 700) is shown, which may be Figure 2A Parallel processor 200 or Figure 1 The general processing unit can be configured to provide support for hardware acceleration of primitives provided by machine learning frameworks to speed up the processing of computational workloads associated with training deep neural networks. In addition, the GPGPU 700 can be directly linked to other instances of the GPGPU to create a multi-GPU cluster to improve the training speed of particular deep neural networks. Primitives are also supported to accelerate inference operations for deployed neural networks.

[0185] GPGPU 700 includes a host interface 702 for connecting to a host processor. Host interface 702 may be a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication architecture. GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute execution threads associated with these commands to a set of processing clusters 706A-706H. The processing clusters 706A-706H share a cache memory 708. The cache memory 708 may act as a higher level cache for the cache memory within the processing clusters 706A-706H. The illustrated processing clusters 706A-706H may be connected to Figure 2A Corresponding to the processing clusters 214A-214N in.

[0186] GPGPU 700 includes memories 714A-714B coupled to processing clusters 706A-706H via a set of memory controllers 712A-712B. Memories 714A-714B may include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random-access memory, such as synchronous graphics random-access memory (SGRAM), including graphics double data rate (GDDR) memory. Memories 714A-714B may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0187] Each of the processing clusters 706A-706H may include a set of graphics multiprocessors, such as Figure 2D Graphics multiprocessor 234, Figure 2E The graphics multiprocessor 235 may include Figure 3 The graphics multiprocessors of the compute clusters include multiple types of integer and floating-point logic units that can perform computational operations at a range of precisions, including those suitable for machine learning computations. For example, at least a subset of the floating-point units in each of the processing clusters 706A-706H can be configured to perform 16-bit or 32-bit floating-point operations, while another different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0188] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary depending on the embodiment. For example, multiple instances of GPGPU 700 communicate via host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 700 to GPU link 710, thereby enabling direct connection to other instances of GPGPU. GPU link 710 can be coupled to a dedicated GPU-to-GPU bridge to enable communication and synchronization between multiple instances of GPGPU 700. Optionally, GPU link 710 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. Multiple instances of GPGPU 700 can be located in separate data processing systems and communicate via network devices accessible via host interface 702. In addition to or in lieu of host interface 702, GPU link 710 can be configured to enable connection to a host processor.

[0189] While the illustrated configuration of GPGPU 700 can be configured to train neural networks, alternative configurations of GPGPU 700 can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 700 includes fewer processing clusters 706A-706H relative to the training configuration. In addition, the memory technology associated with memory 714A-714B may differ between the inference configuration and the training configuration. In one embodiment, the inference configuration of GPGPU 700 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer or floating point dot product instructions, which are commonly used during inference operations of a deployed neural network.

[0190] Figure 8 A multi-GPU computing system 800 is illustrated. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. The host interface switch 804 may be a PCI Express switch device that couples the processor 802 to a PCI Express bus, through which the processor 802 may communicate with the set of GPGPUs 806A-806D. Each of the plurality of GPGPUs 806A-806D may be a Figure 7 GPGPU 700. GPGPUs 806A-806D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links (P2P GPU links 816). The high-speed GPU-to-GPU links may be connected via dedicated GPU links (e.g., Figure 7 806D. P2PGPU link 816 enables direct communication between each of GPGPUs 806A-806D without requiring communication over a host interface bus to which processor 802 is connected. In the event that GPU-to-GPU traffic is directed to the P2P GPU link, the host interface bus remains available for system memory access or communication with other instances of multi-GPU computing system 800, for example, via one or more network devices. Although Figure 8 In the embodiment, GPGPUs 806A-806D are connected to processor 802 via host interface switch 804, but processor 802 may alternatively include direct support for P2P GPU link 816 and connect directly to GPGPUs 806A-806D. In one embodiment, P2P GPU link 816 enables multi-GPU computing system 800 to operate as a single logical GPU.

[0191] Machine Learning Neural Network Implementation

[0192] The computing architecture described herein can be configured to perform a type of parallel processing that is particularly suitable for training and deploying neural networks for machine learning. A neural network can be summarized as a network of functions with graph relationships. As is well known in the art, various types of neural network implementations are used in machine learning. One exemplary type of neural network is a feedforward network, as described above. A second exemplary type of neural network is a convolutional neural network (CNN), and a third exemplary type of neural network is a recurrent neural network (RNN).

[0193] CNNs are specialized feedforward neural networks for processing data with a known grid-like topology, such as image data. CNNs are therefore commonly used for computational vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by the receptive fields present in the retina), and the output of each set of filters is propagated to the nodes in the subsequent layers of the network. The calculation of a CNN involves applying a convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized type of mathematical operation that is performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function to be convolved can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. The input to the convolution layer can be a multidimensional array of data defining the various color components of the input image. The convolution kernel can be a multidimensional array of parameters, where the parameters are adapted by the training process of the neural network.

[0194] RNNs are a family of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data between different parts of the neural network. The architecture of an RNN includes loops that represent the effect of the current value of a variable on its own value at future times, as at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing, due to the variable nature of the data that can constitute language.

[0195] The figures described below illustrate exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of these types of networks, respectively. It will be understood that these descriptions are exemplary and not limiting of any particular embodiment described herein, and that the concepts described can be generally applied to deep neural networks and general machine learning techniques.

[0196] The deep neural networks used in deep learning typically include a front-end network to perform feature recognition, which is coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without requiring manual feature engineering to be performed for the model. Instead, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is generally specialized for the specific task to be performed, and different models will be used to perform different tasks.

[0197] Once a neural network is constructed, a learning model can be applied to the network to train it to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the error in the network's output. Backpropagation of errors is a common method used to train neural networks. An input vector is presented to the network for processing. The network's output is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. The error values ​​are then backpropagated until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then use an algorithm to learn from these errors, such as stochastic gradient descent, to update the weights of the neural network.

[0198] Figures 9A-9B An exemplary convolutional neural network is illustrated. Figure 9A The diagram shows the various layers within a CNN. Figure 9A As shown, an exemplary CNN for modeling image processing may receive an input 902 describing the red, green, and blue (RGB) components of an input image. The input 902 may be processed by a plurality of convolutional layers (e.g., a first convolutional layer 904, a second convolutional layer 906). The outputs from the plurality of convolutional layers may optionally be processed by a fully connected layer 908. The neurons in the fully connected layer have full connections to all activations in the previous layer, as previously described for feedforward networks. The outputs from the fully connected layer 908 may be used to generate output results from the network. Activations within the fully connected layer 908 may be calculated using matrix multiplication rather than convolution. Not all CNN implementations utilize a fully connected layer 908. For example, in some implementations, the second convolutional layer 906 may generate outputs for the CNN.

[0199] The convolutional layers are sparsely connected, unlike traditional neural network configurations found in fully connected layers 908. Traditional neural network layers are fully connected, so that every output unit interacts with every input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the field is input to the nodes of the subsequent layer (rather than the individual state values ​​of each node in the field), as shown in the figure. The kernel associated with the convolutional layer performs the convolution operation, and its output is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0200] Figure 9B The diagram illustrates exemplary computational stages within a convolutional layer of a CNN. Input to a convolutional layer 912 of the CNN may be processed in three stages of a convolutional layer 914. These three stages may include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 may then output data to a subsequent convolutional layer. The final convolutional layer of the network may generate output feature map data or provide input to a fully connected layer to, for example, generate a classification value for the input to the CNN.

[0201] In the convolution stage 916, several convolutions are performed in parallel to produce a set of linear activations. The convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to specific regions in the input, which can be determined as local regions associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the region in the local input to which the neuron is connected. The output from the convolution stage 916 defines a set of linear activations that are processed by subsequent stages of the convolution layer 914.

[0202] The linear activations can be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinear properties of the entire network without affecting the receptive field of the convolutional layer. Several types of nonlinear activation functions can be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) so that the threshold of the activation is zero.

[0203] The pooling stage 920 uses a pooling function that replaces the output of the second convolutional layer 906 using summary statistics of neighboring outputs. The pooling function can be used to introduce translation invariance into the neural network so that small translations of the input do not change the pooled output. Invariance to local translation may be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 920, including maximum pooling, average pooling, and l2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations replace an additional convolution stage with an increased stride relative to the previous convolution stage.

[0204] The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or one of the fully connected layers 908. For example, Figure 9A The first convolutional layer 904 may output to the second convolutional layer 906 , and the second convolutional layer may output to the first layer in the fully connected layer 908 .

[0205] A variant of CNN is the convolutional deep belief network, which has a similar structure to CNN and is trained in a similar way to a deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of random variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining the optimal initial set of weights for the neural network.

[0206] Figures 10A-10B An exemplary language model is illustrated. Figure 10A Illustration of a recurrent neural network

[0207] (RNN 1000). In a recurrent neural network (RNN), the network's previous state influences the output of the network's current state. RNNs can be constructed in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. RNN 1000 can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 that implements a recursive function, a feedback mechanism 1005 that implements a "memory" of the previous state, and an output layer 1006 that outputs the result. RNN 1000 operates based on time steps. The state of the RNN at a given time step is influenced by the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input of the current time step. The initial input (x1) of the first time step can be processed by the hidden layer 1004. The hidden layer 1004 can use the state information determined during the processing of the initial input (x1) to process the second input (x2). A given state can be calculated as s t =f(Ux t +Ws t-1 ), where U and W are parameter matrices. The function f is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or a corrector function f(x) = max(0, x). However, depending on the specific implementation details of the RNN 1000, the specific mathematical function used in the hidden layer 1004 may vary. Acceleration of changes to the RNN network can also be achieved. An example RNN variant is a long short term memory (LSTM) RNN. LSTM RNNs are able to learn long-term dependencies, which may be necessary to process longer language sequences.

[0208] Figure 10B The figure shows the baseline components of the Transformer model 1010. Transformer model 1010 solves the problem of long input sequences in RNN models and achieves higher parallelization. Transformer model 1010 and its variants are used to build language models (LLMs) that perform various tasks such as machine translation, automatic summarization, and dialogue management. Transformer model 1010 can also be configured to perform image generation tasks, such as text-to-image generation.

[0209] Transformer model 1010 includes multiple instances of encoder 1016 and decoder 1026. The encoders are stacked end-to-end, with the final encoder output being routed as input to the multi-head attention layer of each decoder 1026. Input to the bottom-most instance of encoder 1016 is processed by input embedding 1012, which converts the input tokens into vectors that can be processed by encoder 1016. The output dictionary is vectorized by output embedding 1022 before entering the bottom-most instance of decoder 1026. Positional encodings 1014 and 1024 are added to the input and output vectors at the bottom of the encoder 1016 and decoder 1026 stacks. Positional encodings 1014 and 1024 inject information about the relative or absolute position of a token into the sequence of tokens being processed, as Transformer model 1010 cannot naturally encode the order of tokens.

[0210] The encoder 1016 of the transformer model 1010 analyzes the input text and creates several hidden states that preserve the context and meaning of the text data. The encoder 1016 layer forms part of the core of the transformer architecture, although variants of the transformer model 1010 containing only the decoder 1026 are also possible. The encoder 1016 includes two sublayers, a multi-head attention (MHA) sublayer and a feedforward network (FFN) sublayer. The MHA sublayer performs multiple concurrent self-attention operations to calculate attention scores, enabling the transformer model 1010 to weigh the importance and relative relationships of different tokens in the input sequence in a context-aware manner. The FFN sublayer is a position-by-position fully connected feedforward neural network. The output of each sublayer is processed by an addition and normalization (A&N) operation, defined as LayerNorm(x+Sublayer(x)), where the output of the sublayer is added to the input of the sublayer and normalized. In some implementations, the normalization operation can be performed before the sublayer rather than after.

[0211] Decoder 1026 includes three sublayers: a masked MHA sublayer, an MHA sublayer, and an FFN sublayer. The masked MHA sublayer is similar to the MHA layer, but with masking applied to prevent query positions from focusing on keys for future positions. The MHA sublayer of decoder 1026 is similar to the MHA sublayer of the encoder, with an additional input from encoder 1016. The FFN of decoder 1026 is the same as the FFN of encoder 1016. The linear and softmax blocks receive the output of the last instance of decoder 1026 of the decoder stack and generate a probability distribution representing the output probabilities.

[0212] GPU acceleration can also be used for variants of the transformation model 1010 that replace some or all FFN sublayers with sparse mixture of experts (MoE) layers. Each MoE layer includes several experts, each of which is a neural network. The MoE layer can itself be an FFN or an MoE, thus implementing a hierarchical MoE layer.

[0213] Training of the transformer model 1010 can be optimized by using adaptive precision logic that adjusts the precision of calculations applied during training. The adaptive precision logic can attempt to use the smallest possible data types during training without significantly reducing training accuracy. For example, to minimize data loss due to the use of 16-bit, 8-bit, and 4-bit floating point formats, dynamic scaling and projection can be applied during training based on statistical analysis of tensor data generated during training. Various analysis techniques can be used to perform statistical analysis on the tensor data generated during training to determine a set of scaling factors to apply to data blocks, such as the inputs to each layer of the transformer model 1010. For example, absolute minimum and / or maximum values ​​can be used to determine scaling factors that prevent underflow or overflow of low-precision floating point data types.

[0214] Figure 11 The diagram illustrates the training and deployment of a deep neural network. Once a given network is constructed for a task, the neural network is trained using a training dataset 1102. A training framework 1104 is developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning framework 604 can be configured as a training framework 1104. The training framework 1104 can be hooked into the untrained neural network 1106 and enables the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1108. To begin the training process, initial weights can be randomly selected or selected using pre-training of a deep belief network. The training cycle is then executed in a supervised or unsupervised manner.

[0215] Supervised learning is a learning method in which training is performed as a mediated operation, for example, when a training dataset 1102 includes inputs paired with expected outputs for those inputs, or when a training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs to a set of expected or desired outputs. Errors are then propagated back through the system. The training framework 1104 can adjust and control the weights of the untrained neural network 1106. The training framework 1104 can provide tools to monitor the degree to which the untrained neural network 1106 converges toward a model suitable for generating correct answers based on known input data. The training process iterates as the network's weights are adjusted to refine the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically expected level of accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations to generate inference results 1114 based on inputs of new data 1112.

[0216] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training dataset 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the entire dataset. Unsupervised training can be used to generate self-organizing maps, which are trained neural networks 1108 that can perform operations that help reduce the dimensionality of the data. Unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the input dataset that deviate from normal data patterns.

[0217] Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training data set 1102 includes a mixture of labeled and unlabeled data from the same distribution. Incremental learning is a variation of supervised learning in which input data is continuously used to further train the model. Incremental learning enables the trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge instilled into the network during initial training. Whether supervised or unsupervised, the training process for particularly deep neural networks can be too computationally intensive for a single computing node. Instead of using a single computing node, a distributed network of computing nodes can be used to accelerate the training process.

[0218] Figure 12AThe block diagram of illustrates distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training on a neural network. The distributed computing nodes can each include one or more host processors and one or more general processing nodes, such as Figure 7 700 in GPGPU. As shown, distributed learning can be performed using model parallelism 1202, data parallelism 1204, or a combination of model parallelism and data parallelism 1206.

[0219] In model parallelism 1202, different compute nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to extremely large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks where the weights for all layers cannot fit into the memory of a single compute node. In some cases, model parallelism can be particularly useful when performing unsupervised training of large neural networks. Some implementations of model parallelism 1202 may also be referred to as tensor parallelism.

[0220] In data parallelism 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. Although data parallelism may have different schemes, data parallel training schemes all require a technique for combining results and synchronizing model parameters between each node. Exemplary schemes for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of transmitting parameters from nodes to parameter servers, updates to the model are transmitted. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0221] For example, combined model and data parallelism 1206 can be implemented in a distributed system where each compute node includes multiple GPUs. Combined model and data parallelism 1206 can also be referred to as hybrid parallelism. Each node can have a complete instance of the model, with separate GPUs within each node used to train different parts of the model. Distributed training has increased overhead compared to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques for implementing high-bandwidth GPU-to-GPU data transfer and accelerating remote data synchronization. Pipeline parallelism is a variation of combined model and data parallelism 1206 where different nodes contain less than the entire model but more than a single layer of the model. In pipeline parallelism, different groups of layers or sub-models are distributed across different processing nodes. Another variation is expert parallelism, which routes requests for specific experts within the model to different GPUs. Expert parallelism can be used, for example, for MoE transformer models.

[0222] Figure 12B The block diagram of FIG1 illustrates a programmable network interface 1210 and a data processing unit. The programmable network interface 1210 is a programmable network engine that can be used to accelerate network-based computing tasks in a distributed environment. The programmable network interface 1210 can be coupled to a host system via a host interface 1270. The programmable network interface 1210 can be used to accelerate network or storage operations of a CPU or GPU of the host system. The host system can be, for example, a node of a distributed learning system for performing distributed training, such as Figure 12A The host system can also be a data center node in a data center.

[0223] In one embodiment, access to remote storage containing model data may be accelerated via the programmable network interface 1210. For example, the programmable network interface 1210 may be configured to present the remote storage device as a local storage device of the host system. The programmable network interface 1210 may also accelerate remote direct memory access (RDMA) operations performed between a GPU of the host system and a GPU of the remote system. In one embodiment, the programmable network interface 1210 may implement storage functionality such as, but not limited to, NVME-oF. The programmable network interface 1210 may also accelerate encryption, data integrity, compression, and other operations of the remote storage on behalf of the host system, thereby allowing the remote storage to approach the latency of a storage device directly attached to the host system.

[0224] Programmable network interface 1210 can also perform resource allocation and management on behalf of the host system. Storage security operations can be offloaded to programmable network interface 1210 and performed in conjunction with the allocation and management of remote storage resources. Network-based operations that would otherwise be performed by the host system's processor to manage access to remote storage can instead be performed by programmable network interface 1210.

[0225] In one embodiment, network and / or data security operations can be offloaded from the host system to the programmable network interface 1210. Data center security policies for a data center node can be handled by the programmable network interface 1210 rather than by the host system's processor. For example, the programmable network interface 1210 can detect and mitigate attempted network-based attacks (e.g., DDoS) against the host system, preventing the attack from jeopardizing the availability of the host system.

[0226] The programmable network interface 1210 may include a system on a chip (SoC 1220) that executes an operating system via multiple processor cores 1222. The processor cores 1222 may include general-purpose processor (e.g., CPU) cores. In one embodiment, the processor cores 1222 may also include one or more GPU cores. The SoC 1220 may execute instructions stored in a memory device 1240. The storage device 1250 may store local operating system data. The storage device 1250 and the memory device 1240 may also be used to cache remote data for the host system. Network ports 1260A-1260B enable connection to a network or architecture and facilitate network access to the SoC 1220 and the host system via the host interface 1270. The programmable network interface 1210 may also include an I / O interface 1275, such as a USB interface. The I / O interface 1275 may be used to couple external devices to the programmable network interface 1210 or to serve as a debug interface. Programmable network interface 1210 also includes a management interface 1230 that enables software on a host device to manage and configure programmable network interface 1210 and / or SoC 1220. In one embodiment, programmable network interface 1210 may also include one or more accelerators or GPUs 1245 to accept offload of parallel computing tasks from SoC 1220, a host system, or a remote system coupled via network ports 1260A-1260B.

[0227] Demonstration Machine Learning Applications

[0228] Machine learning can be applied to solve various technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The application range of computer vision ranges from reproducing human visual capabilities (e.g., recognizing faces) to creating new categories of visual capabilities. For example, a computer vision application can be configured to recognize sound waves from vibrations induced by objects visible in a video. Parallel processors accelerate machine learning, enabling computer vision applications to be trained using much larger training data sets than were previously feasible, and enabling reasoning systems to be deployed using low-power parallel processors.

[0229] Parallel processors accelerate machine learning for autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0230] Deep neural networks accelerated by parallel processors have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has enabled the replacement of the hidden Markov model (HMM) and Gaussian mixture model (GMM) previously used for ASR.

[0231] Parallel processors accelerating machine learning can also be used to accelerate natural language processing. Automated learning programs can use statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0232] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are generally highly parallel and include optimizations for accelerating multi-GPU single-node training and multi-node and multi-GPU training. Exemplary parallel processors suitable for training include Figure 7 GPGPU 700 and Figure 8 The multi-GPU computing system 800. In contrast, the deployed machine learning platforms generally include low-power parallel processors suitable for products such as cameras, autonomous robots and autonomous vehicles.

[0233] In addition, machine learning techniques can be applied to accelerate or enhance graphics processing activities. For example, a machine learning model can be trained to recognize the output generated by a GPU-accelerated application and generate an enlarged version of the output. This technology can be applied to accelerate the generation of high-resolution images for gaming applications. Various other graphics pipeline activities can benefit from the use of machine learning. For example, a machine learning model can be trained to perform subdivision operations on geometric data to increase the complexity of the geometric model, thereby allowing fine-detail geometry to be automatically generated from relatively low-detail geometry.

[0234] Figure 13 An exemplary reasoning system-on-chip (SOC 1300) suitable for performing reasoning using a trained model is illustrated. SOC 1300 can integrate processing components, including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. GPGPU 1306 can be a GPGPU as described herein, such as GPGPU 700, and multi-core processor 1308 can be a multi-core processor described herein, such as multi-core processors 405-406. SOC 1300 can also include on-chip memory 1305, which can implement a shared on-chip data pool that each processing component can access. The processing components can be optimized for low-power operation so that they can be deployed to various machine learning platforms, including autonomous vehicles and autonomous robots. For example, an implementation of SOC 1300 can be used as part of the main control system of an autonomous vehicle. In the case where SOC 1300 is configured for an autonomous vehicle, the design and configuration of the SOC complies with the relevant functional safety standards of the deployment jurisdiction.

[0235] During operation, the media processor 1302 and the vision processor 1304 can work together to accelerate computer vision operations. The media processor 1302 can implement low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video stream can be written to a buffer in the on-chip memory 1305. The vision processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames using a trained image recognition model. For example, the vision processor 1304 can accelerate convolution operations for a CNN used to perform image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1306.

[0236] The multi-core processor 1308 may include control logic to assist in sequencing and synchronizing data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also function as an application processor to execute software applications that can utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1308. Such software may issue computational workloads directly to the GPGPU 1306, or the computational workloads may be issued to the multi-core processor 1308, which may offload at least a portion of these operations to the GPGPU 1306.

[0237] GPGPU 1306 may include a computational cluster, such as a low-power configuration of processing clusters 706A-706H within GPGPU 700. The computational cluster within GPGPU 1306 may support instructions specifically optimized to perform inference computations on trained neural networks. For example, GPGPU 1306 may support instructions that perform low-precision computations, such as 8-bit and 4-bit integer vector operations.

[0238] Additional System Overview

[0239] Figure 14 is a block diagram of processing system 1400 . Figure 14 Elements having the same or similar names as elements of any other figures herein describe the same elements as those in the other figures, may operate or function in a similar manner thereto, may include the same components, and may be linked to other entities, like those described elsewhere herein, but not limited thereto. Processing system 1400 may be used in a single-processor desktop system, a multi-processor workstation system, or a server system having (one or more) processors 1402 or processor cores 1407. Processing system 1400 may be a processing platform contained within a system-on-a-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device, such as an Internet-of-things (IoT) device having wired or wireless connectivity to a local area network or a wide area network.

[0240] The processing system 1400 may be a system having Figure 1 For example, in different configurations, the processor(s) 1402 or processor core 1407 may be associated with a processor 1402 or processor core 1407. Figure 1 The graphics processor(s) 1408 may correspond to the processor(s) 102 of FIG. Figure 1 The external graphics processor 1418 may be Figure 1One of the additional device(s) 120 .

[0241] The processing system 1400 may include, be coupled with, or be integrated into the following: a server-based gaming platform; a gaming console, including a gaming and media console; a mobile gaming console, a handheld gaming console, or an online gaming console. The processing system 1400 may be part of a mobile phone, a smartphone, a tablet computing device, or a mobile internet-connected device, such as a laptop with low internal storage capacity. The processing system 1400 may also include, be coupled with, or be integrated into the following: a wearable device, such as a smartwatch wearable device; smart glasses or clothing that is enhanced with augmented reality (AR) or virtual reality (VR) features to provide visual, audio, or tactile output to supplement the real-world visual, audio, or tactile experience, or otherwise provide text, audio, graphics, video, holographic images or video, or tactile feedback. The processing system 1400 may include, be part of, or be integrated into a television or set-top box device. Processing system 1400 may include, be coupled to, or be integrated within an autonomous vehicle, such as a bus, a tractor-trailer, an automobile, a motor or electric cycle, an airplane, or a glider (or any combination thereof). The autonomous vehicle may use processing system 1400 to process the environment sensed around the vehicle.

[0242] Processor(s) 1402 may include one or more instances of a processor core 1407 for processing instructions that, when executed, perform operations for system or user software. At least one of the processor cores 1407 may be configured to process a specific instruction set 1409. The instruction set 1409 may facilitate computations using complex instruction set computing (CISC), reduced instruction set computing (RISC), or computations using very long instruction words (VLIW). In one embodiment, one of the processor cores 1407 may process a different instruction set 1409, which may include instructions that facilitate emulation of other instruction sets. The processor cores 1407 may also include other processing devices, such as a digital signal processor (DSP).

[0243] Processor(s) 1402 may include cache memory 1404. Depending on the architecture, processor(s) 1402 may have a single internal cache or multiple levels of internal cache. In some embodiments, cache memory is shared between various components of processor(s) 1402. In some embodiments, processor(s) 1402 also utilizes external caches (e.g., Level 3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared between processor cores 1407 using known cache coherence techniques. A register file 1406 may also be included in processor(s) 1402, and the register file may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of processor(s) 1402.

[0244] The processor(s) 1402 may be coupled to one or more interface buses 1410 to transmit communication signals, such as address, data, or control signals, between the processor(s) 1402 and other components in the processing system 1400. In one of these embodiments, the interface bus(es) 1410 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus, but may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. For example, the processor(s) 1402 may include a memory controller 1416 and a platform controller hub 1430. The memory controller 1416 facilitates communication between memory devices and other components of the processing system 1400, while the platform controller hub 1430 provides connectivity to I / O devices via a local I / O bus.

[0245] Memory device 1420 may be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance for use as process memory. Memory device 1420 may, for example, operate as system memory for processing system 1400 to store data 1422 and instructions 1421 for use by processor(s) 1402 when executing applications or processes. Memory controller 1416 may optionally be coupled to an external graphics processor 1418, which may communicate with graphics processor(s) 1408 in processor(s) 1402 to perform graphics and media operations. In some embodiments, graphics, media, and / or compute operations may be assisted by accelerator 1412, which is a coprocessor that can be configured to perform a specialized set of graphics, media, or compute operations. For example, accelerator 1412 may be a matrix multiplication accelerator for optimizing machine learning or compute operations. The accelerator 1412 may be a ray tracing accelerator that can be used to perform ray tracing operations in conjunction with the graphics processor(s) 1408. The accelerator 1412 may also be an AI accelerator or NPU that is used to accelerate neural network training or inference operations. In one embodiment, the external accelerator 1419 may be used in place of or in conjunction with the accelerator 1412. The accelerator 1412 and / or the external accelerator 1419 may have the same Figure 1 The accelerator device(s) 130 have similar functions.

[0246] A display device 1411 may be provided and connected to the processor(s) 1402. The display device 1411 may be one or more of an internal display device, such as in a mobile electronic device or laptop, or an external display device attached via a display interface (e.g., DisplayPort, etc.). The display device 1411 may be a head mounted display (HMD), such as a stereoscopic display device, for use in VR or AR applications.

[0247] The platform controller hub 1430 can enable peripheral devices to connect to the memory device 1420 and the processor(s) 1402 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 1446, a network controller 1434, a firmware interface 1428, a wireless transceiver 1426, a touch sensor 1425, and a data storage device 1424 (e.g., non-volatile memory, volatile memory, hard drive, flash memory, NAND, 3D NAND, 3D XPoint / Optane, etc.). The data storage device 1424 can be connected via a storage interface (e.g., SATA) or via a peripheral bus (e.g., PCI, PCI Express). The touch sensor 1425 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 1426 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, 5G, or Long-Term Evolution (LTE) transceiver. The firmware interface 1428 enables communication with the system firmware and may be, for example, a unified extensible firmware interface (UEFI). A network controller 1434 may enable network connectivity to a wired network. In some embodiments, a high-performance network controller (not shown) is coupled to the interface bus(es) 1410. An audio controller 1446 may be a multi-channel high-definition audio controller. In some of these embodiments, the processing system 1400 includes an optional legacy I / O controller 1440 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. The platform controller hub 1430 may also be connected to one or more Universal Serial Bus (USB) controllers 1442 to connect to input devices, such as a keyboard and mouse 1443 combination, a camera 1444, or other USB input devices.

[0248] It will be appreciated that the processing system 1400 shown is exemplary and not limiting, as other types of data processing systems in different configurations may also be used. For example, instances of the memory controller 1416 and the platform controller hub 1430 may be integrated into a discrete external graphics processor, such as the external graphics processor 1418. The platform controller hub 1430 and / or the memory controller 1416 may be external to the processor(s) 1402. For example, the memory controller 1416 and the platform controller hub 1430 may be external to the processing system 1400 and configured as a memory controller hub and a peripheral controller hub in a system chipset that communicate with the processor(s) 1402.

[0249] For example, a circuit board ("sled") can be used on which components such as the CPU, memory, and other components are placed and which is designed to improve thermal performance. Processing components, such as processors, can be located on the top side of the sled, while proximal memory, such as DIMMs, are located on the bottom side of the sled. Because this design provides enhanced airflow, the components can operate at higher frequencies and power levels than in a typical system, thereby improving performance. In addition, the sled is configured to blindly mate with power and data communication cables in the rack, thereby enhancing its ability to be quickly removed, upgraded, reinstalled, and / or replaced. Similarly, individual components located on the sled, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to the increased spacing between them. In an illustrative embodiment, these components also include hardware authentication features to prove their authenticity.

[0250] The data center can utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and Omni-Path. The shelves can be coupled to the switches via optical fibers that provide higher bandwidth and lower latency than typical twisted pair cables (e.g., Category 5, Category 5e, Category 6, Category 7, Category 8, etc.). Due to the high-bandwidth, low-latency interconnect and network architecture, the data center can pool resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and / or artificial intelligence accelerators, etc.), and physically disaggregated data storage drives and provide them to computing resources (e.g., processors) as needed, enabling the computing resources to access the pooled resources as if the resources were local.

[0251] The power supply or power source can provide voltage and / or current to the processing system 1400 or any component or system described herein. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter to be plugged into a wall socket. This AC power can be a renewable energy (e.g., solar) power source. In one example, the power supply includes a DC power source, such as an external AC to DC converter. The power supply or power supply may also include wireless charging hardware to charge via proximity to a charging field. The power supply may include an internal battery, an AC supply, a motion-based power supply, a solar power supply, or a fuel cell source.

[0252] Figures 15A-15C A computing system and a graphics processor are illustrated. Figures 15A-15C Elements having the same or similar names as elements of any other figures herein describe the same elements as those in the other figures, may operate or function in a similar manner thereto, may include the same components, and may be linked to other entities like those described elsewhere herein, but are not limited thereto.

[0253] Figure 15A 1402. FIGURE 1403 is a block diagram of a processor 1500, which may be a variant of one of the processor(s) 1402 and may be used in place of one of them. Therefore, any feature disclosed herein in conjunction with processor 1500 also discloses the corresponding combination with processor(s) 1402, but is not limited thereto. Processor 1500 may have one or more processor cores 1502A-1502N, at least one memory controller 1514, and a graphics processor 1508. Graphics processor 1508 may be integrated within processor 1500, within a system chipset, or coupled via a system bus. Processor 1500 may include additional cores, up to and including additional core 1502N, represented by a dashed box. Each of processor cores 1502A-1502N includes one or more internal cache units 1504A-1504N. In some embodiments, each processor core 1502A-1502N may also have access to one or more shared cache units 1506. Internal cache units 1504A-1504N and shared cache unit(s) 1506 represent a cache memory hierarchy within processor 1500. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, with the highest level of cache before external memory being categorized as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units (e.g., shared cache unit(s) 1506 and internal cache unit(s) 1504A-1504N).

[0254] Processor 1500 may also include one or more bus controller units 1516 and a system agent core 1510. The one or more bus controller units 1516 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. The one or more bus controller units 1516 may also manage one or more memory buses to various external memory devices (not shown). The system agent core 1510 provides management functions for various processor components and may include at least one memory controller 1514.

[0255] For example, one or more of the processor cores 1502A-1502N may include support for simultaneous multithreading. The system agent core 1510 includes components for coordinating and operating the cores 1502A-1502N during multithreaded processing. The system agent core 1510 may also include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1502A-1502N and the graphics processor 1508.

[0256] Processor 1500 may also include a graphics processor 1508 for performing graphics processing operations. In some of these embodiments, graphics processor 1508 is coupled to one or more shared cache units 1506 and a system agent core 1510 (including at least one memory controller 1514). System agent core 1510 may also include a display controller 1511 to drive the graphics processor output to one or more coupled displays. Display controller 1511 may also be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within graphics processor 1508.

[0257] A ring or mesh-based interconnect 1512 may be used to couple the internal components of the processor 1500. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some of these embodiments having a ring or mesh-based interconnect 1512, the graphics processor 1508 is coupled to the ring or mesh-based interconnect 1512 via an I / O link 1513.

[0258] Exemplary I / O links 1513 represent at least one of a variety of I / O interconnects, including on-package I / O interconnects, that facilitate communication between various processor components and high-performance memory modules 1518, such as embedded DRAM modules (eDRAM) or high-bandwidth memory (HBM) modules. Optionally, when a DRAM memory system is also present, each of the processor cores 1502A-1502N and the graphics processor 1508 can use the high-performance memory modules 1518 as a unified memory and / or shared last-level cache. Optionally, one or more accelerators 1515, such as an NPU, can also be included within the processor 1500 to accelerate certain neural network operations. The NPU can enable lower-power inference operations relative to using the graphics processor 1508, or can operate in conjunction with the graphics processor 1508 to achieve higher inference performance than using the graphics processor 1508 alone. In one embodiment, an NPU within one or more accelerators 1515 may include matrix or tensor acceleration logic and may be used to implement at least some of the computational operations described herein as being implementable via graphics processor 1508 .

[0259] The processor cores 1502A-1502N can be, for example, homogeneous cores that execute the same instruction set architecture. Alternatively, the processor cores 1502A-1502N can be heterogeneous with respect to instruction set architecture (ISA), wherein one or more of the processor cores 1502A-1502N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or a different instruction set. The processor cores 1502A-1502N can be heterogeneous with respect to microarchitecture, wherein one or more cores having relatively higher power consumption are coupled with one or more power cores having lower power consumption. As another example, the processor cores 1502A-1502N can be heterogeneous with respect to computing power. Furthermore, the processor 1500 can be implemented on one or more chips or corelets, or as a SoC integrated circuit having the components shown in the figure in addition to other components. The SoC integrated circuit can be implemented using multiple corelets.

[0260] Figure 15B is a block diagram of the hardware logic of the graphics processor core block 1519 according to some embodiments described herein. In some embodiments, Figure 15BElements having the same reference numerals (or names) as elements of any other figure herein may operate or function in a manner similar to that described elsewhere herein. In one embodiment, the graphics processor core block 1519 is an example of a partition of the graphics processor. The graphics processor core block 1519 may be included in Figure 15A 1521F, each comprising modules of fixed-function logic and general-purpose programmable logic. The graphics processor core block 1519 further includes a shared / cache memory 1536 accessible to all graphics cores 1521A-1521F, a rasterizer logic 1537, and additional fixed-function logic 1538.

[0261] In some embodiments, functional block 1530 includes a geometry / fixed function pipeline 1531 that can be shared by all graphics cores in graphics processor core block 1519. In various embodiments, geometry / fixed function pipeline 1531 includes a 3D geometry pipeline, a video front-end unit, a thread spawner, a global thread dispatcher, and a unified return buffer manager that manages the unified return buffer. In one embodiment, functional block 1530 also includes a graphics SoC interface 1532, a graphics microcontroller 1533, and a media pipeline 1534. Graphics SoC interface 1532 provides an interface between graphics processor core block 1519 and other core blocks within a graphics processor or compute accelerator SoC. Graphics microcontroller 1533 is a programmable subprocessor that can be configured to manage various functions of graphics processor core block 1519, including thread dispatching, scheduling, and preemption. Media pipeline 1534 includes logic to facilitate decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. The media pipeline 1534 implements media operations via requests to computational or sampling logic within the graphics cores 1521-1521F. One or more pixel backends 1535 may also be included within the functional block 1530. The one or more pixel backends 1535 include cache memory for storing pixel color values ​​and may perform blending operations and lossless color compression of rendered pixel data.

[0262] In one embodiment, graphics SoC interface 1532 enables graphics processor core block 1519 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, or a system host CPU coupled to the SoC via a peripheral interface. Graphics SoC interface 1532 also enables communication with off-chip memory hierarchy elements, such as shared last-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. Graphics SoC interface 1532 may also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable the use and / or implementation of global memory atomics that can be shared between graphics processor core block 1519 and the CPU within the SoC. Graphics SoC interface 1532 may also enable power management control for graphics processor core block 1519 and enable interfacing between the clock domain of graphics processor core block 1519 and other clock domains within the SoC. In one embodiment, graphics SoC interface 1532 enables reception of command buffers from the command stream processor and the global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. When media operations are to be performed, commands and instructions may be dispatched to the media pipeline 1534, and when graphics processing operations are to be performed, commands and instructions may be dispatched to the geometry and fixed function pipeline 1531. When compute operations are to be performed, compute dispatch logic may dispatch commands to the graphics cores 1521A-1521F, bypassing the geometry and media pipelines.

[0263] Graphics microcontroller 1533 can be configured to perform various scheduling and management tasks for graphics processor core block 1519. In one embodiment, graphics microcontroller 1533 can perform graphics and / or compute workload scheduling for the various vector engines 1522A-1522F, 1524A-1524F, and matrix engines 1523A-1523F, 1525A-1525F within graphics cores 1521A-1521F. In this scheduling model, host software executing on a CPU core of the SoC containing graphics processor core block 1519 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. Scheduling operations include determining the next workload to run, submitting the workload to the command stream processor, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In one embodiment, the graphics microcontroller 1533 may also facilitate a low power or idle state for the graphics processor core block 1519, providing the graphics processor core block 1519 with the ability to save and restore registers within the graphics processor core block 1519 during low power state transitions without relying on the operating system and / or graphics driver software on the system.

[0264] The graphics processor core block 1519 may have more or fewer graphics cores 1521A-1521F than shown, up to a maximum of N modular graphics cores. For each set of N graphics cores, the graphics processor core block 1519 may also include shared / cache memory 1536 (which may be configured as shared memory or cache memory), rasterizer logic 1537, and additional fixed-function logic 1538 to accelerate various graphics and compute processing operations.

[0265] Within each graphics core 1521A-1521F is a set of execution resources that can be used to execute graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. Graphics cores 1521A-1521F include multiple vector engines 1522A-1522F, 1524A-1524F, matrix acceleration units 1523A-1523F, 1525A-1525D, cache / shared local memory (SLM), samplers 1526A-1526F, and ray tracing units 1527A-1527F.

[0266] The vector engines 1522A-1522F, 1524A-1524F are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations to service graphics, media, or compute operations, including graphics, media, or compute / GPGPU programs. The vector engines 1522A-1522F, 1524A-1524F can operate with variable vector widths using SIMD, SIMT, or SIMT+SIMD execution modes. The matrix acceleration units 1523A-1523F, 1525A-1525D include matrix-matrix and matrix-vector acceleration logic that improves the performance of matrix operations, particularly low-precision and mixed-precision (e.g., INT8, FP16, BF16, FP8, FP4) matrix operations for machine learning. In one embodiment, the matrix acceleration units 1523A-1523F, 1525A-1525D support the microscale (MX) format. In one embodiment, each of the matrix acceleration units 1523A-1523F, 1525A-1525D includes one or more systolic arrays of processing elements that can perform concurrent matrix multiplication or dot product operations on matrix elements.

[0267] Samplers 1526A-1526F can read media or texture data into memory and can sample the data differently based on the configured sampler state and the texture / media format being read. Threads executing on vector engines 1522A-1522F, 1524A-1524F or matrix acceleration units 1523A-1523F, 1525A-1525D can utilize caches / SLMs 1528A-1528F within each of graphics cores 1521A-1521F. Caches / SLMs 1528A-1528F can be configured as cache memory or as a pool of shared memory local to each of the respective graphics cores 1521A-1521F. The ray tracing units 1527A-1527F within the graphics cores 1521A-1521F include ray traversal / intersection circuitry for performing ray traversals using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volumes. In one embodiment, the ray tracing units 1527A-1527F include circuitry for performing depth testing and culling (e.g., using a depth buffer or similar arrangement). In one implementation, the ray tracing units 1527A-1527F perform traversal and intersection operations in conjunction with image denoising, at least a portion of which may be performed using associated matrix acceleration units 1523A-1523F, 1525A-1525D.

[0268] Figure 15C 15 is a block diagram of a general-purpose graphics processing unit (GPGPU 1570) that can be configured as a graphics processor (e.g., graphics processor 1508) and / or a computing accelerator according to embodiments described herein. GPGPU 1570 can be interconnected with a host processor (e.g., one or more CPUs 1546) and memory 1571, 1572 via one or more system and / or memory buses. Memory 1571 can be system memory that can be shared with one or more CPUs 1546, while memory 1572 is device memory dedicated to GPGPU 1570. For example, components within GPGPU 1570 and memory 1572 can be mapped to memory addresses accessible to one or more CPUs 1546. Access to memories 1571 and 1572 can be facilitated via memory controller 1568. Memory controller 1568 can include an internal direct memory access (DMA) controller 1569, or can include logic for performing operations that would otherwise be performed by a DMA controller. In one embodiment, at least one of the one or more CPUs 1546 may include one or more accelerators 1545, including but not limited to a neural network accelerator.

[0269] GPGPU 1570 includes multiple global cache memories, including an L2 cache 1553, an L1 cache 1554, an instruction cache 1555, and a shared memory 1556, at least a portion of which may also be partitioned as cache memory. GPGPU 1570 also includes multiple compute units 1560A-1560N. Each compute unit 1560A-1560N includes a set of vector registers 1561, a scalar register 1562, a vector logic unit 1563, a scalar logic unit 1564, and a scheduler 1584. Compute units 1560A-1560N may also include local shared memory 1565 and local cache memory 1566. Compute units 1560A-1560N may be coupled to a constant cache 1567, which may be used to store constant data, i.e., data that does not change during the execution of a kernel or shader program executed on GPGPU 1570. The constant cache 1567 can be a scalar data cache, and the cached data can be directly fetched into the scalar register 1562. In one embodiment, the compute units 1560A-1560N further include at least one matrix unit 1580 to accelerate matrix, tensor, or artificial intelligence operations, and at least one ray tracing unit (RT unit 1582) to accelerate ray tracing operations. The at least one matrix unit 1580 and the RT unit 1582 can include functionality similar to the other matrix / tensor accelerators and ray tracing accelerators described herein.

[0270] During operation, one or more CPUs 1546 may write commands to registers or memory mapped into the accessible address space of GPGPU 1570. Command processor 1557 may read commands from registers or memory and determine how to process these commands within GPGPU 1570. Thread dispatcher 1558 may then be used to dispatch threads to compute units 1560A-1560N to execute these commands. Each compute unit 1560A-1560N may execute threads independently of other compute units. In addition, each compute unit 1560A-1560N may be independently configured for conditional computation and may conditionally output the results of the computation to memory. When the submitted commands are completed, command processor 1557 may interrupt one or more CPUs 1546.

[0271] Figure 161 is a block diagram of a graphics processor 1600, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores or other semiconductor devices (such as, but not limited to, memory devices or network interfaces). Elements of graphics processor 1600 that have the same or similar names as elements of any other figures herein describe the same elements in the other figures, may operate or function in a similar manner thereto, may include the same components, and may be linked to other entities, like those described elsewhere herein, but not limited thereto. For example, graphics processor 1600 may be a variant of graphics processor 1508 and may be used in place of graphics processor 1508. The graphics processor may communicate with registers on the graphics processor and commands placed in processor memory via a memory-mapped I / O interface. Graphics processor 1600 may include a memory interface 1614 to access local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0272] Graphics processor 1600 may include a display controller 1602 to drive display output data to a display device 1618. Display controller 1602 includes hardware for displaying multiple layers of video or user interface elements and composing one or more overlay planes. Display device 1618 may be an internal or external display device. In one embodiment, display device 1618 is a head-mounted display device, such as a VR or AR display device. The graphics processor 1600 may include a video codec engine 1606 for encoding media to one or more media coding formats, decoding media from one or more media coding formats, or transcoding media between one or more media coding formats, including but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9, ​​and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG and Motion JPEG (MJPEG) formats.

[0273] Graphics processor 1600 may include a block image transfer (BLIT) engine 1603 to perform two-dimensional (2D) rasterization operations, such as bit-boundary block transfers, or may use one or more components of a graphics processing engine (GPE 1610) to perform 2D graphics operations. GPE 1610 may include a 3D pipeline 1612 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1612 includes programmable and fixed functional elements that perform various tasks within the element and / or spawn execution threads to a 3D / media subsystem 1615. While 3D pipeline 1612 may be used to perform media operations, GPE 1610 may also include a media pipeline 1616 specifically for performing media operations, such as image or video decoding, encoding, post-processing, and enhancement. The media pipeline 1616 may include fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, in place of or on behalf of the video codec engine 1606. The media pipeline 1616 may also include a thread spawning unit to spawn threads for execution on the 3D / media subsystem 1615. The spawned threads perform calculations for the media operations on one or more graphics execution units included in the 3D / media subsystem 1615.

[0274] Figure 17A Graphics processor 1720 is shown, which is Figure 161720. The graphics processor 1720 is a variant of the graphics processor 1600 and can be used in place of the graphics processor 1600, and vice versa. Therefore, any feature disclosed herein in conjunction with the graphics processor 1600 also discloses the corresponding combination with the graphics processor 1720, but is not limited thereto. According to the embodiments described herein, the graphics processor 1720 has a tiled architecture. The graphics processor 1720 may include a graphics processing engine cluster 1722 having multiple graphics processing engines within multiple graphics engine tiles. Each graphics engine tile 1710A-1710D may be interconnected via a set of tile interconnects 1723A-1723F. Each graphics engine tile 1710A-1710D may also be connected to a memory module or memory device 1726A-1726D via a memory interconnect 1725A-1725D. The memory devices 1726A-1726D may use any graphics memory technology. For example, the memory devices 1726A-1726D may be graphics double data rate (GDDR) memory. The memory devices 1726A-1726D may be high bandwidth memory (HBM) modules that may be on-die with the respective graphics engine tiles 1710A-1710D. The memory devices 1726A-1726D may be stacked memory devices that may be stacked on top of their respective graphics engine tiles 1710A-1710D. Each graphics engine tile 1710A-1710D and associated memory devices 1726A-1726D may be on separate die that are bonded to a base die or base substrate, such as Figures 25A-25B As described in further detail in .

[0275] The graphics processor 1720 may be configured with a non-uniform memory access (NUMA) system in which memory devices 1726A-1726D are coupled to associated graphics engine tiles 1710A-1710D. A given memory device may be accessed by a graphics engine tile other than the tile to which it is directly connected. However, access latency to the memory devices 1726A-1726D may be lowest when accessing the local tile. In one embodiment, a cache coherent NUMA (ccNUMA) system is enabled that uses tile interconnects 1723A-1723F to enable communication between cache controllers within the graphics engine tiles 1710A-1710D to maintain a consistent memory image when more than one cache stores the same memory location.

[0276] The graphics processing engine cluster 1722 can be connected to an interconnect fabric 1724, which can be interconnected with an on-chip or on-package architecture. In one embodiment, the interconnect fabric 1724 includes a network processor, a network on a chip (NoC), or other switching processor to enable the interconnect fabric 1724 to function as a packet switching interconnect fabric for exchanging data packets between components of the graphics processor 1720. The interconnect fabric 1724 can enable communication between the graphics engine tiles 1710A-1710D and components such as the video codec engine 1706 and one or more copy engines 1704. The one or more copy engines 1704 can be used to move data to, from, and between memory devices 1726A-1726D and memory external to the graphics processor 1720 (e.g., system memory). The interconnect fabric 1724 can also be used to interconnect the graphics engine tiles 1710A-1710D. The graphics processor 1720 may optionally include a display controller 1702 to enable connection to a display device 1718. The graphics processor may also be configured as a graphics or computing accelerator. In an accelerator configuration, the display controller 1702 and the display device 1718 may be omitted.

[0277] The graphics processor 1720 can be connected to the host system via a host interface 1728. The host interface 1728 enables communication between the graphics processor 1720, system memory, and / or other system components. The host interface 1728 can be, for example, a PCI Express bus or other type of host system interface. For example, the host interface 1728 can be an NVLink or NVSwitch interface. The host interface 1728 and the interconnect architecture 1724 can cooperate to enable multiple instances of the graphics processor 1720 to act as a single logical device. The cooperation between the host interface 1728 and the interconnect architecture 1724 can also enable individual graphics engine tiles 1710A-1710D to be presented to the host system as different logical graphics devices.

[0278] Figure 17B The computing accelerator 1730 is shown in accordance with an embodiment described herein. The computing accelerator 1730 may include Figure 17BThe compute engine cluster 1732 may include a set of compute engine tiles 1740A-1740D that include execution logic optimized for parallel or vector-based general-purpose compute operations. In one embodiment, the compute accelerator 1730 may be configured as an AI accelerator or an NPU. In such an embodiment, the execution logic of the compute engine tiles 1740A-1740D may be primarily targeted at matrix or tensor operations and include the tensor cores or matrix engines described herein. The compute engine tiles 1740A-1740D may not include fixed-function graphics processing logic, but in some embodiments, one or more of the compute engine tiles 1740A-1740D may include logic to perform media acceleration. The compute engine tiles 1740A-1740D may be connected to memory devices 1726A-1726D via memory interconnects 1725A-1725D. The memory devices 1726A-1726D and memory interconnects 1725A-1725D may employ similar technology as the graphics processor 1720, or may be different. The compute engine tiles 1740A-1740D may also be interconnected via a set of tile interconnects 1723A-1723F, and may be connected to and / or interconnected through the interconnect fabric 1724. In one embodiment, the compute accelerator 1730 includes a large L3 cache 1736 that may be configured as a device-wide cache. The compute accelerator 1730 may also be connected to the host processor and memory via the host interface 1728 in the same manner as the host interface 1728. Figure 17B Similar to the graphics processor 1720.

[0279] The computing accelerator 1730 may also include an integrated network interface 1742. In one embodiment, the integrated network interface 1742 includes a network processor and controller logic that enables the computing engine cluster 1732 to communicate via the physical layer interconnect 1744 without requiring data to traverse the host system's memory. In one embodiment, one of the computing engine tiles 1740A-1740D is replaced by the network processor logic, and data sent or received via the physical layer interconnect 1744 can be directly transferred to or from the memory devices 1726A-1726D. Multiple instances of the computing accelerator 1730 can be connected into a single logical device via the physical layer interconnect 1744. Alternatively, the various computing engine tiles 1740A-1740D can be presented as different network-accessible computing accelerator devices.

[0280] Graphics processing resources

[0281] Figures 18A-18C Execution logic including an array of processing elements employed in a graphics processor is illustrated according to embodiments described herein. Figure 18AA graphics core cluster is illustrated according to one embodiment. Figure 18B Illustrated is a vector engine of a graphics core according to one embodiment. Figure 18C A matrix engine of a graphics core is illustrated according to one embodiment. Figures 18A-18C Elements having the same reference numerals as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Figure 15B Consider the context of the graphics processor core block 1519 Figures 18A-18C In one embodiment, Figures 18A-18C The elements have Figure 15A Graphics processor 1508 or Figure 15C The equivalent components of the GPGPU 1570 have similar functions.

[0282] like Figure 18A As shown, in one embodiment, graphics core cluster 1800 includes graphics processor core block 1519, which may include any number of graphics cores (e.g., graphics core 1815A, graphics core 1815B, up to graphics core 1815N). Multiple instances of graphics processor core block 1519 may be included. In one embodiment, the elements of graphics cores 1815A-1815N have the same Figure 15B 1802N, a matrix engine 1803A-1803N, a memory load / store unit 1804A-1804N, an instruction cache 1805A-1805N, a data cache / shared local memory 1806A-1806N, a ray tracing unit 1808A-1808N, and a sampler 1810A-1810N. The circuitry of graphics cores 1815A-1815N may also include fixed-function logic 1812A-1812N. The number of vector engines 1802A-1802N and matrix engines 1803A-1803N within a design of graphics cores 1815A-1815N may vary based on the workload, performance, and power targets of the design.

[0283] Referring to graphics core 1815A, vector engine 1802A and matrix engine 1803A can be configured to perform parallel computation operations on data in various integer and floating-point data formats based on instructions associated with a shader program. Each vector engine 1802A and matrix engine 1803A can act as a programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. Vector engine 1802A and matrix engine 1803A support processing variable-width vectors with various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. Input data elements can be stored in registers as packed data types, and vector engine 1802A and matrix engine 1803A can process various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the bits of the vector are stored in registers, and the vector is processed as four separate 64-bit packed data elements (quadword (QW) sized data elements), eight separate 32-bit packed data elements (doubleword (DW) sized data elements), sixteen separate 16-bit packed data elements (word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible. In one embodiment, the vector engine 1802A and the matrix engine 1803A can also be configured for SIMT operations on warps or thread groups of various sizes (e.g., 8, 16, or 32 threads).

[0284] Continuing with the graphics core 1815A, the memory load / store unit 1804A services memory access requests issued by the vector engine 1802A, the matrix engine 1803A, and / or other components of the graphics core 1815A that are capable of accessing memory. Memory access requests may be processed by the memory load / store unit 1804A to load the requested data from a cache or memory into a register file associated with the vector engine 1802A and / or the matrix engine 1803A, or to store the requested data from the register file into a cache or memory. The memory load / store unit 1804A may also perform prefetch operations. Also refer to Figure 19 In one embodiment, the memory load / store unit 1804A is configured to provide SIMT scatter / gather prefetches or block prefetches for data stored in the memory 1910 from memories local to other tiles or from system memory via the tile interconnect 1908. Prefetches can be performed to a specific L1 cache (e.g., data cache / shared local memory 1806A), the L2 cache 1904, or the L3 cache 1906. In one embodiment, prefetches to the L3 cache 1906 automatically cause the data to be stored in the L2 cache 1904.

[0285] Instruction cache 1805A stores instructions to be executed by graphics core 1815A. In one embodiment, graphics core 1815A also includes instruction fetch and prefetch circuitry that fetches or prefetches instructions into instruction cache 1805A. Graphics core 1815A also includes instruction decode logic for decoding instructions within instruction cache 1805A. Data cache / shared local memory 1806A can be configured as a data cache managed by a cache controller that implements a cache replacement policy, and / or configured as explicitly managed shared memory. Ray tracing unit 1808A includes circuitry for accelerating ray tracing operations. Sampler 1810A provides texture sampling for 3D operations and media sampling for media operations. Fixed function logic 1812A includes fixed function circuitry shared between various instances of vector engine 1802A and matrix engine 1803A. Graphics cores 1815B-1815N can operate in a manner similar to graphics core 1815A.

[0286] The functionality of the instruction caches 1805A-1805N, data cache / shared local memory 1806A-1806N, ray tracing units 1808A-1808N, samplers 1810A-1810N, and fixed function logic 1812A-1812N corresponds to the equivalent functionality in the graphics processor architecture described herein. For example, the instruction caches 1805A-1805N may operate in a manner similar to that described herein. Figure 15C The data cache / shared local memory 1806A-1806N, ray tracing units 1808A-1808N and samplers 1810A-1810N can operate in a similar manner to the instruction cache 1555 of FIG. Figure 15B The cache / SLM 1528A-1528F, ray tracing units 1527A-1527F and samplers 1526A-1526F are similar. The fixed function logic 1812A-1812N may include Figure 15B In one embodiment, ray tracing units 1808A-1808N include elements of the geometry / fixed function pipeline 1531 and / or additional fixed function logic 1538. Figure 3 The ray tracing core 372 performs circuitry for ray tracing acceleration operations.

[0287] like Figure 18BAs shown, in one embodiment, vector engine 1802 includes an instruction fetch unit 1837, a general register file array (GRF 1824), an architectural register file array (ARF 1826), a thread arbiter 1822, an issue unit 1830, a branch unit 1832, a SIMD FPU 1834, and, in one embodiment, a SIMD ALU 1835. GRF 1824 and ARF 1826 include a set of general register files and architectural register files associated with each hardware thread that may be active in vector engine 1802. In one embodiment, per-thread architectural state is maintained in ARF 1826, while data used during thread execution is stored in GRF 1824. The execution state of each thread, including the instruction pointer for each thread, can be stored in thread-specific registers in ARF 1826. Register renaming can be used to dynamically allocate registers to hardware threads.

[0288] In one embodiment, vector engine 1802 employs an architecture that combines simultaneous multi-threading (SMT) and fine-grained interleaved multi-threading (IMT). This architecture features a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per graphics core, where graphics core resources are partitioned into logical areas for executing multiple simultaneous threads. The number of logical threads that vector engine 1802 can execute is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0289] In one embodiment, vector engine 1802 can collectively issue multiple instructions, each of which can be a different instruction. Thread arbiter 1822 can dispatch instructions to one of issue unit 1830, branch unit 1832, or SIMD FPU 1834 for execution. Each execution thread can access 128 general-purpose registers within GRF 1824, each of which can store 32 bytes, which can be accessed as variable-width vectors of 32-bit data elements. In one embodiment, each thread can access 4K bytes within GRF 1824, but embodiments are not limited in this regard; more or fewer register resources may be provided in other embodiments. In one embodiment, vector engine 1802 is partitioned into seven hardware threads that can independently execute computational operations, but the number of threads per vector engine 1802 may vary depending on the embodiment. For example, in one embodiment, up to 16 hardware threads are supported. In an embodiment where seven threads can access 4K bytes, GRF 1824 can store a total of 28K bytes. With 16 threads accessing 4K bytes, a total of 64K bytes can be stored in GRF 1824. Flexible addressing modes allow registers to be addressed together, effectively building wider registers or representing strided rectangular block data structures.

[0290] In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions, which are executed by the message passing send unit 1830. In one embodiment, branch instructions are dispatched to the branch unit 1832 to facilitate SIMD divergence and eventual convergence.

[0291] In one embodiment, the SIMD FPU 1834 of the vector engine 1802 performs floating-point operations. In one embodiment, the SIMD FPU 1834 also supports integer computations. In one embodiment, the SIMD FPU 1834 can perform up to M 32-bit floating-point (or integer) operations, or up to 2M 16-bit integer or 16-bit floating-point operations. In one embodiment, at least one of the FPUs provides extended math capabilities to support high-throughput transcendental math functions and double-precision 64-bit floating-point. In some embodiments, a SIMD ALU 1835 configured to perform 8-bit integer operations is also present and is specifically optimized to perform operations associated with machine learning computations. In one embodiment, the SIMD ALU 1835 is replaced by a SIMD FPU 1834 configurable to perform both integer and floating-point operations. In one embodiment, the SIMD FPU 1834 and the SIMD ALU 1835 are configurable to execute SIMT programs. In one embodiment, combined SIMD+SIMT operations are supported.

[0292] In one embodiment, an array of multiple instances of vector engine 1802 can be instantiated within a graphics core. To achieve scalability, product architects can select the exact number of vector engines per graphics core group. In one embodiment, vector engine 1802 can execute instructions across multiple execution lanes. In another embodiment, each thread executing on vector engine 1802 executes on a different lane.

[0293] like Figure 18C As shown, in one embodiment, the matrix engine 1803 includes an array of processing elements that are configured to perform tensor operations, including vector / matrix and matrix / matrix operations, such as but not limited to matrix multiplication and / or dot product operations. The matrix engine 1803 is configured with M rows and N columns of processing elements (1852AA-1852MN), which include multipliers and adder circuits organized in a pipeline manner. In one embodiment, the processing elements 1852AA-1852MN constitute the physical pipeline stage of an N-wide M-deep systolic array, which can be used to perform vector / matrix or matrix / matrix operations in a data-parallel manner, including matrix multiplication, fused multiplication-addition, dot product or other general matrix-matrix multiplication (GEMM) operations. In one embodiment, the matrix engine 1803 supports 16-bit and 8-bit floating-point operations, as well as 8-bit, 4-bit, 2-bit and binary integer operations. The matrix engine 1803 can also be configured to accelerate specific machine learning operations. In such an embodiment, the matrix engine 1803 can be configured to support the bfloat (brain floating point) 16-bit floating point format or the tensor float 32-bit floating point format (TF32), which have different numbers of mantissa and exponent bits relative to the Institute of Electrical and Electronics Engineers (IEEE) 754 format.

[0294] In one embodiment, during each cycle, each stage can add the result of the operation performed in that stage to the output of the previous stage. In other embodiments, after a set of computation cycles, the pattern of data movement between processing elements 1852AA-1852MN can vary based on the instruction or macro-operation being executed. For example, in one embodiment, partial sum loopback is enabled, and the processing elements can instead add the output of the current cycle to the output generated in the previous cycle. In one embodiment, the final stage of a systolic array can be configured to loop back to the initial stage of the systolic array. In such an embodiment, the number of physical pipeline stages can be decoupled from the number of logical pipeline stages supported by matrix engine 1803. For example, if processing elements 1852AA-1852MN are configured as a systolic array of M physical stages, looping back from stage M to the initial pipeline stage can enable processing elements 1852AA-1852MN to operate as a systolic array of, for example, 2M, 3M, 4M, and so on, logical pipeline stages.

[0295] In one embodiment, the matrix engine 1803 includes memories 1841A-1841N, 1842A-1842M to store input data in the form of row and column data of the input matrix. The memories 1842A-1842M can be configured to store the row elements (A0-Am) of the first input matrix, and the memories 1841A-1841N can be configured to store the column elements (B0-Bn) of the second input matrix. The row elements and column elements are provided as input to the processing elements 1852AA-1852MN for processing. In one embodiment, the row elements and column elements of the input matrix can be stored in a systolic register file 1840 within the matrix engine 1803 before being provided to the memories 1841A-1841N, 1842A-1842M. In one embodiment, the systolic register file 1840 is not included, and the memories 1841A-1841N, 1842A-1842M are stored from registers in the associative vector engine (e.g., Figure 18B 1802 of the vector engine 1802) or other memory of the graphics core including the matrix engine 1803 (e.g., Figure 18A The results generated by processing elements 1852AA-1852MN are then output to output buffers and / or written to register files (e.g., systolic register file 1840, GRF 1824, data cache / shared local memory 1806A-1806N) for further processing by other functional units of the graphics processor or output to memory.

[0296] In some embodiments, the matrix engine 1803 is configured to support input sparsity, in which case multiplication operations for sparse regions of input data can be bypassed by skipping multiplication operations with zero-valued operands. In one embodiment, processing elements 1852AA-1852MN are configured to skip the execution of certain operations with zero-valued inputs. In one embodiment, sparsity within the input matrix can be detected, and operations with known zero output values ​​can be bypassed before being submitted to processing elements 1852AA-1852MN. The process of loading zero-valued operands into the processing elements can be bypassed, and processing elements 1852AA-1852MN can be configured to perform multiplication on non-zero-valued input elements. The matrix engine 1803 can also be configured to support output sparsity, thereby bypassing operations whose results are predetermined to be zero. For input sparsity and / or output sparsity, in one embodiment, metadata is provided to processing elements 1852AA-1852MN to indicate which processing elements and / or data channels will be active during a processing cycle.

[0297] In one embodiment, the matrix engine 1803 includes hardware for implementing operations on sparse data, which has a compressed representation of a sparse matrix storing non-zero values ​​and metadata identifying the locations of non-zero values ​​within the matrix. Exemplary compressed representations include, but are not limited to, compressed tensor representations, such as compressed sparse row (CSR), compressed sparse column (CSC), and compressed sparse fiber (CSF). Support for compressed representations enables operations to be performed on inputs in compressed tensor format without requiring the compressed representation to be decompressed or decoded. In such embodiments, operations can be performed only on non-zero input values, and the resulting non-zero output values ​​can be mapped to the output matrix. In some embodiments, hardware support is also provided for machine-specific lossless data compression formats, which are used when transferring data within the hardware or across a system bus. Such data can be maintained in a compressed format for sparse input data, and the matrix engine 1803 can use the compressed metadata of the compressed data to enable operations to be performed only on non-zero values, or to enable blocks of zero data input to be bypassed for multiplication operations.

[0298] In various embodiments, input data may be provided by a programmer in a compressed tensor representation, or a codec may compress the input data into a compressed tensor representation or other sparse data encoding. In addition to support for compressed tensor representations, streaming compression of sparse input data may be performed before the data is provided to processing elements 1852AA-1852MN. In one embodiment, compression is performed on data written to cache memory associated with graphics core cluster 1800, the compression being performed using an encoding supported by matrix engine 1803. In one embodiment, matrix engine 1803 includes support for inputs with structured sparsity, where a predetermined level or pattern of sparsity is applied to the input data. This data may be compressed to a known compression ratio, where the compressed data is processed by processing elements 1852AA-1852MN based on metadata associated with the compressed data.

[0299] Figure 19 A tile 1900 of a multi-tile processor is shown in accordance with one embodiment. In one embodiment, the tile 1900 represents Figure 17A Graphics engine tiles 1710A-1710D or Figure 17B The multi-tile graphics processor 1900 includes an array of graphics core clusters (e.g., graphics core cluster 1800A, graphics core cluster 1800B, through graphics core cluster 1800N), each of which includes an array of graphics cores 515A-515N. The tile 1900 also includes a global dispatcher 1902 for dispatching threads to processing resources within the tile 1900.

[0300] Tile 1900 may include or be coupled with an L3 cache 1906 and a memory 1910. In various embodiments, L3 cache 1906 may not be included, or tile 1900 may include additional levels of cache, such as an L4 cache. In one embodiment, each instance of tile 1900 in a multi-tile graphics processor is associated with a memory 1910, such as in Figure 17A and Figure 17B In one embodiment, the multi-tile processor may be configured as a multi-chip module in which the L3 cache 1906 and / or memory 1910 reside on a separate coredie from the graphics core clusters 1800A-1800N. In this context, a coredie is an at least partially packaged integrated circuit that includes different logic units that can be assembled with other coredies into a larger package. For example, the L3 cache 1906 may be included in a dedicated cache coredie, or may reside on the same coredie as the graphics core clusters 1800A-1800N. In one embodiment, the L3 cache 1906 may be included in an active substrate die or an active interposer.

[0301] The memory architecture 1903 enables communication between the graphics core clusters 1800A-1800N, the L3 cache 1906, and the memory 1910. The L2 cache 1904 is coupled to the memory architecture 1903 and can be configured to cache transactions executed via the memory architecture 1903. The tile interconnect 1908 enables communication with other tiles on the graphics processor and can be Figure 17A and 17B 1723F. In embodiments where the L3 cache 1906 is excluded from the tile 1900, the L2 cache 1904 can be configured as a combined L2 / L3 cache. The memory architecture 1903 can be configured to route data to the L3 cache 1906 or to a memory controller associated with the memory 1910 based on the presence or absence of the L3 cache 1906 in a particular implementation. The L3 cache 1906 can be configured as a per-tile cache dedicated to the processing resources of the tile 1900, or it can be a partition of the GPU-wide L3 cache.

[0302] Figure 20 The block diagram illustrates a graphics processor instruction format 2000. The graphics processor execution unit supports an instruction set with instructions in a variety of formats. Solid-line boxes illustrate components typically included in execution unit instructions, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the described and illustrated graphics processor instruction format 2000 are macroinstructions because they are instructions provided to the execution unit, rather than micro-operations generated by decoding the instruction once it is processed. Consequently, a single instruction may cause the hardware to execute multiple micro-operations.

[0303] As described herein, the graphics processor execution unit can natively support instructions in the 128-bit instruction format 2010. Depending on the selected instruction, instruction options, and the number of operands, a compact 64-bit instruction format 2030 may be used for some instructions. The native 128-bit instruction format 2010 provides access to all instruction options, while some options and operations are restricted in the 64-bit instruction format 2030. The native instructions available in the 64-bit instruction format 2030 vary depending on the embodiment. A portion of the instruction is compacted using a set of index values ​​in the index field 2013. The execution unit hardware references a set of compaction tables based on the index values ​​and uses the compaction table output to reconstruct the native instruction in the 128-bit instruction format 2010. Instructions of other sizes and formats may also be used.

[0304] For each format, the instruction opcode 2012 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel on multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a simultaneous addition operation on each color channel representing a texture element or picture element. By default, the execution unit executes each instruction on all data channels of the operand. The instruction control field 2014 can enable control of certain execution options, such as channel selection (e.g., predication) and data channel sorting (e.g., swizzle). For instructions 2010 in the 128-bit instruction format, the execution size field 2016 limits the number of data channels that will be executed in parallel. The execution size field 2016 may not be used for the compact 64-bit instruction format 2030.

[0305] Some execution unit instructions have up to three operands, including two source operands src0 2020 and src1 2022, and one destination operand (dest 2018). Other instructions, such as data manipulation instructions, dot product instructions, multiply-add instructions, or multiply-accumulate instructions, may have a third source operand (e.g., src2 2024). The instruction opcode 2012 determines the number of source operands. The last source operand of an instruction may be an immediate value (e.g., hard-coded) passed with the instruction. The execution unit may also support multiple destination instructions, where one or more destinations are implicit or undefined based on the instruction and / or the specified destination.

[0306] The 128-bit instruction format 2010 includes an access / address mode field 2026 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

[0307] The 128-bit instruction format 2010 may include an access / address mode field 2026 that specifies the address mode and / or access mode of the instruction. The access mode may be used to define the data access alignment of the instruction. Access modes including 16-byte aligned access mode and 1-byte aligned access mode may be supported, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction may use byte-aligned addressing for source and destination operands, while in a second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0308] The address mode portion of the access / address mode field 2026 determines whether the instruction uses direct or indirect addressing. When direct register addressing is used, bits in the instruction directly provide the register addresses of one or more operands. When indirect register addressing is used, the register addresses of one or more operands are calculated based on the address register value and the address immediate field in the instruction.

[0309] Instructions can be grouped based on the instruction opcode 2012 bit field to simplify opcode decoding 2040. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is just an example. Move and logic opcode group 2042 may include data movement and logic instructions (e.g., move (mov), compare (cmp)). Move and logic opcode group 2042 may share five least significant bits (LSB), where the form of move (mov) instruction is 0000xxxxb and the form of logic instruction is 0001xxxxb. Flow control instruction group 2044 (e.g., call, jump (jmp)) includes instructions of the form 0010xxxxb (e.g., 0x20). Miscellaneous instruction group 2046 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) of the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 2048 includes component-wise arithmetic instructions (e.g., addition, multiplication (mul)) of the form 0100xxxxb (e.g., 0x40). The parallel math instruction group 2048 performs arithmetic operations in parallel across the data lanes. The vector math group 2050 includes arithmetic instructions (e.g., dp4) of the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations, such as dot product calculations on vector operands. In one embodiment, the opcode decode 2040 can be used to determine which portion of the execution unit will be used to execute the decoded instruction. For example, some instructions can be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), can be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic.

[0310] Graphics pipeline

[0311] Figure 21 is a block diagram of a graphics processor 2100 according to another embodiment. Figure 21 Elements having the same or similar names as elements of any other figures herein describe the same elements as those in the other figures, may operate or function in a similar manner thereto, may include the same components, and may be linked to other entities like those described elsewhere herein, but are not limited thereto.

[0312] The graphics processor 2100 may include different types of graphics processing pipelines, such as a geometry pipeline 2120, a media pipeline 2130, a display engine 2140, thread execution logic 2150, and a render output pipeline 2170. The graphics processor 2100 may be a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor may be controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 2100 via a ring or mesh interconnect 2102. The ring or mesh interconnect 2102 may couple the graphics processor 2100 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring or mesh interconnect 2102 are interpreted by a command stream processor 2103, which provides instructions to individual components of the geometry pipeline 2120 or the media pipeline 2130.

[0313] The command stream processor 2103 may direct the operation of the vertex fetcher 2105, which reads vertex data from memory and executes vertex processing commands provided by the command stream processor 2103. The vertex fetcher 2105 may provide the vertex data to the vertex shader 2107, which performs coordinate space transformation and lighting operations on each vertex. The vertex fetcher 2105 and the vertex shader 2107 may execute the vertex processing instructions by dispatching execution threads to the graphics cores 2152A-2152B via the thread dispatcher 2131.

[0314] Graphics cores 2152A-2152B may be arrays of vector processors with instruction sets for performing graphics and media operations. Graphics cores 2152A-2152B may have an attached L1 cache 2151, which may be specific to each array or shared between arrays. The cache may be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0315] The geometry pipeline 2120 may include a tessellation component for performing hardware-accelerated tessellation of 3D objects. The programmable hull shader 2111 may configure the tessellation operation. The programmable domain shader 2117 may provide back-end evaluation of the tessellation output. The tessellation controller 2113 may operate under the direction of the programmable hull shader 2111 and contain special-purpose logic to generate a set of detailed geometric objects based on the coarse geometric model provided as input to the geometry pipeline 2120. Furthermore, if tessellation is not used, the tessellation components (e.g., the programmable hull shader 2111, the tessellation controller 2113, and the programmable domain shader 2117) may be bypassed. The tessellation components may operate based on data received from the vertex shader 2107.

[0316] The complete geometric object may be processed by the geometry shader 2119 via one or more threads dispatched to the graphics cores 2152A-2152B, or may proceed directly to the clipper 2129. The geometry shader may operate on entire geometric objects, rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2119 receives input from the vertex shader 2107. The geometry shader 2119 may be programmed by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0317] Before rasterization, the clipper 2129 processes the vertex data. The clipper 2129 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. The rasterizer and depth test component 2173 in the render output pipeline 2170 can dispatch pixel shaders to convert geometric objects into per-pixel representations. The pixel shader logic can be included in the thread execution logic 2150. Alternatively, the application can bypass the rasterizer and depth test component 2173 and access unrasterized vertex data via the stream output unit 2123.

[0318] The graphics processor 2100 has an interconnect bus, interconnect architecture, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, the graphics cores 2152A-2152B and associated logic units (e.g., L1 cache 2151, samplers 2154, texture cache 2158, etc.) are interconnected via data ports 2156 to perform memory accesses and communicate with the processor's rendering output pipeline components. The samplers 2154, L1 cache 2151, texture cache 2158, and graphics cores 2152A-2152B can each have a separate memory access path. Optionally, the texture cache 2158 can also be configured as a sampler cache.

[0319] The render output pipeline 2170 may include a rasterizer and depth test component 2173 that converts vertex-based objects into associated pixel-based representations. The rasterizer logic may include a windower / masker unit to perform fixed-function triangle and line rasterization. In some embodiments, an associated render buffer 2178 and depth buffer 2179 are also available. A pixel operation component 2177 performs pixel-based operations on data, but in some cases, pixel operations associated with 2D operations (e.g., bit-block image transfers with blending) are performed by the 2D engine 2141 or replaced by a display controller 2143 using an overlay display plane when displaying. A shared L3 cache 2175 may be available to all graphics components, allowing data to be shared without using main system memory.

[0320] The media pipeline 2130 may include a media engine 2137 and a video front end 2134. The video front end 2134 may receive pipeline commands from the command stream processor 2103. The media pipeline 2130 may include a separate command stream processor. The video front end 2134 may process media commands before sending them to the media engine 2137. The media engine 2137 may include thread spawning functionality to spawn threads for dispatching to the thread execution logic 2150 via the thread dispatcher 2131.

[0321] The graphics processor 2100 may include a display engine 2140. This display engine 2140 may be external to the graphics processor 2100 and may be coupled to the graphics processor via a ring or mesh interconnect 2102 or some other interconnect bus or architecture. The display engine 2140 may include a 2D engine 2141 and a display controller 2143. The display engine 2140 may contain dedicated logic capable of operating independently of the 3D pipeline. The display controller 2143 may be coupled to a display device (not shown), which may be a system-integrated display device, such as in a laptop computer, or an external display device attached via a display device connector.

[0322] The geometry pipeline 2120 and media pipeline 2130 may be configured to operate based on multiple graphics and media programming interfaces, rather than being specific to any one application programming interface (API). Driver software for the graphics processor can translate API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. Support may be provided for the Open Graphics Library (OpenGL), the Open Computing Language (OpenCL), and / or the Vulkan graphics and compute APIs, all from the Khronos Group. Support may also be provided for the Direct3D library from Microsoft. Combinations of these libraries may be supported. Support may also be provided for the OpenSource Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if mapping from their pipelines to the graphics processor's pipeline is possible.

[0323] Graphics pipeline programming

[0324] Figure 22A The block diagram illustrates a method for programming a graphics processing pipeline (e.g., Figure 16 and Figure 21 The graphics processor command format 2200 of the pipeline described above is shown in FIG. Figure 22B The block diagram of 2210 illustrates a graphics processor command sequence 2210 according to one embodiment. Figure 22A The solid-line boxes in the figure illustrate components that are generally included in the graphics commands, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Figure 22A The graphics processor command format 2200 includes a field for identifying the client 2202, a command operation code (opcode 2204), and a data field for the command 2206. Some commands also include a sub-opcode 2205 and a command size 2208.

[0325] Client 2202 may specify the client unit of the graphics device that processes the command data. The graphics processor command parser may examine the client field of each command to determine the conditions for further command processing and route the command data to the appropriate client unit. The graphics processor client unit may include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit may have a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 2204 and sub-opcode 2205 (if any) to determine the operation to be performed. The client unit executes the command using the information in the data field 2206. For some commands, the expected command size 2208 explicitly specifies the size of the command. The command parser may automatically determine the size of at least some commands based on the command opcode. Commands may be aligned to multiple double words. Other command formats may also be used.

[0326] Figure 22B The flowchart in FIG2 illustrates a graphics processor command sequence 2210. Software or firmware of a data processing system featuring an exemplary graphics processor can use a version of the illustrated command sequence to set up, execute, and terminate a set of graphics operations. The sample command sequence shown and described is for illustrative purposes only and is not limited to these specific commands or this command sequence. In addition, commands can be issued as batches in a command sequence so that the graphics processor will process the sequence of commands at least partially concurrently.

[0327] Graphics processor command sequence 2210 may begin with a pipeline flush command 2212 to cause any active graphics pipeline to complete any pending commands currently being processed by that pipeline. Optionally, 3D pipeline 2222 and media pipeline 2224 may not be operating simultaneously. A pipeline flush is performed to cause any pending commands to be completed by the active graphics pipeline. In response to a pipeline flush, the graphics processor's command parser will suspend command processing until the active graphics engine completes pending operations and the associated read buffers are invalidated. Optionally, any data marked as "dirty" in the render buffers may be flushed to memory. Pipeline flush command 2212 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0328] When a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 2213 may be used. Unless the context issues commands for both pipelines, a pipeline select command 2213 may only be required once within the execution context before issuing a pipeline command. A pipeline flush command 2212 may be required immediately before a pipeline switch via a pipeline select command 2213.

[0329] Pipeline control commands 2214 can configure the graphics pipeline for operation and can be used to program the 3D pipeline 2222 and the media pipeline 2224. Pipeline control commands 2214 can configure the pipeline state for the active pipeline. Pipeline control commands 2214 can be used to synchronize pipelines and flush data from one or more cache memories within the active pipeline before processing a batch of commands.

[0330] Commands associated with return buffer status 2216 can be used to configure a set of return buffers for each pipeline to write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers, into which these operations write intermediate data during processing. A graphics processor may also use one or more return buffers to store output data and perform cross-thread communication. Return buffer status 2216 may include selecting the size and number of return buffers to use for a set of pipeline operations.

[0331] The remaining commands in the command sequence differ based on the active pipeline being operated on. Based on pipeline determination 2220 , the command sequence is tailored for either the 3D pipeline 2222 starting from 3D pipeline state 2230 or the media pipeline 2224 starting from media pipeline state 2240 .

[0332] The commands that configure the 3D pipeline state 2230 include 3D state setup commands for configuring vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables before 3D primitive commands are processed. The values ​​of these commands are determined at least in part based on the specific 3D API in use. The 3D pipeline state 2230 commands may also be able to selectively disable or bypass certain pipeline elements if they are not being used.

[0333] 3D primitive 2232 commands can be used to submit 3D primitives for processing by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2232 commands are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 2232 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. The 3D primitive 2232 commands can be used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 2222 dispatches the shader execution thread to the graphics processor execution unit.

[0334] The 3D pipeline 2222 can be triggered via an execute 2234 command or event. Registers can be written to trigger command execution. Execution can be triggered via a "go" or "kick" command within a command sequence. Command execution can be triggered using pipeline synchronization commands to flush the command sequence through the graphics pipeline. The 3D pipeline performs geometry processing on 3D primitives. Once the operation is complete, the resulting geometry is rasterized and the pixel engine shades the resulting pixels. These operations may also include additional commands that control pixel shading and pixel backend operations.

[0335] The graphics processor command sequence 2210 may follow the media pipeline 2224 path when performing media operations. In general, the specific use and programming of the media pipeline 2224 depends on the media or compute operation to be performed. Certain media decoding operations can be offloaded to the media pipeline during media decoding. The media pipeline can also be bypassed, and media decoding can be performed in whole or in part using resources provided by one or more general-purpose processing cores. The media pipeline may also include elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0336] The media pipeline 2224 can be configured in a similar manner to the 3D pipeline 2222. A set of commands that configure the media pipeline state 2240 are dispatched or placed into a command queue before the media object commands 2242. The commands for the media pipeline state 2240 may include data used to configure the media pipeline elements that will be used to process the media objects. This includes data used to configure the video decoding and video encoding logic within the media pipeline, such as the encoding or decoding format. The commands for the media pipeline state 2240 may also support the use of one or more pointers to "indirect" state elements, which contain a collection of state settings.

[0337] The media object command 2242 may provide a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer containing the video data to be processed. Optionally, all media pipeline states must be valid before issuing the media object command 2242. Once the pipeline state is configured and the media object command 2242 is queued, the media pipeline 2224 is triggered via an execute command 2244 or an equivalent execute event (e.g., a register write). The output from the media pipeline 2224 may then be post-processed by operations provided by the 3D pipeline 2222 or the media pipeline 2224. The configuration and execution of GPGPU operations may be similar to media operations.

[0338] Graphics software architecture

[0339] Figure 23 An exemplary graphics software architecture for a data processing system 2300 is illustrated. Such a software architecture may include a 3D graphics application 2310, an operating system 2320, and a processor 2330. The processor 2330 may include a graphics processor 2332 and one or more general-purpose processor cores 2334. The processor 2330 may be a variant of one of the (one or more) processors 1402 or any other processor described herein, and may be used in their place. Therefore, any feature disclosed herein in conjunction with the (one or more) processors 1402 or any other processor described herein also discloses the corresponding combination with the graphics processor 2332, but is not limited thereto. In addition, Figure 23 Elements having the same or similar names as elements of any other figures herein describe the same elements as those in the other figures, may operate or function in a similar manner thereto, may include the same components, and may be linked to other entities, like those described elsewhere herein, but not limited thereto. 3D graphics application 2310 and operating system 2320 are each executed in system memory 2350 of the data processing system.

[0340] 3D graphics application 2310 may include one or more shader programs, including shader instructions 2312. Shader language instructions may be in a high-level shader language, such as Direct3D's High-Level Shader Language (HLSL), OpenGL Shader Language (GLSL), or the like. The application may also include executable instructions 2314 in a machine language suitable for execution by a general-purpose processor core(s) 2334. The application may also include graphics objects 2316 defined by vertex data.

[0341] The operating system 2320 may be from Microsoft Corporation. An operating system, a proprietary UNIX-like operating system, or an open source UNIX-like operating system that uses a variant of the Linux kernel. The operating system 2320 may support a graphics API 2322, such as the Direct3D API, the OpenGL API, or the Vulkan API. When using the Direct3D API, the operating system 2320 uses a front-end shader compiler 2324 to compile any shader instructions 2312 of HLSL into a lower-level shader language. The compilation can be just-in-time (JIT) compilation, or the application can perform shader precompilation. High-level shaders can be compiled into low-level shaders during the compilation of the 3D graphics application 2310. The shader instructions 2312 can be provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0342] The user-mode graphics driver 2326 may include a backend shader compiler 2327 that converts shader instructions 2312 into a hardware-specific representation. When using the OpenGL API, shader instructions 2312 in the GLSL high-level language are passed to the user-mode graphics driver 2326 for compilation. The user-mode graphics driver 2326 may use operating system kernel-mode functionality 2328 to communicate with the kernel-mode graphics driver 2329. The kernel-mode graphics driver 2329 may communicate with the graphics processor 2332 to dispatch commands and instructions.

[0343] IP core implementation

[0344] One or more aspects may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to fabricate logic to perform the techniques described herein. This representation, known as an "IP core," is a reusable unit of logic for an integrated circuit that may be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be provided to various customers or manufacturing facilities that load the hardware model on a fabrication machine that manufactures the integrated circuit. The integrated circuit may be fabricated so that the circuit performs the operations described in association with any of the embodiments described herein.

[0345] Figure 24The block diagram illustrates an IP core development system 2400 according to one embodiment, which can be used to manufacture integrated circuits to perform operations. The IP core development system 2400 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to construct entire integrated circuits (e.g., SoC integrated circuits). A design facility 2430 can generate a software simulation 2410 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 2410 can be used to design, test, and verify the behavior of the IP core using a simulation model 2412. The simulation model 2412 may include functional, behavioral, and / or timing simulations. A register transfer level design (RTL design 2415) can then be created or synthesized from the simulation model 2412. The RTL design 2415 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including associated logic executed using the modeled digital signals. In addition to the RTL design 2415, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

[0346] The RTL design 2415 or equivalent may also be synthesized by the design facility into a hardware model 2420, which may take the form of a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored for transport to a fabrication facility 2465 using a non-volatile memory 2440 (e.g., a hard disk, flash memory, or any other non-volatile storage medium). The fabrication facility 2465 may be a third-party fabrication facility. Alternatively, the IP core design may be transmitted via a wired connection 2450 or a wireless connection 2460 (e.g., via the Internet). The fabrication facility 2465 may then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0347] Figure 25AA cross-sectional side view of a package assembly 2590 of an integrated circuit is shown, the integrated circuit including multiple units of hardware logic cores connected to a substrate 2580 (e.g., a base die). A graphics processing unit, parallel processor, and / or computational accelerator as described herein can be constructed from different silicon cores manufactured separately. In this context, a core is an at least partially packaged integrated circuit that includes different logic units that can be assembled with other cores into a larger package. Different groups of cores with different IP core logic can be assembled into a single device. In addition, cores can be integrated into a base die or base core using active interposer technology. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. IP cores can be manufactured using different process technologies and assembled during manufacturing, which avoids the complexity of converging multiple IP (especially on large SoCs with several flavors of IP) into the same manufacturing process. Allowing the use of multiple process technologies improves time to market and provides a cost-effective way to create multiple product SKUs. Furthermore, disaggregated IP is more amenable to independent power gating; components not used for a given workload can be powered down, reducing overall power consumption.

[0348] In various embodiments, the package assembly 2590 may include a fewer or greater number of components and die that are interconnected via an interconnect fabric 2585 or a bridge structure 2587. The bridge structure 2587 may be used to facilitate point-to-point interconnections between, for example, a logic or I / O die 2574 and a memory die 2575. In some implementations, the bridge structure 2587 may also be embedded within the substrate 2580. The die within the package assembly 2590 may have a 2.5D arrangement using chip-on-wafer-on-substrate (CoWoS) stacking, where multiple dies are stacked side-by-side on a silicon interposer that includes through-silicon vias (TSVs) to couple the die to the substrate 2580, which includes electrical connections to the package interconnects 2583.

[0349] In one embodiment, the silicon interposer is an active interposer 2589 that includes embedded logic in addition to the TSVs. In such an embodiment, the cores within the package assembly 2590 are arranged using 3D face-to-face die stacking atop the active interposer 2589. In addition to the interconnect architecture 2585 and the bridge structure 2587, the active interposer 2589 may also include I / O hardware logic 2591, cache memory 2592, and other hardware logic 2593. The interconnect architecture 2585 enables communication between the various logic cores within the active interposer 2589. The interconnect architecture 2585 can be a NoC interconnect or another form of packet switching architecture that exchanges data packets between components of the package assembly. For complex assemblies, the interconnect architecture 2585 can be a dedicated core that enables communication between the various hardware logic of the package assembly 2590.

[0350] The hardware logic core particles may include dedicated hardware logic core particles 2572, logic or I / O core particles 2574 and / or memory core particles 2575. The dedicated hardware logic core particles 2572 and logic or I / O core particles 2574 may be implemented at least in part in configurable logic or fixed-function logic hardware and may include one or more portions of any (one or more) processor cores, (one or more) graphics processors, parallel processors, or other accelerator devices described herein. The memory core particles 2575 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory. The cache memory 2592 within the active interposer 2589 (or substrate 2580) may serve as a global cache for the package assembly 2590, as part of a distributed global cache, or as a dedicated cache for the interconnect fabric 2585.

[0351] Each core can be fabricated as a separate semiconductor die and coupled to a base die that is embedded within or coupled to substrate 2580. Coupling to substrate 2580 can be performed via interconnect structure 2573. Interconnect structure 2573 can be configured to route electrical signals between various cores and logic within substrate 2580. Interconnect structure 2573 can include interconnects such as, but not limited to, bumps or pillars. In some embodiments, interconnect structure 2573 can be configured to route electrical signals, such as input / output (I / O) signals and / or power or ground signals associated with the operation of logic, I / O, and memory cores. In one embodiment, additional interconnect structures couple active interposer 2589 to substrate 2580.

[0352] Substrate 2580 may be an epoxy-based laminate substrate and / or may include other suitable types of substrates. Package assembly 2590 may be connected to other electrical devices via package interconnects 2583. Package interconnects 2583 may be coupled to the surface of substrate 2580 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0353] The logic or I / O core 2574 and the memory core 2575 can be electrically coupled via a bridge structure 2587, which is configured to transmit electrical signals between the logic or I / O core 2574 and the memory core 2575. The bridge structure 2587 can be a dense interconnect structure that provides a route for electrical signals. The bridge structure 2587 may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide chip-to-chip connections between the logic or I / O core 2574 and the memory core 2575. The bridge structure 2587 can also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge structure 2587 is an embedded multi-die interconnect bridge (EMIB). Alternatively, the bridge structure 2587 may simply be a direct connection from one core to another.

[0354] Figure 25B A package assembly 2594 including interchangeable cores 2595 is illustrated according to one embodiment. Interchangeable cores 2595 can be assembled into standardized core slots or core receptacles on base cores 2596, 2598. The base cores 2596, 2598 can be coupled via a bridge interconnect 2597, which can be similar to other bridge interconnects described herein and can be, for example, EMIB. Memory cores can also be connected to logic or I / O cores via the bridge interconnect. The I / O and logic cores can communicate via the interconnect architecture. The base cores can each support one or more slots in a standardized format for one of logic or I / O or memory / cache.

[0355] The SRAM and power delivery circuits can be fabricated into one or more base core particles 2596, 2598, which can be fabricated using different process technologies relative to the interchangeable core particles 2595 stacked on top of the base core particles. For example, the base core particles 2596, 2598 can be fabricated using a larger process technology, while the interchangeable core particles can be fabricated using a smaller process technology. One or more interchangeable core particles 2595 can be memory (e.g., DRAM) core particles. Based on the power and / or performance targets of the product using the package assembly 2594, different memory densities can be selected for the package assembly 2594. In addition, logic core particles with different numbers of functional unit types can be selected at the time of assembly based on the power and / or performance targets of the product. In addition, core particles containing different types of IP logic cores can be inserted into the interchangeable core particle sockets, enabling hybrid processor designs that can mix and match different technology IP blocks.

[0356] Exemplary system-on-chip integrated circuit

[0357] Figure 26 The diagram illustrates an exemplary integrated circuit that can be fabricated using one or more IP cores. In addition to what is shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. Figure 26 Elements having the same or similar names as elements of any other figures herein describe the same elements as those in the other figures, may operate or function in a similar manner thereto, may include the same components, and may be linked to other entities like those described elsewhere herein, but are not limited thereto.

[0358] The system-on-chip integrated circuit 2600 includes one or more application processors 2605 (e.g., CPUs), a graphics processor 2610 (which may be a variant of the graphics processor(s) 1408 or any graphics processor described herein and may be used in place of any graphics processor described herein). Thus, any feature disclosed herein in conjunction with a graphics multiprocessor also discloses the corresponding combination with the graphics processor 2610, but is not limited thereto. The system-on-chip integrated circuit 2600 may also include an image processor 2615 and / or a video processor 2620, either of which may be a modular IP core from the same or multiple different design facilities. The system-on-chip integrated circuit 2600 may include peripheral or bus logic, including a USB controller 2625, a UART controller 2630, an SPI / SDIO controller 2635, and an I / O controller. 2 S / I 2C controller 2640. In addition, the integrated circuit may include a display device 2645, which is coupled to one or more of a high-definition multimedia interface (HDMI) controller 2650 and a reliability, availability, and serviceability engine (RAS engine 2655). The RAS engine 2655 is used to identify potential failures that may occur during device runtime to minimize the downtime that would result if these potential failures occur. Storage can be provided by a flash memory subsystem 2660, which includes flash memory and a flash memory controller. A memory interface can be provided via a memory controller 2665 for accessing SDRAM or SRAM memory devices. Some integrated circuits also include an embedded security engine 2670.

[0359] Training glitches during extended duration training of neural networks

[0360] Given that training runs span multiple GPU clusters over multiple days and weeks, they can encounter numerous failures. Training failures can occur due to hardware errors that corrupt workload results. There are many sources of hardware failure. For example, bit flips can occur, which are random changes to individual data bits, leading to corrupted computations and unexpected behavior. Other causes of failure include memory access or integrity issues leading to data loss or program crashes, and physical component failures within the GPU leading to complete system instability or crashes. Some errors are difficult to detect, such as silent errors that do not immediately produce symptoms and are difficult to detect until they accumulate and lead to more serious problems, or asymptomatic errors that do not directly impact the training process and are even more difficult to pinpoint without additional monitoring. Hardware errors can lead to training interruptions and data loss, including those that require restarting or resynchronizing the training process, resulting in wasted time and computing resources, or, in severe cases, data corruption, which can corrupt training data and require restarting the entire training process from scratch.

[0361] Figures 27A-27B Plotting training failure rates and CPU-based checkpointing. Figure 27A A graph 2700 is shown showing the percentage 2702 of failed jobs relative to the failure time 2704 in seconds. Figure 27B A system 2720 for performing CPU checkpointing is shown.

[0362] Training deep neural networks (DNNs) typically involves extensive computing resources, large datasets, and long-running jobs that may span hours, days, or even weeks. While long-running training jobs are crucial for achieving state-of-the-art results, they are also susceptible to various failure modes. Figure 27A As shown, in some scenarios, when the job length increases to 300,000 seconds (failure time in seconds 2704), the training run can see a workload failure rate (percentage of failed jobs 2702) that approaches 100%. Training jobs can fail for a variety of reasons, including coding defects that cause memory leaks for extended periods, insufficient storage space to store unexpectedly large amounts of intermediate data, or resource contention in data center environments. Additionally, long training runs in stressed computing environments can expose hardware defects or instabilities due to thermal stress.

[0363] like Figure 27B As shown, some systems mitigate failures by using software-based checkpointing of CPU threads. A checkpoint is essentially a snapshot of the state of a running job captured at regular intervals and stored in permanent storage. For example, system 2720 may include a reader cluster 2721 coupled to a training dataset 2722. Reader cluster 2721 reads training dataset 2722 to provide training data 2723 to training cluster 2724. Training cluster includes a CPU coupled to a training GPU 2726. Training GPU 2726 may be coupled to training GPU 2726 within the same server or rack as training cluster 2724 via an interconnect, including but not limited to PCIe, CXL, NVLink and NVSwitch, InfiniBand, Ethernet, or Hyper-Ethernet. During training, training cluster 2724 may periodically perform CPU checkpointing 2725 using software executed on the CPU, in which checkpoints 2728 are transferred to checkpoint cluster 2729. The checkpoint cluster is coupled to a checkpoint storage 2730 that stores checkpoints. To recover from a failure and continue training, the most recent checkpoint is loaded. However, software-based checkpointing via the CPU requires stopping expensive GPU resources to collect atomic checkpointing information and software intervention to facilitate checkpointing. Stopping GPU resources during training can significantly extend the training time of a neural network.

[0364] HW-assisted checkpointing

[0365] This article describes a technique for implementing hardware-driven checkpointing within an accelerator device without requiring explicit host software intervention to generate checkpoints. Host software can send a workload containing a set of batch jobs to be executed, along with an embedded checkpoint marker for creating a checkpoint. The accelerator device includes compression and DMA engines for faster data movement and compression of the workload's memory. The accelerator device also stores metadata for workload recovery and workload memory checkpoint information. The compression and DMA engines in the accelerator device copy memory blocks and continuously notify the GPU hardware of progress. Once the copy is complete, the accelerator device hardware resumes computation on the copied memory. Appropriate checkpoints are performed atomically, which may require a brief pause in the accelerator device's functionality. When generating atomic checkpoints, these techniques keep expensive accelerator device resources idle for the shortest possible period of time. Furthermore, the accelerator device can implement differential checkpointing, which only stores incremental information from the previous and current checkpoints, for faster snapshot collection and reduced storage. The techniques described in this article are applicable to a variety of accelerator devices used for neural network training, not limited to GPUs or compute accelerators.

[0366] Figures 28A-28C A system 2800 for implementing hardware-assisted checkpointing during neural network training is illustrated, according to an embodiment. The system 2800 enables host software 2802 (e.g., via Figure 6 The machine learning application 602 (using a machine learning framework 604 in the example) can perform hardware-assisted checkpointing during neural network training. Checkpoint data can be stored in a compressed format in memory. In one embodiment, differential checkpointing is implemented, where only data that has changed between updates is saved when a checkpoint is performed. In such an embodiment, a full checkpoint can be saved after a configurable number of differential checkpoints.

[0367] like Figure 28AAs shown, host software 2802 can execute a training timeline 2803, which includes a checkpoint creation marker (e.g., checkpoint creation marker 2804). The checkpoint creation marker includes or triggers the execution of a workload, which consists of a batch of jobs to be executed on an accelerator device, including but not limited to a GPU, NPU, computing accelerator, or AI accelerator as described herein. The batch job will ultimately result in the generation of a compressed checkpoint 2812, which can be stored in the memory of the accelerator and / or the host CPU. The accelerator's memory can be device memory attached to the accelerator device and dedicated to the accelerator device, or device memory attached to the accelerator device and shared with the host CPU, such as in an XPU device. In this configuration, the memory can be HBM memory, and the system can additionally include larger storage devices such as DDR memory. The memory can also include DDR or LPDDR memory attached to the host CPU and accessible by the accelerator. The memory can also include remote memory accessible via CXL.mem. In one embodiment, the accelerator and associated memory can be slices of a partitioned accelerator or virtual instances of the accelerator.

[0368] To create a compressed checkpoint 2812, a batch job is submitted (1) to the hardware scheduler of the accelerator device (HW scheduler 2805). The HW scheduler includes compression and DMA circuitry 2806 for transferring data associated with the checkpoint data and compressing the checkpoint data without requiring the accelerator core 2810 or the host CPU to perform the data transfer or compression. The HW scheduler 2805 can indicate to the accelerator core 2810 (2) the hardware-assisted checkpoint creation operation to be performed. In response, the accelerator core 2810 temporarily suspends execution and triggers (3) the write back of cached information to the memory 2808 used by the accelerator core 2810 or accelerator slice.

[0369] like Figure 28BAs shown, the HW scheduler 2805 uses the compression and DMA circuit 2806 to read (4) checkpoint data from the memory 2808 used by the accelerator core 2810 or accelerator slice via the DMA engine. The compression circuit within the compression and DMA circuit 2806 can then copy the working data from the memory 2808 used by the accelerator slice or core to the memory storing the checkpoint data. During the copy, the compression circuit within the compression and DMA circuit 2806 will compress the data as it is written to the checkpoint memory. Since the copy and compression operations are performed via the HW scheduler 2805, there is no requirement to perform a context switch on the accelerator core 2810 to execute the accelerator code to create the compression checkpoint 2812. Instead, the training operation is only temporarily paused during the data copy. Once the checkpoint copy operation reaches a logical stage where the accelerator core can continue execution, the HW scheduler 2805 can provide a recovery update to the accelerator core 2810. The HW scheduler 2805 can optimize the DMA operations to minimize the idle time of the accelerator core 2810. In one embodiment, the DMA operations are performed as asynchronous DMA operations. In one embodiment, training operations at a single core of the accelerator core 2810 can be resumed without waiting for the entire checkpoint to be created. For example, when the operation of a first accelerator core is independent of the operation of a second accelerator core, for example, when the training operations do not have data interdependencies or overlapping working memory, the training operations on the first accelerator core can be resumed while still replicating the checkpoint data for the second accelerator core.

[0370] The HW scheduler 2805 can then construct multiple instances of compressed checkpoints 2812 over time based on the checkpoint creation markers in the training timeline, where each compressed checkpoint 2812 is associated with a checkpoint creation marker. As described above, the checkpoint memory can reside in the accelerator's memory, the CPU's memory, or a combination of the accelerator and CPU memory. Any compression mechanism or algorithm can be used to compress the checkpoint data. In one embodiment, zip-based compression, delta compression, or another data compression algorithm is used, which can be lossy or lossless data compression algorithm. In one embodiment, a data-aware compression algorithm is used that is customized to the distribution of data to be found within the checkpoint data.

[0371] In one embodiment, differential checkpointing is used across multiple checkpoints. When differential checkpointing is used, a full checkpoint is created, and for the next checkpoint, only the data that has changed since the previous checkpoint is saved. Differential checkpointing reduces the size of checkpoints and speeds up the generation of checkpoints beyond the initial checkpoint. When differential checkpointing is performed, checkpoints similar to the I-frame and P-frame checkpoints used in media compression can be generated. A full checkpoint is generated, followed by a certain number of differential checkpoints. After the certain number of differential checkpoints, a new full checkpoint can be generated.

[0372] like Figure 28C As shown, the HW scheduler 2805 can use the compression and DMA circuit 2806 to generate multiple compressed checkpoints 2812A-2812D based on the compressed checkpoint markers (e.g., checkpoint creation markers 2804) within the training timeline 2803. In one embodiment, the HW scheduler 2805 configures the compression and DMA circuit 2806 to read data and metadata 2818 from the working data set within the memory 2808 of the accelerator core. The data includes checkpoint data that can be used to recover the training process in the event of an error or failure during the training process, which is compressed into the compressed checkpoints 2812A-2812D. The metadata within the data and metadata 2818 includes a mapping of the data that has been updated since the previous checkpoint was created. The metadata simplifies the creation of differential checkpoints by specifying the specific data to be copied so that the HW scheduler 2805 is not responsible for calculating the difference during checkpoint creation.

[0373] For a given set of instances of compressed checkpoints 2812, first compressed checkpoint 2812A is a complete checkpoint, containing the entire dataset required to resume the training process. Subsequently, a second compressed checkpoint 2812B may be created in response to a second checkpoint creation marker. Second compressed checkpoint 2812B is based on differences 2820A, which include updated working data since first compressed checkpoint 2812A. Similarly, third checkpoint 2812C is based on differences 2820B, which include updated working data since second compressed checkpoint 2812B. In one embodiment, a fourth checkpoint 2812D may be created based on the complete 2822 dataset. The number of differential checkpoints to be created between full checkpoints may vary based on the configuration of system 2800. In one embodiment, a fixed number of differential checkpoints are created before creating a full checkpoint. In one embodiment, a full checkpoint is created when the total size of the differential data since the previous full checkpoint exceeds a threshold.

[0374] Figure 29Components of an HW scheduler 2805, which implements the creation of compressed checkpoint data, are illustrated in accordance with an embodiment. In one embodiment, the HW scheduler 2805 includes compression and DMA circuitry 2806, a memory arbiter 2902, a gateway 2906, a core interconnect 2908, an incoming job queue 2915, and a microcontroller 2916. The microcontroller 2916 executes firmware code to control the operation of the HW scheduler 2805, including request operations via the subcomponents of the HW scheduler 2805. Incoming jobs to be scheduled to the accelerator core 2810 (including training jobs to be executed along the training timeline, checkpoint creation markers for creating checkpoints, and other workloads to be executed via the accelerator core 2810) are queued within the incoming job queue 2915. The microcontroller executes operations associated with the jobs within the incoming job queue 2915 and / or executes commands for the jobs within the incoming job queue 2915, including operations and / or commands for copying and compressing training checkpoint data. The compression and DMA circuitry 2806 includes a DMA engine 2904 for copying checkpoint data from the memory 2808 used by the accelerator core or accelerator slice to a checkpoint memory 2920 that stores the checkpoints.

[0375] The CODEC engine 2910 enables compression and decompression of checkpoint data during copying. The CODEC engine 2910 can compress checkpoint data during copying. During restore, the CODEC engine 2910 can decompress checkpoint data while copying back to memory 2808. To copy data, the DMA engine 2904 is configured to queue requests to the memory arbiter 2902 to perform requested memory transfers between memory 2808 and checkpoint memory 2920. To implement atomic checkpointing, the microcontroller 2916 can suspend operations on the accelerator core 2810 via a message transmitted via the core interconnect 2908. As the checkpoint copy operation progresses, operations on the accelerator core 2810 can be resumed. In one embodiment, the DMA engine 2904 includes an asynchronous DMA unit 2914 to asynchronously perform data transfers between memory 2808 and checkpoint memory 2920. The DMA engine 2904 and asynchronous DMA unit 2914 are coupled to a gateway 2906 that is used to indicate when an asynchronous DMA transaction is complete, which allows the DMA engine 2904 and microcontroller 2916 to perform other operations during checkpoint creation.

[0376] The embodiment is not limited to having Figure 29The HW scheduler 2805 for the particular architecture shown. Other scheduling techniques may be used, including fixed functions or software-based schedulers that schedule operations executed on the accelerator device. In such an implementation, the benefits of hardware-assisted checkpointing are still achieved because the training software is not required to use the CPU to perform software-based checkpointing.

[0377] Figure 30 30 is a block diagram of a portion of data center 3000 that includes computing assets that can be configured to perform distributed training operations. Data center 3000 includes multiple logical elements that form multiple nodes, each of which can be provided by a physical server, a group of servers, or other hardware. Each server can also host one or more virtual machines, depending on its application. Fabric 3070 is provided to interconnect various aspects of data center 3000. Fabric 3070 can be provided by any suitable interconnect technology, including but not limited to InfiniBand, Ethernet, PCIe, or CXL. Fabric 3070 of data center 3000 can interconnect data center elements, including server nodes (e.g., memory server nodes 3004, heterogeneous compute server nodes 3006, CPU server nodes 3008, storage server nodes 3010), accelerators 3030, and gateways 3040A-3040B, to other fabrics, fabric architectures, or interconnect technologies, as well as coordinator 3060.

[0378] The server nodes of data center 3000 may include, but are not limited to, memory server nodes 3004, heterogeneous computing server nodes 3006, CPU server nodes 3008, and storage server nodes 3010. Heterogeneous computing server nodes 3006 and CPU server nodes 3008 may perform independent operations for different tenants or collaboratively perform operations for a single tenant. Heterogeneous computing server nodes 3006 and CPU server nodes 3008 may also host virtual machines that provide virtual server functionality to tenants of the data center.

[0379] Each server node may be connected to the fabric 3070 via a fabric interface 3072. The specific type of fabric interface 3072 used depends at least in part on the technology or protocol used to implement the fabric 3070. For example, where the fabric 3070 is an Ethernet fabric, each fabric interface 3072 may be an Ethernet network interface controller. Where the fabric 3070 is a PCIe-based fabric, the fabric interface may be a PCIe-based interconnect. Where the fabric 3070 is an InfiniBand fabric, the fabric interfaces 3072 of the heterogeneous compute server nodes 3006 and the CPU server nodes 3008 may be host channel adapters (HCAs), while the fabric interfaces 3072 of the memory server nodes 3004 and the storage server nodes 3010 may be target channel adapters (TCA).

[0380] (Target Channel Adapter, TCA). TCA functionality may be an implementation-specific subset of HCA functionality. Various fabric interfaces may be implemented as intellectual property (IP) blocks that can be inserted as modular units into integrated circuits, as well as other circuits within the data center 3000.

[0381] The heterogeneous computing server node 3006 includes multiple CPU sockets, each of which can accommodate a CPU 3019. Each CPU 3019 can be, but is not limited to, a CPU with multiple cores. Xeon TM Processor. CPU 3019 can also be a multi-core data center type, for example CPU, e.g. Grace TM The heterogeneous computing server node 3006 includes a memory device 3018 for storing data for runtime execution and a storage device 3016 for implementing permanent storage of data within a non-volatile memory device. The heterogeneous computing server node 3006 is implemented to perform heterogeneous processing, such as the neural network training operations described herein, via the presence of a GPU (e.g., GPU 3017). In one configuration, the GPUs can be interconnected with each other and with the CPU of the heterogeneous computing server node 3006 via an interconnect technology such as PCIe, CXL, or NVLink.

[0382] The CPU server node 3008 includes multiple CPUs (e.g., CPU 3019), memory (e.g., memory device 3018), and storage (storage device 3016) to execute applications and other program code that provide server functionality (e.g., a web server or other type of functionality remotely accessible by clients of the CPU server node 3008). The CPU server node 3008 may also execute program code that provides services or microservices that implement distributed training operations. The structure 3070 will be provided with sufficient throughput to enable the CPU server node 3008 to be accessed simultaneously by a large number of clients, while also maintaining sufficient throughput for use by the heterogeneous compute server nodes 3006 and enabling the heterogeneous compute server nodes 3006 and the CPU server nodes 3008 to use the memory server nodes 3004 and storage server nodes 3010. In addition, in one configuration, the CPU server node 3008 may rely primarily on the distributed services provided by the memory server nodes 3004 and storage server nodes 3010 because the memory and storage of the CPU server node 3008 may be insufficient for all operations intended to be performed by the CPU server node 3008. Instead, a large pool of high-speed or dedicated memory can be dynamically provisioned across multiple nodes so that each node has access to a large pool of resources, but these resources do not sit idle when a particular node does not need them. In one embodiment, the CPU server node 3008 can serve as a training manager to manage the execution of distributed training operations, including the creation and restoration of checkpoints.

[0383] The memory server node 3004 may include a memory node 3005 having a memory technology suitable for storing data used during the execution of program code by the heterogeneous compute server node 3006 and the CPU server node 3008. The memory node 3005 may include volatile memory modules (e.g., DRAM modules) and / or non-volatile memory technologies that can operate at speeds similar to DRAM, such that those modules have sufficient throughput and latency performance metrics to serve as a layer of system memory during execution. The memory server node 3004 may be linked to the heterogeneous compute server node 3006 and / or the CPU server node 3008 using a technology such as CXL.mem that enables memory access from the host to the device. In this configuration, the CPU 3019 of the heterogeneous compute server node 3006 and the CPU server node 3008 may be linked to the memory server node 3004 and access the memory node 3005 of the memory server node 3004 in a manner similar to how, for example, the CPU 3019 of the heterogeneous compute server node 3006 can access the device memory of a GPU within the heterogeneous compute server node 3006. For example, the memory server node 3004 can provide remote direct memory access (RDMA) to the memory node 3005, wherein, for example, the CPU server node 3008 can access memory resources on the memory server node 3004 using DMA operations via the fabric 3070 in a manner similar to how the CPU would access its own onboard memory. The memory server node 3004 can be used to store training data used during distributed training of a machine learning model.

[0384] The memory server node 3004 can be used by the heterogeneous compute server node 3006 and the CPU server node 3008 to expand the runtime memory available during memory-intensive activities (e.g., training of a machine learning model). A tiered memory system can be implemented in which model data can be exchanged between the memory device 3018 of the heterogeneous compute server node 3006 and the memory of the memory server node 3004 with higher performance and / or lower latency than local storage (e.g., storage device 3016). During workload execution setup, the entire working data set can be loaded into one or more memory nodes in the memory nodes 3005 of the memory server node 3004 and loaded into the memory device 3018 of the heterogeneous compute server node 3006 as needed during the execution of the heterogeneous workload.

[0385] The storage server node 3010 provides storage functionality to the heterogeneous computing server nodes 3006, the CPU server nodes 3008, and possibly the memory server nodes 3004. The storage server node 3010 can provide networked disk clusters (NBOD), program flash memory (PFM), redundant arrays of independent disks (RAID), redundant arrays of independent nodes (RAIN), network attached storage (NAS), or other non-volatile memory solutions. In one configuration, the storage server node 3010 can be coupled with the heterogeneous computing server nodes 3006, the CPU server nodes 3008, and / or the memory server nodes 3004 (e.g., NNVMe-oF, which enables the NVMe protocol to be implemented on the fabric 3070). In such a configuration, the fabric interface 3072 of those servers can be an intelligent interface that includes hardware for accelerating NVMe-oF operations. The storage server node 3010 can be used to store compressed checkpoint data for GPUs (e.g., GPU 3017) and accelerators 3030 used to perform training operations. The storage server node 3010 can enable storage of multiple sources of truth to record the progress of the training workload during execution. Multiple sources of truth can be used to enable fine-grained recovery of training data in the event of a failure during the training process.

[0386] The accelerators 3030 within the data center 3000 can provide various acceleration functions, including hardware or coprocessor acceleration for functions such as packet processing, encryption, decryption, compression, decompression, network security, or other acceleration functions in the data center. In some examples, the accelerators 3030 may include deep learning accelerators such as neural processing units (NPUs) that can receive matrix multiplication operations for other neural network operations from heterogeneous computing server nodes 3006 or CPU server nodes 3008. In some configurations, the accelerators 3030 may reside in dedicated accelerator servers or be distributed among the various server nodes in the data center 3000. For example, the NPU may be directly attached to one or more CPU cores within the heterogeneous computing server nodes 3006 or CPU server nodes 3008. In some configurations, the accelerators 3030 may include or be included in intelligent network controllers, infrastructure processing units (IPUs), or data processing units that combine network controller functions with accelerator, processor, or coprocessor functions.

[0387] In one configuration, data center 3000 may include gateways 3040A-3040B from fabric 3070 to other fabrics, fabric architectures, or interconnect technologies. For example, if fabric 3070 is an InfiniBand fabric, gateways 3040A-3040B may be gateways to an Ethernet fabric. If fabric 3070 is an Ethernet fabric, gateways 3040A-3040B may include routers to route data to other parts of data center 3000 or to a larger network, such as the Internet. For example, a first gateway 3040A may connect to different networks or subnets within data center 3000, while a second gateway 3040B may be a router to the Internet.

[0388] The orchestrator 3060 manages the provisioning, configuration, and operation of network resources within the data center 3000. The orchestrator 3060 may comprise hardware or software executing on a dedicated orchestration server. The orchestrator 3060 may also be embodied in software executing, for example, on a CPU server node 3008, which configures software-defined networking (SDN) functionality for components within the data center 3000. In various configurations, the orchestrator 3060 may automate the provisioning and configuration of components within the data center 3000 by performing network resource allocation and template-based deployment. Template-based deployment is a method of provisioning and managing IT resources using predefined templates, where the templates can be based on standard templates required by governments, service providers, finance, standards, or customers. The templates may also specify service level agreements (SLAs) or service level obligations (SLOs). The orchestrator 3060 may also perform functions including, but not limited to, load balancing and traffic engineering, network segmentation, security automation, real-time telemetry monitoring, and adaptive switching management (including telemetry-based adaptive switching). In some configurations, the orchestrator 3060 can also provide multi-tenancy and virtualization support by implementing virtual network management, including the creation and deletion of virtual LANs (VLANs), virtual private networks (VPNs), and tenant isolation in multi-tenant data centers.

[0389] In one embodiment, a training manager executing on a CPU server node 3008 can track instances of checkpoint recovery due to failure of all or part of a training operation. In the event that training failures occur more frequently on a particular node, GPU, or accelerator, the training manager can rebalance the training workload to avoid the potentially defective node, GPU, or accelerator.

[0390] Figure 31The diagram illustrates a system 3100 that enables scheduling of other jobs while a checkpoint operation is in progress. A GPU scheduler can schedule jobs to run on GPU cores that do not share checkpoint-related data while a checkpoint operation is in progress. The GPU scheduler may have multiple acceleration backends, including but not limited to rendering 3102, GPU compute 3103, video encoding 3110, video enhancement 3112, and blitter 3114. The scheduler can use two possible approaches to effectively parallelize checkpoint creation during job idle boundaries on a per-context basis. First, if a job context (e.g., context 3101) is scheduled on two engines because the two engines share the same address space, the GPU scheduler (scheduler A 3104) can time-slice the single job context across the two engine instances. During a time interval, context 3101 may have a rendering-preferred phase 3106 and a compute-preferred phase 3108. For this time slicing, the engine that becomes idle will have its checkpoint submitted. Second, if multiple job contexts are running on multiple engines (e.g., video 110, video enhancement 3112, bit-block transfer 3114), completion frames can be inserted into each job context. When the engine processing the job context reaches a completion frame, it will initiate a checkpoint creation based on the running job context via the scheduler (e.g., scheduler B 3111).

[0391] Figures 32A-32B Illustrate how to save and restore checkpoint data during a training operation. Figure 32A The method 3200 can be performed during a training operation in response to a checkpoint creation marker within a training workflow. Figure 32B Method 3220 may be performed to restore checkpoint data and resume training after a failure.

[0392] like Figure 32A As shown, method 3200 includes performing a training operation of a neural network via one or more accelerator devices (3202). The training operation can be performed by an application configured to train the neural network. The training can be performed via a neural network framework. Figure 11 , a training operation can be executed via a training framework 1104 to perform operations for generating a trained neural network 1108. In response to a checkpoint creation marker within the training workload, the training framework can submit a checkpoint creation job to an accelerator device (3204) of one or more accelerator devices. The accelerator device to which the checkpoint creation job is submitted can be a GPU, an NPU, a computational accelerator, a tensor processing unit (TPU), an AI accelerator, or another device that can be configured to perform computational operations in service of a neural network training operation.

[0393] Submission of the checkpoint creation job may cause the checkpoint creation job to be executed at a scheduler of the accelerator device (3206). In one embodiment, the scheduler is a hardware scheduler that includes a microcontroller for executing firmware that performs scheduling operations for the accelerator device. Other embodiments may use a hardware scheduler with fixed-function scheduling logic, or may use software-based scheduling for the accelerator device. The checkpoint creation job causes the scheduler to atomically create a compressed checkpoint for at least a portion of the training operation executed at the accelerator device (3208). The atomic creation of the compressed checkpoint may include temporarily pausing the execution of the training operation at a core or slice of the accelerator, copying the working data associated with the core or slice, and resuming the operation at the core or slice of the accelerator once the training operation can be resumed without affecting the validity of the checkpoint data. In one embodiment, the checkpoint creation may be performed during a period of pausing the training operation while non-training operations are being performed on the accelerator device. The scheduler may then store the compressed checkpoint to a checkpoint storage device associated with the accelerator device (3210).

[0394] like Figure 32B As shown, method 3220 (3222) can be performed based on detecting a training failure at an accelerator in one or more accelerators performing training operations for a neural network. Method 3220 can be performed by fault recovery logic within an application or training framework that is performing training for a machine learning model. In one embodiment, method 3220 can be performed by firmware executed on a hardware scheduler including a microcontroller. The firmware can configure the microcontroller to monitor the status of the training operations performed on the accelerator and automatically perform recovery operations in response to a training failure.

[0395] Fault recovery logic within the training application, training framework, or hardware scheduler can determine a recovery checkpoint (3224) for resuming training operations on the accelerator. The recovery checkpoint can be the latest checkpoint saved during training. In the case of using multiple accelerators, it may be necessary to roll back other accelerators involved in the training process so that all accelerators are restored from a common set of checkpoints. In the case where the failure may be isolated to a single accelerator or a set of accelerators in a large distributed training operation, it is possible to recover from the training failure by resuming training from a checkpoint at only a subset of all accelerators involved in the training. Using the determined recovery checkpoint, the fault recovery logic can restore the recovery checkpoint to the accelerator (3226). The fault recovery logic can then instruct the scheduler, training application, or training framework to resume training operations at the accelerator (3228).

[0396] Additional Exemplary Computing Devices

[0397] Figure 333300 includes a graphics processor 3304. A version of the computing device 3300 may be, or may be included within, a communication device, such as a set-top box (e.g., an internet-based cable TV set-top box, etc.), a device based on a global positioning system (GPS), or the like. The computing device 3300 may also be, or may be included within, a mobile computing device, such as a cellular phone, a smartphone, a personal digital assistant (PDA), a tablet computer, a laptop computer, an e-reader, a smart TV, a TV platform, a wearable device (e.g., glasses, watches, bracelets, smart cards, jewelry, clothing, etc.), a media player, or the like. For example, in one embodiment, the computing device 3300 comprises a mobile computing device that utilizes an integrated circuit ("IC"), such as a system on a chip ("SoC" or "SOC"), integrating various hardware and / or software components of the computing device 3300 on a single chip.

[0398] Computing device 3300 includes a graphics processor 3304. Graphics processor 3304 represents any graphics processor described herein. In one embodiment, graphics processor 3304 includes a cache 3314, which can be a single cache or divided into multiple cache memory segments, including but not limited to any number of L1, L2, L3, or L4 caches, render caches, depth caches, sampler caches, and / or shader unit caches. In one embodiment, cache 3314 can be a last-level cache shared with application processor 3306. In one embo...

Claims

1. An accelerator device, comprising: memory interconnects; multiple accelerator cores; as well as A scheduler is coupled to the plurality of accelerator cores, the scheduler being configured to: receiving a checkpoint creation job to cause generation of a compressed checkpoint for a training operation performed via the plurality of accelerator cores; Atomically creating a compressed checkpoint for at least a portion of the training operation; as well as The compressed checkpoint is stored in a checkpoint storage associated with the accelerator device.

2. The accelerator device according to claim 1, wherein The scheduler is a hardware scheduler that includes circuitry for performing operations associated with the checkpointing job.

3. The accelerator device according to claim 2, wherein: The circuitry for performing operations associated with the checkpointing job includes a microcontroller.

4. The accelerator device according to claim 2, wherein: The scheduler includes a direct memory access (DMA) engine and a compression circuit coupled to the DMA engine.

5. The accelerator device according to claim 4, wherein: In order to create the compression checkpoint atomically, the scheduler is configured to: pausing execution of the training operation on an accelerator core among the plurality of accelerator cores; requesting, via the DMA engine, copying data associated with the accelerator core; configuring the compression circuitry to compress data associated with the accelerator core during copying; as well as Execution of the training operation on the accelerator core is resumed.

6. The accelerator device according to claim 5, wherein: The DMA engine includes asynchronous DMA circuitry for performing asynchronous DMA operations to copy checkpoint data.

7. The accelerator device according to claim 6, wherein: The scheduler is configured to: During the copying of data associated with a second accelerator core among the plurality of accelerator cores, execution of the training operation on a first accelerator core among the plurality of accelerator cores is resumed.

8. The accelerator device according to any one of claims 1 to 7, wherein: The accelerator device is a graphics processing device.

9. The accelerator device according to any one of claims 1 to 7, wherein: The accelerator device is a neural processing unit.

10. A method for creating a hardware-assisted checkpoint, the method comprising: executing a training operation for the neural network via one or more accelerator devices; In response to a checkpoint creation marker within the training workload, submitting a checkpoint creation job to an accelerator device of the one or more accelerator devices; executing the checkpoint creation job at a scheduler of the accelerator device; atomically creating a compressed checkpoint for at least a portion of the training operation executed at the accelerator device; as well as The compressed checkpoint is stored in a checkpoint storage associated with the accelerator device.

11. The method of claim 10, comprising: The checkpoint creation job is executed via a microcontroller within a hardware scheduler of the accelerator device.

12. The method of claim 11, comprising: The checkpointing operation is performed via a direct memory access (DMA) engine and a compression circuit coupled to the DMA engine.

13. The method of claim 12, wherein: Atomically creating the compression checkpoint includes: pausing execution of the training operation on an accelerator core among the plurality of accelerator cores; requesting, via the DMA engine, copying data associated with the accelerator core; configuring the compression circuitry to compress data associated with the accelerator core during copying; and Execution of the training operation on the accelerator core is resumed.

14. The method of claim 13, comprising: An asynchronous copy of data associated with the accelerator core is requested via asynchronous DMA circuitry within the DMA engine.

15. The method of claim 14, comprising: During the copying of data associated with a second accelerator core among the plurality of accelerator cores, execution of the training operation on a first accelerator core among the plurality of accelerator cores is resumed.

16. A data processing system comprising: general-purpose processors; as well as An accelerator device is coupled to the general-purpose processor, the accelerator device comprising a plurality of accelerator cores and a scheduler coupled to the plurality of accelerator cores, the scheduler being configured to: receiving a checkpoint creation job to cause generation of a compressed checkpoint for a training operation performed by the general purpose processor via the plurality of accelerator cores; Atomically creating a compressed checkpoint for at least a portion of the training operation; as well as The compressed checkpoint is stored in a checkpoint storage associated with the accelerator device.

17. The data processing system according to claim 16, wherein: The scheduler is a hardware scheduler, and the hardware scheduler includes: a microcontroller configured to execute operations associated with the checkpoint creation job; Direct Memory Access (DMA) engine; and A compression circuit is coupled to the DMA engine.

18. The data processing system according to claim 17, wherein: In order to create the compression checkpoint atomically, the scheduler is configured to: pausing execution of the training operation on an accelerator core among the plurality of accelerator cores; requesting, via the DMA engine, copying data associated with the accelerator core; configuring the compression circuitry to compress data associated with the accelerator core during the copying; as well as Execution of the training operation on the accelerator core is resumed.

19. The data processing system of claim 18, wherein: The DMA engine includes asynchronous DMA circuitry for performing asynchronous DMA operations to copy checkpoint data, and the scheduler is configured to resume execution of the training operation on a first accelerator core among the plurality of accelerator cores during copying data associated with a second accelerator core among the plurality of accelerator cores.

20. The data processing system of claim 19, wherein: The accelerator device is a graphics processing device or a neural processing unit.

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