Hardware simulation system and reset processing method

Abstract

The invention discloses a hardware simulation system and a reset processing method, and relates to the technical field of integrated circuit design and verification, and the method comprises the steps that when a reset detection circuit detects a reset control signal, a corresponding data transmission channel switching operation is executed based on the reset control signal. When the data processing circuit detects that a first data transmission channel between the data processing circuit and the simulation test circuit is connected and detects that a data transmission signal is in a first state, the data processing circuit receives to-be-transmitted data which is not written into the storage device by the simulation test circuit through the first data transmission channel and prestores the to-be-transmitted data. Therefore, the problem that the subsequent test cannot be continued due to data loss or jamming caused by the reset operation can be avoided.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design and verification, and in particular to a hardware simulation system and a reset processing method. Background Art

[0002] In the field of integrated circuit technology, hardware simulation systems (also commonly referred to as hardware simulation acceleration platforms) are often used during the design process for integrated circuits. During simulation testing, it is necessary to instantiate test circuits and other related circuits on the hardware simulation acceleration platform, and then use relevant code to control the operations of each instantiated circuit. The instantiated test circuit is called a simulation test circuit.

[0003] For example, certain integrated circuits requiring high-performance data exchange often require verification of their reset functionality. To prevent data freezing or loss, the console in the hardware emulation acceleration platform first checks whether data is being transmitted to the test circuit properly before sending a reset signal. If so, it stops data transmission before sending a reset signal. This makes it impossible to verify whether the test circuit can perform a reset operation while data is being transmitted, lacking relevant test scenarios. Summary of the Invention

[0004] The present application provides a hardware simulation system and a reset processing method, an electronic device, a storage medium, and a program product to solve the problem of being unable to verify the reset function of a test circuit in a data transmission scenario.

[0005] The present application provides a hardware simulation system, which includes a simulation test circuit, a reset signal generation circuit, a reset detection circuit, a data processing circuit, and a storage device;

[0006] A reset detection circuit, configured to, upon receiving a reset control signal sent by a target object, execute a data transmission channel switching operation corresponding to the reset control signal based on the reset control signal;

[0007] A data processing circuit is used to receive the data to be transmitted sent by the simulation test circuit through the first data transmission channel when it detects that the first data transmission channel between itself and the simulation test circuit is connected and the data transmission signal is detected to be in the first state, wherein the connection of the first data transmission channel is achieved through a data transmission channel switching operation, the data to be transmitted is data that has not been written to the storage device when the simulation test circuit detects the reset enable signal sent by the reset signal generation circuit, and the reset enable signal is one of the reset control signals; the data to be transmitted is stored in the data processing circuit.

[0008] The present application provides a reset processing method, which can be applied to the above-mentioned hardware simulation system, and the method includes:

[0009] When the reset detection circuit receives the reset control signal sent by the target object, it performs a data transmission channel switching operation corresponding to the reset control signal based on the reset control signal;

[0010] When the data processing circuit detects that it is connected to the first data transmission channel of the simulation test circuit and detects that the data transmission signal is in the first state, it receives the data to be transmitted sent by the simulation test circuit through the first data transmission channel, wherein the connection of the first data transmission channel is achieved through the data transmission channel switching operation, and the data to be transmitted is the data that has not been written to the storage device when the simulation test circuit detects the reset enable signal sent by the reset signal generation circuit, and the reset enable signal is one of the reset control signals; the data to be transmitted is stored in the data processing circuit.

[0011] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above reset processing methods when executing the computer program.

[0012] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above reset processing methods are implemented.

[0013] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above reset processing methods when executed by a processor.

[0014] Through this application, the simulation test circuit may be in a state reset stage when it is reset. If the storage device is forcibly written at this time, data conflicts may occur (such as incomplete writing or verification failure), and the storage device may enter an abnormal state due to a sudden interruption during the reset process. During the reset operation (reset enable signal triggering), the data originally flowing to the storage device is temporarily redirected to the data processing circuit by dynamically switching the data transmission channel, which can avoid data loss or damage caused by reset. In this way, there is no need to let the console stop data transmission first and then send a reset signal, that is, it is possible to verify whether the simulation test circuit can perform the reset operation normally in the scenario of data transmission, making the test more comprehensive and sufficient, and more accurately verifying whether the reset function of the simulation test circuit is normal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 A schematic diagram of the architecture of a hardware simulation system provided in an embodiment of the present application;

[0017] Figure 2 A schematic diagram of the architecture of another hardware simulation system provided in an embodiment of the present application;

[0018] Figure 3 A flowchart of a reset processing method provided in an embodiment of the present application;

[0019] Figure 4 A schematic diagram of the architecture of another hardware simulation system provided in an embodiment of the present application;

[0020] Figure 5 A flowchart of another reset processing method provided in an embodiment of the present application;

[0021] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0024] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] The professional terms involved in the embodiments of this application are explained in detail below.

[0026] A hardware emulation acceleration platform is a hardware platform used to verify integrated circuits before tape-out. It can be based on a Field Programmable Gate Array (FPGA) or a Central Processing Unit (CPU) architecture.

[0027] Integrated circuit tape-out: refers to the process of converting design code into physical integrated circuits.

[0028] Hardware emulation acceleration platform prototype verification: refers to the process of porting the register transfer level (RTL) circuit to the hardware emulation acceleration platform to pre-verify the functionality of the RTL circuit so that the integrated circuit firmware and underlying driver development can be carried out after the verification is passed.

[0029] RTL circuit: refers to the hardware description language that describes how data flows between registers.

[0030] Integrated circuit re-wafer: The process of testing and verifying the physical integrated circuits actually produced.

[0031] Application Specific Integrated Circuit (ASIC): refers to an integrated circuit designed and manufactured to meet specific user requirements and the needs of specific electronic systems.

[0032] Device Under Test (DUT): In digital circuit design, FPGA development, and ASIC design processes, especially during the simulation and verification phases, DUT refers to the module or system being tested, that is, the design object to be verified.

[0033] In the current field of integrated circuit design, integrated circuits with high-performance data exchange requirements generally incorporate a hard disk interface into their designs to exchange data with an external hard disk. The hard disk interface connects the hard disk to the integrated circuit and the host system, transferring data between the hard disk cache and the chip and host memory. Within the entire system, the stability and reliability of the hard disk interface directly impacts program execution speed and system performance. During firmware execution in actual integrated circuits, it's often necessary to reset the running integrated circuit, such as during firmware upgrades or to save data before a power outage. Ensuring that useful data is saved before the chip is reset and that it can continue to function normally after the reset requires special attention and verification.

[0034] The traditional method is to simulate the high-speed data exchange between the actual integrated circuit and the external hard disk when the integrated circuit is working, which is achieved by directly connecting the DUT and the virtual hard disk model through the hard disk interface. In the hardware simulation acceleration platform, the DUT, clock generation circuit, and reset signal generation circuit are respectively instantiated to synthesize and implement the engineering version of the hardware simulation acceleration platform. In the actual process of debugging the engineering version on the hardware simulation acceleration platform, before the console of the hardware simulation acceleration platform initiates the reset notification, the IO data transmission between the DUT and the virtual hard disk model should be stopped first, and then a reset signal should be sent to the reset signal generation circuit so that the reset signal generation module can send a reset enable signal to the DUT, and the DUT performs a reset action. After the reset action is completed, when the reset needs to be released, the console initiates the release of the reset signal, and the DUT and the virtual hard disk model return to normal working state.

[0035] However, this traditional method has the following problems:

[0036] First, the reset operation ensures stable operation when there is no IO data exchange. However, if there is IO data exchange before the reset, the reset will cause the IO data being transmitted to be lost and may cause the virtual disk model to freeze.

[0037] Second, because IO data transmission needs to be stopped before the reset action is performed, in this case, it is impossible to verify the special scenario of a sudden reset action during IO data transmission, and the adequacy of the verification cannot be ensured.

[0038] In order to solve the above technical problems, this application provides a hardware simulation system suitable for the process of prototyping verification of the above hardware acceleration platform. Figure 1 As shown, the hardware simulation system may include a reset detection circuit 10 , a data processing circuit 20 , a storage device 30 , a reset signal generation circuit 40 , and a simulation test circuit 50 .

[0039] The reset detection circuit 10 is electrically connected to the data processing circuit 20, and the data processing circuit 20 can be electrically connected to the storage device 30. The simulation test circuit 50 can be electrically connected to the data processing circuit 20 and the storage device 30.

[0040] The reset signal generating circuit 40 can be electrically connected to the simulation test circuit 50, and the simulation test circuit 50 is electrically connected to the reset detection circuit 10. Figure 1 Alternatively, in addition to being electrically connected to the simulation test circuit 50, the reset signal generating circuit 40 may also be directly electrically connected to the reset detection circuit 10, so that the reset detection circuit 10 does not need to be connected to the simulation test circuit 50. Figure 2The connection in can enable the reset detection circuit 10 to detect the reset control signal more timely.

[0041] The reset detection circuit 10 may be configured to, upon receiving a reset control signal sent by a target object, execute a data transmission channel switching operation corresponding to the reset control signal based on the reset control signal.

[0042] The simulation test circuit 50 may be the DUT described above, and the storage device 30 may be the virtual hard disk model described above. The reset control signal may be a reset enable signal or a reset release signal. Depending on the reset control signal, the specific functions of the reset detection circuit 10 may include the following two:

[0043] In case one, when the reset control signal is a reset enable signal, the reset detection circuit 10 can be specifically used to disconnect the second data transmission channel between the simulation test circuit 50 and the storage device 30, and connect the first data transmission channel to complete the data transmission channel switching operation corresponding to the reset enable signal.

[0044] In case two, when the reset control signal is a reset release signal, the reset detection circuit 10 can be specifically used to disconnect the first data transmission channel and connect the second data transmission channel between the simulation test circuit 50 and the storage device 30 to complete the data transmission channel switching operation corresponding to the reset release signal.

[0045] The data processing circuit 20 can be configured to receive data to be transmitted from the simulation test circuit 50 via the first data transmission channel when it detects that the first data transmission channel between the simulation test circuit 50 and the data transmission signal is in the first state. The connection of the first data transmission channel is achieved by switching the data transmission channel. The data to be transmitted is data that was not written to the storage device 30 when the simulation test circuit 50 detected the reset enable signal sent by the reset signal generation circuit 40. The data to be transmitted is stored in the data processing circuit 20.

[0046] Specifically, the reset signal generating circuit 40 can automatically generate a reset enable signal and transmit the reset enable signal to the simulation test circuit 50. When the reset enable signal is detected, the simulation test circuit 50 can perform a reset operation. Since the simulation test circuit 50 resets its internal state when it detects the reset enable signal, it is also possible that it is transmitting data to the storage device 30 at this time. Therefore, if the simulation test circuit 50 forcibly writes data to the storage device 30 at this time, it may cause data corruption, the storage device 30 is stuck, and other problems, resulting in the inability to perform subsequent tests. In order to avoid this problem, the reset signal generating circuit 40 can also send the reset enable signal to the reset detection circuit 10 after generating the reset enable signal. The reset detection circuit 10 can receive the reset enable signal sent by the reset signal generating circuit 40. In this case, the reset signal generating circuit 40 is the target object. Alternatively, when the simulation test circuit 50 detects the reset enable signal, it sends the reset enable signal to the reset detection circuit 10, and the reset detection circuit 10 can receive the reset enable signal sent by the simulation test circuit 50. In this case, the simulation test circuit 50 is the target object.

[0047] When the reset detection circuit 10 detects the reset enable signal, the second data transmission channel between the simulation test circuit 50 and the storage device 30 can be disconnected, and the first data transmission channel between the data processing circuit 20 and the simulation test circuit 50 can be connected, completing the data transmission channel switching operation corresponding to the reset enable signal.

[0048] When the data processing circuit 20 detects that the first data transmission channel is connected and detects that the data transmission signal is in the first state (for example, a high level state), it determines that the simulation test circuit 50 has data that has not been written to the storage device 30. At this time, the data processing circuit 20 can receive the data to be transmitted sent by the simulation test circuit 50 through the first data transmission channel and store it.

[0049] In the hardware simulation system of the embodiment of the present application, the simulation test circuit 50 may be in a state reset stage during reset. If the storage device 30 is forcibly written at this time, a data conflict may be caused (such as incomplete writing or verification failure), and the storage device 30 may enter an abnormal state due to a sudden interruption during the reset process. During the reset operation (reset enable signal triggering), the data originally flowing to the storage device 30 is temporarily redirected to the data processing circuit 20 by dynamically switching the data transmission channel, which can avoid data loss or damage caused by reset. In this way, there is no need to let the console stop data transmission first and then send a reset signal, that is, it is possible to verify whether the simulation test circuit 50 can perform the reset operation normally in the scenario of data transmission, making the test more comprehensive and sufficient, and more accurately verifying whether the reset function of the simulation test circuit 50 is normal.

[0050] In some optional embodiments, in addition to preventing data loss, in order to enable normal testing after the reset is released, the data processing circuit 20 may also be configured to send the data to be transmitted to the storage device 30 when it is determined that all the data to be transmitted has been received. The storage device 30 may be configured to reassemble the data to be transmitted and the stored data after receiving all the data to be transmitted.

[0051] Specifically, when the data processing circuit 20 detects that the state of the data transmission signal is the second state (for example, a low-level state), it determines that all the data to be transmitted has been received. At this time, the data processing circuit 20 can send all the stored data to be transmitted to the storage device 30 separately, and the storage device 30 can store the received data to be transmitted after the stored data to ensure the orderliness of the data.

[0052] In some optional implementations, the simulation test circuit 50 is connected to a first port of the storage device 30 , and the data processing circuit 20 is connected to a second port of the storage device 30 .

[0053] The storage device 30 may be used for:

[0054] Whenever a piece of data to be transmitted is received from the second port, the received data to be transmitted is stored in a target location in the target queue of the second storage area. When all the data to be transmitted are determined to have been received, an end address of the first storage area is obtained. Using the end address as the start address, each piece of data to be transmitted is stored in the first storage area in the order in which each piece of data to be transmitted is arranged in the target queue.

[0055] The target position is the position with the largest arrangement order among the positions in the target queue that are not occupied by any data to be transmitted. The first storage area can be used to store data received from the first port.

[0056] In some optional embodiments, the hardware simulation system may further include a console. To ensure that the hardware simulation system can be restored to normal operating state after the data reassembly operation is completed, the storage device 30 may further be configured to send a completion notification to the console upon determining that the data reassembly operation is complete. The console may be configured to, upon receiving the completion notification, send a reset release notification to the reset signal generation circuit 40 and the simulation test circuit 50. The reset signal generation circuit 40 may be configured to, upon receiving the reset release notification, generate a reset release signal and send the reset release signal to the simulation test circuit 50. The simulation test circuit 50 may be configured to release the reset state upon receiving the reset release signal.

[0057] Specifically, when the storage device 30 completes the data reorganization operation, it can send a completion notification to the console. When the console receives the completion notification, it can send a reset release notification to the reset signal generating circuit 40. In this way, when the reset signal generating circuit 40 receives the reset release notification, it can generate a reset release signal and send it to the simulation test circuit 50. When the simulation test circuit 50 receives the reset release signal, it releases the reset state and resumes normal operation.

[0058] Alternatively, upon completing the data reassembly operation, the storage device 30 can directly send a completion notification to the reset signal generation circuit 40. Upon receiving the completion notification, the reset signal generation circuit 40 generates a reset release signal and sends the reset release signal to the simulation test circuit 50. Upon receiving the reset release signal, the simulation test circuit 50 releases the reset state and resumes normal operation. This improves task processing efficiency.

[0059] In the case where the hardware simulation system includes a console, the reset signal generation circuit 40 may generate a reset enable signal after receiving a reset notification sent by the console, and send the signal to the simulation test circuit 50 .

[0060] In some optional embodiments, the reset detection circuit 10 is connected to the reset signal generation circuit 40, and the target object is the reset signal generation circuit 40. The reset signal generation circuit 40 can also be used to send a reset release signal to the reset detection circuit 10, so that the reset detection circuit 10 performs a switching operation of the data transmission channel corresponding to the reset release signal.

[0061] Specifically, refer to Figure 2 When the reset detection circuit 10 is connected to the reset signal generation circuit 40, the target object is the reset signal generation circuit 40. The reset signal generation circuit 40 can also send a reset release signal to the reset detection circuit 10. When the reset detection circuit 10 detects the reset release signal, it can perform a data transmission channel switching operation corresponding to the reset release signal. Specifically, it can be: disconnecting the first data transmission channel and connecting the second data transmission channel, corresponding to the above-mentioned situation 2.

[0062] First, the timeliness of task processing can be improved by directly sending the reset release signal through the reset signal generation circuit 40. Second, if the simulation test circuit 50 cannot normally send the reset release signal due to a reset anomaly, the reset signal generation circuit 40 can still independently trigger the reset release operation to avoid system freezes.

[0063] In some optional embodiments, the reset detection circuit 10 is connected to the simulation test circuit 50, and the target object is the simulation test circuit 50. The simulation test circuit 50 can also be used to send a reset release signal to the reset detection circuit 10, so that the reset detection circuit 10 performs a switching operation of the data transmission channel corresponding to the reset release signal.

[0064] Specifically, refer to Figure 1 , when the reset detection circuit 10 is connected to the simulation test circuit 50, the target object is the simulation test circuit 50. The simulation test circuit 50 can also send a reset release signal to the reset detection circuit 10. When the reset detection circuit 10 detects the reset release signal, it can perform a data transmission channel switching operation corresponding to the reset release signal, specifically: disconnecting the first data transmission channel and connecting the second data transmission channel, corresponding to the above-mentioned situation 2. In this way, hardware resources can be saved by multiplexing the communication link between the reset signal generating circuit 40 and the simulation test circuit 50. In addition, the reset release signal is sent autonomously by the simulation test circuit 50, indicating that it can work normally, which can ensure that the timing of data channel switching is safer to avoid data conflicts caused by premature reset release.

[0065] The embodiment of the present application provides a reset processing method, which can be applied to the above-mentioned hardware simulation system, such as Figure 3 As shown, the specific processing steps of the reset processing method may include:

[0066] In step S301 , when the reset detection circuit 10 receives a reset control signal sent by a target object, the reset detection circuit 10 performs a data transmission channel switching operation corresponding to the reset control signal based on the reset control signal.

[0067] The reset control signal is a reset enable signal or a reset release signal, and the target object is the simulation test circuit 50 or the reset signal generation circuit 40 .

[0068] Specifically, when the reset control signal is a reset enable signal, the reset detection circuit 10 disconnects the second data transmission channel between the simulation test circuit 50 and the storage device 30 and connects the first data transmission channel to complete the data transmission channel switching operation corresponding to the reset enable signal. Alternatively, when the reset control signal is a reset release signal, the first data transmission channel is disconnected and the second data transmission channel between the simulation test circuit 50 and the storage device 30 is connected to complete the data transmission channel switching operation corresponding to the reset release signal.

[0069] In step S302 , when the data processing circuit 20 detects that the first data transmission channel between itself and the simulation test circuit 50 is connected and the data transmission signal is in the first state, the data processing circuit 20 receives the data to be transmitted sent by the simulation test circuit 50 through the first data transmission channel.

[0070] The connection of the first data transmission channel is achieved by a data transmission channel switching operation, and the data to be transmitted is data that has not been written to the storage device 30 when the simulation test circuit 50 detects the reset enable signal sent by the reset signal generation circuit 40. The reset enable signal is a type of reset control signal.

[0071] Specifically, when the data processing circuit 20 detects that the first data transmission channel is connected and detects that the data transmission signal is in the first state (for example, a high level state), it determines that the simulation test circuit 50 has data that has not been written to the storage device 30. At this time, the data processing circuit 20 can receive the data to be transmitted sent by the simulation test circuit 50 through the first data transmission channel.

[0072] In step S303 , the data processing circuit 20 stores the data to be transmitted in the data processing circuit 20 .

[0073] Specifically, each data to be transmitted can be stored in the order in which it is received, so that when the data to be transmitted is subsequently sent to the storage device 30, it can also be sent in the order in which it is received, thereby ensuring the orderliness of the data in the storage device 30. After the reset is released, the test process of the hardware simulation system can also be ensured to proceed normally.

[0074] In the reset processing method of the embodiment of the present application, the simulation test circuit 50 may be in a state reset stage during reset. If the storage device 30 is forcibly written at this time, a data conflict may be caused (such as incomplete writing or verification failure), and the storage device 30 may enter an abnormal state due to a sudden interruption during the reset process. During the reset operation (reset enable signal triggering), the data originally flowing to the storage device 30 is temporarily redirected to the data processing circuit 20 by dynamically switching the data transmission channel, which can avoid data loss or damage caused by reset. In this way, there is no need to let the console stop data transmission first and then send a reset signal, that is, it is possible to verify whether the simulation test circuit 50 can perform the reset operation normally in the scenario of data transmission, making the test more comprehensive and sufficient, and more accurately verifying whether the reset function of the simulation test circuit 50 is normal.

[0075] The following is a detailed description of the execution process of the reset processing method executed by the hardware simulation system using a specific example. Figure 4 As shown, the corresponding flowchart can be as follows Figure 5As shown. Among them, the hardware simulation system may include a console, a first clock signal generating circuit, a reset signal generating circuit 40, a simulation test circuit 50, a reset processing circuit, and a storage device 30. The reset processing circuit may specifically include a reset detection circuit 10, a data processing circuit 20, and a second clock signal generating circuit. The console is electrically connected to the first clock signal generating circuit, and is also electrically connected to the storage device 30. The simulation test circuit 50 is electrically connected to the reset detection circuit 10, and is also electrically connected to the data processing circuit 20. The second clock signal generating circuit is electrically connected to the data processing circuit 20. The data processing circuit 20 is electrically connected to the storage device 30. The first clock signal generating circuit is used to provide a clock signal for the simulation test circuit 50, and the data processing circuit 20 is used to provide a clock signal for the reset detection circuit 10 and the data processing circuit 20. By setting different clock signal generating circuits, the clock signal generating circuits can be set to different frequencies according to the functions of their respective corresponding circuits, and the flexibility and stability are relatively high.

[0076] Hardware simulation system can also be generally called hardware simulation acceleration platform. Figure 5 The process shown in the figure is to first synthesize and implement the prototype version. For example, in the process of making the engineering version of the hardware simulation acceleration platform, the above-mentioned console, the first clock signal generating circuit, the reset signal generating circuit 40, the simulation test circuit 50, the reset processing circuit, the storage device 30, etc. can be instantiated respectively through the relevant codes pre-built by the technicians, so that the hardware resources of the hardware simulation acceleration platform can be configured as follows. Figure 4 The circuit connection relationship shown is allocated and connected.

[0077] In addition, after obtaining the test file, the hardware simulation acceleration platform can process the test file to generate a binary bit stream and project configuration file that can be used for upper-level debugging, so that the hardware simulation acceleration platform can perform related test operations according to the information in the test file.

[0078] During the reset test process, the console first initiates the reset process, which can be specifically as follows: first, a reset notification is sent to the reset signal generating circuit 40. When the reset signal generating circuit 40 receives the reset notification, it can send a reset enable signal to the simulation test circuit 50. The simulation test circuit 50 then transmits the reset enable signal to the reset detection circuit 10. After detecting the reset enable signal, the reset detection circuit 10 disconnects the second data transmission channel and connects the first data transmission channel. After detecting that the first data transmission channel is connected, the data processing circuit 20 detects whether the data transmission signal is in the first state. If so, the data to be transmitted can be read from the simulation test circuit 50 and stored until the data transmission signal is detected to be in the second state, and the transmission operation of the data to be transmitted is determined to be completed. At this time, the data processing circuit 20 can transmit all the temporarily stored data to be transmitted to the storage device 30 respectively, and the storage device 30 performs the data reorganization operation.

[0079] After completing the data reorganization operation, the storage device 30 may send a completion notification to the console. Upon receiving the completion notification, the console may initiate a reset release process, specifically by sending a reset release notification to the reset signal generation circuit 40. Upon receiving the reset release notification, the reset signal generation circuit 40 may generate a reset release signal and send it to the simulation test circuit 50. The simulation test circuit 50 may then release the reset state, resume normal operation, and send the reset release signal to the reset detection circuit 10. Upon detecting the reset release signal, the reset detection circuit 10 disconnects the first data transmission channel and connects the second data transmission channel.

[0080] This reciprocating process allows for multiple reset tests. During the reset test, resetting the simulation test circuit 50 may cause an abnormal interruption, which in turn may cause the storage device to freeze due to the abnormal interruption. By switching the data transmission channel, this solution can prevent the storage device 30 from freezing, thereby ensuring a smooth test process and improving test efficiency. Furthermore, there is no need to stop the console from transmitting data in advance, ensuring the adequacy of the test scenario.

[0081] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0082] The embodiment of the present application also provides an electronic device, such as Figure 6 As shown, it includes a memory 60 and a processor 70. The memory 60 stores a computer program, and the processor 70 is configured to run the computer program to execute the steps in any of the above reset processing method embodiments. The electronic device can be the above hardware simulation acceleration platform.

[0083] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above reset processing method embodiments when running.

[0084] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0085] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above reset processing method embodiments are implemented.

[0086] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above reset processing method embodiments are implemented.

[0087] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0088] The above is a detailed introduction to a hardware simulation system and reset processing method, electronic device, storage medium, and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

Claims

1. A hardware simulation system, characterized in that: The hardware simulation system includes a simulation test circuit, a reset signal generating circuit, a reset detection circuit, a data processing circuit, and a storage device; The reset detection circuit is configured to, upon receiving a reset control signal sent by a target object, execute a data transmission channel switching operation corresponding to the reset control signal based on the reset control signal; The data processing circuit is used to receive the data to be transmitted sent by the simulation test circuit through the first data transmission channel when it detects that the first data transmission channel between itself and the simulation test circuit is connected and the data transmission signal is detected to be in the first state, wherein the connection of the first data transmission channel is achieved through the data transmission channel switching operation, and the data to be transmitted is the data that has not been written to the storage device when the simulation test circuit detects the reset enable signal sent by the reset signal generation circuit, and the reset enable signal is one of the reset control signals; the data to be transmitted is stored in the data processing circuit.

2. The hardware simulation system according to claim 1, wherein: The reset control signal is the reset enable signal, and the reset detection circuit is specifically used to: The second data transmission channel between the simulation test circuit and the storage device is disconnected, and the first data transmission channel is connected to complete the data transmission channel switching operation corresponding to the reset enable signal.

3. The hardware simulation system according to claim 1, wherein: When the reset control signal is a reset release signal, the reset detection circuit is specifically configured to: The first data transmission channel is disconnected, and a second data transmission channel between the simulation test circuit and the storage device is connected to complete a data transmission channel switching operation corresponding to the reset release signal.

4. The hardware simulation system according to any one of claims 1 to 3, characterized in that: The data processing circuit is further configured to send the data to be transmitted to the storage device when it is determined that all the data to be transmitted has been received; The storage device is used to perform a data reorganization operation on the data to be transmitted and the stored data after receiving all the data to be transmitted.

5. The hardware simulation system according to claim 4, wherein: The hardware simulation system also includes a console; The storage device is further configured to send a completion notification to the console when determining that the data reorganization operation is completed; The console is configured to send a reset release notification to the reset signal generating circuit and the simulation test circuit upon receiving the completion notification; The reset signal generating circuit is configured to generate a reset release signal upon receiving the reset release notification, and send the reset release signal to the simulation test circuit; The simulation test circuit is used to release the reset state when receiving the reset release signal.

6. The hardware simulation system according to claim 5, characterized in that The reset detection circuit is connected to the reset signal generating circuit, and the target object is the reset signal generating circuit; The reset signal generating circuit is further configured to send the reset release signal to the reset detection circuit, so that the reset detection circuit performs a switching operation of the data transmission channel corresponding to the reset release signal.

7. The hardware simulation system according to claim 5, characterized in that The reset detection circuit is connected to the simulation test circuit, and the target object is the simulation test circuit; The simulation test circuit is further configured to send the reset release signal to the reset detection circuit, so that the reset detection circuit performs a switching operation of the data transmission channel corresponding to the reset release signal.

8. The hardware simulation system according to claim 4, wherein: The data processing circuit is specifically used for: When it is detected that the state of the data transmission signal is the second state, it is determined that all the data to be transmitted are received.

9. The hardware simulation system according to claim 4, wherein: The simulation test circuit is connected to the first port of the storage device, and the data processing circuit is connected to the second port of the storage device; The storage device is specifically used for: Whenever a piece of data to be transmitted is received from the second port, the received data to be transmitted is stored in a target position in the target queue of the second storage area, wherein the target position is the position with the largest arrangement order among the positions in the target queue that are not occupied by any piece of data to be transmitted; When it is determined that all the data to be transmitted has been received, obtaining an end address of a first storage area, wherein the first storage area is used to store data received from the first port; The end address is used as the start address, and each of the data to be transmitted is stored in the first storage area according to the arrangement order of each of the data to be transmitted in the target queue.

10. A reset processing method, characterized in that: The method is applied to the hardware simulation system according to any one of claims 1 to 9, wherein the hardware simulation system comprises a simulation test circuit, a reset signal generating circuit, a reset detection circuit, a data processing circuit, and a storage device; When the reset detection circuit receives the reset control signal sent by the target object, the reset detection circuit performs a data transmission channel switching operation corresponding to the reset control signal based on the reset control signal; When the data processing circuit detects that it is connected to the first data transmission channel of the simulation test circuit and detects that the data transmission signal is in the first state, it receives the data to be transmitted sent by the simulation test circuit through the first data transmission channel, wherein the connection of the first data transmission channel is achieved by the data transmission channel switching operation, and the data to be transmitted is the data that has not been written to the storage device when the simulation test circuit detects the reset enable signal sent by the reset signal generation circuit, and the reset enable signal is one of the reset control signals; the data to be transmitted is stored in the data processing circuit.

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