Simulation information generation method and system, equipment, storage medium and program product

Abstract

The embodiment of the invention provides a simulation information generation method and system, equipment, a storage medium and a program product, relates to the technical field of integrated circuits, and aims at solving the problems that single-round simulation data processing is bottleneck, information such as resource use of simulation tasks cannot be monitored, log analysis efficiency is low, and accuracy is not high. The generation method comprises the following steps: submitting a simulation task set corresponding to a to-be-simulated chip to a job scheduling system; determining maximum resource use information of each first simulation task based on the resource use information of the at least one first simulation task; wherein the first simulation task is an executed simulation task in a simulation task set; analyzing the simulation log corresponding to each first simulation task by using a preset multi-mode matcher to generate log analysis information; and based on the log analysis information and the maximum resource use information of each first simulation task, generating simulation information of the to-be-simulated chip.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of integrated circuit technology, and in particular to a method and system, device, storage medium, and program product for generating simulation information. Background Art

[0002] In digital chip verification projects, the verification process based on existing simulation tools often suffers from bottlenecks in single-round simulation data processing, an inability to monitor information such as resource usage of simulation tasks, and low efficiency and accuracy in log analysis. Summary of the Invention

[0003] Embodiments of the present disclosure provide a method and system for generating simulation information, a device, a storage medium, and a program product.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows: The present disclosure provides a method for generating simulation information, including: Submitting a simulation task set corresponding to the chip to be simulated to a job scheduling system; wherein the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel at the same time; Determining maximum resource usage information of each first simulation task based on resource usage information of at least one first simulation task; wherein the first simulation task is a completed simulation task in the simulation task set; Analyze the simulation log corresponding to each of the first simulation tasks using a preset multi-pattern matcher to generate log analysis information; Based on the log analysis information and the maximum resource usage information of each of the first simulation tasks, simulation information of the chip to be simulated is generated; wherein, the simulation information is used for at least one of the following: generating a visual simulation report, determining the parallelism of the job scheduling system.

[0005] The present disclosure provides a system for generating simulation information, including: A task scheduling adapter module is used to submit a simulation task set corresponding to the chip to be simulated to a job scheduling system; wherein the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel at the same time; a resource monitoring module, configured to determine maximum resource usage information of each first simulation task based on resource usage information of at least one first simulation task; wherein the first simulation task is a completed simulation task in the simulation task set; a log analysis engine, configured to analyze the simulation log corresponding to each of the first simulation tasks using a preset multi-pattern matcher, and generate log analysis information; An information generation module is used to generate simulation information of the chip to be simulated based on the log analysis information and the maximum resource usage information of each of the first simulation tasks; wherein the simulation information is used for at least one of the following: generating a visual simulation report, determining the parallelism of the job scheduling system.

[0006] An embodiment of the present disclosure provides an electronic device, including a processor and a memory, wherein the memory stores a computer program that can be run on the processor, and the above method is implemented when the processor executes the computer program.

[0007] An embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the above method is implemented.

[0008] An embodiment of the present disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, the above method is implemented.

[0009] In the disclosed embodiments, first, by submitting a simulation task set to a job scheduling system for execution, multiple simulation tasks can be executed concurrently, thereby greatly improving the processing of single-round simulation data; second, by monitoring the resources of each running simulation task, not only can bottlenecks be warned in advance, avoiding simulation interruptions or performance degradation due to resource exhaustion, and ensuring stable operation of simulation tasks, but resource allocation can also be optimized, thereby improving the utilization rate of the job scheduling system and accelerating the overall execution speed of simulation tasks; third, by analyzing each simulation log through a multi-pattern matcher, the efficiency and accuracy of log analysis are improved; finally, simulation information is generated based on log analysis information and each maximum resource usage information, which not only improves the accuracy and comprehensiveness of the simulation information, but also provides strong data support for the subsequent generation of visual simulation reports and adjustment of the parallelism of the job scheduling system.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0012] Figure 1 A schematic diagram of the implementation process of a method for generating simulation information provided in an embodiment of the present disclosure Figure 1 ; Figure 2 A schematic diagram of the structure of a simulation information generation system provided in an embodiment of the present disclosure Figure 1 ; Figure 3 A schematic diagram of the structure of a simulation information generation system provided in an embodiment of the present disclosure Figure 2 ; Figure 4 A schematic diagram of the implementation process of a method for generating simulation information provided in an embodiment of the present disclosure Figure 2 ; Figure 5 A schematic diagram of a hardware entity of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0014] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0015] In the following description, the terms "first\second\third" are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0017] The methods provided in the embodiments of the present disclosure can be performed by electronic devices, which can be various types of terminals such as laptops, tablet computers, desktop computers, set-top boxes, mobile devices (e.g., mobile phones, portable music players, personal digital assistants, dedicated messaging devices, portable gaming devices), etc., or can be implemented as servers. The server can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0018] Below, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings in the embodiments of the present disclosure.

[0019] Figure 1 A schematic diagram of the implementation process of a method for generating simulation information provided in an embodiment of the present disclosure Figure 1 ,like Figure 1 As shown, the generation method includes steps S11 to S14, wherein: Step S11: submitting a simulation task set corresponding to the chip to be simulated to a job scheduling system; wherein the simulation task set includes at least one simulation task, and the job scheduling system is used to simultaneously execute the simulation tasks in parallel.

[0020] Here, the chip to be simulated can be any suitable chip that needs to be simulated. For example, a digital chip. The simulation task can be any suitable task that tests at least part of the functions of the chip to be simulated. In some embodiments, the simulation task can also be referred to as a test case. Each simulation task can test different functions or the same function. For example, the simulation task can verify the clock function, computing function, storage function, etc. of a digital chip.

[0021] The job scheduling system can be any suitable system capable of implementing task scheduling. For example, LSF, Slurm, etc. In some embodiments, the job scheduling system can also be a distributed resource management system. The job scheduling system can include multiple nodes, and the multiple nodes can concurrently execute a certain degree of parallelism of simulation tasks. It is understood that the degree of parallelism of the job scheduling system can be dynamically set based on its remaining resources and the resources required for each simulation task.

[0022] The job scheduling system may include a built-in simulation tool to execute the simulation task. The simulation tool can be any suitable tool capable of simulating and testing the chip's hardware functions, such as VCS or XRUN. During implementation, the simulation task is executed by calling the simulation tool.

[0023] Step S12: Based on the resource usage information of at least one first simulation task, determine the maximum resource usage information of each first simulation task; wherein the first simulation task is a simulation task in the simulation task set that has been completed.

[0024] Here, since resource usage information is only available after a simulation task is executed, it is necessary to wait until the simulation task switches to the running state before obtaining its resource usage information. During implementation, the job scheduling system can provide a task status acquisition interface and a resource acquisition interface. The task status acquisition interface can be used to determine the status of each simulation task, and the resource acquisition interface can be used to obtain resource usage information for each running or completed simulation task.

[0025] Resource usage information may include, but is not limited to, at least one of overall resource usage information and resource usage information at each moment (i.e., local resource usage information). Resource usage information may include, but is not limited to, memory usage information, CPU usage information, and I / O load information. Memory usage information reflects the memory consumption of the first simulation task during execution, and may include, but is not limited to, peak memory usage and memory usage. CPU usage information reflects the CPU consumed by the first simulation task, and may also be referred to as CPU usage.

[0026] Maximum resource usage information refers to the maximum resource usage information, which may include but is not limited to maximum memory usage information, maximum CPU usage information, maximum I / O load information, etc. Methods for determining this maximum resource usage information may include but are not limited to resource usage information at a certain moment, weighted resource usage information at a certain moment, overall resource usage information, and weighted overall resource usage information.

[0027] For example, determine whether the resource usage information at the current moment is greater than the current maximum resource usage information. If so, update the current maximum resource usage information to the resource usage information at the current moment; otherwise, keep the current maximum resource usage information unchanged; and use the maximum resource usage information determined at the last moment as the final maximum resource usage information.

[0028] For another example, determine whether the resource usage information at the final moment is greater than the overall resource usage information. If so, use the resource usage information at the final moment as the final maximum resource usage information; otherwise, use the overall resource usage information as the final maximum resource usage information.

[0029] Step S13: Analyze the simulation log corresponding to each of the first simulation tasks using a preset multi-pattern matcher to generate log analysis information.

[0030] Here, the multi-pattern matcher includes at least one matcher, with different matchers applicable to different stages. In some embodiments, the multi-pattern matcher includes a first matcher for processing simulation during the compilation stage and a second matcher for processing simulation during the runtime stage. The first matcher is primarily used to handle problems encountered during the compilation stage, such as syntax errors, undefined identifiers, and pattern mismatches. The first matcher includes a built-in compilation regular expression library, which includes at least one regular expression for identifying compilation problems. The second matcher is primarily used to handle problems encountered during the runtime stage. The second matcher may include, but is not limited to, a standard matcher, a custom matcher, etc. The standard matcher is primarily used to handle standard printing error messages in the simulation tool. The standard matcher includes a built-in first regular expression library, which includes at least one regular expression for identifying standard printing content. The custom matcher is primarily used to handle custom error messages, i.e., non-standard printing errors. The custom matcher includes a built-in second regular expression library, which includes at least one regular expression for identifying non-standard printing content.

[0031] The log analysis information can include error types, error counts, and locations of various errors. Error types include compile-stage error types and runtime-stage error types. During implementation, different matchers are used to analyze each simulation log to obtain the log analysis information.

[0032] Step S14: Generate simulation information of the chip to be simulated based on the log analysis information and the maximum resource usage information of each of the first simulation tasks; wherein the simulation information is used for at least one of the following: generating a visual simulation report, determining the parallelism of the job scheduling system.

[0033] Here, the simulation information includes at least log analysis information and maximum resource usage information of each first simulation task. In some implementations, the simulation information may also include resource usage information of each first simulation task at each moment.

[0034] The simulation information may be generated in any suitable manner. In some embodiments, a structured generation template may be pre-built, and the log analysis information and the maximum resource usage information of each first simulation task may be entered into the template to obtain the simulation information. In some embodiments, the log analysis information and the maximum resource usage information of each first simulation task may be input into a generative model to obtain the simulation information. The generative model may be any suitable neural network model capable of realizing the function.

[0035] During implementation, the simulation information can be stored locally or in the cloud and managed in a versioned manner.

[0036] This simulation information can be used to generate a visual simulation report that can be automatically pushed to relevant personnel, enabling real-time information sharing. This simulation information can also be synchronized with the job scheduling system, allowing the job scheduling system to configure its parallelism based on the simulation information and remaining resource information.

[0037] In the disclosed embodiments, first, by submitting a simulation task set to a job scheduling system for execution, multiple simulation tasks can be executed concurrently, thereby greatly improving the processing of single-round simulation data; second, by monitoring the resources of each running simulation task, not only can bottlenecks be warned in advance, avoiding simulation interruptions or performance degradation due to resource exhaustion, and ensuring stable operation of simulation tasks, but resource allocation can also be optimized, thereby improving the utilization rate of the job scheduling system and accelerating the overall execution speed of simulation tasks; third, by analyzing each simulation log through a multi-pattern matcher, the efficiency and accuracy of log analysis are improved; finally, simulation information is generated based on log analysis information and each maximum resource usage information, which not only improves the accuracy and comprehensiveness of the simulation information, but also provides strong data support for the subsequent generation of visual simulation reports and adjustment of the parallelism of the job scheduling system.

[0038] In some embodiments, step S12 includes steps S121 to S123, wherein: Step S121: periodically obtain resource usage information of at least one second simulation task in the running queue at the current moment through the first resource acquisition interface provided by the job scheduling system; wherein, the second simulation task is a running simulation task in the simulation task set.

[0039] Here, the run queue is primarily used to store various currently running simulation tasks. The length of this run queue is no less than the parallelism of the job scheduling system. In practice, when a simulation task switches to the running state, it is pushed into the run queue; when a simulation task switches to the completed state, it is ejected from the run queue. It is understood that the run queue is initially empty.

[0040] The first resource acquisition interface is primarily used to obtain resource usage information for a simulation task. It is understood that different job scheduling systems may provide the same or different first resource acquisition interfaces. During implementation, by passing the identifier of a second simulation task into the first resource acquisition interface, the resource usage information for the second simulation task at the current moment can be obtained.

[0041] The timing can be any appropriate length of time, for example, 20 seconds, 1 minute, etc.

[0042] Step S122: For each second simulation task, determine the maximum resource usage information of the second simulation task based on the resource usage information of the second simulation task at the current moment.

[0043] Here, after obtaining resource usage information for a second simulation task at a certain moment, the maximum resource usage information for the second simulation task is determined based on the resource usage information at that moment. For example, if the resource usage information at that moment is greater than the maximum resource usage information, the resource usage information at that moment, or a weighted amount of the resource usage information at that moment, is used as the maximum resource usage information. If the resource usage information at that moment is not greater than the maximum resource usage information, the maximum resource usage information may remain unchanged.

[0044] In some implementations, when it is detected that resource usage information of a second simulation task at a certain moment is abnormal (eg, exceeds a set threshold), an alarm may be issued in a timely manner to facilitate the normal execution of other subsequent simulation tasks.

[0045] Step S123: In response to detecting that the state of any second simulation task is switched to a completed state, the second simulation task is treated as a first simulation task, and the overall resource usage information of the first simulation task is obtained through the second resource acquisition interface provided by the job scheduling system. Based on the overall resource usage information of the first simulation task, the maximum resource usage information of the first simulation task is determined.

[0046] Here, the second resource acquisition interface is mainly used to obtain the overall resource usage information of the first simulation task. The second resource acquisition interface can be the same as or different from the first resource acquisition interface. When the second resource acquisition interface is the same as the first resource acquisition interface, the interface parameters can be used to specify whether to obtain real-time resource usage information or overall resource usage information.

[0047] When it is detected that the state of a second simulation task is switched to the completed state, the second simulation task will be updated to the first simulation task, and the maximum resource usage information determined at the last moment of the second simulation task will be used as the maximum resource usage information of the first simulation task.

[0048] The overall resource information represents the overall resource usage of the first simulation task, and may include but is not limited to overall memory usage, overall peak value, overall I / O load, etc.

[0049] After obtaining the overall resource usage information of the first simulation task, the maximum resource usage information of the first simulation task is determined based on the overall resource usage information. For example, if the overall resource usage information is greater than the maximum resource usage information, the overall resource usage information or a weighted amount of the overall resource usage information is used as the maximum resource usage information; if the overall resource usage information is not greater than the maximum resource usage information, the maximum resource usage information may remain unchanged.

[0050] In the disclosed embodiments, on the one hand, by real-time monitoring of system-level resource consumption (such as CPU peak, memory overflow), bottlenecks can be warned in advance, simulation interruptions or performance degradation due to resource exhaustion can be avoided, and stable operation of simulation tasks can be ensured; on the other hand, the maximum resource usage information is determined through the resource usage information and overall resource usage information of the simulation task at each moment to ensure the accuracy of the maximum resource usage information, which can not only provide accurate and powerful data support for the parallelism setting of the subsequent job scheduling system, but also optimize resource allocation, thereby improving the utilization rate of the job scheduling system and accelerating the overall execution speed of the simulation task.

[0051] In some embodiments, the generation method further includes steps S1201 to S1203, wherein: Step S1201: periodically obtain the status of at least one second simulation task and at least one third simulation task through the task status acquisition interface provided by the job scheduling system; wherein the third simulation task is a simulation task in the simulation task set that has not been run.

[0052] Here, the task status acquisition interface is primarily used to obtain the status of each simulation task. The status of a simulation task may include, but is not limited to, queued, running, and completed. During implementation, each simulation task is in a queued state after being submitted to the job scheduling system. When the job scheduling system executes a simulation task, the status of the simulation task may be updated to running. After the job scheduling system completes execution of a simulation task, the status of the simulation task may be updated to completed.

[0053] The timing can be any suitable duration. For example, 10 seconds, 1 minute, etc. During implementation, the status of the simulation task can be obtained by entering the simulation task identifier into the task status acquisition interface. It is understood that only the status of running simulation tasks and unrunning simulation tasks need to be obtained; the status of completed simulation tasks is no longer required.

[0054] Step S1202: In response to detecting that the state of any of the third simulation tasks is switched to the running state, add the third simulation task to the running queue.

[0055] Here, the run queue is mainly used to store various running simulation tasks. The length of the run queue is not less than the parallelism of the job scheduling system. During implementation, when the state of a non-running simulation task is switched to the running state, it is pushed into the run queue.

[0056] Step S1203: In response to detecting that the state of any second simulation task is switched to a completed state, popping the second simulation task from the running queue.

[0057] Here, when the state of a running simulation task is switched to the completed state, it is removed from the running queue to facilitate the entry of a new simulation task.

[0058] In the embodiment of the present disclosure, the status of each simulation task is obtained at regular intervals so as to facilitate subsequent timely and accurate monitoring of the simulation task.

[0059] In some embodiments, the step S122 of “determining the maximum resource usage information of the second simulation task based on the resource usage information of the second simulation task at the current moment” includes steps S1221 to S1222, wherein: Step S1221: If the resource usage information of the second simulation task at the current moment is greater than the maximum resource usage information of the second simulation task, update the maximum resource usage information of the second simulation task to the resource usage information of the second simulation task at the current moment; Step S1222: When the resource usage information of the second simulation task at the current moment is not greater than the maximum resource usage information of the second simulation task, the maximum resource usage information of the second simulation task is kept unchanged.

[0060] Here, after obtaining the resource usage information of the second simulation task at a certain moment, it is determined whether the resource usage information at that moment is greater than the current maximum resource usage information. If so, the current maximum resource usage information is updated. It is understandable that, at the initial moment, the maximum resource usage information of the second simulation task can be a default value.

[0061] In the embodiment of the present disclosure, the maximum resource usage information is determined by comparing the resource usage information at the current moment with the current maximum resource usage information, thereby improving the accuracy of the maximum resource usage information.

[0062] In some embodiments, the generation method further includes step S124, wherein: Step S124: Serialize and store the resource usage information of the second simulation task at the current moment.

[0063] Here, the resource usage information of the second simulation task at the current moment can be stored in the file corresponding to the second simulation task. During implementation, the files corresponding to each simulation task can be the same or different. If the files corresponding to each simulation task are different, then the resource usage information of the second simulation task at the current moment can be serialized and stored in its corresponding file; if the files corresponding to each simulation task are the same, then when storing the resource usage information of the second simulation task at the current moment, other information of the second simulation task (for example, name, identification, etc.) can be stored at the same time to facilitate the subsequent distinction of the resource usage information of each second simulation task. In some embodiments, the resource usage information of the second simulation task at each moment can also be stored in the cloud.

[0064] In the embodiment of the present disclosure, during the execution of the second simulation task, the resource usage information of the second simulation task at each moment is stored, providing strong data support for subsequent simulation report generation, review, problem tracing, design optimization, etc.

[0065] In some implementations, the step S123 of “determining the maximum resource usage information of the first simulation task based on the overall resource usage information of the first simulation task” includes steps S1231 to S1232, wherein: Step S1231: If the overall resource usage information of the first simulation task is greater than the maximum resource usage information of the first simulation task, update the maximum resource usage information of the first simulation task to the overall resource usage information of the first simulation task; Step S1232: When the overall resource usage information of the first simulation task is not greater than the maximum resource usage information of the first simulation task, the maximum resource usage information of the first simulation task is kept unchanged.

[0066] Here, after the first simulation task is completed, the overall resource usage information of the first simulation task is compared with the current maximum resource usage information of the first simulation task to obtain the final maximum resource usage information of the first simulation task. It is understandable that the maximum resource usage information of the first simulation task is the maximum resource usage information determined at the last moment of the corresponding second simulation task.

[0067] In the disclosed embodiment, the final maximum resource usage information is determined by comparing the overall resource usage information and the maximum resource usage information, thereby improving the accuracy of the final maximum resource usage information and providing data support for the parallelism setting of the subsequent job scheduling system.

[0068] In some embodiments, the generation method further includes step S125 and / or step S126, wherein: Step S125: Store the maximum resource usage information of the first simulation task in a file corresponding to the first simulation task.

[0069] Here, the maximum resource usage information may include but is not limited to maximum memory usage, memory peak, maximum CPU occupancy, maximum I / O load, etc. During implementation, the files corresponding to each simulation task may be the same or different. If the files corresponding to each simulation task are different, then, after a certain simulation task is executed, the maximum resource usage information of the simulation task is stored in its corresponding file; if the files corresponding to each simulation task are the same, then, when storing the maximum resource usage information of the simulation task, other information of the simulation task (for example, name, identification, etc.) can be stored at the same time to facilitate subsequent distinction of the maximum resource usage information of each simulation task. In some embodiments, the file corresponding to the simulation task can also be used to store the resource usage information of the simulation task at each moment.

[0070] Step S126: Obtain coverage information corresponding to the first simulation task.

[0071] Here, coverage information may include but is not limited to code coverage, function coverage, etc.

[0072] Code coverage reflects the adequacy of testing. Code coverage is a static metric that can include, but is not limited to, branch coverage, line coverage, condition coverage, flip coverage, and state machine coverage. Code coverage is automatically calculated by simulation tools to measure the execution of the design code and the extent to which the test traverses the code structure. Branch coverage checks whether all branch paths of each conditional statement are triggered. Line coverage measures the percentage of executable code lines that are executed. Condition coverage checks the true and false value combinations of each subcondition in a Boolean expression. Flip coverage records the bit transitions of signals or registers (0→1 and 1→0) and is used to verify dynamic behavior. State machine coverage verifies whether the state machine traverses all states and legal state transition paths.

[0073] Functional coverage reflects code correctness. Power coverage is a dynamic metric that can include, but is not limited to, assertion coverage and test point coverage. Assertion coverage monitors the number of times assertions in a design are triggered or violated, allowing for real-time error detection or signal sequence verification. Test point coverage quantifies the key functional scenarios defined in the verification plan (e.g., whether the "FIFO overflow handling" scenario is tested).

[0074] During implementation, after a simulation task is completed, the coverage information corresponding to the simulation task is obtained from the simulation tool and stored for subsequent analysis. It is understood that the coverage information corresponding to the simulation task can be stored locally or in the cloud.

[0075] In some implementations, the coverage information corresponding to each simulation task may be aggregated to obtain coverage information of the chip to be simulated, and finally the coverage information of the chip to be simulated may be presented through a visual simulation report.

[0076] In an embodiment of the present disclosure, after the first simulation task is completed, the maximum resource usage information of the first simulation task is stored and the coverage information corresponding to the first simulation task is obtained, providing strong data support for subsequent review, problem tracing, design optimization, etc.

[0077] In some embodiments, the multi-mode matcher includes a first matcher that processes the simulation in the compile phase and a second matcher that processes the simulation in the run phase; step S13 includes steps S131 to S133, wherein: Step S131: Utilize the first matcher to analyze the simulation log corresponding to each of the first simulation tasks to obtain first log analysis information of each of the first simulation tasks in the compilation phase.

[0078] Here, the first matcher is mainly used to handle problems in the compilation stage. For example, syntax errors, undefined identifiers, pattern mismatches, etc. During implementation, the first matcher is mainly for texts starting with ERROR errors in the compilation stage. The first matcher has a built-in compilation regular expression library, which includes at least one regular expression for identifying compilation problems. If there is content in the simulation log that matches the regular expression, it indicates that there is a compilation problem, and it is added to the first log analysis. It is understandable that the compilation regular expression library should be related to the compiler of the simulation tool.

[0079] Step S132: Utilize the second matcher to analyze the simulation log corresponding to each of the first simulation tasks to obtain second log analysis information of each of the first simulation tasks in the running phase.

[0080] Here, the second matcher is mainly used to handle problems existing in the running stage. The second matcher may include but is not limited to a standard matcher, a custom matcher, etc.

[0081] The standard matcher is mainly used for standard printing error information in the simulation tool. The standard matcher has a built-in first regular expression library, which includes at least one regular expression for identifying standard printing content. If there is content matching the regular expression in the simulation log, it indicates that there is a running problem and it is added to the second log analysis. The standard printing content is related to the simulation tool. For example, for simulation tools such as VCS and XRUN, the standard printing content refers to UVM printing, and UVM printing includes UVM_INFO, UVM_WARNING, UVM_ERROR, and UVM_FATAL. Among them, UVM_INFO is used to print general debugging information. UVM_WARNING indicates a non-fatal warning, which prompts potential problems but does not interrupt the simulation. UVM_ERROR records simulation errors and terminates the simulation by default after a certain number of accumulations. UVM_FATAL indicates a fatal error and terminates the simulation immediately after triggering. It can be understood that the various regular expressions in the first regular expression library can be dynamically self-configured according to the simulation tool.

[0082] The custom matcher is mainly used to process custom error messages, that is, non-standard printing errors. The custom matcher has a built-in second regular expression library, which includes at least one regular expression for identifying non-standard printing content. If there is content matching the regular expression in the simulation log, it indicates that there is an operational problem and is added to the second log analysis. For example, a custom regular expression can be used to determine if a test case has failed to execute. If there is content matching the regular expression in the simulation log, it indicates that the test case has failed to execute.

[0083] Step S133 : Aggregate the first log analysis information of each first simulation task in the compiling phase and the second log analysis information of each first simulation task in the running phase to obtain the log analysis information.

[0084] Here, the log analysis information may include error type, error number, and location of each error. The first log analysis information and the second log analysis information may be aggregated simultaneously, or separately. During implementation, any suitable existing tool capable of information aggregation may be used, or software code may be utilized to dynamically aggregate the analysis information.

[0085] In the embodiment of the present disclosure, on the one hand, by setting a first matcher in the compilation phase and a second matcher in the runtime phase, only the regular expressions in the corresponding matchers are matched during the log analysis process, which can speed up the matching speed of the current phase and reduce the interference between them. On the other hand, by aggregating compilation phase errors (such as syntax and semantic errors) and runtime phase errors (such as logical exceptions), first, through the aggregation mechanism, the compilation phase can report the location and type (such as line number, error nature) of multiple errors at one time, avoiding the termination of the compilation process due to a single error, thereby saving debugging time and accelerating iteration; second, runtime phase error aggregation (such as unified exception handling) allows centralized processing of exception logic, separating business code from error recovery logic, making the code more concise and easy to maintain; finally, it provides user-friendly error information, while facilitating log troubleshooting and context recording; finally, compilation phase error aggregation exposes problems in the early stages of development, reduces the error rate during runtime, and combined with runtime exception monitoring, it can form a full life cycle error defense system, reducing later debugging costs and system crash risks.

[0086] In some embodiments, the generating method further includes steps S141 and S142, wherein: Step S141 : Aggregate the coverage information corresponding to each of the first simulation tasks to obtain coverage information of the chip to be simulated.

[0087] Here, coverage information may include, but is not limited to, code coverage, functional coverage, etc. Code coverage may include, but is not limited to, branch coverage, line coverage, condition coverage, flip coverage, state machine coverage, etc. Power coverage may include, but is not limited to, assertion coverage, test point coverage, etc.

[0088] During implementation, after each first simulation task is completed, coverage information corresponding to the first simulation task can be obtained from the simulation tool. In some implementations, aggregation of coverage information can be dynamically implemented using existing tools (eg, urg) or software code.

[0089] Step S142 : Generate a visual simulation report based on the simulation results of each of the first simulation tasks, the coverage information of the chip to be simulated, and the simulation information of the chip to be simulated.

[0090] Here, the simulation results may include but are not limited to a first simulation result, a second simulation result, etc. The first simulation result indicates a successful simulation, and the second simulation result indicates a failed simulation. The simulation result may be a result output by a simulation tool, or a result generated based on simulation information. In some embodiments, if the simulation information indicates that the first simulation task has a compilation error, a runtime error, etc., the second simulation result is used as the simulation result of the first simulation task; otherwise, the first simulation result is used as the simulation result of the first simulation task.

[0091] Coverage information may include but is not limited to code coverage, functional coverage, etc.

[0092] In some embodiments, the visual simulation report can be generated using any suitable charting tool (e.g., echarts), software code, etc. For example, simulation results, simulation information, coverage information, etc. can be converted into charts using echarts. In some embodiments, the visual simulation report can be stored or forwarded via email, messaging tools, etc. It is understood that the visual simulation report can be stored locally or in the cloud.

[0093] In the embodiment of the present disclosure, on the one hand, by aggregating the coverage information corresponding to each simulation task to obtain the coverage information of the chip to be simulated, first, since a single test case is difficult to cover all boundary scenarios, the aggregate analysis can integrate the coverage data of multiple test cases, expose the overall verification loopholes, thereby eliminating coverage blind spots, and comprehensively evaluate the verification integrity; secondly, it can automatically identify code areas with repeated coverage, avoid repeated execution of invalid test cases, and optimize regression test resource allocation; finally, by analyzing the coverage information of each test case, it is easy to identify efficient test case combinations, thereby optimizing subsequent verification strategies. On the other hand, by converting data into a visual report, not only can complex information be simplified and understanding efficiency improved, but also data change trends and correlations between variables can be displayed intuitively and clearly, assisting in discovering deep information.

[0094] Based on the above embodiments, the present disclosure also provides a system for generating simulation information. Figure 2A schematic diagram of the structure of a simulation information generation system provided in an embodiment of the present disclosure Figure 1 ,like Figure 2 As shown, the generation system 20 includes: The task scheduling adaptation module 21 is used to submit the simulation task set corresponding to the chip to be simulated to the job scheduling system; wherein the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel at the same time; a resource monitoring module 22, configured to determine maximum resource usage information of each first simulation task based on resource usage information of at least one first simulation task; wherein the first simulation task is a completed simulation task in the simulation task set; The log analysis engine 23 is configured to analyze the simulation log corresponding to each of the first simulation tasks using a preset multi-pattern matcher to generate log analysis information; The information generation module 24 is used to generate simulation information of the chip to be simulated based on the log analysis information and the maximum resource usage information of each of the first simulation tasks; wherein the simulation information is used for at least one of the following: generating a visual simulation report, determining the parallelism of the job scheduling system.

[0095] Here, the task scheduling adapter module 21 can be any suitable module that can implement this function. The task scheduling adapter module 21 is mainly used to connect to various job scheduling systems, such as LSF, Slurm, etc. The task scheduling adapter module 21 can submit the simulation task set to the job scheduling system according to the task submission interface provided by the job scheduling system. During implementation, the process of the task scheduling adapter module 21 submitting the simulation task set to the job scheduling system can be referred to the specific implementation method of the aforementioned step S11.

[0096] The resource monitoring module 22 can be any suitable module capable of implementing this function. For example, the resource monitoring module 22 can be implemented in a language such as Golang or Python. The resource monitoring module 22 primarily obtains resource usage information for each first simulation task through a resource acquisition interface provided by the job scheduling system, and determines the maximum resource usage information for the first simulation task. For implementation, please refer to the specific implementation of the aforementioned step S12.

[0097] The log analysis engine 23 can be any suitable module that can implement this function. For example, the log analysis engine 23 can be implemented using a language such as Golang. The log analysis engine 23 is mainly used to perform structured analysis on each simulation log through a multi-pattern matcher. When implementing it, please refer to the specific implementation of the aforementioned step S13.

[0098] In some embodiments, the log analysis engine 23 can also be used to separately count the resource usage information (for example, maximum memory usage, CPU time consumption, etc.) of each first simulation task during the compilation phase and the running phase of the simulation process, forming a resource consumption detail to facilitate the subsequent generation of a simulation report.

[0099] The information generation module 24 can be any suitable module capable of implementing this function. The simulation information of the chip to be simulated includes at least log analysis information and maximum resource usage information of each first simulation task. In some embodiments, the simulation information may also include resource usage information of each first simulation task at each moment. During implementation, please refer to the specific implementation of the aforementioned step S14.

[0100] In some embodiments, the generation system 20 also includes a data visualization module and / or a notification distribution module; the data visualization module is used to generate a visual simulation report based on the simulation results of each of the first simulation tasks, the coverage information of the chip to be simulated, and the simulation information of the chip to be simulated; the notification distribution module is used to push the visual simulation report to a preset recipient.

[0101] Here, the data visualization module can be any suitable module that can realize this function. The data visualization module is mainly used to organize data to form a visual simulation report.

[0102] The simulation results may include but are not limited to a first simulation result, a second simulation result, etc. The first simulation result indicates a successful simulation, and the second simulation result indicates a failed simulation.

[0103] The coverage information of the chip to be simulated may include but is not limited to code coverage, function coverage, etc. The completeness of the simulation can be effectively evaluated and verified through the coverage information.

[0104] In some implementations, due to the advantages of echarts such as wide cross-platform compatibility, rich charts, and high flexibility, simulation results, simulation information, coverage information, etc. can be converted into parameters that meet the echarts conditions, and the corresponding visual charts can be returned through echarts.

[0105] During implementation, the process of the data visualization module generating a visualization simulation report may refer to the specific implementation of the aforementioned step S142.

[0106] The notification distribution module can be any suitable module capable of implementing this functionality. Push methods may include, but are not limited to, email, messaging tools, and the like. In some embodiments, simulation reports can be pushed via SMTP, webhooks, and the like. The recipients can be pre-defined. The number of recipients can be at least one. In some embodiments, the notification distribution module can be implemented using Golang.

[0107] In the disclosed embodiments, on the one hand, data is converted into visual reports through a data visualization module, which not only simplifies complex information and improves understanding efficiency, but also intuitively and clearly displays data change trends and correlations between variables, assisting in discovering deep information; on the other hand, visual simulation reports are automatically pushed to relevant personnel through a notification distribution module, realizing real-time information sharing.

[0108] Figure 3 A schematic diagram of the structure of a simulation information generation system provided in an embodiment of the present disclosure Figure 2 ,like Figure 3 As shown, the generation system 20 is implemented using a distributed microservice architecture, and mainly includes a task scheduling adaptation module 21, a resource monitoring module 22, a log analysis engine 23, an information generation module 24, a data visualization module 25 and a notification distribution module 26, wherein: Task scheduling adaptation module 21: mainly responsible for connecting with various job scheduling systems (such as LSF, Slurm), and supporting the reception of task submission requests through standardized interfaces.

[0109] Resource monitoring module 22: A program implemented based on Golang / python, which regularly collects simulation task resource usage data (corresponding to the aforementioned resource usage information) and stores it in the program memory. After the simulation task is completed, the resource usage data is stored in a designated file.

[0110] Log analysis engine 23: integrated multi-pattern regular matcher (corresponding to the aforementioned multi-pattern matcher), supporting dynamic loading of user-defined rule sets.

[0111] Information generation module 24: generates simulation information based on the log analysis information obtained by the log analysis engine 23 and the maximum resource usage information of each simulation task generated by the resource monitoring module 22; Data visualization module 25: Generate parameters that meet the echarts conditions through golang, and then return the graph (corresponding to the aforementioned visualization report).

[0112] Notification distribution module 26: supports SMTP, Webhook and other multi-protocol message push for the visualization report.

[0113] The following uses a digital chip as an example of a chip to be simulated to illustrate the technical solution provided by the embodiment of the present disclosure.

[0114] In digital chip verification projects, the verification process based on traditional simulation tools has systemic flaws, specifically the following problems: 1. Bottleneck of single-round simulation data processing Existing simulation tools (such as VCS and ModelSim) output verification information in text format to a console or log file. Manual log analysis is feasible in small- to medium-sized verification scenarios (such as IP-level verification). However, in advanced process chip verification, the log volume generated by a single simulation can reach terabytes (typically, GPU chip verification logs can exceed 1 billion lines or more). Traditional manual analysis methods cannot meet engineering requirements in terms of efficiency (long processing time for a single log) and completeness (high rate of missed detection of critical timing information). While keyword searches can be performed using tools like grep, these tools only support static text matching and cannot perform multi-dimensional data correlation analysis (such as cross-analysis of functional coverage and timing violations), dynamic data flow tracing (such as visualization of cross-clock domain signal transmission paths), and intelligent identification of abnormal patterns (such as intermittent metastable errors).

[0115] 2. Multi-round regression verification management dilemma Verification strategies that employ random stimuli, such as the UVM verification methodology, require hundreds of repeated simulations to cover all possible scenarios. Taking PCIe 6.0 protocol verification as an example, a single regression test can generate hundreds or even more log files. Traditional automation tools can only aggregate basic data (such as counting the number of passes and fails) but are unable to address test case execution efficiency evaluation (such as the resource utilization distribution of each test sequence), quantitative analysis of random scenario coverage (such as the trigger frequency of specific exception injection scenarios), or cross-version regression result comparison (such as the impact of different compilation options on verification results).

[0116] 3. Deficiencies in information presentation and collaboration efficiency The output interface of existing verification tools is limited to command line mode and lacks intuitive data visualization capabilities. For example, real-time status monitoring is missing: simulation progress (such as the completion percentage of each stage) and resource consumption curves (CPU / Memory usage) cannot be dynamically displayed; the abnormal warning mechanism is weak: alarms can only be triggered by fixed keywords, and potential risks (such as timing margins approaching thresholds) cannot be identified; collaboration efficiency is low: verification results need to be manually screenshot / organized and then sent via email, which extends the problem feedback cycle by 4-6 hours. 4. Defects of relying on string matching to complete use case status judgment First, the lack of semantic recognition leads to a high risk of misjudgment. Since words like "error" and "fail" are often used as signal names or register identifiers in digital chip design, using plain text keyword matching can easily misinterpret normal design elements as verification anomalies. For example, in PCIe bus verification, if there is a status register named "data_error_flag," a simple string match could misinterpret a normal state transition of that signal as a verification failure.

[0117] Second, the lack of a standardized analysis framework makes verification results less reliable. Existing methods lack a unified log parsing standard, making it difficult to distinguish between design names and actual error messages, and to categorize errors. This unstructured analysis approach cannot accurately identify different types of verification defects, such as timing violations, functional anomalies, and resource conflicts. This leads to a high rate of missed detections for critical issues, severely impacting verification efficiency and chip design quality.

[0118] Therefore, in order to solve the above problems, the generation system provided by the present disclosure mainly includes the following functions: 1) Build an automated log parsing engine: This engine uses natural language processing technology to achieve semantic understanding and structured analysis of simulation logs, automatically identifying and classifying various verification events (such as timing violations, assertion failures, and resource overflows). This addresses issues such as high misjudgment rates and a lack of typological analysis capabilities caused by traditional keyword matching methods.

[0119] 2) Realize real-time simulation status monitoring and prediction 3) Ability to visualize simulation results in multiple dimensions 4) Establish automated notification and decision support mechanisms: When resource monitoring reaches a threshold or simulation is completed, formatted reports are pushed via email, instant messaging tools, etc. Each function can be implemented as follows: 1. Implementation of task resource monitoring mechanism When the user submits the simulation task to the job scheduling system (such as LSF, or other distributed resource management systems) through a script (for example, using instructions such as bsub and srun to submit the simulation task), the monitoring module built in the Golang language on the back end of the generation system is automatically connected. During the execution of the simulation task, the monitoring module will query the real-time resource usage data of the simulation task (corresponding to the aforementioned first resource usage information) through instructions every preset time (for example, 1 minute) and record it. After the simulation task is completed, it will further obtain resource usage data such as overall memory usage and peak value through instructions, compare the overall resource usage data with the real-time resource usage data recorded during the execution process, and take the maximum value as the final result (that is, the maximum resource usage data of the simulation task) to ensure the accuracy of the data.

[0120] 2. Implementation process of automated analysis of simulation results After the simulation task is completed, the golang backend server will do the following things in sequence: 1) Resource usage analysis: statistics on the maximum memory usage and CPU time consumed during the compilation phase and the running phase of the simulation process, forming a detailed resource consumption chart.

[0121] 2) Log text parsing: Use regular expression matching technology to perform structured analysis on the log files in the simulation directory: The first is compilation error diagnosis. For errors starting with ERROR during the compilation phase, a predefined regular expression library (corresponding to the first matcher mentioned above) is used to accurately identify different types of compilation problems, such as syntax errors, undefined identifiers, and pattern mismatches.

[0122] Then, the information printed by UVM is divided into UVM_INFO, UVM_WARNING, UVM_ERROR, and UVM_FATAL statistics. Focus on tracking UVM_WARNING, UVM_ERROR, and UVM_FATAL, locate the first error message, and aggregate subsequent similar error logs to assist in troubleshooting the root cause of the problem.

[0123] Finally, there is the custom output detection. For user-defined non-UVM standard print content, it is matched through the pre-configured regular expression in the detection script. If the match is successful, it is determined to be compatible with the custom output. For example, the corresponding test case execution fails.

[0124] 3) Result integration and visualization: After completing the above information capture, the generation system automatically determines whether there are any errors in the simulation. Combined with key indicators such as coverage, the resource usage data, the above log analysis results and simulation conclusions are generated through Golang into parameters that meet the echarts conditions, and integrated to generate a visual chart (corresponding to the aforementioned simulation report).

[0125] 4. Multi-channel push of simulation results. The generation system supports access to the mail server via the SMTP protocol. Based on the default mail list or the parameters specified by the script, the simulation information or simulation report will be sent to various email addresses in batches, realizing real-time information sharing.

[0126] Figure 4 A schematic diagram of the implementation process of a method for generating simulation information provided in an embodiment of the present disclosure Figure 2 ,like Figure 4 As shown, the generation method includes steps S401 to S409, wherein: Step S401: After determining the simulation tool and the scheduling tool (corresponding to the aforementioned job scheduling system), execute the script; Here, you can customize simulation tools, scheduling tools, etc. through interfaces, files, etc. Since different scheduling tools provide different interfaces and functions, you need to determine the scheduling tool you are currently using to ensure the normal execution of subsequent work.

[0127] Step S402: The backend server (corresponding to the generation system) exposes the application port and continuously receives the simulation monitoring request of the script; Step S403: The script sends data such as the process identifier (corresponding to the aforementioned simulation task), regular expression matching (corresponding to the aforementioned multi-pattern matcher) to the background server; Step S404: The backend server receives the data and starts monitoring the simulation data throughout the process; Step S405: The backend server accesses the scheduling tool at regular intervals to query resource usage information of the corresponding process; Step S406: After the simulation is completed, the script sends an instruction to end the process; Step S407: The backend server compares and records resource usage information; Here, the recorded real-time resource usage information and the overall resource usage information are compared, and the highest one is taken as the maximum resource usage information.

[0128] Step S408: The backend server reads the simulation log; Step S409: The backend server processes the simulation log, organizes it and resource usage information into a report form, and sends it to a designated mailbox.

[0129] Then, the technical solution disclosed in this disclosure can bring the following beneficial effects: 1. Intelligent log parsing enables efficient and accurate analysis The intelligent simulation log parsing engine (corresponding to the aforementioned log analysis engine 23) constructed in this disclosure uses natural language processing algorithms to automatically identify relevant error messages related to key information in logs, overcoming the limitations of traditional keyword matching. Compared to manual analysis, this solution can increase log parsing efficiency by several times and significantly reduce the error rate. Through automated data extraction and classification, the need for manually pre-setting search keywords is eliminated, reducing repetitive labor while ensuring the completeness and accuracy of verification results analysis, significantly improving the efficiency of digital chip verification.

[0130] Providing custom regular expression input and corresponding information classification can provide customized information output (for example, adding a new indicator detection).

[0131] 2. Realize dynamic resource monitoring and intelligent scheduling The resource monitoring module developed based on Golang / python realizes the full life cycle tracking of simulation tasks through deep integration with the job scheduling system. The monitoring module regularly collects multiple core indicators such as the simulation task status (for example, queue status, running status, abnormal status), the resource usage of the simulation resources in the running state (for example, CPU usage, memory consumption, I / O load), and stores them in real time to the running memory. After completion, they will be directly stored to the specified location on the hard disk. After actual testing, this mechanism can predict resource bottlenecks and assist engineers in dynamically adjusting simulation strategies. For example, the optimal number of concurrent tasks is automatically calculated based on the remaining resources of the job scheduling system and the resources required for the simulation task. Under the premise of ensuring the completion of regression testing, resource utilization is greatly improved, effectively avoiding the extension of the verification cycle due to insufficient resources.

[0132] 3. Automated notification and full-cycle data management An innovative automated simulation result notification mechanism supports user-defined email sending strategies (such as task completion, exception triggering, and periodic summaries). This email automatically generates a structured report covering core information such as test case pass rates (down to the execution details of a single test case), key performance indicator comparisons, and abnormal event classification statistics, forming standardized verification documentation. This feature not only enables engineers to shift from "passive monitoring" to "active response," significantly reducing wait time, but also addresses the long-term storage limitations of log files in traditional verification processes due to limited storage space. Through cloud-based storage and versioning, the retention rate of critical verification data has increased to 100%, providing comprehensive data support for subsequent project reviews, problem tracing, and design optimization.

[0133] In some implementations, the resource monitoring module 22 is further configured to serialize and store the resource usage information of the second simulation task at the current moment.

[0134] In some implementations, the resource monitoring module 22 is further configured to store the maximum resource usage information of the first simulation task in a file corresponding to the first simulation task; and / or obtain coverage information corresponding to the first simulation task.

[0135] In some embodiments, the resource monitoring module 22 is also used to periodically obtain the status of at least one second simulation task and at least one third simulation task through the task status acquisition interface provided by the job scheduling system; wherein, the third simulation task is a non-running simulation task in the simulation task set; in response to detecting that the status of any of the third simulation tasks is switched to a running state, the third simulation task is added to the running queue; in response to detecting that the status of any of the second simulation tasks is switched to a completed state, the second simulation task is removed from the running queue.

[0136] In some implementations, the log analysis engine 23 is further configured to aggregate the coverage information corresponding to each of the first simulation tasks to obtain coverage information of the chip to be simulated.

[0137] The description of the above system embodiment is similar to the description of the above method embodiment and has similar beneficial effects as the method embodiment. For technical details not disclosed in the system embodiment of the present disclosure, please refer to the description of the method embodiment of the present disclosure for understanding.

[0138] It should be noted that in the embodiments of the present disclosure, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present disclosure, or the part that contributes to the relevant technology, can be embodied in the form of a software product. The software product is stored in a storage medium and includes a number of instructions for enabling an electronic device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk. In this way, the embodiments of the present disclosure are not limited to any specific combination of hardware and software.

[0139] The present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the above methods. The computer-readable storage medium may be transient or non-transient.

[0140] The present disclosure provides a computer program product comprising a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, the computer program implements some or all of the steps of the above-described method. The computer program product may be implemented in hardware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK).

[0141] It should be noted that Figure 5 A hardware entity diagram of an electronic device provided in an embodiment of the present disclosure, such as Figure 5 As shown, the hardware entity of the electronic device 500 includes: a processor 501, a communication interface 502 and a memory 503, wherein: The processor 501 generally controls the overall operations of the electronic device 500 .

[0142] The communication interface 502 enables the electronic device to communicate with other terminals or servers through a network.

[0143] Memory 503 is configured to store instructions and applications executable by processor 501. It can also cache data to be processed or processed by processor 501 and various modules in electronic device 500 (e.g., image data, audio data, voice communication data, and video communication data). This can be implemented using flash memory (FLASH) or random access memory (RAM). Data can be transmitted between processor 501, communication interface 502, and memory 503 via bus 504.

[0144] It should be noted that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0145] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0146] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0147] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0148] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, the various functional units in the embodiments of the present disclosure may all be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0149] Those skilled in the art will understand that all or part of the steps of the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, and other media that can store program codes.

[0150] Alternatively, if the above-mentioned integrated units of the present disclosure are implemented in the form of software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the relevant technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes a number of instructions for enabling an electronic device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of the present disclosure. The aforementioned storage medium includes: various media that can store program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0151] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A method for generating simulation information, characterized in that: include: Submitting a simulation task set corresponding to the chip to be simulated to a job scheduling system; wherein the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel at the same time; Determining maximum resource usage information of each first simulation task based on resource usage information of at least one first simulation task; wherein the first simulation task is a completed simulation task in the simulation task set; Analyze the simulation log corresponding to each of the first simulation tasks using a preset multi-pattern matcher to generate log analysis information; Based on the log analysis information and the maximum resource usage information of each of the first simulation tasks, simulation information of the chip to be simulated is generated; wherein, the simulation information is used for at least one of the following: generating a visual simulation report, determining the parallelism of the job scheduling system.

2. The generation method according to claim 1, characterized in that The determining, based on the resource usage information of at least one first simulation task, the maximum resource usage information of each first simulation task includes: Regularly obtain resource usage information of at least one second simulation task in the running queue at the current moment through a first resource acquisition interface provided by the job scheduling system; wherein the second simulation task is a running simulation task in the simulation task set; For each second simulation task, determining maximum resource usage information of the second simulation task based on resource usage information of the second simulation task at a current moment; In response to detecting that the state of any second simulation task is switched to a completed state, the second simulation task is treated as a first simulation task, and the overall resource usage information of the first simulation task is obtained through the second resource acquisition interface provided by the job scheduling system. Based on the overall resource usage information of the first simulation task, the maximum resource usage information of the first simulation task is determined.

3. The generation method according to claim 2, characterized in that The determining the maximum resource usage information of the second simulation task based on the resource usage information of the second simulation task at the current moment includes: if the resource usage information of the second simulation task at the current moment is greater than the maximum resource usage information of the second simulation task, updating the maximum resource usage information of the second simulation task to the resource usage information of the second simulation task at the current moment; if the resource usage information of the second simulation task at the current moment is not greater than the maximum resource usage information of the second simulation task, keeping the maximum resource usage information of the second simulation task unchanged; The generation method further includes: serializing and storing the resource usage information of the second simulation task at the current moment.

4. The generation method according to claim 2, characterized in that The determining, based on the overall resource usage information of the first simulation task, the maximum resource usage information of the first simulation task, comprises: updating the maximum resource usage information of the first simulation task to the overall resource usage information of the first simulation task if the overall resource usage information of the first simulation task is greater than the maximum resource usage information of the first simulation task; and maintaining the maximum resource usage information of the first simulation task unchanged if the overall resource usage information of the first simulation task is not greater than the maximum resource usage information of the first simulation task; The generation method further includes at least one of the following: storing the maximum resource usage information of the first simulation task in a file corresponding to the first simulation task; and obtaining coverage information corresponding to the first simulation task.

5. The generation method according to claim 2, wherein the characteristic value is: The generating method further comprises: Regularly acquiring the status of at least one second simulation task and at least one third simulation task through a task status acquisition interface provided by the job scheduling system; wherein the third simulation task is an unrunning simulation task in the simulation task set; In response to detecting that the state of any of the third simulation tasks is switched to a running state, adding the third simulation task to the running queue; In response to detecting that the state of any second simulation task is switched to a completed state, the second simulation task is removed from the running queue.

6. The generation method according to claim 1, characterized in that The multi-mode matcher includes a first matcher that processes the simulation in the compile phase and a second matcher that processes the simulation in the run phase; The using of a preset multi-pattern matcher to analyze the simulation log corresponding to each of the first simulation tasks to generate log analysis information includes: Analyzing the simulation log corresponding to each of the first simulation tasks using the first matcher to obtain first log analysis information of each of the first simulation tasks in the compiling phase; Analyzing the simulation log corresponding to each of the first simulation tasks using the second matcher to obtain second log analysis information of each of the first simulation tasks in the running phase; The first log analysis information of each first simulation task in the compiling phase and the second log analysis information of each first simulation task in the running phase are aggregated to obtain the log analysis information.

7. The generation method according to any one of claims 1 to 6, characterized in that: The generating method further comprises: Aggregating the coverage information corresponding to each of the first simulation tasks to obtain coverage information of the chip to be simulated; A visual simulation report is generated based on the simulation results of each of the first simulation tasks, the coverage information of the chip to be simulated, and the simulation information of the chip to be simulated.

8. A system for generating simulation information, characterized in that: include: A task scheduling adaptation module is used to submit a simulation task set corresponding to the chip to be simulated to a job scheduling system; wherein the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel at the same time; a resource monitoring module, configured to determine maximum resource usage information of each first simulation task based on resource usage information of at least one first simulation task; wherein the first simulation task is a completed simulation task in the simulation task set; A log analysis engine, configured to analyze the simulation log corresponding to each of the first simulation tasks using a preset multi-pattern matcher to generate log analysis information; An information generation module is used to generate simulation information of the chip to be simulated based on the log analysis information and the maximum resource usage information of each of the first simulation tasks; wherein the simulation information is used for at least one of the following: generating a visual simulation report, determining the parallelism of the job scheduling system.

9. The generation system according to claim 8, characterized in that Also includes at least one of the following: a data visualization module, configured to generate a visual simulation report based on the simulation results of each of the first simulation tasks, the coverage information of the chip to be simulated, and the simulation information of the chip to be simulated; The notification distribution module is used to push the visual simulation report to a preset recipient.

10. An electronic device comprising a processor and a memory, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

11. A computer-readable storage medium, characterized in that A computer program is stored thereon, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

12. A computer program product, characterized in that The computer program product includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, the method according to any one of claims 1 to 7 is implemented.

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