Method and system for generating simulation information, device, storage medium and program product

Abstract

Embodiments of the present disclosure provide a simulation information generation method and system, device, storage medium and program product, relating to the technical field of integrated circuits, to solve the problems of single round simulation data processing bottleneck, inability to monitor resource usage of simulation tasks, low log analysis efficiency, low accuracy and the like. The generation method comprises: submitting a simulation task set corresponding to a chip to be simulated to a job scheduling system; determining maximum resource usage information of each first simulation task based on resource usage information of at least one first simulation task; wherein the first simulation task is an executed completed simulation task in the simulation task set; using a preset multi-mode matcher to analyze a simulation log corresponding to each first simulation task to generate log analysis information; and generating simulation information of the chip to be simulated based on the log analysis information and the maximum resource usage information of each first simulation task.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of integrated circuit technology, and in particular to a method and system for generating simulation information, an apparatus, a storage medium, and a program product. Background Technology

[0002] In digital chip verification projects, verification processes based on existing simulation tools often suffer from bottlenecks in single-round simulation data processing, inability to monitor information such as resource usage of simulation tasks, and low efficiency and accuracy of log analysis. Summary of the Invention

[0003] This disclosure provides a method, system, device, storage medium, and program product for generating simulation information.

[0004] The technical solution of this disclosure embodiment is implemented as follows:

[0005] This disclosure provides a method for generating simulation information, including:

[0006] The simulation task set corresponding to the chip to be simulated is submitted to the job scheduling system; wherein, the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel.

[0007] Based on the resource usage information of at least one first simulation task, determine the maximum resource usage information of each first simulation task; wherein, the first simulation task is one of the simulation tasks that has been executed and completed in the set of simulation tasks;

[0008] Using a preset multi-pattern matcher, the simulation logs corresponding to each of the first simulation tasks are analyzed to generate log analysis information;

[0009] Based on the log analysis information and the maximum resource usage information of each of the first simulation tasks, simulation information of the chip to be simulated is generated; wherein, the simulation information is used for at least one of the following: generating a visual simulation report, determining the parallelism of the job scheduling system.

[0010] This disclosure provides a simulation information generation system, including:

[0011] A task scheduling adaptation module is used to submit the simulation task set corresponding to the chip to be simulated to the job scheduling system; wherein, the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel.

[0012] A resource monitoring module is used to determine the maximum resource usage information of each of the first simulation tasks based on the resource usage information of at least one first simulation task; wherein, the first simulation task is one of the simulation tasks that has been completed in the set of simulation tasks.

[0013] The log analysis engine is used to analyze the simulation logs corresponding to each of the first simulation tasks using a preset multi-pattern matcher, and generate log analysis information.

[0014] An information generation module is used to generate simulation information for the chip to be simulated based on the log analysis information and the maximum resource usage information for each of the first simulation tasks; wherein the simulation information is used for at least one of the following: generating a visual simulation report, or determining the parallelism of the job scheduling system.

[0015] This disclosure provides an electronic device, including a processor and a memory, wherein the memory stores a computer program that can run on the processor, and the processor executes the computer program to implement the above-described method.

[0016] This disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0017] This disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, the above-described method is implemented.

[0018] In this embodiment, firstly, by submitting the simulation task set to the job scheduling system for execution, multiple simulation tasks can be executed concurrently, greatly improving the processing speed of single-round simulation data. Secondly, by monitoring the resources of each running simulation task, bottlenecks can be warned in advance, avoiding simulation interruptions or performance drops due to resource exhaustion and ensuring stable operation of simulation tasks. Furthermore, resource allocation can be optimized, thereby improving the utilization rate of the job scheduling system and accelerating the overall execution speed of simulation tasks. Thirdly, by analyzing each simulation log through a multi-pattern matcher, the efficiency and accuracy of log analysis are improved. Finally, simulation information is generated based on log analysis information and maximum resource usage information, which not only improves the accuracy and comprehensiveness of simulation information but also provides strong data support for subsequent generation of visualized simulation reports and adjustment of the parallelism of the job scheduling system.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0021] Figure 1 A schematic diagram of the implementation process of a simulation information generation method provided in this embodiment of the present disclosure. Figure 1 ;

[0022] Figure 2 A schematic diagram of the composition structure of a simulation information generation system provided in this embodiment of the disclosure. Figure 1 ;

[0023] Figure 3 A schematic diagram of the composition structure of a simulation information generation system provided in this embodiment of the disclosure. Figure 2 ;

[0024] Figure 4 A schematic diagram of the implementation process of a simulation information generation method provided in this embodiment of the present disclosure. Figure 2 ;

[0025] Figure 5 This is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] In the following description, the terms “first, second, third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first, second, third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0030] The method provided in this disclosure can be executed by an electronic device, which can be a laptop, tablet, desktop computer, set-top box, mobile device (e.g., mobile phone, portable music player, personal digital assistant, dedicated messaging device, portable gaming device), or a server. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0031] The technical solutions in the embodiments of this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0032] Figure 1 A schematic diagram of the implementation process of a simulation information generation method provided in this embodiment of the present disclosure. Figure 1 ,like Figure 1 As shown, the generation method includes steps S11 to S14, wherein:

[0033] Step S11: Submit the simulation task set corresponding to the chip to be simulated to the job scheduling system; wherein, the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel.

[0034] Here, the chip to be simulated can be any suitable chip that needs to be simulated, such as a digital chip. The simulation task can be any suitable task that tests at least some of the functions of the chip to be simulated. In some embodiments, the simulation task can also be called a test case. The various simulation tasks can test different functions or test the same function. For example, the simulation task can be to verify the clock function, arithmetic function, storage function, etc. of a digital chip.

[0035] The job scheduling system can be any suitable system capable of task scheduling. Examples include LSF and Slurm. In some implementations, the job scheduling system can also be a distributed resource management system. The job scheduling system can include multiple nodes, which can concurrently execute simulation tasks with a parallelism of [number missing]. It is understood that the parallelism of the job scheduling system can be dynamically set based on its remaining resources and the resources required by each simulation task.

[0036] The job scheduling system can have a built-in simulation tool to execute the simulation task. This simulation tool can be any suitable tool capable of simulating and testing the hardware functionality of the chip, such as VCS or XRUN. During implementation, the simulation task is executed by calling this simulation tool.

[0037] Step S12: Based on the resource usage information of at least one first simulation task, determine the maximum resource usage information of each first simulation task; wherein, the first simulation task is a simulation task that has been completed in the simulation task set.

[0038] Here, since resource usage information for simulation tasks only becomes available after execution, it's necessary to wait until the simulation task switches to a running state before obtaining its resource usage information. In implementation, this job scheduling system can provide task status acquisition interfaces and resource acquisition interfaces. The task status acquisition interface determines the status of each simulation task, while the resource acquisition interface retrieves the resource usage information of each running or completed simulation task.

[0039] Resource usage information may include, but is not limited to, at least one of the following: overall resource usage information, resource usage information at various times (i.e., local resource usage information). Resource usage information may include, but is not limited to, memory usage information, CPU usage information, and I / O load information. Memory usage information reflects the memory consumption of the first simulation task during execution; this memory usage information may include, but is not limited to, peak memory usage and total memory usage. CPU usage information reflects the CPU consumed by the first simulation task, also known as CPU utilization.

[0040] Maximum resource usage information refers to the highest resource usage information, which may include, but is not limited to, the highest memory usage, the highest CPU usage, and the highest I / O load. The methods for determining this maximum resource usage information may include, but are not limited to, resource usage information at a specific moment, a weighted average of resource usage information at a specific moment, overall resource usage information, and a weighted average of overall resource usage information.

[0041] For example, determine whether the current resource usage information is greater than the current maximum resource usage information. If so, update the current maximum resource usage information to the current resource usage information; otherwise, keep the current maximum resource usage information unchanged; and use the maximum resource usage information determined at the last moment as the final maximum resource usage information.

[0042] For example, determine whether the resource usage information at the final moment is greater than the overall resource usage information. If so, the resource usage information at the final moment is taken as the final maximum resource usage information; otherwise, the overall resource usage information is taken as the final maximum resource usage information.

[0043] Step S13: Using a preset multi-pattern matcher, analyze the simulation logs corresponding to each of the first simulation tasks to generate log analysis information.

[0044] Here, the multi-pattern matcher includes at least one matcher, with different matchers suitable for different stages. In some implementations, the multi-pattern matcher includes a first matcher handling simulation during the compilation stage and a second matcher handling simulation during the runtime stage. The first matcher is primarily used to handle problems existing during the compilation stage, such as syntax errors, undefined identifiers, and pattern mismatches. This first matcher incorporates a built-in compilation regular expression library, which includes at least one regular expression to identify compilation problems. The second matcher is primarily used to handle problems existing during the runtime stage. This second matcher may include, but is not limited to, a standard matcher and a custom matcher. The standard matcher is primarily used for standard printed error messages in the simulation tool. This standard matcher incorporates a first regular expression library, which includes at least one regular expression to identify standard printed content. The custom matcher is primarily used to handle custom error messages, i.e., non-standard printed errors. This custom matcher incorporates a second regular expression library, which includes at least one regular expression to identify non-standard printed content.

[0045] The log analysis information can include error type, error quantity, and the location of various errors. Error types include those from the compilation phase and those from the runtime phase. During implementation, this log analysis information can be obtained by analyzing each simulation log using different matchers.

[0046] Step S14: Based on the log analysis information and the maximum resource usage information of each of the first simulation tasks, generate simulation information for the chip to be simulated; wherein the simulation information is used for at least one of the following: generating a visual simulation report, determining the parallelism of the job scheduling system.

[0047] Here, the simulation information includes at least log analysis information and maximum resource usage information for each first simulation task. In some implementations, the simulation information may also include resource usage information for each first simulation task at various times.

[0048] The simulation information can be generated in any suitable way. In some implementations, a structured generation template can be pre-built, and the log analysis information and the maximum resource usage information of each first simulation task can be filled into the template to obtain the simulation information. In some implementations, the log analysis information and the maximum resource usage information of each first simulation task can also be input into a generative model to obtain the simulation information. The generative model can be any suitable neural network model that can achieve the function.

[0049] During implementation, the simulation information can be stored locally or stored in the cloud and managed in a versioned manner.

[0050] This simulation information can be used to generate visual simulation reports, which can then be automatically pushed to relevant personnel, enabling real-time information sharing. This simulation information can also be synchronized with the job scheduling system, allowing the system to configure its parallelism based on the simulation information and remaining resource information.

[0051] In this embodiment, firstly, by submitting the simulation task set to the job scheduling system for execution, multiple simulation tasks can be executed concurrently, greatly improving the processing speed of single-round simulation data. Secondly, by monitoring the resources of each running simulation task, bottlenecks can be warned in advance, avoiding simulation interruptions or performance drops due to resource exhaustion and ensuring stable operation of simulation tasks. Furthermore, resource allocation can be optimized, thereby improving the utilization rate of the job scheduling system and accelerating the overall execution speed of simulation tasks. Thirdly, by analyzing each simulation log through a multi-pattern matcher, the efficiency and accuracy of log analysis are improved. Finally, simulation information is generated based on log analysis information and maximum resource usage information, which not only improves the accuracy and comprehensiveness of simulation information but also provides strong data support for subsequent generation of visualized simulation reports and adjustment of the parallelism of the job scheduling system.

[0052] In some embodiments, step S12 includes steps S121 to S123, wherein:

[0053] Step S121: Through the first resource acquisition interface provided by the job scheduling system, periodically acquire the resource usage information of at least one second simulation task in the running queue at the current time; wherein, the second simulation task is a running simulation task in the simulation task set.

[0054] Here, the run queue is primarily used to store all currently running simulation tasks. The length of this run queue is no less than the parallelism of the job scheduling system. During implementation, when a simulation task's state changes to running, it is pushed into the run queue; when a simulation task's state changes to completed, it is popped from the run queue. It is understood that the run queue is initially empty.

[0055] The first resource acquisition interface is primarily used to obtain resource usage information for simulation tasks. It's understandable that different job scheduling systems may provide the same or different first resource acquisition interfaces. In implementation, by passing the identifier of the second simulation task to the first resource acquisition interface, the resource usage information of that second simulation task at the current moment can be obtained.

[0056] The timer can be any suitable duration, such as 20 seconds, 1 minute, etc.

[0057] Step S122: For each second simulation task, determine the maximum resource usage information of the second simulation task based on the resource usage information of the second simulation task at the current time.

[0058] Here, after obtaining the resource usage information of a second simulation task at a certain moment, the maximum resource usage information of the second simulation task is determined based on the resource usage information at that moment. For example, if the resource usage information at that moment is greater than the maximum resource usage information, then the resource usage information at that moment, or a weighted average of the resource usage information at that moment, is taken as the maximum resource usage information; if the resource usage information at that moment is not greater than the maximum resource usage information, then the maximum resource usage information can be kept unchanged.

[0059] In some implementations, when an anomaly is detected in the resource usage information of a second simulation task at a certain moment (e.g., exceeding a set threshold), an alarm can be issued in a timely manner to facilitate the normal execution of subsequent simulation tasks.

[0060] Step S123: In response to detecting that the state of any of the second simulation tasks has switched to the completed state, the second simulation task is treated as a first simulation task. The overall resource usage information of the first simulation task is obtained through the second resource acquisition interface provided by the job scheduling system. Based on the overall resource usage information of the first simulation task, the maximum resource usage information of the first simulation task is determined.

[0061] Here, the second resource acquisition interface is mainly used to obtain the overall resource usage information of the first simulation task. This second resource acquisition interface can be the same as or different from the first resource acquisition interface. When the second resource acquisition interface is the same as the first resource acquisition interface, the interface parameters can be used to specify whether to obtain real-time resource usage information or overall resource usage information.

[0062] When the status of a second simulation task is detected to have changed to the completed state, the second simulation task will be updated to the first simulation task, and the maximum resource usage information determined by the second simulation task at the last moment will be used as the maximum resource usage information of the first simulation task.

[0063] The overall resource information represents the overall resource usage of the first simulation task. This overall resource information may include, but is not limited to, overall memory usage, overall peak usage, and overall I / O load.

[0064] Once the overall resource usage information for the first simulation task is obtained, the maximum resource usage information for that task is determined based on this information. For example, if the overall resource usage information is greater than the maximum resource usage information, then the overall resource usage information, or a weighted average of the overall resource usage information, is used as the maximum resource usage information; if the overall resource usage information is not greater than the maximum resource usage information, then the maximum resource usage information can remain unchanged.

[0065] In this embodiment, on the one hand, by monitoring system-level resource consumption in real time (such as CPU peak and memory overflow), bottlenecks can be warned in advance, avoiding simulation interruptions or performance drops due to resource exhaustion, and ensuring the stable operation of simulation tasks. On the other hand, by determining the maximum resource usage information through the resource usage information of the simulation task at each moment and the overall resource usage information, the accuracy of the maximum resource usage information can be ensured. This not only provides accurate and powerful data support for the subsequent parallelism setting of the job scheduling system, but also optimizes resource allocation, thereby improving the utilization rate of the job scheduling system and accelerating the overall execution speed of the simulation task.

[0066] In some embodiments, the generation method further includes steps S1201 to S1203, wherein:

[0067] Step S1201: Obtain the status of at least one second simulation task and at least one third simulation task periodically through the task status acquisition interface provided by the job scheduling system; wherein, the third simulation task is an unrunning simulation task in the simulation task set.

[0068] Here, the task status acquisition interface is mainly used to obtain the status of each simulation task. The status of a simulation task can include, but is not limited to, queued status, running status, and completed status. In implementation, all simulation tasks are in a queued state after being submitted to the job scheduling system. When the job scheduling system executes a simulation task, the status of that simulation task can be updated to running status. When the job scheduling system completes the execution of a simulation task, the status of that simulation task can be updated to completed status.

[0069] The timing can be any suitable duration, such as 10 seconds or 1 minute. During implementation, the status of the simulation task can be obtained by filling in its identifier into the task status acquisition interface. It's understood that only the status of running and non-running simulation tasks needs to be obtained; the status of completed simulation tasks is no longer necessary.

[0070] Step S1202: In response to detecting that the state of any of the third simulation tasks has switched to the running state, the third simulation task is added to the running queue.

[0071] Here, the run queue is primarily used to store all currently running simulation tasks. The length of the run queue is no less than the parallelism of the job scheduling system. In implementation, when a simulation task that is not currently running switches to a running state, it is pushed into the run queue.

[0072] Step S1203: In response to detecting that the state of any of the second simulation tasks has switched to the completed state, pop the second simulation task from the run queue.

[0073] Here, when the status of a running simulation task changes to the completed state, it is removed from the running queue to facilitate the push of new simulation tasks.

[0074] In this embodiment of the disclosure, the status of each simulation task is acquired periodically to facilitate timely and accurate monitoring of the simulation tasks.

[0075] In some implementations, the step S122, "determining the maximum resource usage information of the second simulation task based on the resource usage information of the second simulation task at the current moment," includes steps S1221 to S1222, wherein:

[0076] Step S1221: If the resource usage information of the second simulation task at the current time is greater than the maximum resource usage information of the second simulation task, update the maximum resource usage information of the second simulation task to the resource usage information of the second simulation task at the current time.

[0077] Step S1222: If the resource usage information of the second simulation task at the current moment is not greater than the maximum resource usage information of the second simulation task, keep the maximum resource usage information of the second simulation task unchanged.

[0078] Here, after obtaining the resource usage information of the second simulation task at a certain moment, it is determined whether the resource usage information at that moment is greater than the current maximum resource usage information. If so, the current maximum resource usage information is updated. It can be understood that, initially, the maximum resource usage information of the second simulation task can be a default value.

[0079] In this embodiment of the disclosure, the maximum resource usage information is determined by comparing the current resource usage information with the current maximum resource usage information, thereby improving the accuracy of the maximum resource usage information.

[0080] In some embodiments, the generation method further includes step S124, wherein:

[0081] Step S124: Serialize and store the resource usage information of the second simulation task at the current moment.

[0082] Here, the resource usage information of the second simulation task at the current moment can be stored in the file corresponding to the second simulation task. In implementation, the files corresponding to each simulation task can be the same or different. If the files corresponding to each simulation task are different, then the resource usage information of the second simulation task at the current moment can be serialized and stored in its corresponding file; if the files corresponding to each simulation task are the same, then when storing the resource usage information of the second simulation task at the current moment, other information of the second simulation task (e.g., name, identifier, etc.) can be stored simultaneously to facilitate subsequent differentiation of the resource usage information of each second simulation task. In some embodiments, the resource usage information of the second simulation task at various moments can also be stored in the cloud.

[0083] In this embodiment of the disclosure, during the execution of the second simulation task, the resource usage information of the second simulation task at each moment is stored, providing strong data support for subsequent simulation report generation, review, problem tracing, design optimization, etc.

[0084] In some implementations, the step S123, "determining the maximum resource usage information of the first simulation task based on the overall resource usage information of the first simulation task," includes steps S1231 to S1232, wherein:

[0085] Step S1231: If the overall resource usage information of the first simulation task is greater than the maximum resource usage information of the first simulation task, update the maximum resource usage information of the first simulation task to the overall resource usage information of the first simulation task.

[0086] Step S1232: If the overall resource usage information of the first simulation task is not greater than the maximum resource usage information of the first simulation task, keep the maximum resource usage information of the first simulation task unchanged.

[0087] Here, after the first simulation task is completed, the overall resource usage information of the first simulation task is compared with the current maximum resource usage information of the first simulation task to obtain the final maximum resource usage information of the first simulation task. It can be understood that the maximum resource usage information of the first simulation task is the maximum resource usage information determined by the corresponding second simulation task at the last moment.

[0088] In this embodiment, the final maximum resource usage information is determined by comparing the overall resource usage information and the maximum resource usage information, thereby improving the accuracy of the final maximum resource usage information and providing data support for the subsequent parallelism setting of the job scheduling system.

[0089] In some embodiments, the generation method further includes steps S125 and / or S126, wherein:

[0090] Step S125: Store the maximum resource usage information of the first simulation task in the file corresponding to the first simulation task.

[0091] Here, maximum resource usage information may include, but is not limited to, maximum memory utilization, peak memory usage, maximum CPU utilization, and maximum I / O load. In implementation, the files corresponding to each simulation task may be the same or different. If the files corresponding to each simulation task are different, then after a simulation task is completed, its maximum resource usage information is stored in its corresponding file. If the files corresponding to each simulation task are the same, then when storing the maximum resource usage information of the simulation task, other information about the simulation task (e.g., name, identifier, etc.) can be stored simultaneously to facilitate subsequent differentiation of the maximum resource usage information of each simulation task. In some embodiments, the file corresponding to the simulation task can also be used to store the resource usage information of the simulation task at various times.

[0092] Step S126: Obtain the coverage information corresponding to the first simulation task.

[0093] Here, coverage information may include, but is not limited to, code coverage, feature coverage, etc.

[0094] Code coverage reflects the adequacy of tests. Code coverage is a static metric that can include, but is not limited to, branch coverage, line coverage, condition coverage, inversion coverage, and state machine coverage. Code coverage is automatically calculated by simulation tools to measure the extent to which tests traverse the code structure. Branch coverage checks whether all branch paths of each conditional statement are triggered. Line coverage counts the percentage of executable lines of code that are executed. Condition coverage checks the true / false combinations of each sub-condition in a Boolean expression. Inversion coverage records the bit transitions of signals or registers (0→1 and 1→0) to verify dynamic behavior. State machine coverage verifies whether the state machine traverses all states and the valid state transition paths.

[0095] Functional coverage reflects code correctness. Power coverage is a dynamic metric that may include, but is not limited to, assertion coverage and test point coverage. Assertion coverage monitors the number of times assertions in a design are triggered or violated, used to capture errors or check signal sequences in real time. Test point coverage quantifies the key functional scenarios defined in the verification plan (such as whether the "FIFO overflow handling" scenario has been tested).

[0096] During implementation, after a simulation task is completed, the coverage information corresponding to that simulation task is retrieved from the simulation tool and stored for subsequent analysis. It is understood that the coverage information for this simulation task can be stored locally or in the cloud.

[0097] In some implementations, the coverage information corresponding to each simulation task can be aggregated to obtain the coverage information of the chip to be simulated. Finally, the coverage information of the chip to be simulated can be presented through a visual simulation report.

[0098] In this embodiment of the disclosure, after the first simulation task is completed, the maximum resource usage information of the first simulation task and the coverage information corresponding to the first simulation task are stored, providing strong data support for subsequent review, problem tracing, design optimization, etc.

[0099] In some embodiments, the multi-mode matcher includes a first matcher that processes the simulation during the compilation phase and a second matcher that processes the simulation during the runtime phase; step S13 includes steps S131 to S133, wherein:

[0100] Step S131: Using the first matcher, analyze the simulation logs corresponding to each of the first simulation tasks to obtain the first log analysis information of each of the first simulation tasks during the compilation phase.

[0101] Here, the first matcher is primarily used to handle problems that occur during the compilation phase. Examples include syntax errors, undefined identifiers, and pattern mismatches. In implementation, this first matcher mainly targets text starting with "ERROR" during the compilation phase. This first matcher has a built-in compiler regular expression library, which includes at least one regular expression to identify compilation problems. If the simulation log contains content that matches a regular expression, it indicates a compilation problem, and this content is added to the first log analysis. It is understandable that this compiler regular expression library is related to the compiler of the simulation tool.

[0102] Step S132: Using the second matcher, analyze the simulation logs corresponding to each of the first simulation tasks to obtain the second log analysis information of each of the first simulation tasks during the running phase.

[0103] Here, the second matcher is mainly used to handle problems that occur during the runtime phase. This second matcher can include, but is not limited to, a standard matcher, a custom matcher, etc.

[0104] This standard matcher is primarily used to print standard error messages within simulation tools. It incorporates a first regular expression library, which includes at least one regular expression to identify standard print content. If a simulation log contains content matching a regular expression, it indicates a runtime problem and is added to the second log analysis. The standard print content is related to the simulation tool. For example, for simulation tools like VCS and XRUN, standard print content refers to UVM printing, which includes UVM_INFO, UVM_WARNING, UVM_ERROR, and UVM_FATAL. UVM_INFO prints general debugging information. UVM_WARNING indicates a non-fatal warning, indicating a potential problem but not interrupting the simulation. UVM_ERROR records simulation errors, terminating the simulation after a certain number of errors are accumulated. UVM_FATAL indicates a fatal error, immediately terminating the simulation upon triggering. It is understood that the regular expressions in this first regular expression library can be dynamically configured according to the simulation tool.

[0105] This custom matcher is primarily used to handle custom error messages, i.e., non-standard printing errors. It incorporates a second regular expression library, which includes at least one regular expression to identify non-standard printing content. If the simulation log contains content matching a regular expression, it indicates a runtime problem and is added to the second log analysis. For example, a custom regular expression can be defined to determine if a test case has failed; if the simulation log contains content matching this regular expression, it indicates that the test case has failed.

[0106] Step S133: Aggregate the first log analysis information of each first simulation task in the compilation stage and the second log analysis information of each first simulation task in the running stage to obtain the log analysis information.

[0107] Here, the log analysis information can include error type, error quantity, and the location of various errors. The first and second log analysis information can be aggregated simultaneously, or they can be aggregated separately. In implementation, any existing suitable tool capable of information aggregation can be used, or software code can be used to dynamically implement the aggregation of analysis information.

[0108] In this disclosed embodiment, on the one hand, by setting a first matcher in the compilation phase and a second matcher in the runtime phase, the log analysis process only matches the regular expressions in the corresponding matchers, which can speed up the matching speed of the current phase and reduce interference between them. On the other hand, by aggregating compilation phase errors (such as syntax and semantic errors) and runtime phase errors (such as logical exceptions), firstly, through the aggregation mechanism, the compilation phase can report the location and type (such as line number and error nature) of multiple errors at once, avoiding termination of the compilation process due to a single error, thereby saving debugging time and accelerating iteration; secondly, runtime phase error aggregation (such as unified exception handling) allows centralized handling of exception logic, separating business code from error recovery logic, making the code more concise and easier to maintain; finally, it provides user-friendly error information, while facilitating log investigation and context recording; finally, compilation phase error aggregation exposes problems in the early stages of development, reducing the occurrence rate of runtime errors. Combined with runtime phase exception monitoring, a full lifecycle error defense system can be formed, reducing later debugging costs and system crash risks.

[0109] In some embodiments, the generation method further includes steps S141 and S142, wherein:

[0110] Step S141: Aggregate the coverage information corresponding to each of the first simulation tasks to obtain the coverage information of the chip to be simulated.

[0111] Here, coverage information may include, but is not limited to, code coverage, functional coverage, etc. Code coverage may include, but is not limited to, branch coverage, line coverage, condition coverage, inversion coverage, state machine coverage, etc. Power coverage may include, but is not limited to, assertion coverage, test point coverage, etc.

[0112] In implementation, coverage information corresponding to each first simulation task can be obtained from the simulation tool after the first simulation task is completed. In some implementations, the aggregation of coverage information can be dynamically implemented using existing tools (such as urg) or software code.

[0113] Step S142: Generate a visual simulation report based on the simulation results of each of the first simulation tasks, the coverage information of the chip to be simulated, and the simulation information of the chip to be simulated.

[0114] Here, the simulation results may include, but are not limited to, a first simulation result and a second simulation result. The first simulation result indicates that the simulation was successful, and the second simulation result indicates that the simulation failed. The simulation result can be the output of the simulation tool or a result generated based on the simulation information. In some implementations, if the simulation information indicates that the first simulation task has compilation errors, runtime errors, etc., then the second simulation result is taken as the simulation result of the first simulation task; otherwise, the first simulation result is taken as the simulation result of the first simulation task.

[0115] Coverage information may include, but is not limited to, code coverage, feature coverage, etc.

[0116] In some implementations, the visualization simulation report can be generated using any suitable charting tool (e.g., ECharts), software code, etc. For example, ECharts can be used to convert simulation results, simulation information, coverage information, etc., into charts. In some implementations, the visualization simulation report can be stored or forwarded via email, communication tools, etc. It is understood that the visualization simulation report can be stored locally or in the cloud.

[0117] In this embodiment, on the one hand, by aggregating the coverage information corresponding to each simulation task to obtain the coverage information of the chip to be simulated, firstly, since a single test case is difficult to cover all boundary scenarios, aggregation analysis can integrate the coverage data of multiple test cases, expose overall verification vulnerabilities, thereby eliminating coverage blind spots and comprehensively evaluating verification integrity; secondly, it can automatically identify code areas with duplicate coverage, avoid the repeated execution of invalid test cases, and optimize the allocation of regression testing resources; finally, by analyzing the coverage information of each test case, it is easier to identify efficient test case combinations, thereby optimizing subsequent verification strategies. On the other hand, by converting the data into a visual report, not only can complex information be simplified and the efficiency of understanding be improved, but the data change trends and correlations between variables can also be displayed intuitively and clearly, assisting in the discovery of deeper information.

[0118] Based on the above embodiments, this disclosure also provides a simulation information generation system. Figure 2 A schematic diagram of the composition structure of a simulation information generation system provided in this embodiment of the disclosure. Figure 1 ,like Figure 2 As shown, the generation system 20 includes:

[0119] The task scheduling adaptation module 21 is used to submit the simulation task set corresponding to the chip to be simulated to the job scheduling system; wherein, the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel.

[0120] The resource monitoring module 22 is used to determine the maximum resource usage information of each of the first simulation tasks based on the resource usage information of at least one first simulation task; wherein, the first simulation task is one of the simulation tasks that has been completed in the set of simulation tasks.

[0121] Log analysis engine 23 is used to analyze the simulation logs corresponding to each of the first simulation tasks using a preset multi-pattern matcher, and generate log analysis information.

[0122] The information generation module 24 is used to generate simulation information of the chip to be simulated based on the log analysis information and the maximum resource usage information of each of the first simulation tasks; wherein the simulation information is used for at least one of the following: generating a visual simulation report, determining the parallelism of the job scheduling system.

[0123] Here, the task scheduling adaptation module 21 can be any suitable module capable of implementing this function. This task scheduling adaptation module 21 is mainly used to interface with various job scheduling systems, such as LSF and Slurm. The task scheduling adaptation module 21 can submit the simulation task set to the job scheduling system according to the task submission interface provided by the job scheduling system. In implementation, the process of the task scheduling adaptation module 21 submitting the simulation task set to the job scheduling system can be found in the specific implementation of step S11 described above.

[0124] The resource monitoring module 22 can be any suitable module capable of implementing this function. For example, it can be implemented using languages ​​such as Golang or Python. The resource monitoring module 22 primarily obtains resource usage information for each first simulation task through the resource acquisition interface provided by the job scheduling system, and determines the maximum resource usage information for that first simulation task. In implementation, refer to the specific implementation method of step S12 described above.

[0125] The log analysis engine 23 can be any suitable module capable of implementing this function. For example, it can be implemented using a language such as Golang. The log analysis engine 23 is mainly used to perform structured parsing of various simulation logs through a multi-pattern matcher. In implementation, please refer to the specific implementation method of step S13 above.

[0126] In some implementations, the log analysis engine 23 can also be used to separately collect resource usage information (e.g., maximum memory usage, CPU time consumption, etc.) of each first simulation task during the compilation and runtime phases of the simulation process, forming a resource consumption detail to facilitate the subsequent generation of simulation reports.

[0127] The information generation module 24 can be any suitable module capable of implementing this function. The simulation information of the chip to be simulated includes at least log analysis information and maximum resource usage information for each first simulation task. In some embodiments, the simulation information may also include resource usage information for each first simulation task at various times. For implementation, refer to the specific implementation of step S14 described above.

[0128] In some embodiments, the generation system 20 further includes a data visualization module and / or a notification distribution module; the data visualization module is used to generate a visualized simulation report based on the simulation results of each of the first simulation tasks, the coverage information of the chip to be simulated, and the simulation information of the chip to be simulated; the notification distribution module is used to push the visualized simulation report to a preset recipient.

[0129] Here, the data visualization module can be any suitable module capable of performing this function. This data visualization module is primarily used to organize data and generate visual simulation reports.

[0130] Simulation results may include, but are not limited to, a first simulation result and a second simulation result. The first simulation result indicates that the simulation was successful, and the second simulation result indicates that the simulation failed.

[0131] Coverage information for the chip to be simulated may include, but is not limited to, code coverage and functional coverage. Coverage information can be used to effectively evaluate and verify the completeness of the simulation.

[0132] In some implementations, because echarts has advantages such as wide cross-platform compatibility, rich charts, and high flexibility, simulation results, simulation information, coverage information, etc. can be converted into parameters that meet the conditions of echarts, and the corresponding visualization charts can be returned through echarts.

[0133] In practice, the process of generating a visualization simulation report by the data visualization module can be found in the specific implementation of step S142 above.

[0134] The notification distribution module can be any suitable module capable of implementing this function. Push methods can include, but are not limited to, email, communication tools, etc. In some implementations, simulation reports can be pushed via SMTP, Webhook, etc. Recipients can be pre-defined. The number of recipients can be at least one. In some implementations, this notification distribution module can be implemented using Golang.

[0135] In this embodiment, on the one hand, the data visualization module converts the data into a visualization report, which not only simplifies complex information and improves understanding efficiency, but also intuitively and clearly displays the data change trend and the correlation between variables, helping to discover deeper information; on the other hand, the visualization simulation report is automatically pushed to relevant personnel through the notification distribution module, realizing real-time information sharing.

[0136] Figure 3 A schematic diagram of the composition structure of a simulation information generation system provided in this embodiment of the disclosure. Figure 2 ,like Figure 3 As shown, the generation system 20 is implemented using a distributed microservice architecture, mainly including a task scheduling and adaptation module 21, a resource monitoring module 22, a log analysis engine 23, an information generation module 24, a data visualization module 25, and a notification distribution module 26, wherein:

[0137] Task scheduling adaptation module 21: mainly responsible for interfacing with various job scheduling systems (such as LSF, Slurm), and supports receiving task submission requests through standardized interfaces.

[0138] Resource monitoring module 22: A program implemented in Golang / python that periodically collects resource usage data of simulation tasks (corresponding to the aforementioned resource usage information) and stores it in the program's memory. After the simulation task is completed, the resource usage data is stored in a specified file.

[0139] Log Analysis Engine 23: Integrates a multi-pattern regular expression matcher (corresponding to the aforementioned multi-pattern matcher), supporting dynamic loading of user-defined rule sets.

[0140] Information generation module 24: Generates simulation information based on the log analysis information obtained from the log analysis engine 23 and the maximum resource usage information of each simulation task generated by the resource monitoring module 22;

[0141] Data visualization module 25: Generates parameters that meet the conditions of echarts using Golang, and then returns a graph (corresponding to the aforementioned visualization report).

[0142] Notification distribution module 26: Supports pushing visual reports via multiple protocols such as SMTP and Webhook.

[0143] The following uses a digital chip as an example to illustrate the technical solution provided in the embodiments of this disclosure.

[0144] In digital chip verification engineering, the verification process based on traditional simulation tools has systemic defects, specifically manifested in the following problems:

[0145] 1. Bottleneck in single-round simulation data processing

[0146] Existing simulation tools (such as VCS and ModelSim) output verification information in text form to the console or log files. In small to medium-sized verification scenarios (such as IP-level verification), manual log analysis is still feasible. However, in advanced process chip verification, the amount of logs generated by a single simulation can reach terabytes (typically, GPU chip verification logs exceed 1 billion lines or more). Traditional manual analysis methods cannot meet engineering requirements in terms of efficiency (long processing time per log) and completeness (high rate of missed detection of critical timing information). Although keyword searches can be performed using tools like grep, these tools only support static text matching and cannot achieve: multi-dimensional data correlation analysis (such as cross-analysis of functional coverage and timing violations), dynamic data flow tracing (such as visualization of cross-clock domain signal transmission paths), and intelligent identification of abnormal patterns (such as intermittent metastable errors).

[0147] 2. Management challenges of multiple rounds of regression validation

[0148] In verification strategies employing randomized incentives (such as the UVM verification methodology), hundreds of repeated simulations are required to cover all possible scenarios. Taking PCIe 6.0 protocol verification as an example, a single regression test can generate hundreds or even more log files. Traditional automation tools can only achieve basic data aggregation (such as counting the number of Pass / Fail tests) and cannot solve problems such as evaluating test case execution efficiency (such as the distribution of resource utilization in each test sequence), quantifying random scenario coverage (such as the triggering frequency of specific anomaly injection scenarios), and comparing regression results across versions (such as the impact of different compilation options on verification results).

[0149] 3. Deficiencies in information presentation and collaboration efficiency

[0150] Existing verification tools have output interfaces limited to command-line mode, lacking intuitive data visualization capabilities. For example, real-time status monitoring is missing: simulation progress (such as the percentage of completion for each stage) and resource consumption curves (CPU / Memory utilization) cannot be dynamically displayed; the anomaly warning mechanism is weak: alarms can only be triggered by fixed keywords, failing to identify potential risks (such as timing margins approaching thresholds); and collaboration efficiency is low: verification results need to be manually screenshotted / organized and then sent via email, resulting in a 4-6 hour extension in the problem feedback cycle.

[0151] 4. The drawback of relying on string matching to complete test case status determination

[0152] First, the lack of semantic recognition capabilities leads to an extremely high risk of misjudgment. Because digital chip design frequently uses terms like "error" and "fail" as signal names or register identifiers, plain text keyword matching can easily misjudge normal design elements as verification anomalies. For example, in PCIe bus verification, if a status register named "data_error_flag" exists, simple string matching might misjudge a normal state transition of that signal as a verification failure.

[0153] Secondly, the lack of a standardized analysis framework results in insufficient reliability of verification results. Existing methods lack a unified log parsing standard, making it impossible to distinguish between design naming and actual error information, and also difficult to categorize errors by type. This unstructured analysis approach cannot accurately identify different types of verification defects such as timing violations, functional anomalies, and resource conflicts, leading to a high rate of missed detections of critical issues and severely impacting verification efficiency and chip design quality.

[0154] Therefore, in order to solve the above problems, the generation system provided in this disclosure mainly includes the following functions:

[0155] 1) Build an automated log parsing engine: Use natural language processing technology to achieve semantic understanding and structured analysis of simulation logs, automatically identify and classify various verification events (such as timing violations, assertion failures, and resource overflows), and solve problems such as high false positive rates and lack of typological analysis capabilities caused by traditional keyword matching methods.

[0156] 2) Realize real-time simulation status monitoring and prediction

[0157] 3) Capable of visually presenting simulation results in multiple dimensions.

[0158] 4) Establish an automated notification and decision support mechanism: When resources reach a threshold or the simulation is complete, push formatted reports via email, instant messaging tools, etc.

[0159] The specific functions can be implemented as follows:

[0160] 1. Implementation of the task resource monitoring mechanism

[0161] When a user submits a simulation task to a job scheduling system (such as LSF, or other distributed resource management systems) via a script (e.g., using commands like bsub or srun to submit the simulation task), the monitoring module built in Golang on the backend of the generation system automatically connects. During the execution of the simulation task, the monitoring module queries and records the real-time resource usage data (corresponding to the aforementioned first resource usage information) of the simulation task every preset interval (e.g., 1 minute). After the simulation task ends, it further obtains resource usage data such as overall memory usage and peak usage through commands, compares the overall resource usage data with the real-time resource usage data recorded during the execution process, and takes the maximum value as the final result (i.e., the maximum resource usage data of the simulation task) to ensure the accuracy of the data.

[0162] 2. Implementation process of automated analysis of simulation results

[0163] After the simulation task is completed, the Go backend server will perform the following tasks in sequence:

[0164] 1) Resource usage analysis: The maximum memory usage and CPU time consumed during the compilation and runtime phases of the simulation are statistically analyzed to form a detailed resource consumption list.

[0165] 2) Log text parsing: Using regular expression matching technology, structured analysis is performed on the log files in the simulation directory.

[0166] The first step is compilation error diagnosis. For errors starting with ERROR during the compilation phase, a predefined regular expression library (corresponding to the first matcher mentioned above) is used to accurately identify different types of compilation problems such as syntax errors, undefined identifiers, and pattern mismatches.

[0167] Next, the information printed by UVM is analyzed, which is divided into UVM_INFO, UVM_WARNING, UVM_ERROR, and UVM_FATAL statistics. The focus is on tracking UVM_WARNING, UVM_ERROR, and UVM_FATAL to locate the first error message and aggregate subsequent similar error logs to assist in troubleshooting the root cause of the problem.

[0168] Finally, there is custom output detection. For user-defined non-UVM standard print content, it is matched using pre-configured regular expressions in the detection script. If a match is successful, it is determined to be compatible with the custom output. For example, the corresponding test case will fail to execute.

[0169] 3) Results integration and visualization: After completing the above information capture, the system automatically determines whether there are errors in the simulation, and combines key indicators such as coverage to generate parameters that meet the conditions of echarts through Golang, and integrates them to generate visualization charts (corresponding to the aforementioned simulation report).

[0170] 4. Simulation results are pushed through multiple channels. The generation system supports accessing the mail server via the SMTP protocol and, based on the default mailing list or parameters specified by the script, sends the simulation information or simulation report to various email addresses, achieving real-time information sharing.

[0171] Figure 4 A schematic diagram of the implementation process of a simulation information generation method provided in this embodiment of the present disclosure. Figure 2 ,like Figure 4 As shown, the generation method includes steps S401 to S409, wherein:

[0172] Step S401: After determining the simulation tool and scheduling tool (corresponding to the aforementioned job scheduling system), execute the script;

[0173] Here, simulation tools and scheduling tools can be customized through interfaces, files, etc. Since different scheduling tools offer different interfaces and functionalities, it is necessary to determine the scheduling tool currently being used to ensure the proper execution of subsequent tasks.

[0174] Step S402: The background server (corresponding to the generation system) exposes the application port and continuously receives simulation monitoring requests from the script;

[0175] Step S403: The script sends process (corresponding to the aforementioned simulation task) identifier, regular expression matching (corresponding to the aforementioned multi-pattern matcher) and other data to the background server;

[0176] Step S404: The backend server receives the data and begins full-process monitoring of the simulation data;

[0177] Step S405: The background server accesses the scheduling tool at regular intervals to query the resource usage information of the corresponding process;

[0178] Step S406: After the simulation ends, the script sends a command to terminate the process;

[0179] Step S407: The backend server compares and records resource usage information;

[0180] Here, the real-time resource usage information and the overall resource usage information are compared, and the highest one is taken as the maximum resource usage information.

[0181] Step S408: The background server reads the simulation log;

[0182] Step S409: After processing the simulation logs, the backend server compiles them into a report along with resource usage information and sends it to the designated email address.

[0183] Therefore, the technical solution disclosed herein can bring the following beneficial effects:

[0184] 1. Intelligent log parsing enables efficient and accurate analysis.

[0185] The simulation log intelligent parsing engine (corresponding to the aforementioned log analysis engine 23) constructed in this disclosure employs natural language processing algorithms to automatically identify relevant error messages related to key information in logs, overcoming the limitations of traditional keyword matching. Compared to manual analysis, this solution can improve log parsing efficiency by several times and significantly reduce the false positive rate. Through automated data extraction and classification, there is no need for manual pre-setting of search keywords, which not only reduces a lot of repetitive work but also ensures the completeness and accuracy of verification result analysis, significantly improving the efficiency of digital chip verification.

[0186] It provides custom regular expression input and corresponding information classification, and can provide customized information output (such as adding a new indicator detection).

[0187] 2. Achieve dynamic resource monitoring and intelligent scheduling

[0188] Developed using Golang / Python, this resource monitoring module deeply integrates with the job scheduling system to track the entire lifecycle of simulation tasks. The module periodically collects key metrics such as the status of simulation tasks (e.g., queuing, running, and abnormal states) and the resource usage of running simulation resources (e.g., CPU utilization, memory consumption, I / O load), storing these data in real-time to the runtime memory and then directly to a designated location on the hard drive upon completion. Actual testing has shown that this mechanism can predict resource bottlenecks and assist engineers in dynamically adjusting simulation strategies. For example, it automatically calculates the optimal number of concurrent tasks based on the remaining resources in the job scheduling system and the resources required by the simulation tasks, significantly improving resource utilization while ensuring the completion of regression testing and effectively avoiding extended verification cycles due to insufficient resources.

[0189] 3. Automated notifications and full lifecycle data management

[0190] An innovative automated notification mechanism for simulation results supports user-defined email sending strategies (such as task completion, exception triggering, and periodic summaries). Email content automatically generates structured reports covering core information such as test case pass rates (down to individual test case execution details), key performance indicator comparisons, and exception event classification statistics, forming standardized verification documents. This feature not only shifts engineers from "passive monitoring" to "proactive response," significantly reducing waiting time, but also solves the problem of log files being difficult to retain long-term due to storage space limitations in traditional verification processes. Through cloud storage and version control, the retention rate of important verification data is increased to 100%, providing complete data support for subsequent project reviews, issue tracing, and design optimization.

[0191] In some implementations, the resource monitoring module 22 is also used to serialize and store the resource usage information of the second simulation task at the current moment.

[0192] In some implementations, the resource monitoring module 22 is further configured to store the maximum resource usage information of the first simulation task into a file corresponding to the first simulation task; and / or, obtain the coverage information corresponding to the first simulation task.

[0193] In some embodiments, the resource monitoring module 22 is further configured to periodically acquire the status of at least one second simulation task and at least one third simulation task through the task status acquisition interface provided by the job scheduling system; wherein the third simulation task is an unrunning simulation task in the simulation task set; in response to detecting that the status of any third simulation task has switched to the running state, the third simulation task is added to the running queue; in response to detecting that the status of any second simulation task has switched to the completed state, the second simulation task is removed from the running queue.

[0194] In some implementations, the log analysis engine 23 is also used to aggregate the coverage information corresponding to each of the first simulation tasks to obtain the coverage information of the chip to be simulated.

[0195] The description of the system embodiments above is similar to that of the method embodiments above, and has similar beneficial effects. For technical details not disclosed in the system embodiments of this disclosure, please refer to the description of the method embodiments of this disclosure for understanding.

[0196] It should be noted that, in the embodiments of this disclosure, if the above methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this disclosure, or the parts that contribute to related technologies, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this disclosure are not limited to any specific hardware and software combination.

[0197] This disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the methods described above. The computer-readable storage medium may be transient or non-transient.

[0198] This disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. The computer program product can be implemented specifically through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0199] It should be noted that, Figure 5 This is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of the present disclosure, such as... Figure 5 As shown, the hardware entity of the electronic device 500 includes: a processor 501, a communication interface 502, and a memory 503, wherein:

[0200] Processor 501 typically controls the overall operation of electronic device 500.

[0201] Communication interface 502 enables electronic devices to communicate with other terminals or servers via a network.

[0202] The memory 503 is configured to store instructions and applications executable by the processor 501, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 501 and various modules in the electronic device 500. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 501, the communication interface 502, and the memory 503 can be performed via bus 504.

[0203] It should be noted that the descriptions of the storage medium and device embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0204] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0205] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0206] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0207] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the embodiments of this disclosure, all functional units may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the integrated unit may be implemented in hardware or in a combination of hardware and software functional units.

[0208] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0209] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0210] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for generating simulation information, characterized in that, include: The simulation task set corresponding to the chip to be simulated is submitted to the job scheduling system; wherein, the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel. The resource usage information of at least one second simulation task in the running queue at the current time is obtained periodically through the first resource acquisition interface provided by the job scheduling system; wherein, the second simulation task is a running simulation task in the simulation task set; For each second simulation task, the maximum resource usage information of the second simulation task is determined based on the resource usage information of the second simulation task at the current time. In response to detecting that the state of any of the second simulation tasks has switched to the completed state, the second simulation task is treated as a first simulation task. The overall resource usage information of the first simulation task is obtained through the second resource acquisition interface provided by the job scheduling system. Based on the overall resource usage information of the first simulation task, the maximum resource usage information of the first simulation task is determined. The first simulation task is a completed simulation task in the simulation task set. Using a preset multi-pattern matcher, the simulation logs corresponding to each of the first simulation tasks are analyzed to generate log analysis information; wherein, the multi-pattern matcher includes a first matcher that processes the simulation during the compilation phase and a second matcher that processes the simulation during the runtime phase; the second matcher includes a custom matcher; Based on the log analysis information and the maximum resource usage information of each of the first simulation tasks, simulation information of the chip to be simulated is generated; wherein, the simulation information is used for at least one of the following: generating a visual simulation report, determining the parallelism of the job scheduling system.

2. The generation method according to claim 1, characterized in that, The step of determining the maximum resource usage information of the second simulation task based on its current resource usage information includes: updating the maximum resource usage information of the second simulation task to the current resource usage information when the current resource usage information is greater than the maximum resource usage information of the second simulation task; and keeping the maximum resource usage information of the second simulation task unchanged when the current resource usage information is not greater than the maximum resource usage information of the second simulation task. The generation method further includes: serializing and storing the resource usage information of the second simulation task at the current moment.

3. The generation method according to claim 1, characterized in that, The step of determining the maximum resource usage information of the first simulation task based on the overall resource usage information of the first simulation task includes: updating the maximum resource usage information of the first simulation task to the overall resource usage information of the first simulation task when the overall resource usage information of the first simulation task is greater than the maximum resource usage information of the first simulation task; and keeping the maximum resource usage information of the first simulation task unchanged when the overall resource usage information of the first simulation task is not greater than the maximum resource usage information of the first simulation task. The generation method further includes at least one of the following: storing the maximum resource usage information of the first simulation task into a file corresponding to the first simulation task; and obtaining the coverage information corresponding to the first simulation task.

4. The generation method according to claim 1, wherein the characteristic value is, The generation method further includes: The status of at least one second simulation task and at least one third simulation task are periodically acquired through the task status acquisition interface provided by the job scheduling system; wherein, the third simulation task is an unrunning simulation task in the simulation task set. In response to detecting that the state of any of the third simulation tasks has switched to the running state, the third simulation task is added to the running queue; In response to detecting that the state of any of the second simulation tasks has switched to the completed state, the second simulation task is removed from the run queue.

5. The generation method according to claim 1, characterized in that, The process involves using a preset multi-pattern matcher to analyze the simulation logs corresponding to each of the first simulation tasks, generating log analysis information, including: Using the first matcher, the simulation logs corresponding to each of the first simulation tasks are analyzed to obtain the first log analysis information of each of the first simulation tasks during the compilation phase. Using the second matcher, the simulation logs corresponding to each of the first simulation tasks are analyzed to obtain the second log analysis information of each of the first simulation tasks during the running phase. The log analysis information is obtained by aggregating the first log analysis information of each first simulation task during the compilation phase and the second log analysis information of each first simulation task during the runtime phase.

6. The generation method according to any one of claims 1 to 5, characterized in that, The generation method further includes: The coverage information corresponding to each of the first simulation tasks is aggregated to obtain the coverage information of the chip to be simulated. Based on the simulation results of each of the first simulation tasks, the coverage information of the chip to be simulated, and the simulation information of the chip to be simulated, a visual simulation report is generated.

7. A simulation information generation system, characterized in that, include: A task scheduling adaptation module is used to submit the simulation task set corresponding to the chip to be simulated to the job scheduling system; wherein, the simulation task set includes at least one simulation task, and the job scheduling system is used to execute the simulation tasks in parallel. The resource monitoring module is used to periodically acquire resource usage information of at least one second simulation task in the running queue at the current time through a first resource acquisition interface provided by the job scheduling system; wherein the second simulation task is a running simulation task in the simulation task set; for each second simulation task, the maximum resource usage information of the second simulation task is determined based on the resource usage information of the second simulation task at the current time; in response to detecting that the state of any second simulation task switches to the completed state, the second simulation task is treated as a first simulation task, and the overall resource usage information of the first simulation task is acquired through the second resource acquisition interface provided by the job scheduling system, and the maximum resource usage information of the first simulation task is determined based on the overall resource usage information of the first simulation task; wherein the first simulation task is a completed simulation task in the simulation task set. A log analysis engine is used to analyze the simulation logs corresponding to each of the first simulation tasks using a preset multi-pattern matcher, and generate log analysis information; wherein, the multi-pattern matcher includes a first matcher that processes the simulation during the compilation phase and a second matcher that processes the simulation during the runtime phase; the second matcher includes a custom matcher; An information generation module is used to generate simulation information for the chip to be simulated based on the log analysis information and the maximum resource usage information for each of the first simulation tasks; wherein the simulation information is used for at least one of the following: generating a visual simulation report, or determining the parallelism of the job scheduling system.

8. The generation system according to claim 7, characterized in that, It also includes at least one of the following: The data visualization module is used to generate a visualized simulation report based on the simulation results of each of the first simulation tasks, the coverage information of the chip to be simulated, and the simulation information of the chip to be simulated. The notification distribution module is used to push the visual simulation report to a preset recipient.

9. An electronic device comprising a processor and a memory, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the computer program, it implements the method according to any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the method described in any one of claims 1 to 6.

11. A computer program product, characterized in that, The computer program product includes a non-transitory computer-readable storage medium storing a computer program that, when read and executed by a computer, implements the method of any one of claims 1 to 6.

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