Warping simulation method, electronic equipment and computer readable storage medium

Abstract

The invention discloses a warping simulation method, electronic equipment and a computer readable storage medium, and relates to the technical field of semiconductor packaging, the warping simulation method is applied to a chip packaging structure, the chip packaging structure comprises a heat dissipation cover and a packaging substrate lamination which are arranged on two opposite sides, and the method comprises the following steps: a first body structure based on the heat dissipation cover, according to the initial warping degree of the first incoming material and the initial warping degree of the first incoming material, modeling the heat dissipation cover to obtain a heat dissipation cover model; based on the second body structure of the package substrate lamination and the initial warping degree of the second incoming material, modeling the package substrate lamination to obtain a substrate lamination model; constructing a finite element simulation model based on the heat dissipation cover model and the substrate lamination model; and based on the finite element simulation model, in combination with the temperature load of at least one process site under the process of the chip packaging structure, simulating packaging warping generated by the process to obtain a target packaging warping simulation model. According to the invention, the packaging warping simulation precision can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a warpage simulation method, an electronic device, and a computer-readable storage medium. Background Art

[0002] In the field of modern semiconductor packaging, with the improvement of electronic device performance and the increase in functional complexity, the continuous increase in package size has become a trend. However, this trend is accompanied by new technical challenges, especially the increasingly prominent problem of package warpage caused by the mismatch of the coefficient of thermal expansion (CTE) between package structures. Package warpage may not only lead to shortened solder joint life and reduced Thermal Interface Material (TIM) coverage, but also cause cracks and other quality problems. These problems seriously affect the reliability and performance of packaged products. Therefore, how to accurately predict and control package warpage has become a key issue that the industry urgently needs to solve.

[0003] Currently, the widely used package warpage simulation method in the industry primarily relies on a specific temperature point as a zero-stress reference point. By applying increasing or decreasing temperature loads, the response of the package material under different temperature conditions is simulated, thereby predicting the warpage of the packaged product at high and room temperatures. Although this method can, to a certain extent, account for the impact of factors such as structural dimensions and material properties on package warpage, it has been found in actual applications that related technical means still struggle to accurately predict and control package warpage. This indicates that the related technology has certain limitations and cannot fully meet the needs of high-precision package warpage prediction, which in turn affects the quality assurance and technological advancement of packaged products. Summary of the Invention

[0004] The main purpose of this application is to provide a warpage simulation method, an electronic device and a computer-readable storage medium, aiming to solve the technical problem of low accuracy in predicting the package warpage of a chip package structure in the related art.

[0005] To achieve the above objectives, the present application provides a warpage simulation method, which is applied to a chip packaging structure including a heat dissipation cover and a packaging substrate stack disposed on opposite sides. The method comprises:

[0006] Based on the first body structure of the heat dissipation cover and the first initial warpage of the incoming material generated by the first body structure, the heat dissipation cover is modeled to obtain a heat dissipation cover model having the first initial warpage of the incoming material; based on the second body structure of the package substrate stack and the second initial warpage of the incoming material generated by the second body structure, the package substrate stack is modeled to obtain a substrate stack model having the second initial warpage of the incoming material;

[0007] Based on the heat dissipation cover model and the substrate stack model, a finite element simulation model corresponding to the chip packaging structure is constructed;

[0008] Based on the finite element simulation model and in combination with the temperature load of at least one process station in the process of the chip packaging structure, the package warpage generated by the process is simulated to obtain a target package warpage simulation model.

[0009] In addition, to achieve the above-mentioned purpose, the present application also provides an electronic device, which includes: a memory, a processor, and a computer program stored on the memory and capable of running on the processor, and when the computer program is executed by the processor, the steps of the warping simulation method as described above are implemented.

[0010] In addition, to achieve the above-mentioned purpose, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the warping simulation method as described above are implemented.

[0011] In view of the above background, the package warpage prediction technology in the related art still has a lot of room for improvement, especially in terms of improving the prediction accuracy. It is necessary to further explore and develop new technical solutions to more effectively deal with the chip package warpage problem and ensure the high quality and reliability of chip package products. Based on this, the applicant spent a lot of time and energy on countless experiments. After countless experiments, it was finally found through research that this is because the incoming material warpage of the substrate and the heat dissipation cover in the chip packaging structure is usually unstable. The incoming material warpage value and warpage morphology of the substrate and the heat dissipation cover are different, resulting in different package warpage in the final processing. The current simulation method in the industry does not take into account the initial warpage of the incoming material, so it cannot accurately predict the final package warpage.

[0012] Based on this, the embodiment of the present application provides a warping simulation method, an electronic device and a computer-readable storage medium. The warping simulation method is applied to a chip packaging structure, wherein the chip packaging structure includes a heat dissipation cover and a packaging substrate stack arranged on two opposite sides. The technical solution of the embodiment of the present application is to model the heat dissipation cover based on the first body structure of the heat dissipation cover and the first incoming material initial warping generated by the first body structure, and obtain a heat dissipation cover model with the first incoming material initial warping; based on the second body structure of the packaging substrate stack and the second incoming material initial warping generated by the second body structure, model the packaging substrate stack to obtain a substrate stack model with the second incoming material initial warping, and then construct a chip packaging structure based on the heat dissipation cover model and the substrate stack model. A finite element simulation model corresponding to the structure is constructed, and then based on the finite element simulation model, combined with the temperature load of at least one process station under the process of the chip packaging structure, the package warpage generated by the process is simulated to obtain a target package warpage simulation model, so that the embodiment of the present application can consider the influencing factors of the initial warpage of the incoming material of the substrate and the heat dissipation cover, and dynamically incorporate the initial warpage value of the incoming material into the simulation step calculation of the temperature load corresponding to at least one process station in the process, thereby significantly improving the accuracy of package warpage prediction, and achieving more accurate and reliable chip package warpage prediction, so as to guide packaging design, improve the quality and reliability of chip packaging products, and effectively solve the technical problem of low accuracy in predicting the package warpage of the chip packaging structure in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0015] Figure 1 A schematic diagram of a flow chart of the first embodiment of the warpage simulation method of the present application;

[0016] Figure 2 A schematic diagram of a flow chart of the second embodiment of the warpage simulation method of the present application;

[0017] Figure 3 A schematic diagram of a flow chart provided for the third embodiment of the warpage simulation method of the present application;

[0018] Figure 4A schematic diagram of a flow chart provided for the fourth embodiment of the warpage simulation method of the present application;

[0019] Figure 5 A schematic diagram of a flow chart of a fifth embodiment of the warpage simulation method of the present application;

[0020] Figure 6 A schematic diagram of a package warpage simulation model in a specific embodiment of the present application;

[0021] Figure 7 This is a schematic diagram of an auxiliary body above the heat dissipation cover in a specific embodiment of the present application;

[0022] Figure 8 This is a schematic diagram of an auxiliary body below the package substrate stack in a specific embodiment of the present application;

[0023] Figure 9 A schematic diagram of a warpage simulation process in a specific embodiment of the present application;

[0024] Figure 10 This is a schematic diagram of step-by-step loading of temperature load in a specific embodiment of the present application;

[0025] Figure 11 Schematic diagram of the warpage test results;

[0026] Figure 12 This is a schematic diagram of the warpage simulation results using relevant technologies;

[0027] Figure 13 A schematic diagram of the results of warping simulation using the warping simulation method provided in one embodiment of the present application;

[0028] Figure 14 Schematic diagram of the device structure of the hardware operating environment involved in the warping simulation method in the embodiment of the present application.

[0029] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0030] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0031] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0032] Currently, in existing semiconductor package warpage prediction technologies, simulation methods usually assume that the initial state of package components (such as heat sinks and substrate stacks) before processing is an ideal plane, and use a certain temperature point as a zero-stress reference point to simulate the deformation caused by differences in thermal expansion coefficients by applying temperature loads.

[0033] However, in actual production, the initial warpage values ​​and morphologies of the base plate and heat sink cover, as independent components, vary significantly and are unstable. This initial warpage stems from factors such as residual stress and fluctuations in material properties during the manufacturing process, but is completely ignored in traditional simulations. Because this initial warpage is not incorporated into the model, the simulation process fails to reflect the cumulative effects of true material deformation, leading to errors in the prediction of cumulative warpage under temperature loads in subsequent processes. This limitation directly impacts key performance indicators such as package solder joint life and thermal interface material coverage uniformity, ultimately reducing product reliability.

[0034] In this regard, the main solution of an embodiment of the present application is a warping simulation method, which is applied to a chip packaging structure, wherein the chip packaging structure includes a heat dissipation cover and a packaging substrate stack arranged on opposite sides, and the method includes: based on the first body structure of the heat dissipation cover and the first incoming material initial warping generated by the first body structure, modeling the heat dissipation cover to obtain a heat dissipation cover model with the first incoming material initial warping; based on the second body structure of the packaging substrate stack and the second incoming material initial warping generated by the second body structure, modeling the packaging substrate stack to obtain a substrate stack model with the second incoming material initial warping; based on the heat dissipation cover model and the substrate stack model, constructing a finite element simulation model corresponding to the chip packaging structure; based on the finite element simulation model, combined with the temperature load of at least one process station under the process of the chip packaging structure, simulating the packaging warping generated by the process to obtain a target packaging warping simulation model.

[0035] The embodiment of the present application can take into account the influencing factors of the initial warping of the incoming materials of the substrate and the heat dissipation cover, and dynamically incorporate the initial warping value of the incoming materials into the simulation step calculation of the temperature load corresponding to at least one process station in the process, thereby significantly improving the accuracy of package warping prediction and achieving more accurate and reliable chip package warping prediction to guide package design, improve the quality and reliability of chip package products, and effectively solve the technical problem of low accuracy in predicting the package warping of the chip package structure in related technologies.

[0036] It should be noted that the execution subject of the embodiments of the present application is an electronic device, which may include but is not limited to mobile terminals such as laptop computers, PDAs (Personal Digital Assistants), and PADs (Portable Application Descriptions, tablet computers), as well as fixed terminals such as desktop computers, or any other electronic device capable of implementing the above functions. The embodiments of the present application are not specifically limited to this. The following embodiments of the present application are described using the electronic device as the execution subject.

[0037] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0038] This application proposes a warpage simulation method according to a first embodiment.

[0039] Please refer to Figure 1 , Figure 1 A schematic flow chart of the first embodiment of the warping simulation method of the present application.

[0040] In this embodiment, the warpage simulation method is applied to a chip packaging structure, which includes a heat dissipation cover and a packaging substrate stack disposed on opposite sides. The method includes steps S100 to S300:

[0041] In step S100, the heat dissipation cover is modeled based on the first main body structure of the heat dissipation cover and the first initial warpage of the incoming material generated by the first main body structure, thereby obtaining a heat dissipation cover model having the first initial warpage of the incoming material; and the packaging substrate stack is modeled based on the second main body structure of the packaging substrate stack and the second initial warpage of the incoming material generated by the second main body structure, thereby obtaining a substrate stack model having the second initial warpage of the incoming material.

[0042] Those skilled in the art will recognize that a chip package structure refers to the overall structure that integrates one or more integrated circuit chips and protects them from physical damage and environmental influences. It primarily includes a heat dissipation cover and a package substrate stack disposed on opposite sides. The heat dissipation cover is typically located on top of the chip package and its primary function is to enhance the efficiency of heat conduction from the chip to the external environment, thereby effectively reducing the chip's operating temperature. The package substrate stack refers to the basic board layer structure used to support the chip and other electronic components, providing electrical connections, mechanical support, and thermal management functions.

[0043] In this embodiment, the first main structure refers to the basic physical structure of the heat dissipation cover (including geometric dimensions, material distribution, and connection characteristics); the second main structure refers to the basic physical structure of the package substrate stack; the first incoming material initial warpage refers to the degree of warpage of the heat dissipation cover before entering the chip packaging structure process; and the second incoming material initial warpage refers to the degree of warpage of the package substrate stack before entering the chip packaging structure process. The heat dissipation cover model refers to a model that accurately reflects the actual shape and warpage of the heat dissipation cover as received, and the package substrate stack model refers to a model that accurately reflects the actual shape and warpage of the package substrate stack as received.

[0044] This embodiment uses the heat dissipation cover's first main structure and the resulting first initial warpage of the incoming material to perform three-dimensional modeling of the heat dissipation cover, ensuring that the resulting model accurately reflects the actual shape and warpage of the heat dissipation cover as it arrives. Similarly, the package substrate stack is modeled based on its second main structure and the corresponding second initial warpage of the incoming material, ensuring that the resulting model accurately reflects the actual shape and warpage of the package substrate stack as it arrives. This step forms the foundation for subsequent simulations; by accurately capturing the initial state of the incoming material, warpage that may occur during actual manufacturing can be more realistically simulated.

[0045] By accurately establishing a model that includes the initial warpage of the incoming material, this embodiment can more accurately predict the warpage changes caused by material properties and process conditions in future simulation processes, thereby improving the accuracy of the final simulation results.

[0046] Step S200 : constructing a finite element simulation model corresponding to the chip packaging structure based on the heat dissipation cover model and the substrate stacking model.

[0047] Those skilled in the art will know that a finite element simulation model is a mathematical model that decomposes a complex system into simple units to analyze characteristics such as stress and deformation.

[0048] It should be noted that, in this embodiment, the finite element simulation model may be a 1 / 4 package structure model corresponding to the chip package structure, or a 1:1 package structure model, which is not specifically limited in this embodiment.

[0049] This embodiment integrates the heat dissipation cover model and the substrate stack model obtained in step S100 to construct a finite element simulation model of the entire chip packaging structure, so that in subsequent simulation experiments, the interaction between the two can be comprehensively analyzed, especially the stress distribution and deformation caused by the mismatch of thermal expansion coefficients, thereby providing reliable data support for subsequent warpage prediction.

[0050] Step S300 , based on the finite element simulation model and in combination with the temperature load of at least one process station in the process of the chip package structure, simulate the package warpage generated by the process to obtain a target package warpage simulation model.

[0051] It should be noted that the process refers to the series of processing steps and technologies used in the entire production process from raw materials to final product. For chip packaging, the process includes but is not limited to wafer dicing, chip pasting, wire bonding, plastic molding, electroplating, marking, testing, and other links. The process station refers to the specific execution steps in the process, and each process station represents a stage in completing a specific task. Temperature load refers to the temperature conditions applied to materials or components during the process, which is one of the important factors affecting material behavior.

[0052] It's no surprise that during the chip packaging process, different process stations may require different temperature environments to complete specific tasks, such as high-temperature heating during reflow soldering or cooling during the cooling phase. Temperature loads not only affect material physical properties such as expansion coefficient and strength, but also induce thermal stress in the package structure, leading to problems such as warping. Accurately controlling and simulating temperature loads is crucial to ensuring package quality and predicting the reliability and performance of the package structure.

[0053] It should also be noted that the target package warpage simulation model refers to the final package warpage prediction result generated by finite element simulation technology after comprehensively considering factors such as temperature loads, material properties and geometric deformation of each process station in the complete process of the chip package structure. It reflects the overall warpage state of the chip package structure after undergoing at least one process station (such as fixing the silicon wafer, fixing the heat dissipation cover, plastic packaging molding, etc.) and is the final output of the entire simulation process.

[0054] Through the constructed finite element simulation model, this embodiment dynamically incorporates the initial warpage value of the incoming materials of the package substrate stack and the heat dissipation cover into the simulation step calculation of the temperature load corresponding to at least one process station in the process, simulating the warpage behavior of each component in the chip packaging structure under the process, thereby significantly improving the accuracy of package warpage prediction and achieving more accurate and reliable chip package warpage prediction to guide package design, improve the quality and reliability of chip package products, and effectively solve the technical problem of low accuracy in predicting package warpage of chip packaging structures in related technologies.

[0055] The models in this embodiment are all three-dimensional models, and each model can set model attribute parameters.

[0056] Based on the above-mentioned first embodiment, a warping simulation method according to a second embodiment of the present application is proposed.

[0057] In the second embodiment of the present application, for the same or similar contents as those in the above embodiments, please refer to the above introduction and will not be repeated hereafter.

[0058] Please refer to Figure 2 , Figure 2 A flowchart of the second embodiment of the warping simulation method of the present application is provided.

[0059] In this embodiment, the chip packaging structure further includes a silicon wafer and an underfill filler filled between the contact surface of the package substrate stack and the silicon wafer. The finite element simulation model further includes a silicon wafer model corresponding to the silicon wafer and a filler model corresponding to the underfill filler. The process station includes fixing the silicon wafer.

[0060] Step S300, based on the finite element simulation model and in combination with the temperature load of at least one process station in the process of the chip package structure, simulates the package warpage generated by the process to obtain a target package warpage simulation model, which may include steps S310 to S330:

[0061] Step S310 , suppressing the finite element simulation model and adjusting the model temperature to the first curing process temperature of the underfill.

[0062] Those skilled in the art will know that a silicon wafer refers to a single-crystal silicon substrate used in semiconductor manufacturing, which is used to carry integrated circuit chips and provide electrical signal transmission and mechanical support functions. Bottom filler is a polymer material that fills the gap between the silicon wafer and the packaging substrate stack to enhance mechanical connection, relieve thermal stress, and prevent the intrusion of external contaminants. Its curing process is accompanied by volume shrinkage, which has a significant impact on package warpage. The process site for fixing the silicon wafer specifically refers to the specific operational steps for fixing the silicon wafer to the packaging substrate during the chip packaging process.

[0063] In this embodiment, the bottom filling glue is used to fix the silicon chip on the package substrate stack, and the bottom filling glue can be epoxy resin.

[0064] It should be noted that the silicon wafer model refers to the mathematical model used to simulate the geometry, material properties, and mechanical behavior of the silicon wafer in finite element simulation. The underfill model refers to the mathematical model used to simulate the geometry, material properties, and mechanical behavior of the underfill during the curing process in finite element simulation.

[0065] It should also be noted that the first curing process temperature refers to the specific temperature required for the bottom filler to complete the cross-linking reaction in the process station for fixing the silicon wafer. At this temperature, the bottom filler changes from liquid or semi-solid to solid, forming a stable bonding interface, thereby fixing the silicon wafer to the packaging substrate stack.

[0066] Illustratively, the first curing process temperature may be the curing temperature of the underfill, or a temperature higher than the curing temperature of the underfill.

[0067] In one example, the first curing process temperature ranges from 150°C to 165°C.

[0068] Experimental verification shows that the optimal temperature range for the first curing process is 150°C to 165°C. Within this temperature range, the warping caused by the process station of fixing the silicon wafer is minimal.

[0069] It should be noted that in this embodiment, the second incoming material initial warpage specifically refers to the warpage of the package substrate stack upon entering the fixed silicon wafer process station, at which point the package substrate stack is at the first curing temperature. In other words, the substrate stack model is based on the actual shape and warpage of the package substrate stack at the first curing temperature upon entering the fixed silicon wafer process station.

[0070] Since the default initial temperature of the simulation model is usually set to the ambient temperature (for example, 25 degrees Celsius), although the substrate stack model has the warpage when the package substrate stack is incoming at the first curing process temperature, the model temperature is the ambient temperature. Therefore, in the simulation of the fixed silicon wafer, it is necessary to first suppress the finite element simulation model through the life and death unit technology, temporarily freeze the degrees of freedom and physical response of the finite element simulation model, and then adjust the model temperature to the first curing process temperature to align with the actual process conditions, so that the model temperature is consistent with the first curing process temperature when the substrate stack is incoming, while maintaining its initial geometric shape of the incoming material, ensuring that the adjustment of the model temperature will not cause additional thermal deformation, causing the substrate stack model to deviate from the actual incoming material state.

[0071] This embodiment uses the life-and-death unit technology to suppress the model response and force the alignment of the temperature field, avoiding the introduction of non-physical thermal stress due to the virtual heating process of "rising from ambient temperature to the first curing process temperature", ensuring that the geometric shape and thermodynamic state of the model at the starting point of the simulation are strictly consistent with the actual incoming material conditions, and providing accurate initial conditions for subsequent curing and cooling simulation.

[0072] In step S320, after adjusting to the first curing process temperature, the silicon wafer model, the filling glue model, and the substrate stacking model are activated, and the model temperature is lowered from the first curing process temperature to a preset ambient temperature to simulate the package warpage generated by the process station of fixing the silicon wafer, thereby obtaining a first package warpage simulation model.

[0073] In this embodiment, the preset ambient temperature refers to a normal reference temperature set during the simulation, typically 25°C. This temperature simulates the actual operating or storage conditions of the chip package structure after completing a specific process step. This temperature serves as the endpoint of the temperature load variation, representing a state where material thermal stress has stabilized and serves as a benchmark for assessing the final form of package warpage.

[0074] It is understandable that the preset ambient temperature is not limited to the temperature example of 25°C, but can also be 23°C, 24°C, 26°C, etc. This embodiment does not limit this, and those skilled in the art can set it according to actual conditions.

[0075] It should also be noted that the first package warpage simulation model refers to an intermediate model generated by simulating the temperature load at the wafer-fixing process station (from the first curing process temperature down to the preset ambient temperature). This model reflects the warpage of the package substrate stack, wafer, and underfill during the curing and cooling process due to differences in material thermal expansion coefficients and curing shrinkage. It serves as the initial input for simulations of subsequent process stations (such as heat sink fixing and plastic encapsulation), and represents the independent contribution of the wafer-fixing process station to the overall package warpage of the chip package structure.

[0076] In this embodiment, after adjusting the model temperature to the first curing process temperature and completing the process condition alignment, the response suppression of the silicon wafer model, the filling glue model and the substrate stacking model is released through the activation operation of the life and death unit technology, so that the dynamic response capability to the temperature load is restored. Then, the model temperature is reduced from the first curing process temperature to the preset ambient temperature to simulate the process of cooling the bottom filling glue to the preset ambient temperature after curing.

[0077] Step S330 : obtaining a target package warpage simulation model based on the first package warpage simulation model.

[0078] In this embodiment, step S330 may include step S331 or step S332:

[0079] Step S331 : using the first package warpage simulation model as a target package warpage simulation model.

[0080] Alternatively, in step S332 , based on the first package warpage simulation model and in combination with the temperature loads of other process stations except for the fixed silicon wafer during the process, the package warpage generated during the process is simulated to obtain a target package warpage simulation model.

[0081] In this embodiment, if the warpage simulation is limited to the simulation of a single process site, namely, a fixed silicon wafer, the first package warpage simulation model can be directly used as the target package warpage simulation model. Otherwise, the first package warpage simulation model can be used as the initial condition. Thus, when simulating other process sites, the response capabilities of the corresponding components of other process sites in the first package warpage simulation model are activated, and corresponding temperature loads are applied. By solving the thermal-mechanical coupling response in stages, the warpage contribution of each process site is accumulated step by step, and finally a target package warpage simulation model that integrates the influence of multiple process sites is generated, thereby significantly improving the package warpage prediction accuracy and achieving more accurate and reliable chip package warpage prediction.

[0082] Based on the above second embodiment, a warping simulation method according to a third embodiment of the present application is proposed.

[0083] In the third embodiment of the present application, for the same or similar contents as those in the above embodiments, please refer to the above introduction and will not be repeated hereafter.

[0084] Please refer to Figure 3 , Figure 3 A flowchart of the third embodiment of the warping simulation method of the present application is provided.

[0085] In this embodiment, the chip packaging structure further includes a thermal interface material TIM filled between the contact surface of the silicon chip and the heat dissipation cover, and a structural adhesive filled between the contact surface of the heat dissipation cover and the package substrate stack. The finite element simulation model also includes a TIM model corresponding to the TIM and a structural adhesive model corresponding to the structural adhesive. The process station also includes fixing the heat dissipation cover.

[0086] Step S332 may include steps S333 to S334:

[0087] Step S333 : When the first package warpage simulation model is in an activated state, the model temperature is adjusted to the second curing process temperature of both the TIM and the structural adhesive.

[0088] Those skilled in the art will recognize that thermal interface material (TIM) refers to the material used to fill the interface between the silicon wafer and the heat sink cover during the chip packaging process to enhance heat conduction efficiency. Structural adhesive is a polymer material used to fill the interface between the heat sink cover and the packaging substrate stack, providing a mechanical connection and enhancing the stability of the overall structure. The process station for fixing the heat sink cover specifically refers to the specific steps involved in securing the heat sink cover to the packaging substrate during the chip packaging process.

[0089] It should be noted that the TIM model refers to the mathematical model used to simulate the geometry, material properties, and thermal conductivity of the TIM in finite element simulation. The structural adhesive model refers to the mathematical model used to simulate the geometry, material properties, and mechanical behavior of the structural adhesive during the curing process in finite element simulation.

[0090] It's also important to note that the second curing process temperature refers to the specific temperature required for the TIM and structural adhesive to complete the cross-linking reaction in the process station that secures the heat dissipation cover. At this temperature, the TIM and structural adhesive transition from a liquid or semi-solid state to a solid state, forming a stable bonding interface that securely fixes the heat dissipation cover to the package substrate stack.

[0091] Illustratively, the second curing process temperature may be a target curing temperature, or a temperature above the target curing temperature, wherein the target curing temperature is the maximum value between the curing temperature of the TIM and the curing temperature of the structural adhesive.

[0092] In one example, the second curing process temperature ranges from 125°C to 150°C.

[0093] Experimental verification shows that the optimal temperature range for the second curing process is 125°C to 150°C. Within this temperature range, the warping caused by the process station of fixing the heat dissipation cover is minimal.

[0094] It should be noted that in this embodiment, the initial warpage of the first incoming material refers specifically to the degree of warpage of the heat sink cover upon entering the process station where the heat sink cover is fixed, at which point the heat sink cover is at the second curing temperature. In other words, the heat sink cover model is based on the actual shape and warpage of the heat sink cover at the second curing temperature at the process station where the heat sink cover is fixed.

[0095] In this embodiment, although the heat sink cover model in the first package warpage simulation model exhibits warpage at the second curing process temperature, the model temperature is the preset ambient temperature. Therefore, during the simulation of the fixed heat sink cover, the model temperature must first be adjusted to the second curing process temperature to align with the actual process conditions and ensure that the model temperature is consistent with the second curing process temperature when the heat sink cover is received. During this process, the previously activated silicon wafer model, underfill model, and substrate stack model respond normally to temperature changes, while the inactivated TIM model, structural adhesive model, and heat sink cover model remain suppressed. This simulates the actual process temperature rise of the silicon wafer, underfill, and package substrate stack as they enter the process station where the heat sink cover is fixed. Furthermore, the model temperature adjustment ensures that the TIM, structural adhesive, and heat sink cover models do not cause additional thermal deformation. This ensures that the model geometry and thermodynamic state at the simulation starting point are strictly consistent with the actual incoming material conditions, significantly improving the accuracy of package warpage prediction.

[0096] In step S334, after adjusting to the second curing process temperature, the TIM model, the structural adhesive model, and the heat dissipation cover model are activated, and the model temperature is lowered from the second curing process temperature to the preset ambient temperature to simulate the package warpage generated by the process station of fixing the heat dissipation cover, and obtain the target package warpage simulation model.

[0097] In this embodiment, after adjusting the model temperature to the second curing process temperature and completing the process condition alignment, the response suppression of the TIM model, structural adhesive model, and heat sink cover model is released through the activation operation of the life-death unit technology, so that the dynamic response capability to the temperature load is restored. The model temperature is then lowered from the second curing process temperature to the preset ambient temperature to simulate the process of cooling the TIM and structural adhesive to the preset ambient temperature after curing. The warpage contributions of the two process sites, fixed silicon wafer and fixed heat sink cover, are accumulated to obtain the target package warpage simulation model that comprehensively considers the influence of the two process sites, thereby significantly improving the accuracy of package warpage prediction and achieving more accurate and reliable chip package warpage prediction.

[0098] Based on the above embodiments, a warping simulation method according to a fourth embodiment of the present application is proposed.

[0099] In the fourth embodiment of the present application, for the same or similar contents as those in the above embodiments, reference can be made to the above introduction and will not be repeated hereafter.

[0100] Please refer to Figure 4 , Figure 4 A flowchart of the fourth embodiment of the warping simulation method of the present application is provided.

[0101] In this embodiment, the step of modeling the heat dissipation cover based on the first body structure of the heat dissipation cover and the first initial warpage of the incoming material generated by the first body structure in step S100 to obtain a heat dissipation cover model having the first initial warpage of the incoming material may include steps S110 to S130:

[0102] In step S110 , based on the first body structure of the heat dissipation cover, a three-dimensional model of the heat dissipation cover body corresponding to the first body structure is modeled, and a first warping auxiliary body is constructed on a first target surface of the three-dimensional model of the heat dissipation cover body.

[0103] It should be noted that the 3D model of the heat sink cover body refers to a 3D model built based on the first body structure of the heat sink cover. The first target surface is the surface of the 3D model of the heat sink cover body that is away from the substrate stack model. The first warpage generation auxiliary body is an auxiliary geometric body whose shape and size match the first target surface and has controllable material property parameters (such as thermal expansion coefficient and elastic modulus).

[0104] Exemplarily, in a feasible embodiment, the three-dimensional size of the first warping auxiliary body is consistent with the three-dimensional size of the three-dimensional model of the heat dissipation cover body, and the model attribute parameters of the first warping auxiliary body are consistent with the model attribute parameters of the three-dimensional model of the heat dissipation cover body, wherein the model attribute parameters include Poisson's ratio and Young's modulus (i.e., elastic modulus).

[0105] In this embodiment, the three-dimensional dimensions (including length, width, thickness and surface curvature) of the first warpage generation auxiliary body are completely consistent with the three-dimensional dimensions of the three-dimensional model of the heat dissipation cover body, and its model attribute parameters (such as Poisson's ratio and Young's modulus) are consistent with the parameters of the three-dimensional model of the heat dissipation cover body, ensuring that the first warpage generation auxiliary body is conformally fitted to the first target surface of the three-dimensional model of the heat dissipation cover body, and the mechanical behavior in the elastic deformation stage is consistent, thereby focusing the warpage generation on the single variable control of the thermal expansion coefficient difference, avoiding the additional deformation error introduced by geometric misalignment or mechanical parameter coupling, and realizing the rapid adaptation to the requirements of different incoming material warpages by linearly adjusting the thermal expansion coefficient difference, thereby significantly improving modeling efficiency and process adaptability, and providing a standardized and high-precision reverse modeling solution for warpage simulation of multi-specification chip packaging structures.

[0106] Furthermore, in a feasible embodiment, the first warping auxiliary body is divided into at least three layers of grids in the thickness direction.

[0107] In this embodiment, the first warpage auxiliary body is divided into at least three layers of meshes in the thickness direction. Specifically, the first warpage auxiliary body can be meshed using finite element pre-processing tools, so that the number of mesh layers in the thickness direction (i.e., perpendicular to the first target surface of the three-dimensional model of the heat dissipation cover body) is ≥3. The density of each mesh layer can be set based on the distribution of thermal stress gradients (for example, the surface mesh can be denser to capture high gradient stresses).

[0108] Through layered meshing, this implementation accurately simulates the non-uniform thermal expansion behavior of the first warpage-generating auxiliary body under the first temperature load variation, particularly the cumulative effect of layer-by-layer deformation due to differences in thermal expansion coefficients across the thickness. This allows for a more realistic reproduction of the initial warpage of the first incoming material caused by residual stress release in the 3D model of the heat sink cover. This implementation not only improves the computational stability of thermal-mechanical coupled simulations but also optimizes the accuracy of thermal stress transfer to the 3D model of the heat sink cover through local mesh refinement. This avoids warpage prediction errors caused by oversimplification of a single-layer mesh, providing a high-fidelity numerical foundation for inverse modeling of complex 3D warpage morphologies.

[0109] In step S120, based on the first initial warpage of the incoming material generated by the first main body structure, a first temperature load change condition is applied to the three-dimensional model of the heat dissipation cover body and the first warpage generation auxiliary body, and the model thermal expansion coefficient of the first warpage generation auxiliary body is adjusted to evolve the three-dimensional model of the heat dissipation cover body into a heat dissipation cover model having the first initial warpage of the incoming material.

[0110] It should be noted that the first temperature load change condition includes a temperature change range and a temperature gradient distribution pattern, which can be specifically set according to the thermal expansion coefficient of the heat dissipation cover material and measured or theoretical data of the initial warpage of the first incoming material.

[0111] For example, the first temperature load change condition may be to reduce the model temperature from 180°C, 175°C or 170°C to 25°C, 24°C or 23°C. This embodiment does not impose any specific restrictions on this and can be flexibly set according to actual conditions.

[0112] This embodiment is based on the principle of thermal-structural coupling. By applying a first temperature load change condition and adjusting the thermal expansion coefficient of the first warpage generation auxiliary body, the thermal stress generated by the difference in thermal expansion coefficients between the three-dimensional model of the heat dissipation cover body and the first warpage generation auxiliary body is used to guide the three-dimensional model of the heat dissipation cover body to generate a deformation that matches the initial warpage of the first incoming material, thereby obtaining a heat dissipation cover model with the first initial warpage of the incoming material. The initial warpage of the heat dissipation cover at the time of incoming material (i.e., the initial warpage value of the first incoming material) is taken into consideration in the warpage simulation, significantly improving the accuracy of package warpage prediction, and achieving more accurate and reliable chip package warpage prediction, thereby guiding package design and improving the quality and reliability of chip package products, thereby effectively solving the technical problem of low accuracy in predicting package warpage of chip package structures in related technologies.

[0113] It should be noted that, in this embodiment, step S120 is performed when the three-dimensional model of the heat dissipation cover body and the first warping auxiliary body are in an activated state.

[0114] Step S130 : When the heat dissipation cover model is obtained, suppressing or deleting the first warping auxiliary body.

[0115] After completing the warping evolution of the three-dimensional model of the heat sink cover body, this embodiment uses the geometric editing function or property suppression function of the finite element software to remove the first warping auxiliary body from the simulation model or prevent it from participating in subsequent mechanical calculations. Only the heat sink cover model that already has the first initial warping of the incoming material is retained, ensuring that the finite element simulation model of the chip packaging structure subsequently constructed only contains the deformation state of the real component (the heat sink cover and the packaging substrate stack), avoiding additional interference introduced by the auxiliary body.

[0116] This embodiment achieves high-precision reverse modeling of the initial warpage of incoming heat sink cover material by constructing a virtual auxiliary body on the first target surface and regulating its thermal expansion coefficient, combined with temperature load variation conditions. Compared to the traditional method of directly assigning an initial displacement field, this embodiment generates the initial warpage through a thermal-mechanical coupling mechanism, which is more consistent with the physical nature of material warpage due to residual stress or processing deformation during the actual manufacturing process. At the same time, the dynamic removal mechanism of the auxiliary body ensures the purity of the simulation model in subsequent process station analysis, significantly improving the reliability and process guidance value of the package warpage simulation results.

[0117] Based on the above embodiments, a warping simulation method according to a fifth embodiment of the present application is proposed.

[0118] In the fifth embodiment of the present application, for the same or similar contents as those in the above embodiments, please refer to the above introduction and will not be repeated hereafter.

[0119] Please refer to Figure 5 , Figure 5 A flowchart of the fifth embodiment of the warping simulation method of the present application is provided.

[0120] In this embodiment, the step of modeling the package substrate stack based on the second body structure of the package substrate stack and the second incoming material initial warpage generated by the second body structure in step S100 to obtain a substrate stack model having the second incoming material initial warpage may include steps S140 to S160:

[0121] Step S140 , based on the second body structure of the package substrate stack, a three-dimensional model of the substrate body corresponding to the second body structure is modeled, and a second warpage auxiliary body is constructed on a second target surface of the three-dimensional model of the substrate body.

[0122] It should be noted that the substrate body 3D model refers to a 3D model built based on the second body structure of the package substrate stack, and the second target surface is the surface of the substrate body 3D model on the side away from the substrate stack model. The second warpage generation auxiliary body is an auxiliary geometric body whose shape and size match the second target surface and has controllable material property parameters (such as thermal expansion coefficient and elastic modulus).

[0123] Exemplarily, in a feasible embodiment, the three-dimensional size of the second warping auxiliary body is consistent with the three-dimensional size of the three-dimensional model of the substrate body, and the model attribute parameters of the second warping auxiliary body are consistent with the model attribute parameters of the three-dimensional model of the substrate body, wherein the model attribute parameters include Poisson's ratio and Young's modulus.

[0124] In this embodiment, the three-dimensional dimensions (including length, width, thickness and surface curvature) of the second warping auxiliary body are completely consistent with the three-dimensional dimensions of the three-dimensional model of the substrate body, and its model attribute parameters (such as Poisson's ratio and Young's modulus) are consistent with the parameters of the three-dimensional model of the substrate body, ensuring that the second warping auxiliary body is conformally fitted to the second target surface of the three-dimensional model of the substrate body, and the mechanical behavior in the elastic deformation stage is consistent, thereby focusing the warping generation on the single variable control of the thermal expansion coefficient difference, avoiding the additional deformation error introduced by geometric misalignment or mechanical parameter coupling, and realizing the rapid adaptation to the different warping requirements of incoming materials by linearly adjusting the thermal expansion coefficient difference, thereby significantly improving the modeling efficiency and process adaptability, and providing a standardized and high-precision reverse modeling solution for the warping simulation of multi-specification chip packaging structures.

[0125] Furthermore, in a feasible embodiment, the second warping auxiliary body is divided into at least three layers of grids in the thickness direction.

[0126] In this embodiment, the second warpage auxiliary body is divided into at least three layers of meshes in the thickness direction. Specifically, the second warpage auxiliary body can be meshed in layers using finite element pre-processing tools, so that the number of mesh layers in the thickness direction (i.e., perpendicular to the second target surface of the three-dimensional model of the substrate body) is ≥3. The density of each mesh layer can be set based on the distribution of thermal stress gradients (for example, the surface mesh is denser to capture high gradient stresses).

[0127] Through layered meshing, this implementation accurately simulates the non-uniform thermal expansion behavior of the second warpage-generating auxiliary body under the second temperature load variation condition, particularly the cumulative effect of layer-by-layer deformation due to differences in thermal expansion coefficients across the thickness, thereby more realistically reproducing the initial warpage of the second incoming material caused by residual stress release in the 3D model of the substrate body. This implementation not only improves the computational stability of thermal-mechanical coupling simulations but also optimizes the accuracy of thermal stress transfer to the 3D model of the substrate body through local mesh refinement, avoiding warpage prediction errors caused by oversimplification of single-layer meshes. This provides a high-fidelity numerical foundation for inverse modeling of complex 3D warpage topography.

[0128] In step S150, based on the second initial warpage of the incoming material generated by the second main body structure, a second temperature load change condition is applied to the three-dimensional model of the substrate body and the second warpage generation auxiliary body, and the model thermal expansion coefficient of the second warpage generation auxiliary body is adjusted to evolve the three-dimensional model of the substrate body to obtain a substrate stacking model with the second initial warpage of the incoming material.

[0129] It should be noted that the second temperature load change condition includes the temperature change range and the temperature gradient distribution mode, which can be specifically set according to the thermal expansion coefficient of the package substrate laminate material and the measured or theoretical data of the initial warpage of the second incoming material.

[0130] For example, the second temperature load change condition may be to reduce the model temperature from 180°C, 175°C or 170°C to 25°C, 24°C or 23°C. This embodiment does not impose any specific restrictions on this and can be flexibly set according to actual conditions.

[0131] This embodiment is based on the principle of thermal-structural coupling. By applying a second temperature load change condition and adjusting the thermal expansion coefficient of the second warpage generating auxiliary body, the thermal stress generated by the difference in thermal expansion coefficient between the three-dimensional model of the substrate body and the second warpage generating auxiliary body is used to guide the three-dimensional model of the substrate body to produce a deformation matching the initial warpage of the second incoming material, thereby obtaining a substrate stacking model with the second initial warpage of the incoming material (i.e., the second initial warpage value of the incoming material) when the packaging substrate stack is incoming is taken into consideration in the warpage simulation, significantly improving the accuracy of the package warpage prediction, and achieving more accurate and reliable chip package warpage prediction, so as to guide the package design and improve the quality and reliability of the chip package products, thereby effectively solving the technical problem of low accuracy in predicting the package warpage of the chip package structure in the related art.

[0132] It should be noted that, in this embodiment, step S150 is performed when the three-dimensional model of the substrate body and the second warpage auxiliary body are in an activated state.

[0133] Step S160 : When the substrate stacking model is obtained, suppressing or deleting the second warpage auxiliary body.

[0134] After completing the warping evolution of the three-dimensional model of the substrate body, this embodiment uses the geometric editing function or property suppression function of the finite element software to remove the second warping auxiliary body from the simulation model or prevent it from participating in subsequent mechanical calculations. Only the substrate stacking model that already has the second initial warping degree of the incoming material is retained, ensuring that the finite element simulation model of the chip packaging structure subsequently constructed only contains the deformation state of the real components (package substrate stack and package substrate stack), avoiding additional interference introduced by the auxiliary body.

[0135] This embodiment achieves high-precision reverse modeling of the initial warpage of the package substrate stack by constructing a virtual auxiliary body on the second target surface and regulating its thermal expansion coefficient, combined with temperature load variation conditions. Compared to the traditional method of directly assigning an initial displacement field, this embodiment generates the initial warpage through a thermal-mechanical coupling mechanism, which is more consistent with the physical nature of material warpage due to residual stress or processing deformation during the actual manufacturing process. At the same time, the dynamic removal mechanism of the auxiliary body ensures the purity of the simulation model in subsequent process site analysis, significantly improving the reliability and process guidance value of the package warpage simulation results.

[0136] In order to facilitate understanding of the technical concept or technical principle of the above-mentioned embodiment of the warping simulation method of the present application, a specific embodiment is listed below:

[0137] This specific embodiment adds an additional auxiliary body below the simulation model of the packaging substrate stack (i.e., the three-dimensional model of the substrate body) and above the simulation model of the heat dissipation cover (i.e., the three-dimensional model of the heat dissipation cover body), respectively. By restricting the structural and material parameters of the auxiliary body and adjusting the thermal expansion coefficient (i.e., the model thermal expansion coefficient), the initial warpage of the incoming material of the packaging substrate stack and the heat dissipation cover is constructed. Combined with the life and death unit technology, the initial warpage of the incoming material is included in the subsequent calculation of the packaging warpage, thereby achieving effective packaging warpage prediction.

[0138] like Figures 6 to 8 As shown, in this specific embodiment, the package warpage simulation model mainly includes a heat dissipation cover 201 (i.e., a heat dissipation cover model), a heat dissipation interface material 301 (i.e., a TIM model), a silicon wafer 302 (i.e., a silicon wafer model), a structural adhesive 303 located below the heat dissipation cover model (i.e., a structural adhesive model), an epoxy resin 304 located below the silicon wafer model (i.e., a filling adhesive model), a package substrate stack (i.e., a substrate stack model) consisting of a core board 402, and 401 and 403 formed by pressing metal traces and dielectric layers above and below the core board 402, as well as an auxiliary body 101 (i.e., a first warpage generating auxiliary body) for constructing the initial warpage of the heat dissipation cover incoming material (i.e., the first incoming material initial warpage), and an auxiliary body 501 (i.e., a second warpage generating auxiliary body) for constructing the initial warpage of the package substrate stack incoming material (i.e., the second incoming material initial warpage).

[0139] In this specific embodiment, the auxiliary body 101 is named lid_construct, and the requirements for lid_construct are as follows:

[0140] (1) The thickness of lid_construct should be consistent with the thickness of the heat dissipation cover 201, and the thickness should be uniform in all directions.

[0141] (2) The length and width of lid_construct should be consistent with the heat dissipation cover 201.

[0142] (3) During modeling, the lower surface of lid_construct should be in contact with the upper surface of the heat dissipation cover 201 (i.e., the first target surface), cannot be tilted, and cannot interfere with the heat dissipation cover 201, and the grid should be divided using a common node method.

[0143] (4) When setting parameters, the Poisson's ratio of lid_construct should be kept the same as that of the heat dissipation cover 201.

[0144] (5) When setting parameters, the Young's modulus of lid_construct should be the same as that of the heat dissipation cover 201. It has been verified that when the Young's modulus is the same, the initial warpage of the incoming material of the heat dissipation cover 201 can be constructed more quickly, thereby improving the calculation efficiency.

[0145] That is, a first warping auxiliary body is constructed on the first target surface of the three-dimensional model of the heat dissipation cover body, the three-dimensional size of the first warping auxiliary body is consistent with the three-dimensional size of the three-dimensional model of the heat dissipation cover body, and the model attribute parameters of the first warping auxiliary body are consistent with the model attribute parameters of the three-dimensional model of the heat dissipation cover body, wherein the model attribute parameters include Poisson's ratio and Young's modulus.

[0146] (6) When dividing the mesh, in order to achieve good calculation accuracy, lid_construct divides the mesh into at least 3 layers in the thickness direction.

[0147] That is, the first warpage auxiliary body is divided into at least three layers of grids in the thickness direction.

[0148] (7) The thermal expansion coefficient of lid_construct can be adjusted to achieve the purpose of constructing the initial warping of the heat dissipation cover material.

[0149] In this specific embodiment, the auxiliary body 501 is named sub_construct, and the requirements for sub_construct are as follows:

[0150] (1) The thickness of the sub_construct should be consistent with the thickness of the package substrate stack, and the thickness should be uniform in all directions.

[0151] (2) The length and width of sub_construct should be consistent with the package substrate stack.

[0152] (3) When modeling, the upper surface of sub_construct should be in contact with the lower surface of the package substrate stack (i.e., the second target surface), cannot be tilted, and cannot interfere with the package substrate stack. The grid should be divided using a common node method.

[0153] (4) When setting parameters, the Poisson's ratio of sub_construct should be kept the same as that of the core plate 402.

[0154] (5) When setting parameters, the Young's modulus of sub_construct should be the same as that of the core board 402. It has been verified that when the Young's modulus is the same, the initial warpage of the package substrate stack can be constructed faster, thereby improving the calculation efficiency.

[0155] That is, a second warping auxiliary body is constructed on the second target surface of the three-dimensional model of the substrate body, the three-dimensional size of the second warping auxiliary body is consistent with the three-dimensional size of the three-dimensional model of the substrate body, and the model attribute parameters of the second warping auxiliary body are consistent with the model attribute parameters of the three-dimensional model of the substrate body, wherein the model attribute parameters include Poisson's ratio and Young's modulus.

[0156] (6) When dividing the mesh, in order to achieve good calculation accuracy, sub_construct is divided into at least three layers of mesh in the thickness direction.

[0157] That is, the second warpage auxiliary body is divided into at least three layers of grids in the thickness direction.

[0158] (7) sub_construct is a single-layer structure and should not be modeled in a stacked manner.

[0159] (8) The thermal expansion coefficient of sub_construct can be adjusted to achieve the purpose of constructing the initial warping of the package substrate stack.

[0160] like Figure 9 As shown, in this specific embodiment, after the package warpage simulation model is constructed and the relevant parameters of each structure in the model are set, the temperature load is loaded step by step.

[0161] like Figure 10 As shown, the horizontal axis is the simulation step, and the vertical axis is the model temperature. In this specific embodiment, the temperature load is divided into 5 steps for loading, as follows:

[0162] First simulation step: the model temperature is reduced from 180℃ to 25℃.

[0163] In the first simulation step, this specific embodiment activates lid_construct, heat dissipation cover 201, package substrate stack (including 401, 402 and 403) and sub_construct in the package warpage simulation model, and suppresses other structures in the model so that they do not play a role in the first simulation step. Then, by adjusting the thermal expansion coefficients of lid_construct and sub_construct, the initial warpage of the incoming material of the heat dissipation cover and the package substrate stack is constructed.

[0164] That is, based on the first initial warpage of the incoming material generated by the first main body structure, a first temperature load change condition is applied to the three-dimensional model of the heat dissipation cover body and the first warpage generation auxiliary body, and combined with adjusting the model thermal expansion coefficient of the first warpage generation auxiliary body, the three-dimensional model of the heat dissipation cover body is evolved to obtain a heat dissipation cover model with the first initial warpage of the incoming material; and based on the second initial warpage of the incoming material generated by the second main body structure, a second temperature load change condition is applied to the three-dimensional model of the substrate body and the second warpage generation auxiliary body, and combined with adjusting the model thermal expansion coefficient of the second warpage generation auxiliary body, the three-dimensional model of the substrate body is evolved to obtain a substrate stacking model with the second initial warpage of the incoming material.

[0165] Second simulation step: the model temperature increases from 25℃ to 165℃.

[0166] In the second simulation step, based on the first simulation step, this specific embodiment suppresses all structures in the entire package warpage simulation model, and then increases the model temperature from 25°C (room temperature, i.e., the preset ambient temperature) to 165°C (the curing temperature of the epoxy resin 304, i.e., the first curing temperature) to ensure that the initial warpage of the incoming materials of the heat dissipation cover and the package substrate stack remains unchanged.

[0167] That is, the finite element simulation model is suppressed, and the model temperature is adjusted to the first curing process temperature of the underfill.

[0168] The third simulation step: the model temperature is reduced from 165℃ to 25℃.

[0169] In the third simulation step, based on the second simulation step, this specific embodiment activates the silicon wafer 302, epoxy resin 304 and package substrate stack in the package warpage simulation model, and then reduces the model temperature from 165°C to 25°C to simulate the warpage of the structure after filling with epoxy resin at room temperature.

[0170] That is, after adjusting to the first curing process temperature, the silicon wafer model, the filling glue model and the substrate stacking model are activated, and the model temperature is lowered from the first curing process temperature to the preset ambient temperature to simulate the package warping generated by the process station of fixing the silicon wafer, and obtain a first package warping simulation model.

[0171] The fourth simulation step: the model temperature increases from 25℃ to 150℃.

[0172] In the fourth simulation step, based on the third simulation step, this specific embodiment increases the model temperature from 25° C. to 150° C. (the process temperature for attaching the heat dissipation cover, ie, the second curing temperature).

[0173] That is, when the first package warpage simulation model is in an activated state, the model temperature is adjusted to the second curing process temperature of both the TIM and the structural adhesive.

[0174] Fifth simulation step: the model temperature is reduced from 150℃ to 25℃.

[0175] In the fifth simulation step, based on the fourth simulation step, this specific embodiment activates the heat dissipation cover 201, the heat dissipation interface material 301 and the structural adhesive 303 located under the heat dissipation cover in the package warpage simulation model, and then reduces the model temperature from 150°C to 25°C to simulate the package warpage after ball implantation.

[0176] That is, after adjusting to the second curing process temperature, the TIM model, structural adhesive model and heat dissipation cover model are activated, and the model temperature is lowered from the second curing process temperature to the preset ambient temperature to simulate the package warpage generated by the process station of fixing the heat dissipation cover, and obtain the target package warpage simulation model.

[0177] In one example, after a warpage test is performed on a packaged chip structure, the measurement results are as follows: Figure 11 As shown, the warpage of the packaged chip structure is -22.9 microns. After the warpage simulation method of the related art that does not consider the initial warpage of the incoming material is used to simulate the warpage of the packaged chip structure, the simulation results are as follows: Figure 12 As shown, the warpage of the packaged chip structure is -31.3 microns. After the warpage simulation method provided in this specific embodiment is used to simulate the warpage of the packaged chip structure, the simulation results are as follows: Figure 13 As shown, the warpage of the packaged chip structure is -26.7 microns.

[0178] As shown in the table below, the simulation accuracy of the related art is only 63%, while the simulation accuracy of this specific embodiment can reach 83%, which can improve the package warpage simulation accuracy by nearly 20%.

[0179] Warpage / micron Simulation accuracy Warpage test -22.9 / Related technologies -31.3 63％ This specific embodiment -26.7 83％ Improved accuracy / 20％

[0180] It should be noted that the above examples are only used to assist in understanding the present application and do not constitute a limitation on the warping simulation method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0181] In addition, please refer to Figure 14 , Figure 14 Schematic diagram of the device structure of the hardware operating environment involved in the warping simulation method in the embodiment of the present application.

[0182] The present application also provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the steps of the warping simulation method in the above embodiment.

[0183] Reference below Figure 14 , which shows a schematic diagram of the structure of an electronic device suitable for implementing the embodiments of the present application. The electronic device in the embodiments of the present application may include, but is not limited to, mobile terminals such as laptop computers, PADs (Portable Application Description, tablet computers), etc., and fixed terminals such as desktop computers, etc., or any other electronic device capable of implementing the above functions. Figure 14 The electronic device shown is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0184] like Figure 14 As shown, the electronic device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in a read-only memory 1002 or programs loaded from a storage device 1003 into a random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the electronic device. The processing device 1001, the read-only memory 1002, and the random access memory 1004 are connected to each other via a bus 1005. An input / output interface 1006 is also connected to the bus. Typically, the following systems can be connected to the input / output interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. Although the figures show electronic devices with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have instead.

[0185] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program comprising program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device 1003, or installed from a read-only memory 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are performed.

[0186] The electronic device provided in this application utilizes the warpage simulation method described in the aforementioned embodiments, resolving the technical issue of low accuracy in predicting chip package warpage in the related art. Compared to the prior art, the electronic device provided in this application achieves the same beneficial effects as the warpage simulation method described in the aforementioned embodiments. Other technical features of this electronic device are the same as those disclosed in the aforementioned embodiments and are not further elaborated upon here.

[0187] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0188] The above are merely specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the above claims.

[0189] In addition, the present application also provides a computer-readable storage medium having computer-readable program instructions (ie, a computer program) stored thereon, and the computer-readable program instructions are used to execute the steps of the warping simulation method in the above embodiment.

[0190] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory, a read-only memory (erasable programmable read-only memory, an optical fiber, a portable compact disk read-only memory, an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0191] The computer-readable storage medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0192] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by an electronic device, the electronic device: models the heat dissipation cover based on the first body structure of the heat dissipation cover and the first incoming material initial warpage generated by the first body structure, and obtains a heat dissipation cover model with the first incoming material initial warpage; models the packaging substrate stack based on the second body structure of the packaging substrate stack and the second incoming material initial warpage generated by the second body structure, and obtains a substrate stack model with the second incoming material initial warpage; constructs a finite element simulation model corresponding to the chip packaging structure based on the heat dissipation cover model and the substrate stack model; based on the finite element simulation model, simulates the packaging warpage generated by the process in combination with the temperature load of at least one process station under the process of the chip packaging structure, and obtains a target packaging warpage simulation model.

[0193] Computer program code for performing the operations of the present application can be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0194] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0195] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0196] The computer-readable storage medium provided in this application stores computer-readable program instructions (i.e., a computer program) for executing the steps of the aforementioned warpage simulation method. This addresses the technical issue of low accuracy in predicting chip package warpage in related art. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided in this application are similar to those of the warpage simulation method provided in the aforementioned embodiments, and are not further elaborated here.

[0197] In addition, an embodiment of the present application also provides a computer program product, including a computer program, which implements the steps of the warping simulation method in the above embodiment when executed by a processor.

[0198] The computer program product provided in this application can address the low accuracy of chip package warpage prediction in related technologies. Compared to the prior art, the beneficial effects of the computer program product provided in this embodiment are similar to those of the warpage simulation method provided in the aforementioned embodiment, and are not further elaborated here.

[0199] The above description is only part of the embodiments of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A warpage simulation method, the warpage simulation method being applied to a chip packaging structure comprising a heat dissipation cover and a packaging substrate stack disposed on opposite sides, the method comprising: Based on the first body structure of the heat dissipation cover and the first initial warpage of the incoming material generated by the first body structure, the heat dissipation cover is modeled to obtain a heat dissipation cover model having the first initial warpage of the incoming material; based on the second body structure of the package substrate stack and the second initial warpage of the incoming material generated by the second body structure, the package substrate stack is modeled to obtain a substrate stack model having the second initial warpage of the incoming material; Based on the heat dissipation cover model and the substrate stack model, a finite element simulation model corresponding to the chip packaging structure is constructed; Based on the finite element simulation model and in combination with the temperature load of at least one process station in the process of the chip packaging structure, the package warpage generated by the process is simulated to obtain a target package warpage simulation model.

2. The warping simulation method according to claim 1, wherein: The chip packaging structure further includes a silicon wafer, and an underfill filler filled between the packaging substrate stack and the contact surface of the silicon wafer, the finite element simulation model further includes a silicon wafer model corresponding to the silicon wafer, and a filler model corresponding to the underfill filler, and the process station includes a fixed silicon wafer; The method of simulating the package warpage generated by the process based on the finite element simulation model and combining the temperature load of at least one process station in the process of the chip package structure to obtain a target package warpage simulation model includes: suppressing the finite element simulation model and adjusting the model temperature to a first curing process temperature of the underfill; After adjusting to the first curing process temperature, activating the silicon wafer model, the filler model, and the substrate stack model, and lowering the model temperature from the first curing process temperature to a preset ambient temperature to simulate package warpage generated by the process station for fixing the silicon wafer, thereby obtaining a first package warpage simulation model; A target package warpage simulation model is obtained based on the first package warpage simulation model.

3. The warping simulation method according to claim 2, wherein: Obtaining a target package warpage simulation model based on the first package warpage simulation model includes: Based on the first package warpage simulation model and combined with the temperature loads of other process sites except the fixed silicon wafer under the process, the package warpage generated by the process is simulated to obtain a target package warpage simulation model.

4. The warping simulation method according to claim 2 or 3, wherein: The first curing process temperature ranges from 150°C to 165°C.

5. The warping simulation method according to claim 3, wherein: The chip packaging structure further includes a thermal interface material (TIM) filled between the contact surface of the silicon chip and the heat dissipation cover, and a structural adhesive filled between the contact surface of the heat dissipation cover and the package substrate stack. The finite element simulation model also includes a TIM model corresponding to the TIM and a structural adhesive model corresponding to the structural adhesive. The process station also includes a fixed heat dissipation cover. Based on the first package warpage simulation model, combined with the temperature loads of other process stations except for the fixed silicon wafer under the process, the package warpage generated by the process is simulated to obtain a target package warpage simulation model, including: When the first package warpage simulation model is in an activated state, adjusting the model temperature to a second curing process temperature of both the TIM and the structural adhesive; After adjusting to the second curing process temperature, the TIM model, the structural adhesive model and the heat dissipation cover model are activated, and the model temperature is lowered from the second curing process temperature to a preset ambient temperature to simulate the package warpage generated by the process station of fixing the heat dissipation cover, thereby obtaining a target package warpage simulation model.

6. The warpage simulation method according to claim 5, wherein: The second curing process temperature ranges from 125°C to 150°C.

7. The warpage simulation method according to claim 1, wherein: Based on the first body structure of the heat dissipation cover and the first initial warpage of the incoming material generated by the first body structure, the heat dissipation cover is modeled to obtain a heat dissipation cover model having the first initial warpage of the incoming material, including: Based on the first body structure of the heat dissipation cover, a three-dimensional model of the heat dissipation cover body corresponding to the first body structure is modeled, and a first warping auxiliary body is constructed on a first target surface of the three-dimensional model of the heat dissipation cover body; Based on the first initial warpage of the incoming material generated by the first body structure, a first temperature load variation condition is applied to the three-dimensional model of the heat dissipation cover body and the first warpage generation auxiliary body, and the model thermal expansion coefficient of the first warpage generation auxiliary body is adjusted to evolve the three-dimensional model of the heat dissipation cover body into a heat dissipation cover model having the first initial warpage of the incoming material; When the heat dissipation cover model is obtained, the first warpage auxiliary body is suppressed or deleted.

8. The warpage simulation method according to claim 7, wherein: The three-dimensional size of the first warping auxiliary body is consistent with the three-dimensional size of the three-dimensional model of the heat dissipation cover body, and the model attribute parameters of the first warping auxiliary body are consistent with the model attribute parameters of the three-dimensional model of the heat dissipation cover body, wherein the model attribute parameters include Poisson's ratio and Young's modulus.

9. The warpage simulation method according to claim 7, wherein: The first warpage auxiliary body is divided into at least three layers of grids in a thickness direction.

10. The warpage simulation method according to claim 1, wherein: Modeling the package substrate stack based on the second body structure of the package substrate stack and the second incoming material initial warpage generated by the second body structure to obtain a substrate stack model having the second incoming material initial warpage, including: Based on the second body structure of the package substrate stack, a three-dimensional model of the substrate body corresponding to the second body structure is modeled, and a second warpage generation auxiliary body is constructed on a second target surface of the three-dimensional model of the substrate body; Based on the second initial warpage of the incoming material generated by the second body structure, a second temperature load change condition is applied to the three-dimensional model of the substrate body and the second warpage auxiliary body, and the model thermal expansion coefficient of the second warpage auxiliary body is adjusted to evolve the three-dimensional model of the substrate body into a substrate stack model having the second initial warpage of the incoming material; When the substrate stacking model is obtained, the second warp generation auxiliary body is suppressed or deleted.

11. The warpage simulation method according to claim 10, wherein: The three-dimensional size of the second warping auxiliary body is consistent with the three-dimensional size of the substrate body three-dimensional model, and the model attribute parameters of the second warping auxiliary body are consistent with the model attribute parameters of the substrate body three-dimensional model, wherein the model attribute parameters include Poisson's ratio and Young's modulus.

12. The warpage simulation method according to claim 10, wherein: The second warpage auxiliary body is divided into at least three layers of grids in a thickness direction.

13. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the warpage simulation method according to any one of claims 1 to 12 is implemented.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the warping simulation method according to any one of claims 1 to 12 is implemented.

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