Display method and device of integrated circuit chip, storage medium and electronic equipment

Abstract

The invention relates to an integrated circuit chip display method and device, a storage medium and electronic equipment, and relates to the technical field of chips, and the method comprises the steps: firstly obtaining a configuration file of an integrated circuit; determining a stacking structure of chips in the integrated circuit according to information in the configuration file; and then mapping the stacked structure to an editable three-dimensional visual interface to obtain a three-dimensional view of the chip. By applying the technical scheme of the invention, the stacking structure of each chip in the integrated circuit is determined according to the detailed information in the configuration file, and then the stacking structure of the chips in the integrated circuit is displayed in a three-dimensional visual mode, so that the visual understanding of a user on the spatial relationship and the connection mode between the chips in the integrated circuit is obviously improved, and the user experience is improved. And a customized stacking scene can be conveniently constructed and adjusted through the editing interface, so that the design efficiency and flexibility are improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a display method, device, storage medium, and electronic device for an integrated circuit chip. Background Art

[0002] In integrated circuit layout design, three-dimensional integrated circuit (3DIC) is an advanced packaging technology that achieves higher integration and performance by vertically stacking multiple chips or wafer layers. Multi-layer stacking allows different types of chips (such as logic chips and memory chips) to be integrated together, supporting heterogeneous integration and providing greater flexibility for system-level packaging.

[0003] Currently, integrated circuit layout designs are mostly displayed and manipulated in a two-dimensional format. However, this two-dimensional display method cannot visually demonstrate the spatial relationships and connections between chips, limiting the efficiency and flexibility of integrated circuit design. Summary of the Invention

[0004] In view of this, the present application provides a method, device, storage medium and electronic device for displaying integrated circuit chips. The main purpose is to improve the technical problem that the current existing technology cannot intuitively display the spatial relationship and connection method between chips, which limits the design efficiency and flexibility of integrated circuits.

[0005] In a first aspect, the present application provides a method for displaying an integrated circuit chip, comprising:

[0006] Get the configuration file of the integrated circuit;

[0007] determining a stacking structure of chips in the integrated circuit according to information in the configuration file;

[0008] The stacking structure is mapped to an editable three-dimensional visualization interface to obtain a three-dimensional view of the chip.

[0009] Optionally, mapping the stacking structure to an editable three-dimensional visualization interface to obtain a three-dimensional view of the chip includes:

[0010] generating a three-dimensional model corresponding to the stacking structure of the chips according to the stacking parameters in the configuration file;

[0011] The three-dimensional model is rendered into the three-dimensional visualization interface to generate the three-dimensional view.

[0012] Optionally, the method further includes:

[0013] In response to a movement instruction initiated by a user on the three-dimensional visualization interface, dynamically adjusting the stacking order of the first chip in the integrated circuit layout;

[0014] According to the stacking sequence, a three-dimensional view including the first chip is updated.

[0015] Optionally, the method further includes:

[0016] In response to a modification instruction initiated by a user on the three-dimensional visualization interface, dynamically adjusting a connection mode between the second chip and the third chip;

[0017] According to the connection mode, a three-dimensional view including the second chip and the third chip is updated.

[0018] Optionally, the configuration file includes attribute information of each chip and connection information between different chips.

[0019] Optionally, determining the stacking structure of chips in the integrated circuit according to the information in the configuration file includes:

[0020] Extracting configuration parameters of each chip from the configuration file, wherein the configuration parameters are used to define the spatial layout of each chip;

[0021] Based on the configuration parameters, determining the position and posture of each chip in three-dimensional space;

[0022] The stacking structure of the chips in the integrated circuit is determined according to the position and posture.

[0023] Optionally, determining the position and posture of each chip in three-dimensional space based on the configuration parameters includes:

[0024] Determining the position of each chip in the three-dimensional space according to the position coordinate information in the configuration parameters;

[0025] The posture of each chip in the three-dimensional space is determined according to the rotation angle information in the configuration parameters.

[0026] In a second aspect, the present application provides an integrated circuit chip display device, comprising:

[0027] an acquisition module, configured to acquire a configuration file of the integrated circuit;

[0028] a determination module configured to determine a stacking structure of chips in the integrated circuit according to information in the configuration file;

[0029] A mapping module is configured to map the stacking structure to an editable three-dimensional visualization interface to obtain a three-dimensional view of the chip.

[0030] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the method described in the first aspect when the computer program is executed by a processor.

[0031] In a fourth aspect, the present application provides an electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor implements the method described in the first aspect when executing the computer program.

[0032] By means of the above technical solution, the present application provides a method, device, storage medium, and electronic device for displaying integrated circuit chips. Specifically, the method first obtains a configuration file for the integrated circuit; then, based on the information in the configuration file, determines the stacking structure of the chips in the integrated circuit; and then maps the stacking structure to an editable three-dimensional visualization interface to obtain a three-dimensional view of the chips. Compared with the current existing technology, by applying the technical solution of the present application, the stacking structure of each chip in the integrated circuit is determined based on the detailed information in the configuration file, and then the stacking structure of the chips in the integrated circuit is displayed in a three-dimensional visualization. This significantly improves the user's intuitive understanding of the spatial relationship and connection method between the chips in the integrated circuit. Furthermore, customized stacking scenarios can be conveniently constructed and adjusted through the editing interface, thereby improving design efficiency and flexibility.

[0033] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0036] Figure 1 A schematic diagram showing a flow chart of a method for displaying an integrated circuit chip provided in an embodiment of the present application is shown;

[0037] Figure 2 A schematic diagram showing a flow chart of another integrated circuit chip display method provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram showing an application example provided by an embodiment of the present application is shown;

[0039] Figure 4 A schematic diagram showing an application example provided by an embodiment of the present application is shown;

[0040] Figure 5 A schematic diagram showing an application example provided by an embodiment of the present application is shown;

[0041] Figure 6 A schematic structural diagram of an integrated circuit chip display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0042] In order to more clearly understand the above-mentioned objectives, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0043] In order to improve the technical problem that the existing technology cannot intuitively display the spatial relationship and connection mode between chips, which limits the design efficiency and flexibility of integrated circuits, this embodiment provides a method for displaying integrated circuit chips, such as Figure 1 As shown, the method includes:

[0044] Step 101: Obtain a configuration file of an integrated circuit.

[0045] For example, the configuration file may include attribute information of each chip and connection information between different chips.

[0046] In some examples, by reading the configuration file of the initial 3DIC design (such as an XML format file), detailed information such as the name, position, transformation (Transform) of each sub-chip (chip) included in the layout and the connection (Connection) between each chip can be parsed and displayed.

[0047] For example, attribute information can include each chip's name, type (e.g., HBM, ASIC, logic chip), size, location coordinates, and transformation parameters (e.g., rotation angle, scaling ratio). These details collectively describe the characteristics and layout of a single chip in three-dimensional space. Connection information details how different chips are connected to each other, including the location of the connection points, the electrical characteristics of each connection (e.g., bandwidth, latency), and the physical connection method (e.g., through-silicon vias, microbumps, etc.).

[0048] Step 102: Determine the stacking structure of the chips in the integrated circuit according to the information in the configuration file.

[0049] In some examples, the configuration file contains key attribute information of each sub-chip, such as name, type, size, position coordinates and transformation parameters (such as rotation angle and scaling), as well as connection information between different chips, including the location and electrical characteristics of the connection points. The position and orientation of each sub-chip in three-dimensional space are accurately located based on the attribute information. Then, by analyzing the connection information, the physical connection method and electrical connection requirements between the chips are clarified, such as using micro-bumps or silicon through-via technology to achieve interconnection paths, and then a detailed 3D stacking model can be constructed. The model not only shows the spatial layout of all sub-chips, but also accurately defines how to connect them efficiently and reliably. This process concretizes the design of complex integrated circuits and ensures that the final stacking structure meets the predetermined design specifications and technical standards.

[0050] Step 103: Map the stacking structure to an editable three-dimensional visualization interface to obtain a three-dimensional view of the chip.

[0051] In some examples, a specialized software tool first reads the chip attribute and connection information from the configuration file. This information includes each sub-chip's name, type, size, location coordinates, transformation parameters, and inter-chip connection details. By parsing this data, the spatial layout of each sub-chip and its relative position are precisely located and displayed in a 3D visualization interface. Based on this connection information, the physical connections between the chips are then displayed in the visualization, ensuring accurate and visible electrical connections.

[0052] For example, users can not only intuitively view the 3D view of the chip stacking method of the entire integrated circuit, but also perform editing operations within the interface, such as adjusting the chip position and modifying the connection method. This interactive 3D visualization environment greatly simplifies the design process of complex integrated circuits, allowing users to more conveniently build and optimize customized 3DIC stacking scenarios.

[0053] This embodiment first obtains an integrated circuit configuration file; then, based on the information in the configuration file, determines the chip stacking structure within the integrated circuit; and then maps the stacking structure to an editable 3D visualization interface, resulting in a 3D view of the chips. Compared to existing technologies, this embodiment determines the stacking structure of each chip within the integrated circuit based on the detailed information in the configuration file and then displays the stacking structure within the integrated circuit in a 3D visualization. This significantly improves the user's intuitive understanding of the spatial relationships and connections between the chips within the integrated circuit. Furthermore, customized stacking scenarios can be easily constructed and adjusted through the editing interface, thereby improving design efficiency and flexibility.

[0054] Furthermore, as a refinement and extension of the above embodiment, in order to fully illustrate the specific implementation process of the method of this embodiment, this embodiment provides the following Figure 2 The specific method shown includes:

[0055] Step 201: Obtain a configuration file of an integrated circuit.

[0056] For example, during the design phase of an integrated circuit, electronic design automation (EDA) software can be used to create circuit diagrams and layouts. This software can generate configuration files, such as XML files, containing chip attribute and connection information. To obtain such configuration files, designers can use the export function of the EDA tool to generate them directly from the design project. Alternatively, they can obtain them by consulting product manuals or visiting the manufacturer's official website.

[0057] Optionally, the configuration file includes attribute information of each chip and connection information between different chips.

[0058] In some examples, attribute information ensures that each chip is precisely placed and oriented, while connection information ensures that signals and power can be transmitted efficiently and reliably between chips, providing the necessary data for the subsequent construction of a three-dimensional model of the chip stacking structure.

[0059] Step 202: Determine the stacking structure of the chips in the integrated circuit according to the information in the configuration file.

[0060] For example, when determining the chip stacking structure within an integrated circuit based on information in a configuration file, the first step is to extract the attributes of each chip, including type, size, power consumption, and functionality. The chip connections between them must then be analyzed to determine signal transmission paths, dependencies, and communication protocols. When designing the stacking structure, factors such as chip power consumption, heat dissipation requirements, signal integrity, and functional module division must be comprehensively considered. Generally, chips with high power consumption and high heat generation should be placed in the lower or middle layers of the stack to facilitate heat dissipation; chips with low power consumption and high signal integrity requirements should be placed in the upper layers. For example, suppose the configuration file contains a main control chip A (large size, high power consumption), a memory chip B (small size, low power consumption), and a communication chip C (medium size, low power consumption). Chips A and B are connected via a high-speed data bus, while chips A and C have control and communication signal connections. Based on this, chip A is placed in the lower layer of the stack as the core control unit of the entire integrated circuit. Chip B, due to its lower power consumption and the need for high-speed data transmission with chip A, can be placed above or immediately adjacent to chip A to shorten the data bus length and increase the data transmission rate. Since chip C needs to communicate with external devices and has high requirements for signal integrity, it can be placed in the upper layer of the stacked structure or near the edge to better receive and send signals.

[0061] For example, the main control chip A is located at the bottom layer, serving as the core control unit. The memory chip B is located immediately above chip A and connected to it via a high-speed data bus. The communication chip C is located at the top or edge of the stack, connected to chip A via control and communication signals, and responsible for communicating with other devices or modules. This stacking structure fully considers factors such as chip power consumption, heat dissipation, signal integrity, and functional module division, ensuring the performance and reliability of the integrated circuit.

[0062] In some examples, it is first necessary to parse the file to extract the attribute information of each chip, including name, type, size, power consumption and function, and analyze the connection information between different chips, such as signal transmission path, dependencies and communication protocols. Through these data, the specific position of each chip in three-dimensional space and its positional relationship relative to other chips can be clearly determined. Chips with high power consumption or high heat generation are usually arranged in the lower or middle layers of the stacking structure to facilitate heat dissipation, while low-power chips with higher signal integrity requirements are placed in the upper layer. Based on the connection information, the layout between chips is optimized to ensure the shortest signal transmission path and reduce delays and interference. In this way, combined with all the necessary information provided by the configuration file, the current stacking structure of the chip can be accurately reconstructed, and its performance can be evaluated and necessary optimization adjustments can be made.

[0063] Optionally, step 202 may specifically include: extracting configuration parameters of each chip from a configuration file, the configuration parameters being used to define the spatial layout of each chip; determining the position and posture of each chip in three-dimensional space based on the configuration parameters; and determining the stacking structure of the chips in the integrated circuit based on the position and posture.

[0064] For example, configuration parameters such as the chip name, type, size, power consumption, function, and its position and posture in three-dimensional space are extracted from the configuration file to accurately define the spatial layout of each chip. Based on these configuration parameters, the specific position and posture of each chip in three-dimensional space are accurately determined to ensure that the relative position relationship between all chips is correct. Then, the stacking structure of the chips in the integrated circuit is constructed based on the determined position and posture information, and high-power chips are reasonably distributed to optimize the heat dissipation effect. Chips with high signal integrity requirements are placed in appropriate positions to reduce interference and signal delays. Through this systematic approach, the precise layout and optimization of the integrated circuit chip stacking structure are achieved, ensuring that the final design meets both performance requirements and has good manufacturability and reliability.

[0065] Optionally, the above-mentioned determination of the position and posture of each chip in the three-dimensional space based on the configuration parameters may specifically include: determining the position of each chip in the three-dimensional space according to the position coordinate information in the configuration parameters; determining the posture of each chip in the three-dimensional space according to the rotation angle information in the configuration parameters.

[0066] In some examples, the position and orientation of each chip in three-dimensional space can be determined based on the position coordinate information and rotation angle information in the configuration parameters. First, the configuration parameters are parsed to extract the coordinate information for each chip, typically including the x, y, and z values ​​in a three-dimensional coordinate system, thereby clarifying the chip's specific position in three-dimensional space. Simultaneously, the rotation angle information for each chip is obtained, which may involve rotation angles around the x, y, and z axes to determine the chip's orientation in three-dimensional space. Based on the extracted coordinate information, each chip is then placed at the corresponding coordinate point in three-dimensional space to complete the position determination. Subsequently, each chip is rotated based on the rotation angle information. For example, if a chip needs to be rotated 30 degrees around the z-axis, a corresponding rotation transformation is applied to adjust its orientation in three-dimensional space. By combining coordinate positioning and rotation transformation, the position and orientation of each chip in three-dimensional space can be precisely determined, providing accurate spatial layout information for subsequent integrated circuit design and analysis.

[0067] Step 203: Generate a three-dimensional model corresponding to the chip stacking structure according to the stacking parameters in the configuration file.

[0068] In some examples, stacking parameters can be extracted by parsing a configuration file, including the position coordinates, rotation angle, dimensions, and stacking hierarchy of each chip. The position coordinates and rotation angles are used to determine the position and orientation of the chip in three-dimensional space, the dimensions are used to model the chip's appearance, and the hierarchy defines the stacking order and structure. The extracted parameters are then used for 3D modeling. Based on the position coordinates and rotation angles, each chip is placed at its corresponding position in three-dimensional space and its orientation is adjusted. Subsequently, a 3D model is created for each chip based on the dimensions, ensuring that the model's geometry aligns with the chip's actual dimensions. Finally, the 3D models of each chip are stacked according to the hierarchy to form a complete stacked structure. During the stacking process, it is necessary to ensure that the connectivity and spatial layout between the chips conform to the definitions in the configuration file to ensure the accuracy and reliability of the 3D model. Through these steps, a 3D model accurately describing the chip stacking structure can be generated based on the stacking parameters in the configuration file, providing intuitive spatial layout information for subsequent design and analysis.

[0069] Step 204: Render the 3D model into a 3D visualization interface to generate a 3D view.

[0070] For example, after providing the corresponding configuration file, the user can use the page editing tool to intuitively view the attribute information of each chip and the connection information between different chips, and conveniently construct and customize the 3DIC stacking scenario. This process not only simplifies the complexity of 3DIC design, but also provides users with an interactive platform to adjust and optimize the stacking structure to ensure that the design meets specific requirements, greatly enhancing design flexibility and efficiency, and making complex integrated circuit design more intuitive and easy to manage.

[0071] Optionally, the method of this embodiment may further specifically include: dynamically adjusting the stacking order of the first chip in the integrated circuit layout in response to a move instruction initiated by the user in the three-dimensional visualization interface; and updating the three-dimensional view including the first chip according to the stacking order.

[0072] In some examples, the system can dynamically adjust the stacking order of a first chip within the integrated circuit layout in response to a user-initiated move instruction for the first chip within the 3D visualization interface, enabling more flexible design optimization. Based on the updated stacking order, the system automatically recalculates and adjusts the spatial layout and posture of all related chips, including the first chip, to ensure their relative positions are accurate. The 3D view is instantly updated based on the new layout information, allowing users to intuitively view the adjusted integrated circuit stacking structure.

[0073] Optionally, the method of this embodiment may further include: dynamically adjusting the connection mode between the second chip and the third chip in response to a modification instruction initiated by the user in the three-dimensional visualization interface; and updating the three-dimensional view including the second chip and the third chip according to the connection mode.

[0074] In some examples, the system can dynamically adjust the connection between the second and third chips in response to modification instructions initiated by the user in the 3D visualization interface to optimize signal transmission paths or meet specific design requirements. Based on the updated connection method, the system automatically recalculates and adjusts the interconnection paths and layout between the two chips to ensure that the new design meets electrical characteristics requirements and minimizes signal delays and interference. The 3D view is then updated instantly based on the adjusted connection information, allowing users to intuitively view the new connection relationship between the second and third chips and their specific performance in the stacked structure.

[0075] For example, Figure 3 The interface of the 3DIC stack editing tool shown in the figure can be used to design and adjust the stacking structure of a three-dimensional integrated circuit (3DIC). The panel on the left lists all the chips and their types in the current design, including Chip1 (HBM1), Chip2 (HBM2), Chip3 (ASIC), Chip4 (LOGIC) and Chip5 (INTERPOSER). The three-dimensional view in this embodiment intuitively presents the stacking layout of these chips in space, and the above three-dimensional view can also be used to display the contact layer information between each chip, specifically including the connection layer (Layer) between the top chip (TOP Chip) and the bottom chip (BTM Chip), such as the connection between the top layer (M1 drawing) of Chip1 and the bottom layer (RDV drawing) of Chip5. Users can select and move chips through the "Select" and "Move" buttons on the interface to dynamically adjust the stacking structure and view the adjusted three-dimensional view in real time.

[0076] For example, in Figure 4In the new layout, users can click the "Move" button and use the mouse to drag to swap the stacking of Chip3 and Chip4. Specifically, in the new layout, Chip4 is adjusted above Chip3, and Chip3 is adjusted below Chip4. In addition, the connection layer information in the table below will also be modified accordingly: the top layer of Chip4 changes from "M1 drawing" to "M2 drawing", and its bottom chip changes from "Chip5" to "Chip3"; at the same time, the top layer of Chip3 changes from "M1 drawing" to "M2 drawing", and its bottom chip changes from "Chip5" to "Chip4".

[0077] In some examples, the "Modify" button at the bottom of the interface can be used to further modify the contact layer information between related chips to ensure that the new stacking structure meets the design requirements in terms of electrical characteristics and signal integrity.

[0078] In some examples, you can first get Figure 5 The initial configuration file (such as XML format) shown in the figure defines the properties and connection information of each chip in detail. For example, the configuration file contains parameters such as chip name, type, size, power consumption, function, position and posture in three-dimensional space, and clarifies the connection method between chips. Next, the configuration file path is passed to a dedicated 3DIC layout editing tool through the command line. After starting the tool, the system reads the information in the configuration file and generates a three-dimensional visualization interface to display the stacking structure of all chips and their connection relationships. Users can intuitively view the current stacking layout on this interface and dynamically adjust the position, posture or connection method of the chip according to design requirements. For example, in response to a modification instruction initiated by the user, the tool can update the connection path between the second chip and the third chip in real time, and automatically adjust the involved three-dimensional views to ensure that the new connection method is accurately presented in the three-dimensional space, thereby being able to efficiently optimize the 3DIC layout to meet multiple requirements such as performance, heat dissipation and signal integrity.

[0079] Compared with the current existing technology, this embodiment determines the stacking structure of each chip in the integrated circuit based on the detailed information in the configuration file, and then displays the stacking structure of the chips in the integrated circuit in a three-dimensional visual manner, which significantly improves the user's intuitive understanding of the spatial relationship and connection method between the chips in the integrated circuit. It can then conveniently construct and adjust customized stacking scenarios through the editing interface, thereby improving design efficiency and flexibility.

[0080] Further, as Figure 1 The embodiment of the present invention provides a display device for integrated circuit chips, such as Figure 6As shown, the device includes: an acquisition module 31, a determination module 32, and a mapping module 33.

[0081] An acquisition module 31 is configured to acquire a configuration file of the integrated circuit;

[0082] a determination module 32 configured to determine a stacking structure of chips in the integrated circuit according to information in the configuration file;

[0083] The mapping module 33 is configured to map the stacking structure to an editable three-dimensional visualization interface to obtain a three-dimensional view of the chip.

[0084] In some examples, the mapping module 33 is specifically configured to generate a three-dimensional model corresponding to the stacking structure of the chip according to the stacking parameters in the configuration file; and render the three-dimensional model into the three-dimensional visualization interface to generate the three-dimensional view.

[0085] In some examples, the mapping module 33 is further configured to dynamically adjust the stacking order of the first chip in the integrated circuit layout in response to a movement instruction initiated by the user in the three-dimensional visualization interface; and update the three-dimensional view including the first chip according to the stacking order.

[0086] In some examples, the mapping module 33 is further configured to dynamically adjust the connection mode between the second chip and the third chip in response to a modification instruction initiated by the user in the three-dimensional visualization interface; and update the three-dimensional view including the second chip and the third chip according to the connection mode.

[0087] In some examples, the configuration file includes attribute information of each chip and connection information between different chips.

[0088] In some examples, the determination module 32 is specifically configured to extract configuration parameters of each chip from the configuration file, where the configuration parameters are used to define the spatial layout of each chip; determine the position and posture of each chip in three-dimensional space based on the configuration parameters; and determine the stacking structure of the chips in the integrated circuit based on the position and posture.

[0089] In some examples, the determination module 32 is further configured to determine the position of each chip in the three-dimensional space based on the position coordinate information in the configuration parameters; and determine the posture of each chip in the three-dimensional space based on the rotation angle information in the configuration parameters.

[0090] Based on the above Figure 1 and Figure 2The method shown in FIG. 1 is a method for performing the above-mentioned steps. Accordingly, this embodiment further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program can realize the above-mentioned steps. Figure 1 and Figure 2 The method shown.

[0091] Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, USB flash drive, mobile hard disk, etc.), and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of the present application.

[0092] Based on the above Figure 1 and Figure 2 The method shown, and Figure 6 In order to achieve the above-mentioned purpose, the embodiment of the present application further provides an electronic device, which may include a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to achieve the above-mentioned Figure 1 and Figure 2 The method shown.

[0093] Optionally, the physical device may further include a user interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a Wi-Fi module, and the like. The user interface may include a display, an input unit such as a keyboard, and the like. The optional user interface may also include a USB interface, a card reader interface, and the like. The network interface may optionally include a standard wired interface, a wireless interface (such as a Wi-Fi interface), and the like.

[0094] Those skilled in the art will understand that the above-mentioned physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or a combination of certain components, or different component arrangements.

[0095] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the physical device, supporting the execution of information processing programs and other software and / or programs. The network communication module is used to enable communication between components within the storage medium, as well as with other hardware and software within the physical information processing device.

[0096] Through the description of the above implementation methods, those skilled in the art can clearly understand that the present application can be implemented by means of software plus the necessary general hardware platform, or by means of hardware. By applying the solution of this embodiment, the stacking structure of each chip in the integrated circuit is determined based on the detailed information in the configuration file, and then the stacking structure of the chips in the integrated circuit is displayed in a three-dimensional visual manner, which significantly improves the user's intuitive understanding of the spatial relationship and connection method between the chips in the integrated circuit, and then can conveniently construct and adjust customized stacking scenarios through the editing interface, thereby improving design efficiency and flexibility.

[0097] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article or device. In the absence of further limitations, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0098] The above are merely specific embodiments of the present application, which are intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments herein, but rather is intended to conform to the widest scope consistent with the principles and novel features of the present application.

Claims

1. A method for displaying an integrated circuit chip, characterized in that: include: Get the configuration file of the integrated circuit; determining a stacking structure of chips in the integrated circuit according to information in the configuration file; The stacking structure is mapped to an editable three-dimensional visualization interface to obtain a three-dimensional view of the chip.

2. The method according to claim 1, characterized in that Mapping the stacking structure to an editable three-dimensional visualization interface to obtain a three-dimensional view of the chip includes: generating a three-dimensional model corresponding to the stacking structure of the chips according to the stacking parameters in the configuration file; The three-dimensional model is rendered into the three-dimensional visualization interface to generate the three-dimensional view.

3. The method according to claim 1, characterized in that The method further comprises: In response to a movement instruction initiated by a user on the three-dimensional visualization interface, dynamically adjusting the stacking order of the first chip in the integrated circuit layout; According to the stacking sequence, a three-dimensional view including the first chip is updated.

4. The method according to claim 1, wherein The method further comprises: In response to a modification instruction initiated by a user on the three-dimensional visualization interface, dynamically adjusting a connection mode between the second chip and the third chip; According to the connection mode, a three-dimensional view including the second chip and the third chip is updated.

5. The method according to claim 1, wherein The configuration file includes attribute information of each chip and connection information between different chips.

6. The method according to claim 5, characterized in that The determining, based on the information in the configuration file, a stacking structure of chips in the integrated circuit includes: Extracting configuration parameters of each chip from the configuration file, wherein the configuration parameters are used to define the spatial layout of each chip; Based on the configuration parameters, determining the position and posture of each chip in three-dimensional space; The stacking structure of the chips in the integrated circuit is determined according to the position and posture.

7. The method according to claim 6, characterized in that Determining the position and posture of each chip in three-dimensional space based on the configuration parameters includes: Determining the position of each chip in the three-dimensional space according to the position coordinate information in the configuration parameters; The posture of each chip in the three-dimensional space is determined according to the rotation angle information in the configuration parameters.

8. A display device for an integrated circuit chip, characterized in that: include: an acquisition module, configured to acquire a configuration file of the integrated circuit; a determination module configured to determine a stacking structure of chips in the integrated circuit according to information in the configuration file; A mapping module is configured to map the stacking structure to an editable three-dimensional visualization interface to obtain a three-dimensional view of the chip.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

10. An electronic device comprising a storage medium, a processor, and a computer program stored in the storage medium and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

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