Digital circuit wiring method and related apparatus

Abstract

The application belongs to the technical field of semiconductor design automation, and provides a digital circuit wiring method and related equipment. The method comprises: obtaining wiring grid parameters of each wiring layer in a digital circuit to be wired, and grid lines of a wiring grid are used to constrain wiring tracks; based on the wiring grid parameters, the digital circuit is divided into multiple wiring partitions, and the area size of each wiring layer in each wiring partition is different; each signal path is traversed to determine an access point for wiring indexing of the each signal path; based on the access points of the signal paths in each wiring partition, wiring threads respectively configured for each wiring partition are used to wire the signal paths in each wiring partition in parallel; and wiring of the signal paths in each wiring partition is combined to obtain complete wiring of the digital circuit. The technical scheme provided by the application can improve the wiring efficiency of the digital circuit.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor design automation, and particularly relates to a digital circuit wiring method and related equipment. BACKGROUND

[0002] With the rapid development of semiconductor technology, the scale and complexity of digital circuits (such as digital integrated circuits) are increasing, which makes wiring a crucial link in the field of Electronic Design Automation (EDA).

[0003] Under the FinFET process, due to multiple masks, various metal line widths, irregular shapes of Cell pins, and the presence of FinTrack (transistor fin channel track) conditions, the wiring design rules (such as Metal Spacing, MinStep, End of Line, etc.) are significantly complex. On the same wiring layer, the grid parameters, line widths, and trace densities of different regions are difficult to unify, the wiring DRC (Design Rule Check) convergence pressure is increased, and thus the wiring efficiency of the digital circuit is low. Therefore, how to improve the wiring efficiency of the digital circuit becomes a technical problem to be solved. SUMMARY

[0004] Embodiments of the present application provide a digital circuit wiring method, device, computer program product, computer readable storage medium and electronic equipment, which can improve the wiring efficiency of the digital circuit to a certain extent.

[0005] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0006] According to a first aspect of the embodiments of the present application, a digital circuit wiring method is provided, the method comprising: obtaining wiring grid parameters of each wiring layer in a digital circuit to be wired, wherein a grid line of a wiring grid is used to constrain a wiring track; based on the wiring grid parameters of each wiring layer, the digital circuit is divided into a plurality of wiring partitions, wherein the area size of each wiring layer in each wiring partition is different; traversing each signal path to determine an access point of the each signal path, the access point being used to wire index the each signal path; based on the access points of the signal paths in each wiring partition, the signal paths in each wiring partition are wired in parallel by a wiring thread configured for each wiring partition; and merging the wiring of the signal paths in each wiring partition to obtain a complete wiring of the digital circuit.

[0007] In some embodiments of the present application, based on the foregoing scheme, the wiring grid parameters include a grid pitch, and the dividing the digital circuit into the plurality of wiring partitions based on the wiring grid parameters of each wiring layer includes: traversing each wiring layer to divide the each wiring layer into a plurality of wiring layer regions, each wiring layer region having a length and a width that are integer multiples of the grid pitch of the each wiring layer, and the number of wiring layer regions of the each wiring layer being the same as the number of the wiring partitions; and defining a set of wiring layer regions of each wiring layer that are opposite to each other in the vertical direction as a wiring partition to obtain the plurality of wiring partitions.

[0008] In some embodiments of the present application, based on the foregoing scheme, the access points include original access points and temporary access points, and the determining the access points of the each signal path includes: obtaining the original access points preset on the each signal path; and setting temporary access points on the each signal path according to the distribution characteristics of the original access points of the each signal path in the wiring partitions.

[0009] In some embodiments of the present application, based on the foregoing scheme, the each signal path includes a metal pin for sending and / or receiving signals, and the setting temporary access points on the each signal path according to the distribution characteristics of the original access points of the each signal path in the wiring partitions includes: if any metal pin on the each signal path spans a plurality of wiring partitions, and the any metal pin does not have an original access point in any wiring partition of the plurality of wiring partitions, setting a first temporary access point on the any metal pin, the first temporary access point falling into the any wiring partition.

[0010] In some embodiments of the present application, based on the foregoing scheme, after the first temporary access point is set on the any metal pin, the method further includes: generating a virtual via for the any metal pin at the first temporary access point based on a via design rule defined in a basic process database; calling a violation detection engine to detect whether the virtual via produces a violation; and if the virtual via does not produce a violation, determining an evaluation prediction value of the first temporary access point, the evaluation prediction value being used to represent a probability that the first temporary access point will not be selected in a future actual wiring process.

[0011] In some embodiments of the present application, based on the foregoing scheme, the method further includes: if the virtual via produces a violation, generating a virtual metal line for the virtual via on a target wiring layer based on the via design rule, the target wiring layer being a next wiring layer of a wiring layer on which the virtual via is located, and a projection of the virtual metal line in the vertical direction being surrounded by a projection of the any metal pin in the vertical direction.

[0012] In some embodiments of the present application, based on the foregoing scheme, the setting of temporary access points on each signal path according to the distribution characteristics of original access points in each routing partition comprises: if any two original access points adjacent to each other on the each signal path fall into two routing partitions respectively, determining a boundary line of the two routing partitions on the routing layer where the any two original access points are located; setting a second temporary access point at the intersection position of the guide line connecting the any two original access points and the boundary line, the second temporary access point being used to eliminate the violation generated when routing the each signal path in the two routing partitions respectively.

[0013] In some embodiments of the present application, based on the foregoing scheme, after setting the second temporary access point at the intersection position of the guide line connecting the any two original access points and the boundary line, the method further comprises: generating a virtual metal line at the second temporary access point based on the metal line design rules defined in the basic process database; calling a violation detection engine to detect whether the virtual metal line generates a violation; if the virtual metal line generates a violation, generating a new second temporary access point on the boundary line at a position separated from the intersection position by the grid spacing, and returning to execute the step of generating a virtual metal line at the second temporary access point until the virtual metal line does not generate a violation.

[0014] In some embodiments of the present application, based on the foregoing scheme, the routing of signal paths in each routing partition based on the access points of the signal paths in the routing partition through the routing thread configured for each routing partition in parallel comprises: configuring a routing thread for each routing partition; calling a routing engine through the routing thread to route the signal paths falling into each routing partition based on the original access points and the temporary access points of each signal path in each routing partition, and calling a violation detection engine to detect whether the routing of the signal paths in each routing partition generates a violation; if the routing of the signal paths in each routing partition generates a violation, removing the routing that generates the violation and rerouting; when all the signal paths falling into each routing partition are routed and no violation is generated, terminating the routing of the signal paths in each routing partition.

[0015] In some embodiments of the present application, based on the foregoing scheme, the merging of the wires of the signal paths in each wiring partition comprises: traversing each signal path in the digital circuit, deleting invalid wires generated by the temporary access points in each signal path, and merging the wires of each signal path in different wiring partitions; calling a violation detection engine to detect whether the wires of each signal path produce a violation; if the wires of each signal path produce a violation, removing the wires of each signal path and rewiring until the wires of each signal path do not produce a violation.

[0016] According to a second aspect of the embodiments of the present application, a digital circuit wiring device is provided, the device comprising: an acquisition unit configured to acquire wiring grid parameters of each wiring layer in a digital circuit to be wired, wherein the grid lines of the wiring grid are used to constrain the wiring tracks; a partition unit configured to partition the digital circuit into a plurality of wiring partitions based on the wiring grid parameters of each wiring layer, wherein the area size of each wiring layer in each wiring partition is different; a determination unit configured to traverse each signal path and determine an access point of each signal path, the access point being used for wiring indexing of each signal path; a wiring unit configured to wire the signal paths in each wiring partition in parallel through the wiring threads configured for each wiring partition based on the access points of the signal paths in each wiring partition; and a merging unit configured to merge the wires of the signal paths in each wiring partition to obtain a complete wiring of the digital circuit.

[0017] According to a third aspect of the embodiments of the present application, a computer program product is provided, the computer program product comprising computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the operations performed by the method according to the first aspect described above.

[0018] According to a fourth aspect of the embodiments of the present application, a computer readable storage medium is provided, the computer readable storage medium storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by a processor to implement the operations performed by the method according to the first aspect described above.

[0019] According to a fifth aspect of the embodiments of the present application, an electronic device is provided, the electronic device comprising one or more processors and one or more memories, the one or more memories storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by the one or more processors to implement the operations performed by the method according to the first aspect described above.

[0020] Based on the technical scheme provided in the present application, the overall efficiency of digital circuit routing can be significantly improved by introducing the idea of wiring partition parallel routing. First, the grid parameters of each wiring layer are used to divide the circuit to be routed into several wiring partitions that adapt to the physical characteristics and have appropriately adjustable region sizes, realizing regional-level resource management. This partitioning method fully considers the size differences of different wiring layers in different regions, making the partitioning more in line with actual design needs and optimizing the routing difficulty distribution from the source. Second, within each wiring partition, by traversing all signal paths and precisely defining access points as the indexing of the routing task, the attention of the routing engine to the signal paths can be greatly improved, which is conducive to ensuring the performance and reliability of critical signal paths. Further, by assigning independent routing threads to each wiring partition, parallel routing in multiple wiring partitions on a multi-core or multi-processor platform is supported, which can greatly improve resource utilization and routing speed and effectively reduce the overall design cycle. In addition, based on the partition-level routing, efficient merging and conflict resolution of the routing results of cross-region signal paths are realized, realizing seamless integration of global routing and avoiding process and rule violations that may be caused by partition boundaries. This combination of measures not only improves the concurrency and automation level of digital circuit routing, but also improves the convergence efficiency and design quality of the final physical implementation, greatly meeting the actual needs of large-scale complex circuits in terms of design cycle, reliability and performance, and has outstanding technical application value.

[0021] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0022] The drawings incorporated into the specification and forming a part thereof illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the application. It is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0023] Figure 1 A flowchart of a digital circuit routing method in an embodiment of the present application is shown;

[0024] Figure 2 A wiring partition diagram of each wiring layer in a digital circuit according to an embodiment of the present application is shown;

[0025] Figure 3 A partial perspective view of a digital circuit according to an embodiment of the present application is shown;

[0026] Figure 4A partial top view of each wiring layer in a digital circuit according to an embodiment of the present application is shown.

[0027] Figure 5 A partial cross-sectional view of a digital circuit according to an embodiment of the present application is shown.

[0028] Figure 6 A block diagram of a digital circuit wiring device in an embodiment of the present application is shown.

[0029] Figure 7 A structural schematic diagram of an electronic device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0031] In addition, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a sufficient understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring the aspects of the present application.

[0032] The block diagrams shown in the drawings are only functional entities, and do not necessarily correspond to physically independent entities. That is, the functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices. It should be noted that, in the drawings, some components that do not affect the explanation of the technical solutions of the present application are omitted adaptively to ensure the simplicity of the drawings.

[0033] The flowcharts shown in the drawings are only exemplary illustrations, and do not necessarily include all the contents and operations / steps, nor do they necessarily be executed in the described order. For example, some operations / steps can be further decomposed, and some operations / steps can be combined or partially combined, so the actual execution order can be changed according to the actual situation.

[0034] In the description of the present application, it should be understood that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can be explicitly or implicitly included one or more. In the description of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0035] In order for those skilled in the art to better understand the present application, first, the technical concepts and application background involved in the present application are briefly described.

[0036] Digital Circuit (DC): Digital circuit refers to the electronic circuit that uses digital signals (i.e. only takes a finite number of discrete values, usually "0" and "1") as information carriers, and processes, transmits and stores information through logic gates and other electronic devices. Digital circuit is based on Boolean algebra as the theoretical basis, and can realize various logic operations, arithmetic operations, data storage and control functions, and is the core component of modern computer, communication, automatic control and other systems.

[0037] Digital Circuit Routing (DCR): Digital circuit routing usually refers to the process of connecting various functional units, logic gates, circuit blocks inside the chip (such as FPGA, CPU, GPU, etc.) according to the design requirements through metal lines.

[0038] Signal path: including timing path and logic path. Among them, signal path (Timing Path) refers to the path of a series of logic gates and connections that the signal propagates from the starting point (usually the output of a timing trigger, such as a register, trigger, latch, etc.) to the end point (usually the input or output of the next register, trigger, latch). Logic path (Logic Path) refers to the signal transmission path formed by the signal from a signal source (such as an input pin, the output of the previous logic gate, register output, etc.) to the target node (for example, the input of the logic gate, the output pin, the input of the register, etc.) through a number of logic gates (such as AND gate, OR gate, NOT gate, etc.) and their connections. Logic path focuses on the implementation process of circuit function, ensuring that the signal can be correctly transmitted and processed according to the design intention. Unlike timing path, logic path does not necessarily contain clock constraints, but it reflects the logical connection relationship between the units in the circuit, and is an important basis for realizing and verifying the completeness of the circuit function.

[0039] Metal Pin: Metal Pin refers to a metal contact area exposed by a functional block such as a standard cell, a macro cell, an IP core, etc. in a layout level of a digital circuit, which is used to realize electrical connection with an external metal interconnection.

[0040] At present, with the rapid development of semiconductor technology, the scale and complexity of digital circuits are increasing, which makes routing a crucial link in the field of semiconductor design automation. Under the FinFET process, due to multiple masks, various metal line widths, irregular shapes of Cell pins, and the existence of FinTrack (transistor fin channel track), etc., the routing design rules (such as Metal Spacing, MinStep, End of Line, etc.) are significantly complex.

[0041] In the implementation process of digital circuit routing, the existing mainstream EDA tools mostly adopt a Grid-based Routing method to discretize the routing space into controllable grid tracks. However, the complexity of the routing space and the diversification of routing requirements, especially under the Multi-layer Routing structure, often result in different grid parameters and constraint rules for different routing layers, making it difficult to subdivide the routing space and schedule resources. More seriously, these violations caused by inaccurate virtual access points often occur in the early stage of partition routing and full-chip merging, but are not discovered until the late stage of unified DRC checking, at which time large-scale re-routing repair is required, resulting in low routing efficiency of digital circuits. In this case, the present application proposes a digital circuit routing scheme to improve the routing efficiency of digital circuits.

[0042] The implementation details of the technical solutions of the embodiments of the present application are described below:

[0043] Referring to Figure 1 , a flowchart of a digital circuit routing method in the embodiments of the present application is shown, which can be executed by a device with computing processing function. Referring to Figure 1 , the digital circuit routing method includes at least steps 110 to 170, which are described in detail as follows:

[0044] Referring to Figure 1 , in step 110, the routing grid parameters of each routing layer in the digital circuit to be routed are obtained, wherein the grid lines of the routing grid are used to constrain the routing tracks.

[0045] In modern FinFET and high-end processes, due to the complexity of manufacturing process, the wiring grid parameters of different metal layers in a chip are mostly different. Therefore, the grid parameters need to be obtained for each wiring layer respectively to avoid wiring violations and mismatching problems caused by one-size-fits-all.

[0046] In the present application, the wiring grid parameters can include grid spacing, i.e. the physical distance between two adjacent grid lines, which is a key parameter determining the wiring density and reliability.

[0047] In the present application, the wiring grid parameters can also include the physical coordinates of the grid lines. Through the physical coordinates of the grid lines, the specific positions of each wiring track on the X-axis and Y-axis and the wiring layer where the wiring track is located can be located. The wiring grid parameters can also include the grid coordinates of the grid lines, through which the grid sorting number of each wiring track on the X-axis and Y-axis and the wiring layer where the wiring track is located can also be located.

[0048] In the present application, the wiring grid parameters can also include the grid starting coordinates, the allowed wiring direction, and the number / distribution of grid lines, etc.

[0049] In the present application, the grid lines of the wiring grid can be used to constrain the wiring track, i.e. all automatic wiring engines and manual planning need to refer to the grid line position and cannot deviate from the track for wiring. In this way, process problems such as metal short circuit and distance violation caused by "drifting" can be effectively avoided. In addition, in the subsequent process of dividing the wiring partition, the wiring layer area of each wiring layer in the wiring partition can be physically divided based on the grid, so that the subsequent partition wiring is consistent with the actual process data.

[0050] Continuing to refer to Figure 1 In step 120, based on the wiring grid parameters of each wiring layer, the digital circuit is divided into multiple wiring partitions, wherein the area size of each wiring layer in each wiring partition is different.

[0051] In order for those skilled in the art to better understand the multiple wiring partitions of the digital circuit in the present application, a specific embodiment will be described below. Figure 2

[0052] Referring to Figure 2 , a schematic diagram of the wiring partition of each wiring layer in the digital circuit according to an embodiment of the present application is shown.

[0053] As Figure 2 shown, the digital circuit 100 includes multiple wiring layers from bottom to top, such as multiple silicon layers ploy, via layer V1, metal layer M1, via layer V2, and metal layer M2. ​

[0054] It should be noted that in this application, the polycrystalline silicon layer (Poly layer) is a thin film material composed of many tiny silicon grains, and is a common structural layer in integrated circuit manufacturing. Polycrystalline silicon layers are mainly used as gate materials for MOS transistors, and can also be used as doping and diffusion layers for sources and drains, and even for local interconnects. In the process flow, polycrystalline silicon is first deposited on a silicon oxide substrate, and then the desired pattern is formed through photolithography and etching techniques. Its conductivity is between that of monocrystalline silicon and amorphous silicon, and it is easy to control the doping in subsequent processes.

[0055] A metal layer is a conductive layer in integrated circuit manufacturing processes used for large-area horizontal traces to facilitate signal or power transmission between circuit units. It is primarily made of aluminum (Al) or copper (Cu). Metal layers typically serve as the main interconnecting medium in circuits, transmitting electrical signals, distributing power and ground lines, etc. In modern IC design (especially CMOS and FinFET processes), there can be dozens of metal layers to create complex and dense signal and power networks. Generally, the first metal layer is called "Metal 1" (M1), the second layer is "Metal 2" (M2), and so on (M3, M4...).

[0056] A via layer is a layer used in integrated circuit manufacturing to create a "vertical connection" between different metal layers. It typically consists of small holes (vias) drilled in an insulator (such as SiO2) and then filled with metal material to achieve electrical connection. Since modern ICs often have multiple layers of metal wiring, each metal layer is separated from the others by insulating layers. Via layers allow signals to pass through the insulator from one metal layer and vertically connect to the layer above or below, achieving vertical conduction (electrical connection) within the chip. For example, "V1" represents a via between metal 1 and metal 2, "V2" represents a via between metal 2 and metal 3, and so on.

[0057] In summary, multi-silicon layers are used for device structures, metal layers are responsible for horizontal wiring, and via layers enable vertical connectivity between the metal layers.

[0058] Furthermore, such as Figure 2 As shown, each routing layer is divided into 9 regions by routing partitions K1 to K9, and the region size of each routing layer in each routing partition is different.

[0059] Specifically, in this application, dividing the digital circuit into multiple wiring partitions based on the wiring grid parameters of each wiring layer can be performed according to the following steps 121 to 122:

[0060] Step 121, traverse each routing layer, and divide each routing layer into a plurality of routing layer regions, each routing layer region having a length and a width that are integer multiples of the grid pitch of each routing layer, and the number of routing layer regions of each routing layer being the same as the number of routing partitions.

[0061] Step 122, define a set of routing layer regions on opposite sides of each routing layer in the vertical direction as a routing partition, to obtain the plurality of routing partitions.

[0062] In this application, it should be noted that for non-FinFET processes, since the routing grid parameters (such as grid pitch and starting coordinates) of the routing layers are uniform in design rules, the grid pitch and coordinates of the first routing layer can be directly used as the reference for the routing partitions of all routing layers. In this way, the size, boundary and division method of the routing partitions on all routing layers remain uniform, greatly simplifying subsequent routing processing.

[0063] For advanced processes such as FinFET, different routing layers have their own independent routing grid pitches and grid starting coordinates, and even have process-specific restrictions. Therefore, for each routing layer, it can be divided into a plurality of routing layer regions according to integer multiples of its grid pitch. Specifically, each routing layer can be traversed, and a routing layer region can be divided in the routing layer by taking the starting grid of the routing layer as a reference point, every m grid pitch in the X-axis direction, and every n grid pitch in the Y-axis direction (m and n are partition granularity parameters set by the user or algorithm, and m and n can be different, such as m=4 and n=6, or the same, such as m=n=5). The region range of each routing layer region can be defined by the physical coordinates or grid coordinates of two opposite corner points (such as the lower left corner and the upper right corner of the routing layer region, or the lower right corner and the upper left corner of the routing layer region) in the routing layer region.

[0064] In a preferred embodiment, the region range of each routing layer region can be defined by the grid coordinates of two opposite corner points in the routing layer region, which has the advantage of concise and efficient representation and calculation of grid coordinates, and the required data processing amount is much smaller than that of direct use of physical coordinates. In actual chip design and EDA implementation process, the use of grid coordinates can significantly reduce memory occupation and data transmission overhead, speed up region positioning and judgment, improve algorithm efficiency and scalability, and facilitate unified management and alignment of cross-layer regions, which is suitable for large-scale parallel processing of routing partitions.

[0065] In the present application, it can be understood that the length and width of each wiring layer region can be an integer multiple of the grid spacing of each wiring layer. For example, the grid spacing of the M1 metal layer is 0.1 μm (i.e. 100 nm), and if m = n = 10000, then the size of one wiring layer region of the M1 metal layer is 1000 μm x 1000 μm.

[0066] In the present application, it is also necessary to point out that for the same wiring layer, the area size of the plurality of wiring layer regions divided therefrom can be the same or different.

[0067] In the present application, it is also necessary to point out that the number of wiring layer regions of each wiring layer is the same as the number of wiring partitions, so that each wiring layer can be divided into the same number of wiring layer regions.

[0068] Further, after all the wiring layers complete the division of their respective wiring layer regions, the wiring layer regions can be combined by overlapping along the vertical direction (i.e. Z-axis) of the digital circuit, thereby obtaining the corresponding wiring partitions. Referring to Figure 2 As shown, for example, the set of K1 wiring layer regions of each wiring layer is a wiring partition, and the set of K2 wiring layer regions of each wiring layer is a wiring partition. Each wiring partition has a corresponding wiring layer region in all wiring layers.

[0069] Based on the technical solutions in steps 121-122 described above, through adaptive wiring grid track division design, precise division of multi-level wiring layer regions can be achieved, which can effectively adapt to multiple masks, FinTrack and different complex situations of each wiring layer in FinFET process, thereby greatly reducing the probability of problems such as DRC violation surge and inaccurate wiring path guidance caused by wiring partition division. First, in terms of fine physical alignment, the division of each metal layer region is based on its own wiring grid parameters, ensuring the physical accuracy of the wiring partition and improving the degree of coincidence between the wiring layer region and the actual process layout, thereby avoiding violations and repair difficulties caused by cross-layer inconsistencies. Second, it can flexibly adapt to advanced processes with complex FinFET process parameters and strict rules, achieving automatic adaptation throughout the process and effectively reducing the probability of manual adjustment and rule conflicts. In addition, each wiring partition after wiring partitioning becomes the smallest unit for wiring optimization and parallel processing, improving the parallelism and data isolation of the task, thereby significantly speeding up the overall wiring speed and improving resource utilization. Finally, through parameter setting, the division granularity of the wiring layer region can be flexibly controlled, facilitating the customization of wiring partitioning strategies according to chip size and wiring complexity, and achieving more efficient and accurate wiring optimization.

[0070] Continuing to refer to Figure 1In step 130, access points of each signal path are determined for wiring indexing of each signal path.

[0071] In the present application, an access point refers to a key node or port on a signal path, which usually corresponds to a register, a latch, an input / output port or a key node in a path. These points are usually specific physical locations where signals enter or exit a logic unit. For example, an access point can be the start point or end point of a signal path, as well as a data path and a control signal interface involved in the path.

[0072] In the present application, the access points can include original access points and temporary access points. Specifically, the determination of the access points of each signal path can be performed according to steps 131 to 132 as follows:

[0073] In step 131, original access points on each signal path are obtained.

[0074] In step 132, temporary access points are set on each signal path according to the distribution characteristics of the original access points of each signal path in each wiring partition.

[0075] In the present application, the original access point refers to a key node on each signal path that is predefined according to process rules and design specifications at the initial stage of a process database or chip design. These original access points usually include register inputs / outputs, module interfaces, input / output ports, etc., which are clearly defined in the layout and process layer and have stable physical coordinates. The acquisition of original access points depends on the integrity and accuracy of the process database and is the basis for physical marking of signal paths. By extracting the original access points associated with each signal path, a standard reference can be provided for subsequent wiring allocation.

[0076] In the present application, since a signal path can cross multiple wiring partitions in the actual wiring process, relying only on original access points can lead to unnecessary violations in the process of wiring within a single wiring partition. Therefore, temporary access points need to be intelligently added on the signal path in combination with the spatial distribution characteristics of the original access points in each wiring partition. These temporary access points are not fixed and are dynamically set according to the wiring layer area division, path length, congestion situation or physical distance. In the present application, temporary access points can be set at the boundaries of wiring partitions or wiring turning points to achieve efficient path connection and transition between multiple wiring partitions.

[0077] By combining the original access points and the temporary access points, the complex global signal paths can be decomposed into complete small paths within the wiring partitions, and the indexing and optimization can be performed respectively, so as to effectively improve the utilization of the wiring resources, meet the constraint requirements of the key signal paths, and significantly enhance the adaptability of the wiring tool to the large-scale and complex chip structure.

[0078] In the present application, each signal path includes a metal pin for sending and / or receiving signals. Specifically, each signal path includes a metal pin. The metal pin serves as a sending point and / or a receiving point of a timing signal, and is a key node for signal transmission in a physical chip structure. In a complex chip layout, a metal pin (such as a long-distance bus or a cross-zone network connection) can cross multiple wiring partitions, and the original access points are generally set in only some of the partitions. In this case, only relying on the original access points can easily lead to a lack of effective wiring anchor points in some of the partitions, thereby affecting the subsequent wiring partition optimization and timing convergence.

[0079] To solve this problem, the present application proposes an intelligent dynamic generation mechanism of temporary access points. The implementation steps are as follows:

[0080] In the present application, setting the temporary access points on each signal path according to the distribution characteristics of the original access points of each signal path in each wiring partition can be performed according to the following step 1321:

[0081] Step 1321, if any metal pin on the each signal path crosses multiple wiring partitions, and the any metal pin does not have an original access point in any wiring partition of the multiple wiring partitions that the any metal pin crosses, a first temporary access point is set on the any metal pin, and the first temporary access point falls into the any wiring partition.

[0082] Specifically, first, detect all the metal pins on each signal path to determine whether any metal pin crosses multiple wiring partitions. For the detected metal pin that crosses multiple partitions, check whether an original access point has been set in each wiring partition covered by the metal pin. If it is found that the metal pin does not have an original access point in a wiring partition that it crosses, it indicates that the partition lacks a positioning anchor point in the subsequent wiring processing, which can affect signal integrity and path optimization. In this case, a first temporary access point can be automatically set in the layout partition corresponding to the metal pin. The coordinates of the first temporary access point can be located at the intersection of the metal pin and the boundary of the wiring partition or a key layout point of the metal pin in the wiring partition.

[0083] In order for those skilled in the art to better understand the present application, the following will combine the present application with the prior art to make a better comparison. Figures 3 to 5The setting of temporary access points on a signal path is explained from different perspectives. Among them, Figure 3 A partial perspective view of a digital circuit according to an embodiment of the application is shown; Figure 4 A partial top view of various wiring layers in a digital circuit according to an embodiment of the application is shown; Figure 5 A partial cross-sectional view of a digital circuit according to an embodiment of the application is shown.

[0084] Referring to Figures 3 to 5 The demarcation line 101 of the wiring partition divides the digital circuit 100 into wiring partition 1 and wiring partition 2. In the M1 metal layer (i.e., one wiring layer), there is a metal pin 104 that spans the wiring partition 1 and the wiring partition 2. The metal pin 104 is provided with an original access point T1 in the wiring partition 1, but it is not provided with an original access point in the wiring partition 2. Therefore, the first temporary access point F1 can be set on the metal pin 104 in the wiring partition 1.

[0085] In the present application, by intelligently adding a first temporary access point to a metal pin that spans multiple wiring partitions but lacks an access point, the space blind area that cannot be covered by the original access point on the metal pin can be effectively filled, and a reasonable anchor point can be allocated to the wiring layer area of each wiring partition. The dynamic setting of such temporary access points can ensure that each wiring partition has a clear target when performing independent wiring optimization, timing analysis, and parallel processing, thereby improving the controllability and efficiency of physical implementation. For large-scale SoC, complex heterogeneous integration, or long-distance cross-zone signal transmission, this mechanism can greatly reduce the difficulty of cross-partition wiring and the risk of timing violations, and it is also convenient for the wiring engine to reasonably split the global signal path based on the access point information, to achieve local optimization and global coordination, and to further improve the overall performance and implementation yield of the chip.

[0086] Further, in the present application, after setting the first temporary access point on the arbitrary metal pin, the following steps 1322 to 1325 can also be performed:

[0087] Step 1322, based on the via design rules defined in the basic process database, a virtual via is generated for the arbitrary metal pin at the first temporary access point;

[0088] Step 1323, calling a violation detection engine to detect whether the virtual via produces a violation;

[0089] Step 1324, if the virtual via does not produce a violation, determining an evaluation prediction value of the first temporary access point, the evaluation prediction value being used to represent the probability that the first temporary access point will not be selected in future actual wiring process.

[0090] Step 1325, if the virtual via generates a violation, a virtual metal line is generated for the virtual via on a target routing layer, which is the next routing layer of the routing layer where the virtual via is located, based on the via design rules, and a projection of the virtual metal line in the vertical direction is surrounded by a projection of the arbitrary one metal pin in the vertical direction.

[0091] In the routing flow of the present application, after the first temporary access point is set on the metal pin, a virtual via generation and evaluation mechanism based on the process database (such as TechDatabase) and the virtual via in the via design rules (such as LEF58ENCLOSURE, etc.) can further ensure the feasibility of the temporary access point and the efficiency of the routing implementation.

[0092] Specifically, after the first temporary access point is set on a metal pin, a corresponding virtual via can be generated based on the generation rules of the via in the process database, according to the specific position of the temporary access point, the actual geometric information of the metal pin, and the process constraints (including the layout of each metal layer, the via size, and the metal surrounding requirement, etc.), such as the virtual via 105 shown in the following figure. Figures 3 to 5 The virtual via is only used for feasibility evaluation, which represents the via structure that can be laid out at the temporary access point in future actual routing.

[0093] Subsequently, a violation detection engine (i.e., a design rule check (DRC) module) can be called to perform DRC legality detection (i.e., violation detection) on the relationship between the virtual via and the surrounding original routing shape in the layout, including but not limited to via spacing, distance from surrounding metal lines / pins, and coverage relationship, etc. Through this link, it can be found early whether the temporary access point has the risk of process manufacturing conflict in the existing design resource distribution.

[0094] If the DRC check result is "no violation" (i.e., the virtual via does not generate a violation), it means that the temporary access point is available under the conditions allowed by the process and layout rules. At this time, the evaluation prediction value (DRC EVA value, which is used to represent the probability of being actually selected by the routing engine in future physical routing) of the temporary access point can be calculated in combination with the routing local density, the surrounding resource tightness, etc. In order to control the selection probability of the temporary access point, the evaluation prediction value can be set to be higher than the evaluation prediction value of other real physical access points, so as to ensure that the routing engine is more inclined to preferentially select the original access point, and only when it is extremely necessary, the temporary access point is considered, thereby enhancing the routing robustness and global convergence.

[0095] If the DRC check result is "violation found," it means that the temporary access point cannot be implemented compliantly at this routing layer. In this case, the algorithm will not simply abandon the temporary access point, but will further generate a virtual metal line in the next routing layer after the routing layer containing the via, based on the via generation rules in the process database. Figures 3 to 5 The virtual metal line 106 is shown. The generation process must ensure that the virtual metal line is completely surrounded in the vertical direction by the projection of the original metal pins in the vertical direction. This guarantees both the physical space for electrical connection and improves DRC legitimacy. For example, in advanced processes such as FinFET, unique enclosure rules such as LEF58ENCLOSURE must also be followed to ensure that each endpoint meets the coverage requirements, thereby avoiding gaps or violations caused by special process characteristics.

[0096] This application achieves dynamic prediction and optimization of physical routing anchor point feasibility by generating virtual vias at temporary access points and performing violation detection. Combined with evaluation predictions and a virtual metalline replacement mechanism, it deeply integrates process manufacturability (DFM) with forward-looking verification of digital routing physical design, effectively avoiding the risk of global signal path reconstruction due to anchor point failure later. Automatic optimization of violation access points reduces manual intervention and improves the efficiency and compliance of automated routing. Utilizing evaluation predictions for intelligent routing scheduling ensures that temporary access points only supplement the original access points when they are unavailable, reducing the probability of iteration failures and rework. Furthermore, synchronously updating the 3D database ensures that all virtual structures can accurately participate in subsequent global routing and 3D integration, contributing to improved product yield and convergence speed, especially suitable for multi-layer routing, complex SoCs, and highly integrated chip scenarios. Overall, this application deeply integrates the evaluation of virtual via legality, the adjustment of routing priority, and the cross-layer virtual metal generation mechanism under violation, realizing an efficient closed loop from metal pin shape and process rules to routing point optimization. This can significantly improve the controllability, fault tolerance, and global optimization of physical implementation of the routing engine, thereby optimizing the reliability of chip design and manufacturing.

[0097] Furthermore, in this application, the step of setting temporary access points on each signal path based on the distribution characteristics of the original access points of each signal path in each wiring partition can also be performed according to the following steps 1326 to 1327:

[0098] Step 1326: If any two adjacent original access points on each signal path fall into two wiring partitions respectively, then determine the boundary line between the wiring layers where the two original access points are located in the two wiring partitions.

[0099] Step 1327, a second temporary access point is set at the intersection position of the guide line connecting the two original access points and the demarcation line, and the second temporary access point is used to eliminate the violation generated when the signal path is routed in each of the two routing partitions.

[0100] In this application, for the same signal path, if the two adjacent original access points (i.e. key routing anchor points) belong to different routing partitions, the boundary line between the two routing partitions corresponding to the routing layer where the two original access points are located is first determined. This boundary line is the physical and design rule interface that must be passed through in subsequent cross-zone physical connection.

[0101] At the intersection of the guide line connecting the above two original access points and the demarcation line, a second temporary access point is dynamically generated. The main function of the temporary access point is to serve as an auxiliary anchor point during the splicing of the routing partitions, and to eliminate the DRC violation that may be generated in the independent routing of the signal path across the routing partitions. In other words, since the distributed algorithm performs routing independently in each routing partition, the cross-routing partition path is prone to connectivity interruption, physical rule inconsistency or other conflicts at the interface. The second temporary access point, by determining the position in advance and participating in routing, can effectively guide the subsequent routing algorithm to automatically pass through the connectivity at the boundary of the routing partition and avoid violations, thereby ensuring the correctness of the splicing of the distributed parallel routing and the global physical compliance.

[0102] Please continue to refer to Figures 3 to 5 For example, for the original access point T2 and the original access point T3, they fall into the routing partition 1 and the routing partition 2 respectively, then the demarcation line 101 of the routing layer M2 where the original access point T2 and the original access point T3 are located in the routing partition 1 and the routing partition 2 can be determined, and then the second temporary access point F2 is set at the intersection position of the guide line connecting the original access point T2 and the original access point T3 and the demarcation line.

[0103] It should be noted that if the two adjacent original access points fall into two routing partitions and are located at two different metal routing layers, for example Figures 3 to 5 The original access point T1 and the original access point T3 in the drawing, the via hole 103 connected to the original access point T1 (the via hole connects the metal routing layer M2 where the original access point T3 is located) can be determined first, in this case, the second temporary access point F2 can be set at the intersection position of the guide line connecting the via hole 103 and the original access point T3 and the demarcation line.

[0104] In the present application, it is also necessary to point out that the generation of temporary access points is mainly used to assist distributed parallel routing, and needs to be eliminated in the subsequent merging process. However, in the process of parallel routing, in order to not change the logic of the original routing algorithm, these temporary access points with auxiliary properties need to have corresponding via shapes matched therewith, but this will bring new large DRC violations. Therefore, in the generation process, DRC checking needs to be performed on these temporary access points to ensure that the additional auxiliary shapes do not bring additional DRC violations.

[0105] Specifically, in the present application, after setting the second temporary access point at the intersection position of the guide line connecting the arbitrary two original access points and the demarcation line, the following steps 1328 to 1330 can also be performed:

[0106] Step 1328, generating a virtual metal line at the second temporary access point based on the metal line design rules defined in the basic process database.

[0107] Step 1329, calling a violation detection engine to detect whether the virtual metal line produces a violation.

[0108] Step 1330, if the virtual metal line produces a violation, generating a new second temporary access point on the demarcation line at a position separated from the intersection position by the grid pitch, and returning to perform the step of generating a virtual metal line at the second temporary access point until the virtual metal line does not produce a violation.

[0109] In the present application, after setting the second temporary access point at the intersection position of the guide line connecting the arbitrary two original access points and the demarcation line, a virtual metal line can be generated at the second temporary access point based on the metal line design rules set in the basic process database. The parameters (width, pitch, coverage, level, etc.) of the virtual metal line completely follow the design specifications of the target process environment to ensure the correctness and determinability of the subsequent DRC. Then, a violation detection engine can be automatically called to perform global and local DRC checking on the newly generated virtual metal line. The checking content includes but is not limited to metal pitch, width, and legal relationship with other structures (such as via, other metal lines, cell boundary, etc.). In addition, for FinFET process, complex 3D and process-related special rule detection can also be performed.

[0110] If the current virtual metal line triggers any form of DRC violation at the second temporary access point, it can be immediately determined that the temporary access point is illegal. Subsequently, the boundary line can be pushed forward along the grid spacing as a step, and after one grid spacing from the original intersection point, a new second temporary access point is set, the virtual metal line is generated again, and the above DRC detection process is repeatedly executed. The adaptive search process will continue until the newly generated virtual metal line at a certain position fully complies with all DRC rules (i.e. no violation), at which point the point is confirmed as the final effective second temporary access point.

[0111] Based on the technical solutions in steps 1328 to 1329, the benefits are that the physical interface and path splicing between the distributed parallel routing multi-regions can be fully ensured not to increase new design violation risks due to the introduction of auxiliary structures. Through the DRC-driven automatic temporary access point / virtual metal line iterative search mechanism, the routing compliance efficiency and full-process automation stability can be greatly improved, and the post-processing and failure convergence caused by improper interface management can be avoided to the greatest extent. Especially for rule adaptive determination and adjustment under complex processes such as FinFET, the adaptability to various advanced processes and large-scale high-performance chip physical design can be greatly improved, the design size upper limit of the tool platform can be expanded, and the research and development and engineering implementation efficiency can be improved.

[0112] Continuing to refer to Figure 1 In step 140, based on the access points of the signal paths in each routing partition, the signal paths in each routing partition are routed in parallel by the routing threads respectively configured for each routing partition.

[0113] In the present application, based on the access points of the signal paths in each routing partition, the signal paths in each routing partition are routed in parallel by the routing threads respectively configured for each routing partition, which can be performed according to the following steps 141 to 144:

[0114] Step 141, a routing thread is configured for each routing partition.

[0115] Step 142, based on the original access points and temporary access points of each signal path in each routing partition, the routing engine is called by the routing thread to route the signal paths falling into each routing partition, and the violation detection engine is called to detect whether the routing of the signal paths in each routing partition produces a violation.

[0116] Step 143, if the routing of the signal paths in each routing partition produces a violation, the routing that produces the violation is removed and routed again.

[0117] Step 144, when all signal paths falling into each wiring partition complete the wiring and no violation is generated, terminate the execution of the wiring of the signal paths in each wiring partition.

[0118] In this application, first, a dedicated wiring thread is allocated for each wiring partition. By establishing a thread pool mechanism, the design scheme is managed according to the pre-divided multiple wiring partitions, and resources and execution processes are independently scheduled for each partition, thereby realizing regional-level parallel wiring preparation and ensuring that the subsequent wiring partitions can efficiently and without interference to each other to carry out the wiring work synchronously.

[0119] Subsequently, based on the original access point and the temporary access point of the signal paths contained in each wiring partition, the wiring engine is called by the wiring thread dedicated to the wiring partition to automatically execute the wiring for all signal paths falling into the region in the current wiring partition. At the same time, after each wiring is completed, the violation detection engine can also be automatically called to check the wiring results of the signal paths in the wiring partition one by one (i.e., DRC check) to ensure that the wiring of each signal path does not violate the design rules.

[0120] If it is detected during the wiring process that the wiring of a signal path violates the design rules, i.e., a violation is generated, the wiring result of the signal path can be automatically revoked, and an automatic rewiring operation is immediately started. This process is executed in a loop by the wiring partition dedicated thread until the wiring of all signal paths in the current wiring partition passes the DRC check, ensuring the overall compliance of the wiring in the wiring partition. When all the signal paths involved in a wiring partition complete the wiring and all pass the design rule check without any violation, the corresponding wiring thread automatically terminates the wiring operation of the current wiring partition. Only under this condition, the partition wiring process is considered to be successfully completed, laying a solid foundation for the merging and overall convergence of the subsequent full-chip wiring results.

[0121] In the present application, by dividing the wiring layer area into multiple wiring partitions and assigning each wiring partition an independent wiring thread, the parallel computing resources such as multi-core CPU or GPU can be fully utilized, thereby greatly improving the overall efficiency of the wiring and significantly shortening the total wiring time. This partitioned parallel strategy not only realizes the efficient scalability of the wiring process, but also ensures that each wiring partition is independent and does not interfere with each other in wiring and design rule checking, thereby improving the stability and robustness of the wiring process. At the same time, within each wiring partition, the wiring and DRC (Design Rule Checking) form a real-time closed loop, which can quickly find and correct violations, reduce later rework, and achieve high-quality, process-compliant wiring results. The automatic rollback and rewiring mechanism of the violation can instantly eliminate possible design problems locally, effectively improving the automation and intelligence level of the wiring process. Finally, the process is terminated only after all partition wiring fully complies with the process rules, which not only guarantees the correctness and usability of the full-chip physical design, but also provides a solid foundation for subsequent full-chip stitching and optimization. Therefore, this method can greatly improve the chip design efficiency, convergence speed and final design quality, and is a key technical means for realizing high performance, intelligence and reliability in the field of large-scale chip automatic wiring.

[0122] With reference to the foregoing Figure 1 In step 170, the wiring of the signal paths in each wiring partition is merged to obtain the complete wiring of the digital circuit.

[0123] In the present application, the merging of the wiring of the signal paths in each wiring partition can be performed according to the following steps 151 to 153:

[0124] Step 151: Traverse each signal path in the digital circuit, delete the invalid wiring generated by the temporary access point in each signal path, and merge the wiring of each signal path in different wiring partitions.

[0125] Step 152: Call the violation detection engine to detect whether the wiring of each signal path produces a violation.

[0126] Step 153: If the wiring of each signal path produces a violation, remove the wiring of each signal path and rewire until the wiring of each signal path does not produce a violation.

[0127] In the present application, after the routing tasks of all the wiring partitions are completed and pass the DRC check at the partition level, each signal path in the entire digital circuit can be traversed. For each signal path, first, the virtual access points and their corresponding invalid metal wires (such as virtual vias or virtual metal lines) temporarily generated in the partition routing stage to assist the partition routing are deleted to prevent these temporary structures from interfering with subsequent overall integration and DRC check. Subsequently, the routing segments of the same signal path in different wiring partitions are spliced and fused to establish globally consistent and complete physical-level wire connections, and the metal lines that need to cross multiple wiring partitions are structurally merged and optimized. The merged signal path is included in the global violation detection process as an integrated data structure.

[0128] Specifically, the violation detection engine can be invoked to perform DRC (design rule check) on the complete routing of all signal paths after merging, including but not limited to cross-zone joints, long metal lines, 3D connections, and specific process rules (such as long traces, resistance, and capacitance coupling requirements of FinFET devices), to ensure that the overall routing does not introduce new process violations after regional-level routing to global splicing.

[0129] In the present application, if any signal path has a routing violation during the DRC check, the routing structure corresponding to the signal path will be immediately removed or rolled back to a critical legal state, and an incremental routing algorithm will be started based on the merged global routing. The incremental routing will re-optimize the routing of the local area with violations until all signal paths pass the DRC check in the global range. In this way, the violation problem caused by cross-partition splicing can be efficiently repaired, and the final convergence of the overall design rules is achieved. After completion, the final compliant routing result is written back to the DesignDatabase, 3D Route database, and DRCDatabase to ensure the complete closed loop of the design process and data consistency.

[0130] Based on the technical solutions in steps 151 to 153 described above, through the merging and violation repair process, the flexibility and speed of the early efficient distributed parallel routing can be guaranteed, and through strict merging and global DRC detection, the integrity, process reliability, and electrical performance of the entire chip routing physical implementation are ensured. Moreover, the mechanisms of automatic splicing of partition routing, timely cleaning of invalid structures, and incremental repair can effectively compensate for the potential integration problems caused by the locality of independent partition routing, providing solid technical support for the manufacturability and functional robustness of large-scale chip design.

[0131] Based on the technical scheme provided in the application, the overall efficiency of digital circuit routing can be significantly improved by introducing the idea of wiring partition and parallel wiring. First, the grid parameters of each wiring layer are used to divide the circuit to be routed into several wiring partitions that adapt to physical characteristics and have adjustable region sizes, realizing regional-level resource management. This partitioning method fully considers the size differences of different wiring layers in different regions, making the partitioning more suitable for actual design needs and optimizing the wiring difficulty distribution from the source. Second, within each wiring partition, by traversing all signal paths and precisely defining access points as the indexing of the routing task, the attention of the routing engine to signal paths can be greatly improved, which is beneficial to ensuring the performance and reliability of critical signal paths. Further, by assigning independent routing threads to each wiring partition, parallel routing in multiple wiring partitions on a multi-core or multi-processor platform is supported, which can greatly improve resource utilization and routing speed and effectively reduce the overall design cycle. In addition, based on the partition-level routing, efficient merging and conflict resolution of the routing results of cross-region signal paths are performed to realize seamless integration of global routing and avoid process and rule violations that may be caused by partition boundaries. This combination of measures not only improves the concurrency and automation level of digital circuit routing, but also improves the convergence efficiency and design quality of the final physical implementation, greatly meeting the actual needs of large-scale complex circuits in design cycle, reliability and performance, and has outstanding technical application value.

[0132] The device embodiment of the application is introduced below, which can be used to execute the digital circuit routing method in the above-mentioned embodiments of the application. For details not disclosed in the device embodiment of the application, please refer to the above-mentioned embodiments of the digital circuit routing method of the application.

[0133] Referring to Figure 6 , a block diagram of a digital circuit routing device in an embodiment of the application is shown.

[0134] As shown in Figure 6 , the digital circuit routing device 600 according to the embodiment of the application includes an acquisition unit 601, a division unit 602, a determination unit 603, a routing unit 604 and a merging unit 605.

[0135] The acquisition unit 601 is configured to acquire wiring grid parameters of each wiring layer in a digital circuit to be wired, wherein a grid line of the wiring grid is used to constrain a wiring track.

[0136] In some embodiments of the present application, based on the foregoing scheme, the wiring grid parameters include a grid pitch, and the segmentation unit 602 is configured to: traverse each wiring layer, segment the each wiring layer into a plurality of wiring layer regions, a length and a width of each wiring layer region being an integer multiple of the grid pitch of the each wiring layer, and the number of wiring layer regions of the each wiring layer being the same as the number of the wiring partitions; and define a set of wiring layer regions of each wiring layer that are opposite in a vertical direction as a wiring partition, to obtain the plurality of wiring partitions.

[0137] In some embodiments of the present application, based on the foregoing scheme, the access points include original access points and temporary access points, and the determination unit 603 is configured to: acquire the original access points preset on the each signal path; and set temporary access points on the each signal path according to distribution characteristics of the original access points of the each signal path in the wiring partitions.

[0138] In some embodiments of the present application, based on the foregoing scheme, the each signal path includes a metal pin used to send and / or receive a signal, and the determination unit 603 is configured to: if any metal pin on the each signal path crosses a plurality of wiring partitions, and the any metal pin does not have an original access point in any wiring partition of the plurality of wiring partitions, set a first temporary access point on the any metal pin, the first temporary access point falling into the any wiring partition.

[0139] In some embodiments of the present application, based on the foregoing scheme, the apparatus further comprises a generating unit configured to, after setting the first temporary access point on the arbitrary one of the metal pins, generate a virtual via for the arbitrary one of the metal pins at the first temporary access point based on a via design rule defined in a basic process database; call a violation detection engine to detect whether the virtual via generates a violation; and if the virtual via does not generate a violation, determine an evaluation prediction value of the first temporary access point, the evaluation prediction value being used to represent a probability that the first temporary access point is not selected in a future actual routing process.

[0140] In some embodiments of the present application, based on the foregoing scheme, the generating unit is further configured to, if the virtual via generates a violation, generate a virtual metal line for the virtual via at a target routing layer based on the via design rule, the target routing layer being a next routing layer of a routing layer where the virtual via is located, a projection of the virtual metal line in a vertical direction being surrounded by a projection of the arbitrary one of the metal pins in the vertical direction.

[0141] In some embodiments of the present application, based on the foregoing scheme, the determining unit 603 is further configured to, if any two adjacent original access points on the each signal path fall into two routing partitions respectively, determine a boundary line of the two routing partitions at a routing layer where the any two original access points are located; and set a second temporary access point at an intersection position of a guide line connecting the any two original access points and the boundary line, the second temporary access point being used to eliminate a violation generated when routing the each signal path in the two routing partitions respectively.

[0142] In some embodiments of the present application, based on the foregoing scheme, the generating unit is further configured to, after setting the second temporary access point at the intersection position of the guide line connecting the any two original access points and the boundary line, generate a virtual metal line at the second temporary access point based on a metal line design rule defined in a basic process database; call a violation detection engine to detect whether the virtual metal line generates a violation; and if the virtual metal line generates a violation, generate a new second temporary access point on the boundary line at a position separated from the intersection position by the grid pitch, and return to execute the step of generating the virtual metal line at the second temporary access point until the virtual metal line does not generate a violation.

[0143] In some embodiments of the present application, based on the foregoing scheme, the wiring unit 604 is configured to: configure a wiring thread for each wiring partition; based on the original access point and the temporary access point of each signal path in each wiring partition, call the wiring engine through the wiring thread to wire the signal paths falling into each wiring partition, and call the exception detection engine to detect whether wiring of the signal paths in each wiring partition produces an exception; if wiring of the signal paths in each wiring partition produces an exception, remove the wiring that produces the exception and rewire; and when wiring of all signal paths falling into each wiring partition is completed and no exception is produced, terminate the wiring of the signal paths in each wiring partition.

[0144] In some embodiments of the present application, based on the foregoing scheme, the merging unit 605 is configured to: traverse each signal path in the digital circuit, delete invalid wiring generated at the temporary access point in each signal path, and merge wiring of each signal path in different wiring partitions; call the exception detection engine to detect whether wiring of each signal path produces an exception; if wiring of each signal path produces an exception, remove wiring of each signal path and rewire until wiring of each signal path does not produce an exception.

[0145] Based on the same inventive concept, the embodiments of the present application provide a computer program product, which comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to enable a computer device having the processor to perform operations performed by the digital circuit wiring method as described above.

[0146] Based on the same inventive concept, the embodiments of the present application provide a computer readable storage medium, which stores at least one computer program instruction, and the at least one computer program instruction is loaded and executed by a processor to enable the processor to perform operations performed by the digital circuit wiring method as described above.

[0147] Based on the same inventive concept, the embodiments of the present application further provide an electronic device, which is shown in Figure 7 , which shows a structural schematic diagram of the electronic device in the embodiments of the present application, and the electronic device comprises one or more memories 704, one or more processors 702, and at least one computer program (computer program instructions) stored in the memory 704 and executable on the processor 702, and the processor 702 implements the digital circuit wiring method as described above when executing the computer program.

[0148] In the embodiments of the present application, the processor 702 is configured to implement the digital circuit wiring method as described above when executing the computer program. Figure 7In particular embodiments, a bus architecture, represented generally by the bus 700, can include any number of interconnected buses and bridges, the bus 700 linking together various circuits such as the processor 702 represented by one or more processors and the memory 704 represented by the memory. The bus 700 can also link together various other circuits such as peripheral devices, voltage stabilizers and power management circuits, which are well known in the art, and thus, further description herein will not be provided. The bus interface 705 provides an interface between the bus 700 and the receiver 701 and the transmitter 703. The receiver 701 and the transmitter 703 can be the same element, i.e., a transceiver, providing a means for communicating with various other apparatuses over a transmission medium. The processor 702 is responsible for managing the bus 700 and general processing, while the memory 704 can be used for storing data used by the processor 702 in executing operational processes.

[0149] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transferred over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as technology evolves, the "functionalities" described herein can be implemented by various combinations of digital and analog circuitry, which combinations are not limited to

[0150] In several embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. Among them, the above-mentioned device embodiments are only schematic, for example, the division of the units can be a logical function division, and actual implementation can have another division mode, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, indirect coupling or communication connection between units or modules, which can be electrical or other forms.

[0151] The units described as separate components can or can not be physically separated, and the components of the control device can or can not be physical units, that is, they can be located in one place, or they can be distributed on multiple units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0152] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer program instructions.

[0153] The above only describes the embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the scope of the claims of the present application.

Claims

1. A digital circuit wiring method, characterized in that, The method includes: Obtain the wiring grid parameters of each wiring layer in the digital circuit to be wired, where the grid lines of the wiring grid are used to constrain the wiring paths; Based on the wiring grid parameters of each wiring layer, the digital circuit is divided into multiple wiring partitions, wherein the area size of each wiring layer in each wiring partition is different; Traverse each signal path and determine the access point for each signal path. The access point is used to perform routing indexing for each signal path. Based on the access points of the signal paths in each wiring partition, the signal paths in each wiring partition are wired in parallel by configuring wiring threads for each wiring partition. The signal paths in each wiring partition are merged to obtain the complete wiring of the digital circuit. The access points include original access points and temporary access points. Determining the access point for each signal path includes: acquiring the pre-set original access points on each signal path; and setting temporary access points on each signal path according to the distribution characteristics of the original access points of each signal path in each cabling partition.

2. The method according to claim 1, characterized in that, The wiring grid parameters include the grid spacing. Based on the wiring grid parameters of each wiring layer, the digital circuit is divided into multiple wiring partitions, including: Traverse each routing layer and divide each routing layer into multiple routing layer regions. The length and width of each routing layer region are integer multiples of the grid spacing of each routing layer. The number of routing layer regions in each routing layer is the same as the number of routing partitions. The set of vertically opposite wiring layer regions of each wiring layer is defined as a wiring partition, thus obtaining the plurality of wiring partitions.

3. The method according to claim 2, characterized in that, Each signal path includes a metal pin for transmitting and / or receiving signals; The step of setting temporary access points on each signal path based on the distribution characteristics of the original access points of each signal path in each wiring partition includes: If any metal pin on each signal path spans multiple wiring partitions, and no original access point is set in any of the multiple wiring partitions that the metal pin spans, then a first temporary access point is set on the metal pin, and the first temporary access point falls into the wiring partition.

4. The method according to claim 3, characterized in that, After setting a first temporary access point on any one of the metal pins, the method further includes: Based on the via design rules defined in the basic process database, a virtual via is generated for any one of the metal pins at the first temporary access point; The violation detection engine is invoked to detect whether the virtual via has generated a violation. If the virtual via does not generate a violation, the evaluation prediction value of the first temporary access point is determined, which is used to characterize the probability that the first temporary access point will not be selected in the actual future cabling process.

5. The method according to claim 4, characterized in that, The method further includes: If the virtual via generates a violation, a virtual metal line is generated for the virtual via in the target routing layer based on the via design rules. The target routing layer is the next routing layer after the routing layer where the virtual via is located. The projection of the virtual metal line in the vertical direction is surrounded by the projection of any metal pin in the vertical direction.

6. The method according to claim 2, characterized in that, The step of setting temporary access points on each signal path based on the distribution characteristics of the original access points of each signal path in each wiring partition includes: If any two adjacent original access points on each signal path fall into two wiring partitions respectively, then the boundary line between the two wiring partitions is determined for the wiring layer where the two original access points are located. A second temporary access point is set at the intersection of the guide line connecting any two original access points and the boundary line. The second temporary access point is used to eliminate violations generated when wiring each signal path in the two wiring partitions.

7. The method according to claim 6, characterized in that, After setting a second temporary access point at the intersection of the guide line connecting any two original access points and the boundary line, the method further includes: Based on the metal line design rules defined in the basic process database, a virtual metal line is generated at the second temporary access point; The violation detection engine is invoked to check whether the virtual metal line generates a violation. If the virtual metal line generates a violation, a new second temporary access point is generated at a position on the boundary line at a distance of the grid spacing from the intersection position, and the process returns to the step of generating the virtual metal line at the second temporary access point until the virtual metal line does not generate a violation.

8. The method according to claim 2, characterized in that, The access points based on signal paths in each cabling partition, through cabling threads configured separately for each cabling partition, perform parallel cabling of signal paths in each cabling partition, including: Configure a cabling thread for each of the cabling partitions; Based on the original access point and temporary access point of each signal path in each cabling partition, the cabling thread calls the cabling engine to cable the signal paths falling into each cabling partition, and calls the violation detection engine to detect whether the cabling of the signal paths in each cabling partition has generated a violation. If a violation occurs in the wiring of a signal path in each wiring partition, the wiring that caused the violation shall be removed and rewired. Once all signal paths falling into each of the wiring partitions have been wired without any violations, the wiring of the signal paths in each of the wiring partitions is terminated.

9. The method according to claim 2, characterized in that, The merging of signal paths in each wiring partition includes: Traverse each signal path in the digital circuit, delete invalid wiring generated by the temporary access point in each signal path, and merge the wiring of each signal path in different wiring partitions; The violation detection engine is invoked to detect whether the wiring of each signal path has generated a violation; If a violation occurs in the wiring of any of the signal paths, the wiring of each signal path is removed and rewired until no violation occurs in the wiring of each signal path.

10. A digital circuit wiring device, characterized in that, The device includes: The acquisition unit is used to acquire the wiring grid parameters of each wiring layer in the digital circuit to be wired, wherein the grid lines of the wiring grid are used to constrain the wiring tracks; A segmentation unit is used to divide the digital circuit into multiple wiring partitions based on the wiring grid parameters of each wiring layer, wherein the area size of each wiring layer in each wiring partition is different; A determination unit is used to traverse each signal path and determine the access point of each signal path, wherein the access point is used to perform wiring indexing on each signal path; The routing unit is used to route the signal paths in each routing partition in parallel, based on the access points of the signal paths in each routing partition, through routing threads configured separately for each routing partition. The merging unit is used to merge the wiring of the signal paths in each wiring partition to obtain the complete wiring of the digital circuit. The access points include original access points and temporary access points. Determining the access point for each signal path includes: acquiring the pre-set original access points on each signal path; and setting temporary access points on each signal path according to the distribution characteristics of the original access points of each signal path in each cabling partition.

11. A computer program product, characterized in that, The computer program product includes computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the method as described in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one piece of program code, which is loaded and executed by a processor to perform the operations performed by the method as described in any one of claims 1 to 9.

13. An electronic device, characterized in that, The electronic device includes one or more processors and one or more memories, wherein at least one piece of program code is stored in the one or more memories, and the at least one piece of program code is loaded and executed by the one or more processors to implement the method as described in any one of claims 1 to 9.

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