Wafer yield map matching method and device, equipment and medium

Abstract

The invention provides a wafer yield map matching method and apparatus, a device and a medium. The method comprises the steps of obtaining a to-be-matched wafer yield map; extracting a first failure diagram and a second failure diagram according to the wafer yield diagram to be matched; performing similarity matching on the first failure graph and a plurality of first matching graphs in a graph database, and performing similarity matching on the second failure graph and a plurality of second matching graphs in the graph database; and taking the first matching graph having the highest similarity with the first failure graph and the corresponding process information, and the second matching graph having the highest similarity with the second failure graph and the corresponding process information as matching results of the wafer yield graph to be matched. According to the method provided by the invention, the wafer yield graph is matched with the graph in the graph database established based on the defect measurement data and the process measurement data of the historical wafer, so that the accuracy of the failure analysis process of the wafer can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip manufacturing, and in particular to a method, device, equipment and medium for matching wafer yield maps. Background Art

[0002] During semiconductor chip manufacturing, wafer yield failures can occur due to chip design flaws or process disturbances. To quickly identify the causes of yield failures and avoid the economic losses caused by production line downtime, it is necessary to analyze and investigate the characteristics of wafer yield failures.

[0003] Currently, the main approach to analyzing wafer yield failure characteristics is for engineers to determine whether the location of process defects overlaps with yield failure areas and, based on past experience, to infer the failure causes. However, this approach consumes significant manpower and time, and can easily miss process issues that lead to failures, thereby reducing the accuracy of failure cause analysis. Therefore, the current challenge is to improve the accuracy of wafer failure analysis. Summary of the Invention

[0004] The present application provides a wafer yield map matching method, device, equipment and medium to improve the accuracy of the wafer failure analysis process.

[0005] On the one hand, the present application provides a method for matching a wafer yield map, comprising: obtaining a wafer yield map to be matched; wherein the wafer yield map represents chip test results of chips at various positions of the wafer; extracting a first failure map and a second failure map based on the wafer yield map to be matched; wherein the first failure map represents the test pass status of the chips at various positions in the chip test results, and the second failure map represents the test values ​​of the chips at various positions in the chip test results under different test items; performing similarity matching on the first failure map and a plurality of first matching maps in a graphic database, and performing similarity matching on the second failure map. Similarity matching is performed with multiple second matching graphs in the graphic database; wherein, the first matching graph is established based on defect measurement data of historical wafers, and the second matching graph is established based on process measurement data of historical wafers, and the process measurement data at least includes film thickness data, critical dimension data, wafer acceptable test data, and groove depth data; the first matching graph with the highest similarity to the first failure graph and the process information corresponding to the first matching graph, as well as the second matching graph with the highest similarity to the second failure graph and the process information corresponding to the second matching graph, are used as matching results of the wafer yield graph to be matched.

[0006] In one possible implementation, the second failure map includes second failure maps under different test items, and the second failure map is extracted according to the wafer yield map to be matched, including: obtaining the initial failure map of the wafer yield map to be matched; in the initial failure map, sequentially obtaining the test values ​​of all position chips under each test item, and color-labeling the position chips in the initial failure map according to the test values ​​to obtain the second failure map under the test item; the method also includes: obtaining the process measurement data of the chips at each position of the historical wafer and the initial matching map of the historical wafer; judging whether the number of process measurement data of the chips at each position of the historical wafer meets the number of full map data; if so, color-labeling the position chips in the initial matching map of the historical wafer according to the process measurement data of the chips at each position of the historical wafer to obtain the second matching map; if not, ending the process.

[0007] In a possible implementation, before color-coding the position chips in the initial matching map of the historical wafer based on the process measurement data of the chips at each position of the historical wafer, the method further includes: determining whether the process measurement data is within a preset range; color-coding the position chips in the initial matching map of the historical wafer based on the process measurement data of the chips at each position of the historical wafer, including: if the process measurement data is within the preset range, color-coding the position chips in the initial matching map of the historical wafer based on the process measurement data of the chips at each position of the historical wafer; after determining whether the process measurement data is within the preset range, the method further includes: if the process measurement data is not within the preset range, correcting the process measurement data based on the process measurement data of multiple position chips adjacent to the position chip where the process measurement data is located; and color-coding the position chips in the initial matching map of the historical wafer based on the corrected process measurement data.

[0008] In one possible implementation, extracting a first failure map based on the wafer yield map to be matched includes: obtaining an initial failure map of the wafer yield map to be matched; in the initial failure map, marking the position chip with a pass status of the test as a second mark, and marking the position chip with a fail status of the test as a first mark, to obtain a first failure map; the method also includes: obtaining defect measurement data of each position chip of the historical wafer and the initial matching map of the historical wafer; judging whether the defect measurement data of each position chip of the historical wafer is abnormal; if the defect measurement data of the historical wafer is abnormal, marking the position chip in the initial matching map of the historical wafer as a first mark according to the measurement data; otherwise, marking the position chip in the initial matching map of the historical wafer as a second mark according to the measurement data, to obtain a first matching map.

[0009] In a possible implementation, after marking the position chip with a passed test status as a second mark and marking the position chip with a failed test status as a first mark, it also includes: detecting whether there are multiple consecutive second position chips marked as the first mark in the same direction of the first position chip marked as the first mark in the initial failure map; if so, keeping the first mark marking of the first position chip and the second position chip; otherwise, marking the first position chip as the second mark.

[0010] In one possible implementation, performing similarity matching on the first failure graph and multiple first matching graphs in a graphic database, and performing similarity matching on the second failure graph and multiple second matching graphs in the graphic database, includes: constructing an image recognition model based on a convolutional neural network, and calling the image recognition model to perform similarity matching on the first failure graph and multiple first matching graphs in a graphic database, and performing similarity matching on the second failure graph and multiple second matching graphs in a graphic database.

[0011] On the other hand, the present application provides a circular yield map matching device, comprising:

[0012] An acquisition module is used to acquire a wafer yield map to be matched; wherein the wafer yield map represents the chip test results of the chips at each position of the wafer; a failure module is used to extract a first failure map and a second failure map according to the wafer yield map to be matched; wherein the first failure map represents the test pass status of the chips at each position in the chip test results, and the second failure map represents the test values ​​of the chips at each position in the chip test results under different test items; a matching module is used to perform similarity matching on the first failure map and multiple first matching maps in the graphic database, and to perform similarity matching on the second failure map and the graphic database. Similarity matching is performed on multiple second matching graphs in the database; wherein, the first matching graph is established based on defect measurement data of historical wafers, and the second matching graph is established based on process measurement data of historical wafers, and the process measurement data at least includes film thickness data, critical dimension data, wafer acceptable test data, and groove depth data; an output module is used to use the first matching graph with the highest similarity to the first failure graph and the process information corresponding to the first matching graph, as well as the second matching graph with the highest similarity to the second failure graph and the process information corresponding to the second matching graph, as matching results of the wafer yield graph to be matched.

[0013] In one possible implementation, the failure module is used to: obtain an initial failure map of the wafer yield map to be matched; in the initial failure map, sequentially obtain the test values ​​of all position chips under each test item, and perform color gradation on the position chips in the initial failure map according to the test values ​​to obtain a second failure map under the test item; the matching module is also used to: obtain the process measurement data of the chips at each position of the historical wafer and the initial matching map of the historical wafer; determine whether the number of process measurement data of the chips at each position of the historical wafer meets the number of full map data; if so, perform color gradation on the position chips in the initial matching map of the historical wafer according to the process measurement data of the chips at each position of the historical wafer to obtain the second matching map; if not, end the process.

[0014] On the other hand, the present application provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the above method.

[0015] On the other hand, the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the above method.

[0016] The present application provides a method, device, equipment and medium for matching wafer yield maps, the method comprising: obtaining a wafer yield map to be matched; extracting a first failure map and a second failure map based on the wafer yield map to be matched; performing similarity matching on the first failure map and multiple first matching maps in a graphic database, and performing similarity matching on the second failure map and multiple second matching maps in a graphic database; using the first matching map with the highest similarity to the first failure map and the corresponding process information, and the second matching map with the highest similarity to the second failure map and the corresponding process information as the matching results of the wafer yield map to be matched. The method of the present application matches the wafer yield map with the graphics in the graphic database established based on defect measurement data and process measurement data of historical wafers, which can improve the accuracy of the wafer failure analysis process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 exemplarily shows a flow chart of the wafer yield map matching method provided in the first embodiment;

[0019] Figure 2exemplarily shows a flow chart of another wafer yield map matching method provided in the first embodiment;

[0020] Figure 3 exemplarily shows a flow chart of another wafer yield map matching method provided in the first embodiment;

[0021] Figure 4 exemplarily shows a flow chart of another wafer yield map matching method provided in the first embodiment;

[0022] Figure 5 exemplarily shows a schematic diagram of the first failure diagram provided in the first embodiment;

[0023] Figure 6 exemplarily shows a graphical diagram of obtaining defect measurement data provided by the first embodiment;

[0024] Figure 7 exemplarily shows a schematic diagram of the first matching graph provided in the first embodiment;

[0025] Figure 8 exemplarily shows a flow chart of another wafer yield map matching method provided in the first embodiment;

[0026] Figure 9 exemplarily shows a schematic structural diagram of a wafer yield map matching device provided in the second embodiment;

[0027] Figure 10 Schematic diagram of the structure of the electronic device provided in the third embodiment is shown in FIG.

[0028] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0029] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0030] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings. The terms "including" and "having" in the specification and claims of this application and the above-mentioned drawings, as well as any variations thereof, are intended to cover but not exclude inclusion. For example, a product or device that includes a series of components is not necessarily limited to those components that are clearly listed, but may include other components that are not clearly listed or are inherent to these products or devices. The term "module" used in this application refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic or combination of hardware and / or software code that can perform the functions associated with the element.

[0031] Currently, during the semiconductor chip manufacturing process, some wafers experience low yield after chip probing, manifesting as a ratio of qualified chips to the total number of chips on the wafer falling below a baseline. Low wafer yields are primarily caused by two factors: design flaws in the chips themselves, and instabilities in the various process steps during wafer manufacturing. Yield engineers typically trace process data from the production line for the batch of failed wafers when performing wafer failure analysis. However, to improve production line productivity and reduce measurement time, low-yield wafers may not have corresponding process data. Therefore, yield engineers determine whether the locations of process defects on wafers from other batches overlap with the yield failure area and, based on empirical evidence, infer the cause of the wafer failure. However, current approaches are labor-intensive and time-consuming, and often miss factors that contribute to wafer failures, reducing the accuracy of failure analysis.

[0032] The technical content provided by this application is intended to solve the above-mentioned technical problems of the related art. The wafer yield map matching method, device, equipment and medium provided by this application include: obtaining the wafer yield map to be matched; extracting the first failure map and the second failure map based on the wafer yield map to be matched; performing similarity matching on the first failure map and multiple first matching maps in the graphic database, and performing similarity matching on the second failure map and multiple second matching maps in the graphic database; using the first matching map with the highest similarity to the first failure map and the corresponding process information, and the second matching map with the highest similarity to the second failure map and the corresponding process information as the matching results of the wafer yield map to be matched. The method of this application matches the wafer yield map with the graphics in the graphic database established based on the defect measurement data and process measurement data of historical wafers, which can improve the accuracy of the failure analysis process of the wafer.

[0033] The technical solutions of the present application and the technical solutions of the present application are described in detail below with reference to specific embodiments. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in certain embodiments. In the description of the present application, unless otherwise clearly specified and limited, each term should be understood in a broad sense within the art. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0034] Example 1

[0035] Figure 1 A schematic flow chart of a wafer yield map matching method is shown in FIG. , and the execution subject of this example may be a wafer yield map matching device, such as Figure 1 As shown, the method includes:

[0036] Step 101: Obtain a wafer yield map to be matched; wherein the wafer yield map represents chip test results of chips at various positions on the wafer;

[0037] Step 102: extracting a first failure map and a second failure map based on the wafer yield map to be matched; wherein the first failure map represents the test pass status of the chip at each position in the chip test results, and the second failure map represents the test values ​​of the chip at each position in the chip test results under different test items;

[0038] Step 103: performing similarity matching between the first failure graph and a plurality of first matching graphs in the graph database, and performing similarity matching between the second failure graph and a plurality of second matching graphs in the graph database; wherein the first matching graphs are established based on defect measurement data of historical wafers, and the second matching graphs are established based on process measurement data of historical wafers, and the process measurement data at least includes film thickness data, critical dimension data, wafer acceptance test data, and trench depth data;

[0039] Step 104 : Use the first matching graph having the highest similarity to the first failure graph and the process information corresponding to the first matching graph, and the second matching graph having the highest similarity to the second failure graph and the process information corresponding to the second matching graph as matching results of the wafer yield graph to be matched.

[0040] In practical applications, the executor of this method can be a matching device for the wafer yield map, and there are many ways to implement it. For example, it can be implemented through a computer program, such as application software, etc.; or it can be implemented as a medium that stores relevant computer programs, such as a USB flash drive, a cloud disk, etc.; or it can be implemented through a physical device that integrates or installs relevant computer programs, such as a chip, etc.

[0041] During the chip probing process of a wafer, a tester (Automatic Test Equipment, ATE for short) usually tests the positional chips (DIEs) in the wafer with exposed pins. The yield map of the wafer to be matched can be obtained by the tester or from a database connected to the tester that stores the yield map of the wafer. In practical applications, the yield map of the wafer to be matched can be obtained according to a certain cycle or according to the instructions of the engineer. Depending on the chip design scheme, there may be dozens to hundreds of positional chips on a wafer. After obtaining the yield map of the wafer to be matched, the first failure map and the second failure map are extracted based on the yield map of the wafer to be matched. In the first failure map, if all different test items of a chip at a certain position have passed, the pass status of the chip is passed; if there is at least one test item that has failed, the pass status of the chip at that position is failed. Optionally, to speed up the matching efficiency, if the test results of the same test item corresponding to each chip at each position have passed, the second failure map of the test item is not extracted. In practical applications, different test items can include basic device parameters such as threshold voltage, on-resistance, source-drain breakdown voltage, gate-source leakage current, and drain-source leakage current. The first failure map can be used to obtain the overall test results for each chip in the yield map of the matching wafer. The second failure map can be used to obtain the specific test results for each chip in the yield map of the matching wafer under different test items.

[0042] After obtaining the first failure map and the second failure map, the first failure map is similarly matched with a plurality of first matching maps established based on the defect measurement data of the historical wafer; and the second failure map is similarly matched with a plurality of second matching maps established based on the process measurement data of the historical wafer. Among them, the historical wafer represents a wafer that has undergone the same or similar process steps as the wafer corresponding to the wafer yield map to be matched, and has been measured by a measurement machine after this process, and the batch to which the historical wafer belongs is different from the batch to which the wafer corresponding to the wafer yield map to be matched belongs. Generally speaking, after the historical wafer is measured by a defect measurement machine, it is also necessary to pass through a re-inspection machine such as a scanning electron microscope (SEM) and an optical microscope (OM) to obtain defect measurement data. Among them, the types of defects include arc discharge, residual glue, dust, scratches, etc. On the other hand, after historical wafers are measured by process measurement tools, the process measurement data obtained, such as film thickness data, critical dimension data, wafer acceptance test data, and trench depth data, can be used to quantitatively analyze the process stability of the wafers.

[0043] Through the above-mentioned similarity matching, the matching results of the yield map of the wafer to be matched can be obtained. Among them, the first matching map with the highest similarity to the first failure map can be used to perform a qualitative analysis of the failure cause of the first failure map in the defect dimension; the second matching map with the highest similarity to the second failure map can be used to perform a quantitative analysis of the failure cause of the second failure map in the process dimension. In addition, the process information corresponding to the first matching map or the second matching map can be used to locate potential failure causes and avoid economic losses caused by the same failure cause; wherein, the process information includes: the batch to which the historical wafer belongs, the process machine, the measurement machine, the measurement site, the product information (Product ID), etc. Optionally, after obtaining the matching results, engineers can also judge the validity of the matching results based on experience.

[0044] The wafer yield map matching method provided in this example includes: obtaining a wafer yield map to be matched; extracting a first failure map and a second failure map based on the wafer yield map to be matched; performing similarity matching on the first failure map and multiple first matching maps in a graphic database, and performing similarity matching on the second failure map and multiple second matching maps in a graphic database; using the first matching map with the highest similarity to the first failure map and the corresponding process information, and the second matching map with the highest similarity to the second failure map and the corresponding process information as the matching results of the wafer yield map to be matched. The method of the present application matches the wafer yield map with the graphics in the graphic database established based on defect measurement data and process measurement data of historical wafers, which can improve the accuracy of the wafer failure analysis process.

[0045] To improve the matching accuracy of the second failure image and the second matching image, the second failure image and the second matching image may be subjected to the same image processing. As an example, Figure 2 A schematic flow chart of a wafer yield map matching method is shown as an example. Based on any example, the second failure map includes second failure maps under different test items, and step 102 includes:

[0046] Step 201: Obtain an initial failure map of a wafer yield map to be matched;

[0047] Step 202: In the initial failure map, test values ​​of all chips at each position under each test item are sequentially obtained, and color-coded the chips at each position in the initial failure map according to the test values ​​to obtain a second failure map under the test item.

[0048] The wafer yield map matching method also includes:

[0049] Step 203: Obtain process measurement data of chips at each position of the historical wafer and an initial matching map of the historical wafer;

[0050] Step 204: Determine whether the quantity of process measurement data of chips at each position of the historical wafer meets the quantity of data in the full image; if so, perform color gradation marking on the position chips in the initial matching image of the historical wafer according to the process measurement data of chips at each position of the historical wafer to obtain a second matching image; if not, terminate the process.

[0051] In this example, the initial failure map of the wafer yield map to be matched includes wafer dimensions, the number of chips at each wafer location, and the location information of each chip. Test values ​​for all chips at each test item are sequentially obtained, and the chips at each location in the initial failure map are color-coded based on the test values ​​to obtain a second failure map for that test item. For example, the threshold voltage test values ​​for all chips at each location under the threshold voltage test item can be obtained. Chips with larger threshold voltage test values ​​have a brighter color scale, resulting in a color-coded second matching map for the threshold voltage test item. The brightness of the color scale can be differentiated by different RGB values. Accordingly, by establishing an initial matching map for the historical wafer, the chips at each location are color-coded based on the process measurement data values ​​of each chip at each location under different process measurement data types. In practical applications, to improve the efficiency of pattern matching, the colors of the second failure map and the second matching map can be unified for similarity matching. In practical applications, historical wafers may only have a sampling test performed on a subset of chips at the measurement site, resulting in incomplete process measurement data for the historical wafer. By comparing the number of process measurement data for chips at each location on the historical wafer with the number of full map data, the validity of the process measurement data can be improved. In this example, color-coding the second failure map and the second matching map can improve the accuracy of the matching between the second failure map and the second matching map.

[0052] Considering the random errors in the process measurement data of historical wafers, outliers in the process measurement data of historical wafers can be screened out. As an example, Figure 3 A flow chart of a wafer yield map matching method is shown as an example. Based on any example, before color-coding the position chips in the initial matching map of the historical wafer based on the process measurement data of the chips at each position of the historical wafer in step 204, the method further includes:

[0053] Step 301: Determine whether the process measurement data is within a preset range;

[0054] Step 204: If the process measurement data is within the preset range, color-code the position chips in the initial matching map of the historical wafer according to the process measurement data of the chips at each position of the historical wafer;

[0055] After step 301, the following steps are also included:

[0056] Step 302: If the process measurement data is not within the preset range, the process measurement data is corrected based on the process measurement data of multiple position chips adjacent to the position chip where the process measurement data is located; and the position chips in the initial matching map of the historical wafer are color-coded based on the corrected process measurement data.

[0057] In this example, the preset range can be (μ-3σ, μ+3σ) or (μ-5σ, μ+5σ), where μ is the mean of all process measurement data at the measurement site, and σ is the standard deviation of all process measurement data at the measurement site. If the process measurement data is within the preset range, the position chip in the initial matching map of the historical wafer is color-coded according to the process measurement data of each position chip of the historical wafer; if the process measurement data is not within the preset range, the process measurement data is corrected according to the process measurement data of multiple position chips adjacent to the position chip where the process measurement data is located; and the position chip in the initial matching map of the historical wafer is color-coded according to the corrected process measurement data. The correction of the process measurement data can be to correct the process measurement data to the average value of the process measurement data of the four position chips adjacent to the upper, lower, left and right of the position chip where the process measurement data is located; or, to correct it to the weighted average value of the process measurement data of the eight position chips adjacent to the position chip where the process measurement data is located. The solution provided in this example can correct outliers that are outside a preset range, thereby reducing the impact of random errors in historical wafer process measurement data.

[0058] To improve the matching accuracy between the first failure image and the first matching image, the first failure image and the first matching image may be subjected to the same image processing. As an example, Figure 4 A schematic flow chart of a wafer yield map matching method is shown as an example. Based on any example, in step 102, extracting a first failure map according to the wafer yield map to be matched includes:

[0059] Step 401: Obtain an initial failure map of a wafer yield map to be matched;

[0060] Step 402: In the initial failure map, the chips at positions where the test passes are marked as second marks, and the chips at positions where the test fails are marked as first marks, to obtain a first failure map;

[0061] The wafer yield map matching method also includes:

[0062] Step 403: Obtain defect measurement data of chips at various positions of the historical wafer and an initial matching map of the historical wafer;

[0063] Step 404: Determine whether the defect measurement data of the chips at each position of the historical wafer is abnormal; if the defect measurement data of the historical wafer is abnormal, mark the position chip in the initial matching map of the historical wafer as a first mark based on the measurement data; otherwise, mark the position chip in the initial matching map of the historical wafer as a second mark based on the measurement data to obtain a first matching map.

[0064] In this example, the initial failure map of the wafer yield map to be matched includes the size information of the wafer, the number information of the chips at each position in the wafer, and the position information of the chips at each position. In the initial failure map, the position chips with a pass test status of pass are marked as the second mark, and the position chips with a fail test status are marked as the first mark to obtain the first failure map. Specifically, for a certain position chip, if there is at least one test item with a fail result, the test pass status of the position chip is fail; if the results of all the test items of the position chip are pass, the pass status of the position chip is pass. In actual applications, the second mark annotation can fill the position chip with green or white, and the first mark annotation can fill the position chip with red or black. Figure 5 The schematic diagram of the first failure diagram is shown as an example. Figure 5 As shown, each position chip is distinguished from each other by a grid; among them, the position chip with a pass status of "fail" in the first failure map is filled with dark gray, and it is mainly distributed in the lower left corner; the position chip with a pass status in the first failure map is filled with white. Accordingly, by establishing an initial matching map of the historical wafer, the position chip is marked with a second mark or a first mark according to the defect measurement data of the historical wafer. Among them, whether the defect measurement data is abnormal refers to whether there is defect measurement data on the position chip. In actual applications, if a defect in the defect measurement data, such as dust or scratches, is covered on two position chips, then the defect measurement data of the two position chips are both abnormal. Figure 6 exemplarily shows a graphical diagram of obtaining defect measurement data; wherein, Figure 6 The left figure is a graph drawn based on the data of the historical wafer after it passes through the defect measurement machine. On this basis, the defect measurement data of the historical wafer is obtained after the review machine is reviewed. Figure 6 The right side of the figure. It should be noted that, Figure 6 The methods for obtaining the left and right images are both existing technologies and will not be elaborated on here. Figure 7 A schematic diagram of the first matching graph is shown in FIG. Figure 7 For Figure 6 Based on the right figure, the defect measurement data of the position chip is judged as abnormal, and the position chip is marked with the first mark or the second mark. Figure 7As shown, the chips in the first matching image with abnormal defect metrology data are filled with dark gray, primarily in the lower left corner. Chips in the first matching image with normal defect metrology data are filled with white. This example solution, by annotating the first failure image and the first matching image with the first marker / second marker, improves the accuracy of the matching between the first failure image and the first matching image.

[0065] Considering that the chips with the failed test status in the initial failure map are randomly distributed, they cannot be used to analyze the cause of wafer failure. As an example, Figure 8 A schematic flow chart of a wafer yield map matching method is shown as an example. Based on any example, after step 402, the following steps are further included:

[0066] Step 501: Detect whether there are multiple consecutive chips at the second position marked with the first mark in the same direction in the first position chip marked with the first mark in the initial failure map;

[0067] Step 502: If so, keep the first mark of the first position chip and the second position chip; otherwise, mark the first position chip with the second mark.

[0068] Among them, a plane rectangular coordinate system can be first established based on the initial failure map. If the first position chip marked as the first mark has at least 3 or 5 consecutive second position chips marked as the first mark in the x-axis or y-axis or diagonal direction. If so, keep the first mark marking of the first position chip and the second position chip; otherwise, mark the first position chip as the second mark. In order to improve efficiency, polling can be set for each first-marked position chip. For example, if a first-marked first position chip has been marked as the second position chip in the previous polling, the polling of the first position chip will be skipped. The solution of this example can reduce the random interference of the position chip whose test pass status is failed in the initial failure map.

[0069] As another example, step 103 includes:

[0070] An image recognition model is constructed based on a convolutional neural network, and the image recognition model is called to perform similarity matching on the first failure image and multiple first matching images in the graphic database, as well as on the second failure image and multiple second matching images in the graphic database.

[0071] In this example, the convolutional neural network constructs an image recognition model using multiple convolutional layers to extract local features of the image, and uses average or maximum pooling layers to reduce the dimensionality of the extracted features. Furthermore, by extracting the spatial structure of the image, the convolutional neural network can prevent situations where the wafer cannot be matched to the corresponding image due to angular rotation. This example solution can improve the matching accuracy between the first failure image and multiple first matching images, as well as between the second failure image and multiple second matching images.

[0072] The wafer yield map matching method provided in this embodiment includes: obtaining a wafer yield map to be matched; extracting a first failure map and a second failure map based on the wafer yield map to be matched; performing similarity matching on the first failure map and multiple first matching maps in a graphic database, and performing similarity matching on the second failure map and multiple second matching maps in a graphic database; using the first matching map with the highest similarity to the first failure map and the corresponding process information, and the second matching map with the highest similarity to the second failure map and the corresponding process information as the matching results of the wafer yield map to be matched. The method of the present application matches the wafer yield map with the graphics in the graphic database established based on the defect measurement data and process measurement data of historical wafers, which can improve the accuracy of the wafer failure analysis process.

[0073] Example 2

[0074] Figure 9 FIG. 1 is a schematic diagram showing a structure of a matching device for a wafer yield map according to a second embodiment of the present application. Figure 9 As shown, the device includes:

[0075] An acquisition module 21 is configured to acquire a wafer yield map to be matched; wherein the wafer yield map represents chip test results of chips at various positions on the wafer;

[0076] The failure module 22 is configured to extract a first failure map and a second failure map based on the wafer yield map to be matched; wherein the first failure map represents the test pass status of the chip at each position in the chip test results, and the second failure map represents the test values ​​of the chip at each position in the chip test results under different test items;

[0077] a matching module 23 configured to perform similarity matching between the first failure graph and a plurality of first matching graphs in the graph database, and to perform similarity matching between the second failure graph and a plurality of second matching graphs in the graph database; wherein the first matching graphs are established based on defect measurement data of historical wafers, and the second matching graphs are established based on process measurement data of historical wafers, wherein the process measurement data includes at least film thickness data, critical dimension data, wafer acceptance test data, and trench depth data;

[0078] The output module 24 is used to use the first matching graph with the highest similarity to the first failure graph and the process information corresponding to the first matching graph, and the second matching graph with the highest similarity to the second failure graph and the process information corresponding to the second matching graph as matching results of the wafer yield graph to be matched.

[0079] In actual applications, there are many ways to implement the wafer yield map matching device. For example, it can be implemented through a computer program, such as application software; or it can be implemented as a medium that stores relevant computer programs, such as a USB flash drive, a cloud disk, etc.; or it can be implemented through a physical device that integrates or installs relevant computer programs, such as a chip.

[0080] During the chip probing process of a wafer, a tester (Automatic Test Equipment, ATE for short) usually tests the positional chips (DIEs) in the wafer with exposed pins. The yield map of the wafer to be matched can be obtained by the tester or from a database connected to the tester that stores the yield map of the wafer. In practical applications, the yield map of the wafer to be matched can be obtained according to a certain cycle or according to the instructions of the engineer. Depending on the chip design scheme, there may be dozens to hundreds of positional chips on a wafer. After obtaining the yield map of the wafer to be matched, the first failure map and the second failure map are extracted based on the yield map of the wafer to be matched. In the first failure map, if all different test items of a chip at a certain position have passed, the pass status of the chip is passed; if there is at least one test item that has failed, the pass status of the chip at that position is failed. Optionally, to speed up the matching efficiency, if the test results of the same test item corresponding to each chip at each position have passed, the second failure map of the test item is not extracted. In practical applications, different test items can include basic device parameters such as threshold voltage, on-resistance, source-drain breakdown voltage, gate-source leakage current, and drain-source leakage current. The first failure map can be used to obtain the overall test results for each chip in the yield map of the matching wafer. The second failure map can be used to obtain the specific test results for each chip in the yield map of the matching wafer under different test items.

[0081] After obtaining the first failure map and the second failure map, the first failure map is similarly matched with a plurality of first matching maps established based on the defect measurement data of the historical wafer; and the second failure map is similarly matched with a plurality of second matching maps established based on the process measurement data of the historical wafer. Among them, the historical wafer represents a wafer that has undergone the same or similar process steps as the wafer corresponding to the wafer yield map to be matched, and has been measured by a measurement machine after this process, and the batch to which the historical wafer belongs is different from the batch to which the wafer corresponding to the wafer yield map to be matched belongs. Generally speaking, after the historical wafer is measured by a defect measurement machine, it is also necessary to pass through a re-inspection machine such as a scanning electron microscope (SEM) and an optical microscope (OM) to obtain defect measurement data. Among them, the types of defects include arc discharge, residual glue, dust, scratches, etc. On the other hand, after historical wafers are measured by process measurement tools, the process measurement data obtained, such as film thickness data, critical dimension data, wafer acceptance test data, and trench depth data, can be used to quantitatively analyze the process stability of the wafers.

[0082] Through the above-mentioned similarity matching, the matching results of the yield map of the wafer to be matched can be obtained. Among them, the first matching map with the highest similarity to the first failure map can be used to perform a qualitative analysis of the failure cause of the first failure map in the defect dimension; the second matching map with the highest similarity to the second failure map can be used to perform a quantitative analysis of the failure cause of the second failure map in the process dimension. In addition, the process information corresponding to the first matching map or the second matching map can be used to locate potential failure causes and avoid economic losses caused by the same failure cause; wherein, the process information includes: the batch to which the historical wafer belongs, the process machine, the measurement machine, the measurement site, the product information (Product ID), etc. Optionally, after obtaining the matching results, engineers can also judge the validity of the matching results based on experience.

[0083] The wafer yield map matching device provided in this example includes: obtaining a wafer yield map to be matched; extracting a first failure map and a second failure map based on the wafer yield map to be matched; performing similarity matching on the first failure map and multiple first matching maps in a graphic database, and performing similarity matching on the second failure map and multiple second matching maps in the graphic database; using the first matching map with the highest similarity to the first failure map and the corresponding process information, and the second matching map with the highest similarity to the second failure map and the corresponding process information as the matching results of the wafer yield map to be matched. The method of the present application matches the wafer yield map with the graphics in the graphic database established based on the defect measurement data and process measurement data of historical wafers, which can improve the accuracy of the wafer failure analysis process.

[0084] As an example, the failure module 22 is specifically configured to:

[0085] Obtain an initial failure map of the wafer yield map to be matched; in the initial failure map, sequentially obtain test values ​​of all chips at each position under each test item, and color-code the chips at each position in the initial failure map according to the test values ​​to obtain a second failure map under the test item;

[0086] The matching module 23 is further configured to:

[0087] Obtain the process measurement data of the chips at each position of the historical wafer and the initial matching map of the historical wafer; determine whether the number of process measurement data of the chips at each position of the historical wafer meets the number of data in the full map; if so, perform color gradation marking on the position chips in the initial matching map of the historical wafer according to the process measurement data of the chips at each position of the historical wafer to obtain a second matching map; if not, end the process.

[0088] In this example, the initial failure map of the wafer yield map to be matched includes wafer dimensions, the number of chips at each wafer location, and the location information of each chip. Test values ​​for all chips at each test item are sequentially obtained, and the chips at each location in the initial failure map are color-coded based on the test values ​​to obtain a second failure map for that test item. For example, the threshold voltage test values ​​for all chips at each location under the threshold voltage test item can be obtained. Chips with larger threshold voltage test values ​​have a brighter color scale, resulting in a color-coded second matching map for the threshold voltage test item. The brightness of the color scale can be differentiated by different RGB values. Accordingly, by establishing an initial matching map for the historical wafer, the chips at each location are color-coded based on the process measurement data values ​​of each chip at each location under different process measurement data types. In practical applications, to improve the efficiency of pattern matching, the colors of the second failure map and the second matching map can be unified for similarity matching. In practical applications, historical wafers may only have a sampling test performed on a subset of chips at the measurement site, resulting in incomplete process measurement data for the historical wafer. By comparing the number of process measurement data for chips at each location on the historical wafer with the number of full map data, the validity of the process measurement data can be improved. In this example, color-coding the second failure map and the second matching map can improve the accuracy of the matching between the second failure map and the second matching map.

[0089] As an example, the matching module 23 is further configured to:

[0090] Determine whether the process measurement data is within a preset range; if the process measurement data is within the preset range, perform color gradation on the position chips in the initial matching diagram of the historical wafer according to the process measurement data of the chips at each position of the historical wafer; if the process measurement data is not within the preset range, perform correction on the process measurement data according to the process measurement data of multiple position chips adjacent to the position chip where the process measurement data is located; and perform color gradation on the position chips in the initial matching diagram of the historical wafer according to the corrected process measurement data.

[0091] In this example, the preset range can be (μ-3σ, μ+3σ) or (μ-5σ, μ+5σ), where μ is the mean of all process measurement data at the measurement site, and σ is the standard deviation of all process measurement data at the measurement site. If the process measurement data is within the preset range, the position chip in the initial matching map of the historical wafer is color-coded according to the process measurement data of each position chip of the historical wafer; if the process measurement data is not within the preset range, the process measurement data is corrected according to the process measurement data of multiple position chips adjacent to the position chip where the process measurement data is located; and the position chip in the initial matching map of the historical wafer is color-coded according to the corrected process measurement data. The correction of the process measurement data can be to correct the process measurement data to the average value of the process measurement data of the four position chips adjacent to the upper, lower, left and right of the position chip where the process measurement data is located; or, to correct it to the weighted average value of the process measurement data of the eight position chips adjacent to the position chip where the process measurement data is located. The solution provided in this example can correct outliers that are outside a preset range, thereby reducing the impact of random errors in historical wafer process measurement data.

[0092] As an example, the failure module 22 is specifically configured to:

[0093] Obtain an initial failure map of the wafer yield map to be matched; in the initial failure map, mark the chips at positions where the test passes as a pass as a second mark, and mark the chips at positions where the test fails as a first mark, to obtain a first failure map;

[0094] The matching module 23 is also used to: obtain the defect measurement data of the chip at each position of the historical wafer and the initial matching map of the historical wafer; determine whether the defect measurement data of the chip at each position of the historical wafer is abnormal; if the defect measurement data of the historical wafer is abnormal, mark the position chip in the initial matching map of the historical wafer as a first mark according to the measurement data; otherwise, mark the position chip in the initial matching map of the historical wafer as a second mark according to the measurement data to obtain a first matching map.

[0095] In this example, the initial failure map of the wafer yield map to be matched includes wafer size information, the number of chips at each position on the wafer, and the position information of each chip at each position. In the initial failure map, chips with a pass status are marked with a second marker, and chips with a fail status are marked with a first marker, thereby obtaining a first failure map. Specifically, for a chip at a certain position, if at least one test item fails, the test pass status of that chip at that position is Failed; if all test items for that chip pass, the pass status of that chip at that position is Passed. In actual applications, the second marker can be used to fill the chip at that position with green or white, while the first marker can be used to fill the chip at that position with red or black. Accordingly, by establishing an initial matching map for a historical wafer, the chips at that position are annotated with either the second marker or the first marker based on the defect measurement data of the historical wafer. Whether the defect measurement data is abnormal refers to whether the chip at that position has defect measurement data. In actual applications, if a defect in the defect measurement data, such as dust or scratches, covers two chips at that position, the defect measurement data for both chips at that position are abnormal. In the solution of this example, the first failure image and the first matching image are marked with the first mark / the second mark, which can improve the matching accuracy of the first failure image and the first matching image.

[0096] As an example, the failure module 22 is further configured to:

[0097] Detect whether there are multiple consecutive second position chips marked as the first mark in the same direction of the first position chip marked as the first mark in the initial failure map; if so, keep the first mark marking of the first position chip and the second position chip; otherwise, mark the first position chip as the second mark.

[0098] Among them, a plane rectangular coordinate system can be first established based on the initial failure map. If the first position chip marked as the first mark has at least 3 or 5 consecutive second position chips marked as the first mark in the x-axis or y-axis or diagonal direction. If so, keep the first mark marking of the first position chip and the second position chip; otherwise, mark the first position chip as the second mark. In order to improve efficiency, polling can be set for each first-marked position chip. For example, if a first-marked first position chip has been marked as the second position chip in the previous polling, the polling of the first position chip will be skipped. The solution of this example can reduce the random interference of the position chip whose test pass status is failed in the initial failure map.

[0099] As another example, the matching module 23 is specifically configured to:

[0100] An image recognition model is constructed based on a convolutional neural network, and the image recognition model is called to perform similarity matching on the first failure image and multiple first matching images in the graphic database, as well as on the second failure image and multiple second matching images in the graphic database.

[0101] In this example, the convolutional neural network constructs an image recognition model using multiple convolutional layers to extract local features of the image, and uses average or maximum pooling layers to reduce the dimensionality of the extracted features. Furthermore, by extracting the spatial structure of the image, the convolutional neural network can prevent situations where the wafer cannot be matched to the corresponding image due to angular rotation. This example solution can improve the matching accuracy between the first failure image and multiple first matching images, as well as between the second failure image and multiple second matching images.

[0102] The wafer yield map matching device provided in this embodiment includes: obtaining a wafer yield map to be matched; extracting a first failure map and a second failure map based on the wafer yield map to be matched; performing similarity matching on the first failure map and multiple first matching maps in a graphic database, and performing similarity matching on the second failure map and multiple second matching maps in the graphic database; using the first matching map with the highest similarity to the first failure map and the corresponding process information, and the second matching map with the highest similarity to the second failure map and the corresponding process information as the matching results of the wafer yield map to be matched. The method of the present application matches the wafer yield map with the graphics in the graphic database established based on the defect measurement data and process measurement data of historical wafers, which can improve the accuracy of the wafer failure analysis process.

[0103] Example 3

[0104] Figure 10 This is a schematic diagram of the structure of an electronic device provided in Example 3 of the present application, the electronic device comprising:

[0105] The electronic device includes a processor 291 and a memory 292; a communication interface 293, and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via bus 294. Communication interface 293 can be used for information transmission. The processor 291 can invoke logic instructions in memory 292 to execute the method described above.

[0106] In addition, the logic instructions in the memory 292 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0107] Memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present application. Processor 291 executes the software programs, instructions, and modules stored in memory 292 to execute functional applications and data processing, thereby implementing the methods in the above-mentioned method examples.

[0108] Memory 292 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Memory 292 may also include high-speed random access memory and non-volatile memory.

[0109] An embodiment of the present application further provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method in any embodiment.

[0110] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0111] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A wafer yield map matching method, characterized in that: include: Obtaining a wafer yield map to be matched; wherein the wafer yield map represents chip test results of chips at various positions on the wafer; Extracting a first failure map and a second failure map based on the wafer yield map to be matched; wherein the first failure map represents the test pass status of the chip at each position in the chip test result, and the second failure map represents the test value of the chip at each position in the chip test result under different test items; performing similarity matching between the first failure graph and a plurality of first matching graphs in a graphic database, and performing similarity matching between the second failure graph and a plurality of second matching graphs in the graphic database; wherein the first matching graph is established based on defect measurement data of historical wafers, and the second matching graph is established based on process measurement data of historical wafers, and the process measurement data includes at least film thickness data, critical dimension data, wafer acceptance test data, and trench depth data; The first matching graph having the highest similarity to the first failure graph and the process information corresponding to the first matching graph, as well as the second matching graph having the highest similarity to the second failure graph and the process information corresponding to the second matching graph are used as matching results of the wafer yield graph to be matched.

2. The method according to claim 1, characterized in that The second failure graph includes second failure graphs under different test items, and extracting the second failure graph according to the wafer yield graph to be matched includes: Obtaining an initial failure map of the wafer yield map to be matched; sequentially obtaining test values ​​of all chips at positions under each test item in the initial failure map, and color-coding the chips at positions in the initial failure map according to the test values ​​to obtain a second failure map under the test item; The method further comprises: Obtain the process measurement data of the chips at each position of the historical wafer and the initial matching map of the historical wafer; determine whether the number of the process measurement data of the chips at each position of the historical wafer meets the number of full map data; if so, perform color gradation marking on the position chips in the initial matching map of the historical wafer according to the process measurement data of the chips at each position of the historical wafer to obtain the second matching map; if not, end the process.

3. The method according to claim 2, characterized in that Before color-marking the position chips in the initial matching map of the historical wafer according to the process measurement data of the chips at each position of the historical wafer, the method further includes: Determining whether the process measurement data is within a preset range; According to the process measurement data of the chips at each position of the historical wafer, color-coding the chips at the position in the initial matching map of the historical wafer is performed, including: If the process measurement data is within a preset range, color-marking the position chips in the initial matching map of the historical wafer according to the process measurement data of the chips at each position of the historical wafer; After determining whether the process measurement data is within a preset range, the method further includes: If the process measurement data is not within the preset range, the process measurement data is corrected based on the process measurement data of multiple position chips adjacent to the position chip where the process measurement data is located; and the position chip in the initial matching map of the historical wafer is color-coded based on the corrected process measurement data.

4. The method according to claim 1, wherein The extracting a first failure map according to the wafer yield map to be matched includes: Obtaining an initial failure map of the wafer yield map to be matched; in the initial failure map, marking the chips at positions where the test passes as passed as a second mark, and marking the chips at positions where the test fails as a first mark, to obtain a first failure map; The method further comprises: Obtain defect measurement data of chips at various positions of the historical wafer and an initial matching map of the historical wafer; determine whether the defect measurement data of chips at various positions of the historical wafer are abnormal; if the defect measurement data of the historical wafer is abnormal, mark the position chip in the initial matching map of the historical wafer as a first mark according to the measurement data; otherwise, mark the position chip in the initial matching map of the historical wafer as a second mark according to the measurement data to obtain a first matching map.

5. The method according to claim 4, characterized in that After marking the chip at the position where the test is passed as a second mark and marking the chip at the position where the test is failed as a first mark, the method further includes: Detect whether there are multiple consecutive second position chips marked as the first mark in the same direction of the first position chip marked as the first mark in the initial failure map; if so, keep the first mark marking of the first position chip and the second position chip; otherwise, mark the first position chip as the second mark.

6. The method according to any one of claims 1 to 5, characterized in that The performing similarity matching on the first failure graph and a plurality of first matching graphs in the graph database, and the performing similarity matching on the second failure graph and a plurality of second matching graphs in the graph database, includes: An image recognition model is constructed based on a convolutional neural network, and the image recognition model is called to perform similarity matching on the first failure image and multiple first matching images in a graphic database, as well as on the second failure image and multiple second matching images in the graphic database.

7. A wafer yield map matching device, characterized in that: include: An acquisition module is used to acquire a wafer yield map to be matched; wherein the wafer yield map represents chip test results of chips at various positions on the wafer; A failure module is configured to extract a first failure map and a second failure map based on the wafer yield map to be matched; wherein the first failure map represents the test pass status of the chip at each position in the chip test result, and the second failure map represents the test value of the chip at each position in the chip test result under different test items; a matching module, configured to perform similarity matching between the first failure map and a plurality of first matching maps in a graphic database, and to perform similarity matching between the second failure map and a plurality of second matching maps in the graphic database; wherein the first matching maps are established based on defect measurement data of historical wafers, and the second matching maps are established based on process measurement data of historical wafers, wherein the process measurement data includes at least film thickness data, critical dimension data, wafer acceptance test data, and trench depth data; An output module is used to use the first matching graph with the highest similarity to the first failure graph and the process information corresponding to the first matching graph, as well as the second matching graph with the highest similarity to the second failure graph and the process information corresponding to the second matching graph, as matching results of the wafer yield graph to be matched.

8. The device according to claim 7, characterized in that The failure module is used to: Obtaining an initial failure map of the wafer yield map to be matched; sequentially obtaining test values ​​of all chips at positions under each test item in the initial failure map, and color-coding the chips at positions in the initial failure map according to the test values ​​to obtain a second failure map under the test item; The matching module is further configured to: Obtaining process measurement data of chips at each position of the historical wafer and an initial matching graph of the historical wafer; determining whether the quantity of process measurement data of chips at each position of the historical wafer meets the quantity of full graph data; If the conditions are met, the position chips in the initial matching map of the historical wafer are color-coded according to the process measurement data of the chips at each position of the historical wafer to obtain the second matching map; if the conditions are not met, the process ends.

9. An electronic device, characterized in that: include: a processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.

Images