Detection circuit for output signal of gate drive circuit and display device

Abstract

The embodiment of the invention provides a gate drive circuit output signal detection circuit and a display device, through setting a first selection control unit and a first detection unit, the first selection control unit is controlled by a first gate drive circuit output signal, if the first gate drive circuit output signal is an effective signal, the first detection unit detects that the first gate drive circuit output signal is an effective signal; the first selection control unit can send a first voltage signal connected with the first selection control unit to the first detection unit, the first detection unit judges whether a grid scanning signal is abnormal or not based on real-time detection of the first voltage signal, and the grid scanning signal is abnormal due to the fact that the first detection unit receives the first voltage signal. The first voltage signal is not provided by the output end of the gate drive circuit, so that the load of the GOA is not increased, the output of the gate drive circuit is not interfered, and the detection result of the detection unit is more accurate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a detection circuit for output signals of a gate drive circuit and a display device. Background Art

[0002] To reduce display device manufacturing costs and achieve narrow bezels, gate driver on array (GOA) technology is increasingly being used in display device manufacturing. The GOA circuit outputs corresponding gate scan signals. The proper functioning of each gate scan signal directly impacts the display performance of the display device. If a problem occurs with the gate scan signal output by a GOA at a particular stage, display anomalies may occur.

[0003] Since all GOA circuits are integrated inside the panel, it is impossible to obtain the gate scan signal waveform on each gate line from the outside, which is very unfavorable for later analysis of product problems. Therefore, it is very necessary to detect the gate scan signal.

[0004] Therefore, how to detect the gate scanning signal has become a problem that needs to be solved urgently. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a detection circuit and a display device for a gate drive circuit output signal. The specific technical solution is as follows:

[0006] An embodiment of the present application provides a detection circuit for a gate drive circuit output signal, comprising:

[0007] At least one detection group, each detection group includes at least one selection control unit and a detection unit, each detection group corresponds to a gate drive circuit group, each gate drive circuit group includes at least one gate drive circuit, and one gate drive circuit corresponds to one selection control unit;

[0008] A control end of a first selection control unit is connected to an output end of a first gate drive circuit, a first end of the first selection control unit is connected to a first detection unit, and a second end of the first selection control unit is connected to a first voltage signal; wherein the first selection control unit is a selection control unit in the detection group, the first gate drive circuit is a first gate drive circuit corresponding to the first selection control unit, and the first detection unit is a detection unit in the detection group to which the first selection control unit belongs;

[0009] The first selection control unit is configured to send the first voltage signal to the first detection unit when the first gate driving circuit outputs a valid signal;

[0010] The first detection unit is configured to determine whether there is a gate driving circuit with an abnormal output signal in the corresponding gate driving circuit group based on the received first voltage signal.

[0011] In a possible implementation, the gate driving circuits located in odd-numbered rows form a gate driving circuit group, and the gate driving circuits located in even-numbered rows form a gate driving circuit group.

[0012] In a possible implementation, the first voltage signal connected to the second end of the first selection control unit of the same detection group is the same signal.

[0013] In a possible implementation, the selection control unit includes a transistor;

[0014] The control end of the transistor is connected to the output end of the first gate driving circuit, the first end of the transistor is connected to the first detection unit, and the second end of the transistor is connected to the first voltage signal.

[0015] In a possible implementation, the first detection unit is configured to:

[0016] Collect the number of high-level signals and low-level signals in one cycle;

[0017] and obtaining a preset first quantity and a second quantity, wherein the first quantity is the number of high-level signals when the gate drive circuits in a group of gate drive circuit groups output signals that are normal, and the second quantity is the number of low-level signals when the gate drive circuits in the group of gate drive circuit groups output signals that are normal;

[0018] When the number of the high-level signals is not the first number and / or the number of the low-level signals is not the second number, it is determined that a gate driving circuit having an abnormal output signal exists in the gate driving circuit group.

[0019] In a possible implementation, the first detection unit is configured to:

[0020] Generating a waveform diagram of the received first voltage signal to obtain a first waveform diagram;

[0021] The first waveform diagram is matched with each waveform diagram in a preset waveform diagram set. If the matched waveform diagram is a normal waveform diagram, it is determined that there is no gate drive circuit with an abnormal output signal in the gate drive circuit group. If the matched waveform diagram is an abnormal waveform diagram, it is determined that there is a gate drive circuit with an abnormal output signal in the gate drive circuit group.

[0022] In a possible implementation, the first detection unit includes a first resistor, a second resistor, a first operational amplifier, a third resistor, a fourth resistor, a fifth resistor, a second operational amplifier, a sixth resistor, an analog-to-digital collector, and a control unit;

[0023] The first end of the first selection control unit is connected to the first end of the first resistor, and the second end of the first resistor is connected to the first end of the second resistor and the inverting input end of the first operational amplifier;

[0024] The positive input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier and the first terminal of the third resistor;

[0025] The second end of the third resistor is connected to the first end of the fourth resistor and the positive input end of the second operational amplifier;

[0026] The second end of the fourth resistor is grounded;

[0027] The inverting input terminal of the second operational amplifier is connected to the second terminal of the fifth resistor and the first terminal of the sixth resistor;

[0028] The first end of the fifth resistor is connected to the first reference voltage;

[0029] The second end of the sixth resistor and the output end of the second operational amplifier are connected to the input end of the analog-to-digital collector;

[0030] The output end of the analog-to-digital collector is connected to the control unit.

[0031] In a possible implementation, the first detection unit further includes a third operational amplifier and a fourth operational amplifier;

[0032] The third operational amplifier and the fourth operational amplifier are arranged between the second operational amplifier and the analog-to-digital collector;

[0033] The second end of the sixth resistor and the output end of the second operational amplifier are connected to the positive input end of the third operational amplifier and the positive input end of the fourth operational amplifier;

[0034] The inverting input terminal of the third operational amplifier is connected to a first voltage; the inverting input terminal of the fourth operational amplifier is connected to a second voltage; the first voltage is greater than the second voltage;

[0035] The output end of the third operational amplifier and the output end of the fourth operational amplifier are connected to the input end of the analog-to-digital collector.

[0036] An embodiment of the present application further provides a display device, comprising any of the above-mentioned detection circuits.

[0037] In a possible implementation, the display device includes a first printed circuit board and a second printed circuit board;

[0038] The gate driving circuit and the selection control unit are arranged on the first printed circuit board, and the detection unit is arranged on the second printed circuit board.

[0039] Beneficial effects of the embodiments of the present application:

[0040] The detection circuit and display device of the gate drive circuit output signal provided in the embodiments of the present application are configured by setting a first selection control unit and a first detection unit. The first selection control unit is under the control of the first gate drive circuit output signal. If the first gate drive circuit output signal is a valid signal, the first selection control unit can send the first voltage signal connected to it to the first detection unit. The first inspection unit determines whether the gate scan signal is abnormal based on real-time detection of the first voltage signal. Moreover, because the first inspection unit receives the first voltage signal, the first voltage signal is not provided by the output end of the gate drive circuit. This does not increase the load of the GOA and does not interfere with the output of the gate drive circuit, making the detection result of the detection unit more accurate.

[0041] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0043] Figure 1 A schematic diagram of a first structural example of a detection circuit for a gate drive circuit output signal provided in an embodiment of the present application;

[0044] Figure 2 A second structural diagram of a detection circuit for a gate drive circuit output signal provided in an embodiment of the present application;

[0045] Figure 3 A third structural diagram of a detection circuit for a gate drive circuit output signal provided in an embodiment of the present application;

[0046] Figure 4-1 A schematic diagram of a first structure of a detection unit of a detection circuit for detecting a gate drive circuit output signal provided in an embodiment of the present application;

[0047] Figure 4-2 A second structural diagram of a detection unit of a detection circuit for detecting a gate drive circuit output signal provided in an embodiment of the present application;

[0048] Figure 5 A schematic diagram of waveform diagrams under different situations provided in the embodiments of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0050] An embodiment of the present application provides a detection circuit for a gate drive circuit output signal, comprising:

[0051] At least one detection group, each detection group includes at least one selection control unit and a detection unit, each detection group corresponds to a gate drive circuit group, each gate drive circuit group includes at least one gate drive circuit, and one gate drive circuit corresponds to one selection control unit;

[0052] A control end of a first selection control unit is connected to an output end of a first gate drive circuit, a first end of the first selection control unit is connected to a first detection unit, and a second end of the first selection control unit is connected to a first voltage signal; wherein the first selection control unit is a selection control unit in the detection group, the first gate drive circuit is a first gate drive circuit corresponding to the first selection control unit, and the first detection unit is a detection unit in the detection group to which the first selection control unit belongs;

[0053] The first selection control unit is configured to send the first voltage signal to the first detection unit when the first gate driving circuit outputs a valid signal;

[0054] The first detection unit is configured to determine whether there is a gate driving circuit with an abnormal output signal in the corresponding gate driving circuit group based on the received first voltage signal.

[0055] like Figure 1 As shown, two detection groups are included. One detection group includes multiple selection control units, such as the first group including the first selection control unit 11, the first selection control unit 12, ..., the first selection control unit 1n, and the second group including the first selection control unit 21, the first selection control unit 22, ..., the first selection control unit 2m. Here, m and n can be equal or unequal, and can be determined based on actual conditions.

[0056] The control terminal of each first selection control unit is connected to a corresponding first gate drive circuit. For example, the control terminal of the first selection control unit 11 is connected to the output terminal of the first gate drive circuit 11, the control terminal of the first selection control unit 12 is connected to the output terminal of the first gate drive circuit 12, and the control terminal of the first selection control unit 1n is connected to the output terminal of the first gate drive circuit 1n. The control terminal of the first selection control unit 21 is connected to the output terminal of the first gate drive circuit 21, the control terminal of the first selection control unit 22 is connected to the output terminal of the first gate drive circuit 22, and the control terminal of the first selection control unit 2m is connected to the output terminal of the first gate drive circuit 2m.

[0057] The first end of each first selection control unit is connected to the first detection unit. For example, the first end of the first selection control units of the first group is connected to the first detection unit 1, and the first end of the first selection control units of the second group is connected to the first detection unit 2.

[0058] The second end of the first selection control unit is connected to a first voltage signal (not shown). The first voltage signal is a stable voltage. The voltage of the first voltage signal can be determined based on actual conditions and is not limited here. For example, the voltage of the first voltage signal is 5V.

[0059] The first selection control unit may be composed of a power switch. For example, the first selection control unit includes a TFT (Thin Film Transistor). The first voltage signal connected to the second end of the first selection control unit may be the same or different.

[0060] Because the control end of the first selection control unit is connected to the output end of the first gate drive circuit, when the output end of the first gate drive circuit outputs a scan signal, the first selection control unit is closed. Because the first end of the first selection control unit is connected to the first detection unit, the second end of the first selection control unit is connected to the first voltage signal. After closing, the first voltage signal is sent to the first detection unit through the first selection control unit.

[0061] Because the gate drive circuit scans row by row, if the signal output by the gate drive circuit is normal, the first detection unit will only receive the first voltage signal when the first selection control unit is closed. Therefore, for each detection group, the detection unit can only receive the first voltage signal sent by at most one first selection control unit.

[0062] For each detection group, if the signals output by each first gate drive circuit are normal, the signals received by the detection unit are regular within a scanning cycle. For example, there are two detection groups in total, the gate drive circuits corresponding to one detection group are the gate drive circuits of odd rows, and the gate drive circuits corresponding to the other detection group are the gate drive circuits of even rows, and the signals received by the detection unit are regular square wave signals. For another example, there are two detection groups in total,

[0063] One detection group corresponds to gate drive circuits in the first predetermined number of rows, while another detection group corresponds to gate drive circuits in the remaining rows. The signals received by the detection units in each group are continuous. The first detection unit is configured to determine, based on the received first voltage signal, whether any gate drive circuit in the corresponding gate drive circuit group has an abnormal output signal.

[0064] By setting a first selection control unit and a first detection unit, the first selection control unit is under the control of the output signal of the first gate drive circuit. If the output signal of the first gate drive circuit is a valid signal, the first selection control unit can send the first voltage signal connected thereto to the first detection unit. The first inspection unit determines whether the gate scan signal is abnormal based on real-time detection of the first voltage signal. Moreover, because the first inspection unit receives the first voltage signal, the first voltage signal is not provided by the output end of the gate drive circuit. This does not increase the load of the GOA and does not interfere with the output of the gate drive circuit, so that the detection result of the detection unit is more accurate.

[0065] In a possible implementation, the gate driving circuits located in odd-numbered rows form a gate driving circuit group, and the gate driving circuits located in even-numbered rows form a gate driving circuit group.

[0066] The gate drive circuits can be divided into two groups according to the number of rows they are in, such as Figure 2 As shown, 2N rows of gate drive circuits (GOA1-GOA2N) are included, corresponding to 2N first selection control units (first selection control unit 1-first selection control unit 2N). The gate drive circuits located in odd rows are a group, and the gate drive circuits located in even rows are a group. The detection unit corresponding to the detection group where the gate drive circuits located in odd rows are located is the first detection unit 1, and the detection unit corresponding to the detection group where the gate drive circuits located in even rows are located is the first detection unit 2. Because the gate drive circuits are scanned row by row, adjacent gate drive circuits are not a group, which can avoid signal overlap, thereby generating an obvious periodic waveform, and improving the accuracy of detection.

[0067] In a possible implementation, the first voltage signal connected to the second end of the first selection control unit of the same detection group is the same signal.

[0068] The second ends of the first selection control units of the same detection group are connected to the same signal, that is, the second ends of the first selection control units of the same detection group share a first voltage signal, so that there is no need to generate too many first voltage signals, which can save resources.

[0069] In a possible implementation, the selection control unit includes a transistor;

[0070] The control end of the transistor is connected to the output end of the first gate driving circuit, the first end of the transistor is connected to the first detection unit, and the second end of the transistor is connected to the first voltage signal.

[0071] The transistor can be an N-type transistor or a MOS transistor, and the corresponding transistor can be selected according to actual conditions.

[0072] based on Figure 2 In the embodiment shown, an example is Figure 3 As shown, the selection control unit includes a transistor. The control terminal of the transistor is connected to the output terminal of the GOA, the first terminal of the transistor is connected to the first detection unit, and the second terminal of the transistor is connected to the first voltage signal. The second terminal of the first selection control unit of the same detection group is connected to the same signal, that is, the control terminal of the transistor is controlled by the output terminal of the GOA, the first terminals of the transistors in the same group are connected together, and the first terminals of the transistors in the same group are also connected together. When the detection unit is disposed on a PCB and the access terminal for the first voltage signal is on the PCB, the first terminals of the transistors in the same group are connected together, and the first terminals of the transistors in the same group are also connected together and led out to the PCB.

[0073] The gate drive circuits can be divided into two groups according to the number of rows they are in, such as Figure 3 As shown, 2N rows of gate drive circuits (GOA1-GOA2N) are included, corresponding to 2N TFTs, the gate drive circuits located in odd rows are a group, and the gate drive circuits located in even rows are a group, the detection unit corresponding to the detection group where the gate drive circuits located in odd rows are located is the first detection unit 1, and the detection unit corresponding to the detection group where the gate drive circuits located in even rows are located is the first detection unit 2, the first voltage signal shared by the second end of the first selection control unit of the detection group where the gate drive circuits located in odd rows are located is the first voltage signal 1, and the first voltage signal shared by the second end of the first selection control unit of the detection group where the gate drive circuits located in even rows are located is the first voltage signal 2.

[0074] The second ends of the first selection control units of the same detection group share one first voltage signal, so there is no need to generate too many first voltage signals, which can save resources.

[0075] In a possible implementation, the first detection unit is configured to:

[0076] Collect the number of high-level signals and low-level signals in one cycle;

[0077] and obtaining a preset first quantity and a second quantity, wherein the first quantity is the number of high-level signals when the gate drive circuits in a group of gate drive circuit groups output signals that are normal, and the second quantity is the number of low-level signals when the gate drive circuits in the group of gate drive circuit groups output signals that are normal;

[0078] When the number of the high-level signals is not the first number and / or the number of the low-level signals is not the second number, it is determined that a gate driving circuit having an abnormal output signal exists in the gate driving circuit group.

[0079] The preset first and second quantities are set based on the grouping situation and are specifically determined based on actual conditions. Because the gate drive circuits scan row by row, the gate drive circuits in a group of gate drive circuit groups sequentially output valid signals. When the first gate drive circuit outputs a valid signal, the first voltage signal forms a path with the first detection unit, that is, the first detection unit can obtain the first voltage signal. Because the gate drive circuits scan row by row, the first detection unit can sequentially obtain the first voltage signal. When the gate drive circuit output signals in each gate drive circuit group are normal, there may be a corresponding number of high-level signals and a corresponding number of low-level signals.

[0080] The first detection unit matches the number of high-level signals and the number of low-level signals collected within a cycle with a preset first number and second number, and determines that there is a gate drive circuit with an abnormal output signal in the gate drive circuit group when the number of high-level signals is not the first number and / or the number of low-level signals is not the second number.

[0081] Taking the gate drive circuits located in odd rows as a gate drive circuit group as an example, a gate drive circuit group includes 2 gate drive circuits. When the two voltages collected within a cycle (such as 4 rows of time) have the same time and are high and low, it indicates normal. When the two collected voltages are always different or there is no high-level signal or no low-level signal, it indicates abnormality.

[0082] In a possible embodiment, the first detection unit is used to obtain multiple preset high and low level number groups, wherein the multiple preset high and low level number groups correspond to the high level number and the low level number in different situations respectively; the multiple preset high and low level number groups include: the high level number and the low level number under normal circumstances, the high level number and the low level number when a row of gates cannot be closed, the high level number and the low level number when a row of gates cannot be opened, the high level number and the low level number when a row of gates are not closed tightly, the high level number and the low level number when DGS (short circuit between the power line and the data line) is bad, etc.

[0083] Based on the number of rows of the corresponding gate drive circuits in the detection group, it can be known in advance that when the output signal of the gate drive circuit in each gate drive circuit group is normal, there are corresponding numbers of high-level signals and low-level signals, as well as the corresponding numbers of high-level signals and low-level signals when various abnormal situations occur. The abnormal situations include: the gate of a certain row cannot be closed, the gate of a certain row cannot be opened, the gate of a certain row is not closed tightly, and the DGS (short circuit between the power line and the data line) is bad; a certain row represents one or more rows.

[0084] For example, for the 4 rows of gate drive circuits corresponding to 1 detection group, the abnormal conditions include: the gate of 1 row of gate drive circuit cannot be closed, the gate of 2 rows of gate drive circuit cannot be closed, the gate of 3 rows of gate drive circuit cannot be closed, the gate of 4 rows of gate drive circuit cannot be closed, the gate of 1 row of gate drive circuit cannot be opened, the gate of 2 rows of gate drive circuit cannot be opened, the gate of 3 rows of gate drive circuit cannot be opened, the gate of 4 rows of gate drive circuit cannot be opened, the gate of 1 row of gate drive circuit is not closed tightly, the gate of 2 rows of gate drive circuit is not closed tightly, the gate of 3 rows of gate drive circuit is not closed tightly, and the gate of 4 rows of gate drive circuit is not closed tightly.

[0085] Each abnormal situation corresponds to a number of high-level signals and a number of low-level signals. The number of high-level signals and the number of low-level signals collected within a cycle are matched with the number of high-level signals and the number of low-level signals in each preset high- and low-level number group. If the number of high-level signals and the number of low-level signals are matched successfully, the situation corresponding to the preset high- and low-level number group is determined to be the situation of the gate drive circuit. This solution can accurately determine whether the output signal of the gate drive circuit is normal, and if the output signal of the gate drive circuit is abnormal, the reason for the abnormality.

[0086] In a possible implementation, the first detection unit is configured to:

[0087] Generating a waveform diagram of the received first voltage signal to obtain a first waveform diagram;

[0088] The first waveform diagram is matched with each waveform diagram in a preset waveform diagram set. If the matched waveform diagram is a normal waveform diagram, it is determined that there is no gate drive circuit with an abnormal output signal in the gate drive circuit group. If the matched waveform diagram is an abnormal waveform diagram, it is determined that there is a gate drive circuit with an abnormal output signal in the gate drive circuit group.

[0089] The first detection unit can also generate a waveform diagram for the received first voltage signal to obtain a first waveform diagram, and then match the first waveform diagram with each waveform diagram in a preset waveform diagram set. If the matched waveform diagram is a normal waveform diagram, it is determined that there is no gate drive circuit with an abnormal output signal in the gate drive circuit group. If the matched waveform diagram is an abnormal waveform diagram, it is determined that there is a gate drive circuit with an abnormal output signal in the gate drive circuit group.

[0090] like Figure 5 The waveform shown in the figure, Figure 5 The waveforms under different conditions are shown when the gate drive circuits located in odd-numbered rows are grouped as one gate drive circuit group and the gate drive circuits located in even-numbered rows are grouped as one gate drive circuit group. Figure 5 The waveform diagram includes a normal waveform diagram, a waveform diagram in which a gate of a certain row cannot be closed, a waveform diagram in which a gate of a certain row cannot be opened, a waveform diagram in which a gate of a certain row is not tightly closed, a waveform diagram of a DGS-like (short circuit phenomenon occurs between the power line and the data line) poor waveform diagram, and a waveform diagram of a local GOA abnormality. The first waveform diagram is matched with each waveform diagram in the preset waveform diagram set. Based on the matching result, it can be determined whether there is a gate drive circuit with an abnormal output signal in the gate drive circuit group.

[0091] In a possible embodiment, the first detection unit is used to obtain multiple preset waveform groups, wherein the multiple preset waveform groups correspond to waveforms under different situations; the multiple preset waveform groups include: a waveform under normal circumstances, a waveform when a row of gates cannot be closed, a waveform when a row of gates cannot be opened, a waveform when a row of gates cannot be closed, a waveform under DGS (short circuit between the power line and the data line) poor conditions, etc.

[0092] The waveforms collected within a cycle are matched with the waveforms in each preset high and low level group. If a match is successful, the situation corresponding to the preset waveform group is determined to be the situation of the gate drive circuit. This solution can accurately determine whether the output signal of the gate drive circuit is normal, and if the output signal of the gate drive circuit is abnormal, the reason for the abnormality.

[0093] In a possible implementation, the first detection unit includes a first resistor, a second resistor, a first operational amplifier, a third resistor, a fourth resistor, a fifth resistor, a second operational amplifier, a sixth resistor, an analog-to-digital collector, and a control unit;

[0094] The first end of the first selection control unit is connected to the first end of the first resistor, and the second end of the first resistor is connected to the first end of the second resistor and the inverting input end of the first operational amplifier;

[0095] The positive input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier and the first terminal of the third resistor;

[0096] The second end of the third resistor is connected to the first end of the fourth resistor and the positive input end of the second operational amplifier;

[0097] The second end of the fourth resistor is grounded;

[0098] The inverting input terminal of the second operational amplifier is connected to the second terminal of the fifth resistor and the first terminal of the sixth resistor;

[0099] The first end of the fifth resistor is connected to the first reference voltage;

[0100] The second end of the sixth resistor and the output end of the second operational amplifier are connected to the input end of the analog-to-digital collector;

[0101] The output end of the analog-to-digital collector is connected to the control unit.

[0102] The size of the first reference voltage can be determined based on actual conditions. For example, when the VCOM (common electrode) voltage is interfered with by the TP (touch) drive signal, the first reference voltage is introduced here to the input VCOM voltage. By connecting the first reference voltage to the VCOM voltage, the interference of the TP drive signal can be eliminated, making the detection more accurate.

[0103] like Figure 4-1 As shown, the first resistor is R1, the second resistor is R2, the first operational amplifier OP1, the third resistor is R3, the fourth resistor is R4, the fifth resistor is R5, the second operational amplifier OP2, and the sixth resistor is R6. GND is the ground line. The power lines of each operational amplifier in the figure are shown.

[0104] The first voltage signal is connected to the first selection control unit. During normal operation, due to the opening and closing of the first gate drive circuit, the voltage is output through the first resistor and the second resistor of the rear-end matching resistor. The voltage is processed by the first amplifier follower circuit to stabilize the voltage, and then passes through a differential circuit to eliminate signal interference.

[0105] For example, assuming the voltage of the input first voltage signal is 5V, according to the detection unit and matching resistors, during normal operation, the voltage matched by R1 and R2 is a square wave with a maximum voltage of 3V and a minimum voltage of 0V; when the VCOM voltage is interfered with by the TP drive signal, the first reference voltage is introduced here to the input VCOM voltage. Accessing the VCOM voltage by the first reference voltage can eliminate the interference of the TP drive signal, making the detection more accurate.

[0106] In a possible implementation, the first detection unit further includes a third operational amplifier and a fourth operational amplifier;

[0107] The third operational amplifier and the fourth operational amplifier are arranged between the second operational amplifier and the analog-to-digital collector;

[0108] The second end of the sixth resistor and the output end of the second operational amplifier are connected to the positive input end of the third operational amplifier and the positive input end of the fourth operational amplifier;

[0109] The inverting input terminal of the third operational amplifier is connected to a first voltage; the inverting input terminal of the fourth operational amplifier is connected to a second voltage; the first voltage is greater than the second voltage;

[0110] The output end of the third operational amplifier and the output end of the fourth operational amplifier are connected to the input end of the analog-to-digital collector.

[0111] based on Figure 4-1 The embodiment shown, as Figure 4-2 The first detection unit further includes a third operational amplifier OP3 and a fourth operational amplifier OP4. The power supply lines of the operational amplifiers are shown in FIG.

[0112] The third operational amplifier and the fourth operational amplifier are two operational amplifiers connected in parallel. Because of the amplification setting of the operational amplifier, the output voltage is either high or low. The algorithm is simple. After setting the first voltage and the second voltage, the level of the received signal can be determined.

[0113] The third and fourth operational amplifiers can better determine the voltage level. For example, the first voltage can be 2.8V and the second voltage can be 0.2V. Because the highest voltage is 3V and the lowest voltage is 0V, the output will be high and low. However, when the GOA is abnormal, the matched voltage may always be 3V, 0V or 2.5V, and the output will be different from the normal value.

[0114] After the third operational amplifier and the fourth operational amplifier, an analog-to-digital collector is connected. The analog-to-digital collector sends the signal to the control unit. The control unit determines the start of the cycle through signals such as HS (Horizontal Sync, line synchronization signal), VS (Vertical Sync, field synchronization signal), and TP EN (Touch Panel Enable, touch screen enable signal). After determining that normal operation has begun, the number of high and low levels within the acquisition cycle can be set to M for high levels and N for low levels. A preset first number and a second number are obtained, wherein the first number is the number of high-level signals when the output signals of the gate drive circuits in a group of gate drive circuits are normal, and the second number is the number of low-level signals when the output signals of the gate drive circuits in the group of gate drive circuits are normal. When the number of high-level signals is not the first number and / or the number of low-level signals is not the second number, it is determined that there is a gate drive circuit in the gate drive circuit group with an abnormal output signal.

[0115] An embodiment of the present application further provides a display device, comprising any of the above-mentioned detection circuits.

[0116] In a possible implementation, the display device includes a first printed circuit board and a second printed circuit board;

[0117] The gate driving circuit and the selection control unit are arranged on the first printed circuit board, and the detection unit is arranged on the second printed circuit board.

[0118] The first printed circuit board and the second printed circuit board can be the same printed circuit board or different printed circuit boards, which is determined based on actual conditions.

[0119] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0120] Each embodiment in this specification is described in a related manner. Similar parts between the embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, since the embodiments are generally similar to the method embodiments, the description is relatively simple. For related parts, refer to the description of the method embodiments.

[0121] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A detection circuit for a gate drive circuit output signal, characterized in that: include: At least one detection group, each detection group includes at least one selection control unit and a detection unit, each detection group corresponds to a gate drive circuit group, each gate drive circuit group includes at least one gate drive circuit, and one gate drive circuit corresponds to one selection control unit; A control end of a first selection control unit is connected to an output end of a first gate drive circuit, a first end of the first selection control unit is connected to a first detection unit, and a second end of the first selection control unit is connected to a first voltage signal; wherein the first selection control unit is a selection control unit in the detection group, the first gate drive circuit is a first gate drive circuit corresponding to the first selection control unit, and the first detection unit is a detection unit in the detection group to which the first selection control unit belongs; The first selection control unit is configured to send the first voltage signal to the first detection unit when the first gate driving circuit outputs a valid signal; The first detection unit is configured to determine whether there is a gate driving circuit with an abnormal output signal in the corresponding gate driving circuit group based on the received first voltage signal.

2. The detection circuit according to claim 1, characterized in that The gate driving circuits located in odd-numbered rows are a gate driving circuit group, and the gate driving circuits located in even-numbered rows are a gate driving circuit group.

3. The detection circuit according to claim 1, characterized in that: The first voltage signal connected to the second end of the first selection control unit of the same detection group is the same signal.

4. The detection circuit according to claim 1, characterized in that: The selection control unit includes a transistor; The control end of the transistor is connected to the output end of the first gate driving circuit, the first end of the transistor is connected to the first detection unit, and the second end of the transistor is connected to the first voltage signal.

5. The detection circuit according to claim 1, wherein: The first detection unit is used for: Collect the number of high-level signals and low-level signals in one cycle; and obtaining a preset first quantity and a second quantity, wherein the first quantity is the number of high-level signals when the gate drive circuits in a group of gate drive circuit groups output signals that are normal, and the second quantity is the number of low-level signals when the gate drive circuits in the group of gate drive circuit groups output signals that are normal; When the number of the high-level signals is not the first number and / or the number of the low-level signals is not the second number, it is determined that a gate driving circuit having an abnormal output signal exists in the gate driving circuit group.

6. The detection circuit according to claim 1, characterized in that: The first detection unit is used for: Generating a waveform diagram of the received first voltage signal to obtain a first waveform diagram; The first waveform diagram is matched with each waveform diagram in a preset waveform diagram set. If the matched waveform diagram is a normal waveform diagram, it is determined that there is no gate drive circuit with an abnormal output signal in the gate drive circuit group. If the matched waveform diagram is an abnormal waveform diagram, it is determined that there is a gate drive circuit with an abnormal output signal in the gate drive circuit group.

7. The detection circuit according to claim 1, characterized in that: The first detection unit includes a first resistor, a second resistor, a first operational amplifier, a third resistor, a fourth resistor, a fifth resistor, a second operational amplifier, a sixth resistor, an analog-to-digital collector, and a control unit; The first end of the first selection control unit is connected to the first end of the first resistor, and the second end of the first resistor is connected to the first end of the second resistor and the inverting input end of the first operational amplifier; The positive input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier and the first terminal of the third resistor; The second end of the third resistor is connected to the first end of the fourth resistor and the positive input end of the second operational amplifier; The second end of the fourth resistor is grounded; The inverting input terminal of the second operational amplifier is connected to the second terminal of the fifth resistor and the first terminal of the sixth resistor; The first end of the fifth resistor is connected to the first reference voltage; The second end of the sixth resistor and the output end of the second operational amplifier are connected to the input end of the analog-to-digital collector; The output end of the analog-to-digital collector is connected to the control unit.

8. The detection circuit according to claim 7, characterized in that: The first detection unit further includes a third operational amplifier and a fourth operational amplifier; The third operational amplifier and the fourth operational amplifier are arranged between the second operational amplifier and the analog-to-digital collector; The second end of the sixth resistor and the output end of the second operational amplifier are connected to the positive input end of the third operational amplifier and the positive input end of the fourth operational amplifier; The inverting input terminal of the third operational amplifier is connected to a first voltage; the inverting input terminal of the fourth operational amplifier is connected to a second voltage; the first voltage is greater than the second voltage; The output end of the third operational amplifier and the output end of the fourth operational amplifier are connected to the input end of the analog-to-digital collector.

9. A display device, characterized in that: The invention comprises the detection circuit described in any one of claims 1 to 8.

10. The display device according to claim 9, wherein The display device includes a first printed circuit board and a second printed circuit board; The gate driving circuit and the selection control unit are arranged on the first printed circuit board, and the detection unit is arranged on the second printed circuit board.

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