Memory device and method of operating memory device

Abstract

The invention provides a memory device and a method of operating the memory device. The memory device includes: a memory block including a plurality of memory cells; a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation; a page buffer group configured to apply an erase voltage to a bit line of the memory block during an erase operation; a voltage generation circuit configured to generate a select line voltage applied to a select line of the memory block during an erase operation; and a control logic configured to control the source line driver, the page buffer group, and the voltage generation circuit to perform a pause operation in response to a pause command, the pause operation including a pause erase operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0035646 filed on March 14, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to an electronic device, including but not limited to a memory device and a method of operating the memory device. Background Art

[0004] Among semiconductor devices, memory devices are roughly divided into volatile memory devices and nonvolatile memory devices.

[0005] Non-volatile memory devices have relatively slow write and read speeds, but they retain stored data even when power to the device is interrupted. Therefore, non-volatile memory devices are used to store data that must be retained regardless of power supply. Representative examples of non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is categorized into NOR and NAND types.

[0006] Flash memory combines the advantages of RAM (data can be freely programmed and erased) with the advantage of ROM (data retention), even when power is lost. This type of flash memory is widely used as a storage medium in portable electronic devices such as digital cameras, personal digital assistants (PDAs), and MP3 players. Summary of the Invention

[0007] Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory block including a plurality of memory cells; a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation; a page buffer group configured to apply an erase voltage to a bit line of the memory block during an erase operation; a voltage generation circuit configured to generate a select line voltage applied to a select line of the memory block during an erase operation; and control logic configured to control the source line driver, the page buffer group, and the voltage generation circuit to perform a pause operation in response to a pause command, the pause operation including pausing an erase operation, wherein the control logic is configured to control the voltage generation circuit so that during a rising period in which the erase voltage increases toward a target voltage level in the erase operation, a difference between the erase voltage and the select line voltage is maintained at a first voltage difference, and during a pulse application period in which the erase voltage at the target voltage level is applied, a difference between the erase voltage and the select line voltage is maintained at a second voltage difference, the second voltage difference being greater than the first voltage difference.

[0008] Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory block including a plurality of memory cells; a peripheral circuit configured to apply an erase voltage to a source line or a bit line of the memory block and apply a select line voltage to a select line of the memory block during an erase operation; and control logic configured to control the peripheral circuit to perform a suspend operation in response to receiving a suspend command and to control the peripheral circuit to perform a resume operation in response to receiving a resume command, wherein the suspend operation includes suspending an erase operation and the resume operation includes resuming the suspended erase operation, wherein the control logic is configured to, when the suspend command is received during a pulse application period of applying an erase voltage of a target voltage level in the erase operation, reset the select line voltage during the resume operation by lowering the select line voltage used during the resume pulse application period of the resumed erase operation.

[0009] Embodiments of the present disclosure may provide a method for operating a memory device. The method may include: applying an erase voltage increasing toward a target voltage level to a source line or a bit line of a memory block during a rising period of an erase operation; applying a select line voltage lower than the erase voltage by a first voltage difference to a select line of the memory block during the rising period; pausing the erase operation in response to receiving a pause command during the rising period, and resuming the erase operation in response to receiving a resume command; applying an erase voltage of a target voltage level during a pulse application period of the erase operation after the rising period ends; and applying a select line voltage lower than the erase voltage by a second voltage difference during the pulse application period, wherein the second voltage difference is greater than the first voltage difference.

[0010] Embodiments of the present disclosure may provide a method for operating a memory device. The method may include: applying an erase voltage increasing toward a target voltage level to a source line or a bit line of a memory block during a rising period of an erase operation; applying a select line voltage lower than the erase voltage by a first voltage difference to a select line of the memory block during the rising period; applying an erase voltage of the target voltage level during a pulse application period of the erase operation after the rising period ends; and suspending the erase operation in response to receiving a pause command during the pulse application period, and resuming the erase operation in response to receiving a resume command, wherein the resumed erase operation includes applying the select line voltage during a second rising period and applying the erase voltage of the target voltage level during a resume pulse application period, and the select line voltage during the resume pulse application period is lower by a voltage difference than the select line voltage used during the previous pulse application period.

[0011] An embodiment of the present disclosure includes a method, which may include: applying an increased erase voltage to a memory block during a first rising period of an erase operation, and applying a selection line voltage that is lower than the erase voltage by a first voltage difference to a selection line of the memory block; applying an erase voltage of a constant voltage level during a pulse application period of the erase operation, and pausing the erase operation in response to receiving a pause command; and resuming the erase operation in response to receiving a resume command by applying the selection line voltage during a second rising period and applying the erase voltage of a constant voltage level during a resume pulse application period; wherein the selection line voltage during the resume pulse application period is lower by a voltage difference than the selection line voltage used during the previous pulse application period. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0014] Figure 3 is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0015] Figure 4 is a diagram illustrating an embodiment of a memory block having a three-dimensional (3D) structure.

[0016] Figure 5 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0017] Figure 6 and Figure 7 is a timing diagram illustrating an erase voltage and a select line voltage during an erase operation of a memory device according to an embodiment of the present disclosure.

[0018] Figure 8 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0019] Figure 9 is a timing diagram illustrating an erase voltage and a select line voltage during an erase operation of a memory device according to an embodiment of the present disclosure.

[0020] Figure 10 is a diagram illustrating an embodiment of a memory system including a memory device.

[0021] Figure 11 is a diagram illustrating an embodiment of a memory system including a memory device.

[0022] Figure 12 is a diagram illustrating an embodiment of a memory system including a memory device. DETAILED DESCRIPTION

[0023] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or this application are provided as examples to describe the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in the specification or application.

[0024] A nonvolatile memory device performs an erase operation, which includes erasing stored data. The erase operation may take a relatively long time to complete compared to other typical operations, such as a program operation or a read operation. When a command corresponding to a program operation or a read operation is received during the erase operation, the program operation or the read operation is performed after the erase operation is temporarily suspended. The suspended erase operation is resumed after the program operation or the read operation is completed.

[0025] Various embodiments of the present disclosure relate to a memory device capable of suppressing a change in a threshold voltage of a selection transistor due to a pause operation during an erase operation of the memory device, and a method of operating the memory device.

[0026] The present disclosure will be described in detail by describing one or more embodiments of the present disclosure with reference to the accompanying drawings. One or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Terms such as "vertical," "horizontal," "above," "below," "above," "column," "row," "horizontal," and other terms that suggest relative spatial relationships or directions are used only for the purpose of facilitating description or reference to the accompanying drawings and are not intended to be limiting.

[0027] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0028] Reference Figure 1, under the control of a host 2000 , the memory system 1000 includes a memory device 1100 that stores data and a memory controller 1200 that controls the memory device 1100 .

[0029] The host 2000 can communicate with the memory system 1000 using an interface protocol such as Peripheral Component Interconnect Express (PCIE), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). Furthermore, the interface protocol between the host 2000 and the memory system 1000 is not limited to the above examples and may be one of various other interface protocols such as Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0030] The memory controller 1200 controls the overall operation of the memory system 1000 and controls data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 controls the memory device 1100 to program, read, or erase data in response to a request received from the host 2000. For example, the memory device 1100 may include double data rate synchronous dynamic random access memory (DDR SDRAM), fourth generation low power double data rate (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR) SDRAM, Rambus DRAM (RDRAM), or flash memory.

[0031] The memory device 1100 performs a program operation, a read operation, and an erase operation under the control of the memory controller 1200 .

[0032] During an erase operation, the memory device 1100 receives a command corresponding to a program operation or a command corresponding to a read operation from the memory controller 1200. Upon receiving a pause command for pausing the erase operation, a command corresponding to the program operation, or a command corresponding to the read operation during the erase operation, the memory device 1100 pauses the currently executing erase operation in response to the pause command and executes a program operation or a read operation corresponding to the command corresponding to the program operation or read operation. After the program operation or read operation is completed, the memory device 1100 resumes the erase operation in response to receiving a resume command from the memory controller 1200. Resuming the erase operation includes resuming the erase operation from the beginning of the erase operation (e.g., from the beginning of the rising period of the erase operation) or resuming the erase operation from the point where the erase operation was paused.

[0033] The erase operation includes a rising period during which the erase voltage applied to the source line or bit line of the selected memory block increases toward a target voltage level, and a pulse application period during which the erase voltage of the target voltage level is applied for a predetermined period of time after the end of the rising period.

[0034] When a pause command is received during the rising period, the memory device 1100 restarts the rising period when re-executing the paused erase operation in response to receiving a resume command. When a pause command is received during the pulse application period, the memory device 1100 checks, determines, or identifies a time period that has not been executed in the pulse application period, or determines or identifies a time when the erase operation was suspended within the pulse application period, and when re-executing the paused erase operation in response to receiving a resume command, executes the resumed erase operation within a time period corresponding to the pulse application period that was not executed, thereby continuing the erase operation from the time when the erase operation was interrupted or suspended during the pulse application period.

[0035] The memory device 1100 includes an operating voltage controller 310. During an erase operation, the operating voltage controller 310 controls the level of the operating voltage applied to the select line connected to the transistor of the selected memory block. For example, the operating voltage controller 310 sets the operating voltage so that during the rising period of the erase operation, the operating voltage applied to the select line is a voltage lower than the erase voltage by a first voltage, while during the pulse application period, the operating voltage applied to the select line is a voltage lower than the erase voltage by at least a second voltage. The second voltage is a voltage higher than the first voltage.

[0036] Therefore, the voltage difference between the erase voltage and the operating voltage to be applied to the selection line when the pause command is received during the rising period is a relatively low first voltage difference, and the rising period can be repeated multiple times during the erase operation, thereby suppressing the decrease in the threshold voltage of the selection transistor.

[0037] Figure 2 is shown as Figure 1 Schematic diagram of a memory device shown.

[0038] Reference Figure 2 The memory device 1100 includes a memory cell array 100 for storing data. The memory device 1100 includes a peripheral circuit 200 configured to perform a program operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data. The memory device 1100 includes a control logic 300, which is executed in a memory controller (e.g., Figure 1 The peripheral circuit 200 is controlled under the control of the memory controller 1200 ).

[0039] The memory cell array 100 includes a plurality of memory blocks MB1 to MBk 110, where k is a positive integer. Local lines LL and bit lines BL1 to BLn (where n is a positive integer) are coupled to each of the memory blocks MB1 to MBk 110. For example, the local lines LL include a first select line, a second select line, and a plurality of word lines arranged between the first and second select lines. The local lines LL may include dummy lines, which may be arranged between the first select line and the word lines, and between the second select line and the word lines. For example, the first select line may be a source select line, and the second select line may be a drain select line. For example, the local lines LL include word lines, drain select lines, and source select lines, as well as source lines SL. For example, the local lines LL may include pipe lines. The local lines LL are coupled to each of the memory blocks MB1 to MBk 110, and the bit lines BL1 to BLn are commonly coupled to the memory blocks MB1 to MBk 110. The memory blocks MB1 to MBk 110 may each be implemented as a two-dimensional (2D) structure or a three-dimensional (3D) structure. For example, the memory cells in the memory block 110 having a 2D structure may be arranged horizontally on a substrate. For example, the memory cells in the memory block 110 having a 3D structure may be stacked vertically on a substrate.

[0040] The peripheral circuit 200 may perform a program operation, a read operation, and an erase operation on the selected memory block 110 under the control of the control logic 300. For example, the peripheral circuit 200 includes a voltage generating circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuit 250, a pass / fail check circuit 260, and a source line driver 270.

[0041] The voltage generation circuit 210 generates various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OP_CMD. For example, the voltage generation circuit 210 generates various voltages such as a program voltage, a verification voltage, a pass voltage, a turn-on voltage, a read voltage, a select line voltage, etc. under the control of the control logic 300.

[0042] The voltage generating circuit 210 generates a selection line voltage by adjusting a voltage potential of the selection line voltage applied to the selection line under the control of the operation voltage controller 310 of the control logic 300 .

[0043] The row decoder 220 transmits or applies the operating voltage Vop to the local line LL coupled to the selected memory block 110 in response to receiving the row decoder control signal AD_signals. The row decoder 220 may be included in the voltage generating circuit 210.

[0044] Page buffer group 230 includes a plurality of page buffers PB1 to PBn 231, each coupled to bit lines BL1 to BLn. Page buffers PB1 to PBn 231 operate in response to a page buffer control signal PBSIGNALS. For example, page buffers PB1 to PBn 231 temporarily store data received through bit lines BL1 to BLn during a read or verify operation, or sense the voltage or current of bit lines BL1 to BLn. Page buffers PB1 to PBn 231 apply an erase voltage to bit lines BL1 to BLn during an erase operation.

[0045] The column decoder 240 transfers data between the input / output circuit 250 and the page buffer group 230 in response to receiving the column address CADD. For example, the column decoder 240 exchanges data with the page buffer 231 through the data line DL or exchanges data with the input / output circuit 250 through the column line CL.

[0046] The input / output circuit 250 will receive data from the memory controller (e.g., Figure 1 1200 ) transmits the received command CMD and address ADD to the control logic 300 , or exchanges data DATA with the column decoder 240 .

[0047] During a read operation or a verification operation, the pass / fail check circuit 260 generates a reference current in response to receiving the enable bit VRY_BIT<#>, compares the sensing voltage VPB received from the page buffer group 230 with a reference voltage generated using the reference current, and outputs a pass signal PASS or a fail signal FAIL as a comparison result.

[0048] The source line driver 270 is coupled to the memory cells included in the memory cell array 100 via source lines SL and controls the voltage applied to the source lines SL. For example, the source line driver 270 electrically connects the source lines to a ground node during programming, reading, and verifying operations. The source line driver 270 applies an erase voltage to the source lines SL during an erase operation. The source line driver 270 receives a source line control signal CTRL_SL from the control logic 300 and, in response to the source line control signal CTRL_SL, connects the ground node to the source lines or applies an erase voltage to the source lines.

[0049] In response to receiving the command CMD and the address ADD, the control logic 300 controls the peripheral circuit 200 by outputting the operation signal OP_CMD, the row decoder control signal AD_signals, the page buffer control signal PBSIGNALS, and the enable bit VRY_BIT<#>. The control logic 300 determines whether the verification operation passes or fails in response to the pass signal PASS or the fail signal FAIL.

[0050] When the memory device 1100 is erased during an erase operation Figure 1 When the memory controller 1200 receives the suspend command, the control logic 300 performs a suspend operation including suspending the erase operation currently being executed, and in response to receiving the suspend command from Figure 1 The memory controller 1200 executes a resume command to perform a resume operation including resuming the suspended erase operation.

[0051] The control logic 300 includes an operating voltage controller 310. During an erase operation, the operating voltage controller 310 controls the voltage potential level of the operating voltage applied to the select line coupled to the transistors of the selected memory block. The operating voltage controller 310 controls the voltage generating circuit 210 to generate an operating voltage having a predetermined or given voltage potential.

[0052] For example, the operating voltage controller 310 selects the operating voltage so that during the rising period of the erase operation, the operating voltage applied to the selection line is a voltage lower than the erase voltage by a first voltage, and during the pulse application period, the operating voltage applied to the selection line is a voltage lower than the erase voltage by at least a second voltage. The first voltage is a voltage lower than the second voltage.

[0053] The operating voltage controller 310 sets the voltage potential of the operating voltage applied to the select line based on the number or number of pause operations performed during the pulse application period of the erase operation. For example, the operating voltage controller 310 reduces the potential level of the operating voltage applied to the select line based on the number of pause operations performed during the pulse application period. For example, when the pause operation is performed during the pulse application period, the operating voltage controller 310 controls the voltage generating circuit 210 to reset the operating voltage of the select line applied during the paused pulse application period by reducing the operating voltage by a third voltage difference, and when the resume operation is performed after the pause operation, the pulse application period is resumed using the reset operating voltage of the select line.

[0054] Figure 3 is shown as Figure 2 A diagram of a memory block is shown.

[0055] Reference Figure 3 , multiple word lines arranged in parallel between a first select line and a second select line are coupled to a memory block 110. In this example, the first select line is a source select line SSL, and the second select line is a drain select line DSL. Memory block 110 includes multiple strings ST coupled between bit lines BL1 to BLn and a source line SL. The bit lines BL1 to BLn are each coupled to a string ST, and the strings ST are coupled in common to the source line SL. Since each string ST has a similar configuration, a single string ST coupled to the first bit line BL1 is used as an example for detailed description.

[0056] The string ST includes a source select transistor SST, a plurality of memory cells MC1 to MC16, and a drain select transistor DST, which are connected in series between a source line SL and a first bit line BL1. A single string ST may include at least one source select transistor SST and at least one drain select transistor DST, and the string ST may include more memory cells than the memory cells MC1 to MC16 shown in the figure.

[0057] The source of the source select transistor SST is connected to the source line SL, and the drain of the drain select transistor DST is connected to the first bit line BL1. The memory cells MC1 to MC16 are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST are connected to the source select line SSL, the gates of the drain select transistors DST included in different strings ST are connected to the drain select line DSL, and the gates of the memory cells MC1 to MC16 are respectively connected to a different one of the multiple word lines WL1 to WL16. A group of memory cells included in different strings ST that are connected to the same word line may be referred to as a "physical page PPG" or page. The memory block 110 may include the same number of physical pages PPG as the number of word lines WL1 to WL16.

[0058] At least one dummy memory cell DMC1 is provided between the source select transistor SST and the memory cell MC1 , and at least one dummy memory cell DMC2 is provided between the drain select transistor DST and the memory cell MC16 .

[0059] Dummy memory cells (not shown) may be disposed between memory cells (eg, MC8 and MC9 ) in a center region between the plurality of memory cells MC1 to MC16 , and may be included in a word line group of consecutive memory cells.

[0060] A memory cell can store one bit of data. Such a cell is often designated a "single-level cell (SLC)." In this example, one physical page (PPG) stores data corresponding to one logical page (LPG). The data corresponding to one logical page (LPG) may have the same number of data bits as the number of cells included in one physical page (PPG). A memory cell can store two or more bits of data. Such a cell is often designated a "multi-level cell (MLC)." In this example, one physical page (PPG) stores data corresponding to two or more logical pages (LPG).

[0061] Figure 4 is a diagram illustrating an embodiment of a memory block having a three-dimensional 3D structure.

[0062] Reference Figure 4 , the memory cell array 100 includes a plurality of memory blocks MB1 to MBK 110. The memory block 110 includes a plurality of strings ST11 to ST1n and ST21 to ST2n. Each of the plurality of strings ST11 to ST1n and ST21 to ST2n is connected to Figure 4 The direction of the n strings extends in a vertical direction (e.g., the Z direction). In the memory block 110, n strings are arranged in a row direction (e.g., the X direction). Although the figure shows two strings arranged in a column direction (e.g., the Y direction), this embodiment is only for convenience of description, and in other embodiments, three or more strings may be arranged in the column direction (Y direction).

[0063] Each of the strings ST11 to ST1n and ST21 to ST2n includes at least one source select transistor SST, memory cells MC1 to MCn, and at least one drain select transistor DST.

[0064] The source select transistors SST of each string are coupled between a source line SL and memory cells MC1 to MCn. The source select transistors of the strings arranged in the same row are coupled to the same source select line. For example, the source select transistors of the strings ST11 to ST1n arranged in the first row are coupled to a first source select line SSL1. For example, the source select transistors of the strings ST21 to ST2n arranged in the second row are coupled to a second source select line SSL2. In an embodiment, the source select transistors of the strings ST11 to ST1n and ST21 to ST2n may be coupled in common to a single source select line.

[0065] The memory cells MC1 to MCn in each string are connected in series between a source select transistor SST and a drain select transistor DST. Gates of the memory cells MC1 to MCn are coupled to word lines WL1 to WLn, respectively.

[0066] In an embodiment, at least one of the memory cells MC1 to MCn is used as a dummy memory cell. When the dummy memory cell is provided, a voltage or current of a corresponding string can be stably controlled.

[0067] The drain select transistors DST of each string are coupled between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors DST of the strings arranged along the row direction are coupled to drain select lines extending along the row direction. For example, the drain select transistors DST of the strings ST11 to ST1n in the first row are coupled to the first drain select line DSL1. In another example, the drain select transistors DST of the strings ST21 to ST2n in the second row are coupled to the second drain select line DSL2.

[0068] Figure 4The plurality of memory blocks MB1 to MBk 110 described in can share a source line SL.

[0069] Figure 5 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0070] Figure 6 and Figure 7 is a timing diagram illustrating an erase voltage and a select line voltage during an erase operation of a memory device according to an embodiment of the present disclosure.

[0071] Reference Figures 1 to 7 An operating method of a memory device according to an embodiment of the present disclosure is described.

[0072] The memory device 1100 receives a command CMD corresponding to an erase operation, also referred to as an erase command, from the memory controller 1200 ( S510 ). The control logic 300 of the memory device 1100 controls the peripheral circuit 200 to perform the erase operation in response to the received command CMD.

[0073] The erase voltage Verase is increased toward the target voltage level and applied (S520). For example, during the rising period of the erase operation, the source line driver 270 generates the erase voltage Verase that linearly increases from 0V toward the target voltage level in response to the source line control signal CTRL_SL, and applies the erase voltage Verase to the source line SL. The page buffers PB1 to PBn 231 apply the erase voltage Verase that linearly increases from 0V toward the target voltage level to the bit lines BL1 to BLn during the rising period of the erase operation. The erase voltage Verase that linearly increases from 0V toward the target voltage level may increase at a constant slope.

[0074] The voltage generating circuit 210 generates an operating voltage applied to the source selection line SSL and the drain selection line DSL of the selected memory block in response to the operating signal OP_CMD (S520). The voltage generating circuit 210 generates the selection line voltage by adjusting the voltage potential of the selection line voltage under the control of the operating voltage controller 310 of the control logic 300. For example, Figure 6 or Figure 7 As shown, the selection line voltage V applied to the source selection line SSL or the drain selection line DSL of the selected memory block SSL / V DSL The row decoder 220 generates a voltage lower than the erase voltage Verase by a first voltage difference ΔV1. The row decoder 220 generates the selection line voltage V in response to the row decoder control signal AD_signals. SSL and V DSL The source selection line SSL and the drain selection line DSL of the selected memory block are applied. The selection line voltage VSSL and V DSL Each of may be a voltage that increases from 0V with a constant slope.

[0075] The slope of the erase voltage Verase can be adjusted to the selected line voltage V SSL and V DSL The rate of increase of the slope is similar to the rate of increase.

[0076] It is determined whether a pause command is received during the rising period ( S530 ).

[0077] For example, the memory controller 1200 generates and outputs a suspend command to suspend the erase operation of the memory device 1100. The control logic 300 of the memory device 1100 continues the erase operation or performs a suspend operation (including suspending the currently executed erase operation) based on whether the suspend command is received. The control logic 300 determines whether the suspend command is received during the rising period of the erase operation.

[0078] If a pause command is received during the rising period ("Yes" in S530), the control logic 300 controls the peripheral circuit 200 to pause the currently executing erase operation and perform a normal operation, such as a program operation or a read operation, in response to the received pause command (S540). After the normal operation is completed, the control logic 300 controls the peripheral circuit 200 to perform a resume operation, including resuming the paused erase operation. When the erase operation is resumed from the beginning of the rising period, the resuming process begins at S520.

[0079] When the suspend command is not received during the rising period (No in S530), the erase operation S550 is continued. For example, during the pulse application period after the rising period, the erase voltage Verase of the target voltage level is applied to the source line SL or the bit lines BL1 to BLn for a predetermined time period of the pulse application period (e.g., a predetermined time period based on the amount of data to be erased).

[0080] The voltage generating circuit 210 generates the selection line voltage by adjusting the voltage potential of the selection line voltage under the control of the operation voltage controller 310 of the control logic 300 (S550). Figure 6 As shown, the selection line voltage V applied to the source selection line SSL or the drain selection line DSL of the selected memory block SSL / V DSL The voltage is generated to be lower than the erase voltage Verase by a second voltage difference ΔV2. The second voltage difference ΔV2 is higher than or greater than the first voltage difference ΔV1. In an embodiment, as Figure 7 As shown, the selection line voltage V applied to the source selection line SSL or the drain selection line DSL of the selected memory block SSL / V DSL has a voltage lower than the erase voltage Verase by a second voltage difference ΔV2_1, and selects the line voltage V SSL / V DSL The voltage potential can be gradually reduced over time. For example, the line voltage V SSL / V DSL The difference between the line voltage V and the erase voltage Verase gradually increases. For example, during the first period, the line voltage V SSL / V DSL The potential of the line is lower than the erase voltage Verase by a second voltage difference ΔV2_1. During the second period, the line voltage V SSL / V DSL The potential of the second voltage difference ΔV2_2 is lower than the erase voltage Verase. The second voltage differences ΔV2_1 and ΔV2_2 are higher than or greater than the first voltage difference ΔV1.

[0081] As described above, during the rising period, the erase voltage Verase applied to the source line SL or the bit lines BL1 to BLn is equal to the selection line voltage V applied to the drain selection line DSL or the source selection line SSL. SSL / V DSL The difference between the erase voltage Verase and the select line voltage V SSL / V DSL The voltage difference between them is relatively small, and a pause command is received multiple times to repeatedly increase and apply the voltage (S520), which can also suppress the decrease in the threshold voltage of the drain selection transistor DST or the source selection transistor SST.

[0082] During the pulse application period, the erase voltage Verase is connected to the selection line voltage V applied to the drain selection line DSL or the source selection line SSL. SSL / V DSL The voltage difference between them is maintained at a voltage difference ΔV2 or greater. Therefore, a gate induced drain leakage (GIDL) current from a lower channel of the drain select transistor DST or the source select transistor SST can be sufficiently generated, and erase operation characteristics can be improved.

[0083] Figure 8 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0084] Figure 9 is a timing diagram illustrating an erase voltage and a select line voltage during an erase operation of a memory device according to an embodiment of the present disclosure.

[0085] Reference Figures 1 to 4 、 Figure 8 and Figure 9An operating method of a memory device according to an embodiment of the present disclosure is described.

[0086] The memory device 1100 receives a command CMD corresponding to an erase operation, also referred to as an erase command, from the memory controller 1200 ( S810 ). The control logic 300 of the memory device 1100 controls the peripheral circuit 200 to perform the erase operation in response to the received command CMD.

[0087] The erase voltage Verase is increased toward the target voltage level and applied (S820). For example, during the rising period of the erase operation, the source line driver 270 generates the erase voltage Verase that linearly increases from 0V toward the target voltage level in response to the source line control signal CTRL_SL, and applies the erase voltage Verase to the source line SL. The page buffers PB1 to PBn 231 apply the erase voltage Verase that linearly increases from 0V toward the target voltage level to the bit lines BL1 to BLn during the rising period of the erase operation. The erase voltage Verase that linearly increases from 0V toward the target voltage level may increase at a constant slope.

[0088] The voltage generating circuit 210 generates an operating voltage applied to the source selection line SSL and the drain selection line DSL of the selected memory block in response to the operating signal OP_CMD (S820). The voltage generating circuit 210 generates the selection line voltage by adjusting the voltage potential of the selection line voltage under the control of the operating voltage controller 310 of the control logic 300. For example, Figure 6 、 Figure 7 or Figure 9 As shown, the selection line voltage V applied to the source selection line SSL or the drain selection line DSL of the selected memory block SSL / V DSL The row decoder 220 generates a voltage lower than the erase voltage Verase by a first voltage difference ΔV1. The row decoder 220 generates the selection line voltage V in response to the row decoder control signal AD_signals. SSL and V DSL The source selection line SSL and the drain selection line DSL of the selected memory block are applied. The selection line voltage V SSL and V DSL Each of may be a voltage that increases from 0V with a constant slope.

[0089] The slope of the erase voltage Verase can be adjusted to the selected line voltage V SSL and V DSL The rate of increase of the slope is similar to the rate of increase.

[0090] It is determined whether a pause command is received during the rising period (S830).

[0091] For example, the memory controller 1200 generates and outputs a suspend command to suspend the erase operation of the memory device 1100. The control logic 300 of the memory device 1100 continues the erase operation or performs a suspend operation (including suspending the currently executing erase operation) based on whether the suspend command is received.

[0092] When a pause command is received during the rising period ("Yes" in S830), the control logic 300 controls the peripheral circuit 200 to pause the currently executing erase operation and perform a normal operation such as a program operation or a read operation in response to the received pause command (S840). After the normal operation is completed, the control logic 300 controls the peripheral circuit 200 to perform a resume operation, including resuming the paused erase operation, in response to a resume command received from the memory controller 1200. When the erase operation is resumed from the beginning of the rising period, the resuming process begins at S820.

[0093] When the suspend command is not received during the rising period (No in S830), the erase operation S850 is continued. For example, during the pulse application period after the rising period, the erase voltage Verase of the target voltage level is applied to the source line SL or the bit lines BL1 to BLn for a certain period of time.

[0094] The voltage generating circuit 210 generates the selection line voltage by adjusting the voltage potential of the selection line voltage under the control of the operation voltage controller 310 of the control logic 300. For example, Figure 9 As shown, the selection line voltage V applied to the source selection line SSL or the drain selection line DSL of the selected memory block SSL / V DSL The voltage may be generated to be lower than the erase voltage Verase by a second voltage difference ΔV2. The second voltage difference ΔV2 is higher than or greater than the first voltage difference ΔV1.

[0095] It is determined whether a pause command is received during the pulse application period ( S860 ).

[0096] For example, the memory controller 1200 generates and outputs a suspend command to suspend the erase operation of the memory device 1100. The control logic 300 of the memory device 1100 continues to perform the erase operation or performs a suspend operation (including suspending the erase operation currently being performed) based on whether the suspend command is received. The control logic 300 determines whether the suspend command is received during the pulse application period of the erase operation.

[0097] When a suspend command is received during the pulse application period ("Yes" in S860), the control logic 300 controls the peripheral circuit 200 to suspend the currently executing erase operation and perform a general operation such as a program operation or a read operation in response to the received suspend command (S870). After the general operation is completed, the control logic 300 controls the peripheral circuit 200 to perform a resume operation, including resuming the suspended erase operation, in response to a resume command received from the memory controller 1200.

[0098] When a pause command is received during the pulse application period, in S880, the control logic 300 checks, determines or identifies the previous pulse application period in which the erase voltage Verase was applied before the pause command was received, calculates the remaining application time period of the pulse application period (referred to as the recovery pulse application period) to perform a recovery operation by subtracting the time period of the previous pulse application period in which the erase voltage Verase was last applied (for example, utilizing the time when the erase operation was paused or interrupted) from the predetermined time period of the pulse application period, and resets the application time for applying the erase voltage Verase to the remaining application time period or the recovery pulse application period.

[0099] During the erase operation re-executed during the resume operation, the operating voltage controller 310 resets the voltage potential of the selection line voltage. For example, the operating voltage controller 310 resets the selection line voltage by lowering the potential of the selection line voltage used during the pulse application period executed before the pause operation by the third voltage difference ΔV3, and the process continues from S820.

[0100] The voltage generating circuit 210 generates the selection line voltage by adjusting the voltage potential of the selection line voltage under the control of the operation voltage controller 310 of the control logic 300. For example, Figure 9 As shown, the selection line voltage V applied to the source selection line SSL or the drain selection line DSL of the selected memory block SSL / V DSL The voltage is generated to be lower than the erase voltage Verase by a second voltage difference ΔV2. The second voltage difference ΔV2 is higher than or greater than the first voltage difference ΔV1.

[0101] After the general operation is completed, the control logic 300 controls the peripheral circuit 200 to perform a resume operation, including resuming the suspended erase operation. When the erase operation is resumed from the beginning of the rising period, the re-execution process starts from S820.

[0102] When the suspend command is not received during the pulse application period (No in S860 ), the control logic 300 applies the erase voltage Verase to the source line SL or the bit lines BL1 to BLn within the pulse application period and terminates the erase operation.

[0103] As described above, during the rising period, the erase voltage Verase applied to the source line SL or the bit lines BL1 to BLn is equal to the selection line voltage V applied to the drain selection line DSL or the source selection line SSL. SSL / V DSL The voltage difference between the two is maintained as the first voltage difference ΔV1. Even if the erase voltage Verase is different from the selection line voltage V SSL / V DSL The voltage difference between them is relatively small, and a pause command is received multiple times to repeatedly increase and apply the voltage (S820), which can also suppress the decrease in the threshold voltage of the drain selection transistor DST or the source selection transistor SST.

[0104] During the pulse application period, the erase voltage Verase is connected to the selection line voltage V applied to the drain selection line DSL or the source selection line SSL. SSL / V DSL The voltage difference between them is maintained at a voltage difference ΔV2 or greater. Therefore, a gate induced drain leakage (GIDL) current from a lower channel of the drain select transistor DST or the source select transistor SST can be sufficiently generated, and erase operation characteristics can be improved.

[0105] When a pause command is received during the pulse application period, the selection line voltage V applied to the drain selection line DSL or the source selection line SSL is increased by 100 ms during the pulse application period of the restart operation. SSL / V DSL By setting the potential of the gate electrode to a value lower than the voltage potential used in the previous pulse application period, more gate induced drain leakage (GIDL) current can be controlled to be generated.

[0106] Figure 10 It is shown that including, for example, Figure 2 A diagram of an embodiment of a memory system of a memory device is shown.

[0107] Reference Figure 10Memory system 3000 may be a cellular phone, a smartphone, a tablet computer, a personal digital assistant (PDA), a wireless communication device, or the like. Memory system 3000 includes a memory device 1100 and a memory controller 1200 capable of controlling the operation of memory device 1100. Under the control of processor 3100, memory controller 1200 controls data access operations of memory device 1100, such as programming, erasing, and reading operations. For example, memory controller 1200 controls memory device 1100 to perform an erase operation, controls memory device 1100 to suspend an erase operation in response to a suspend command, and controls memory device 1100 to perform a resume operation in response to a resume command. When a suspend command is received during the pulse application period of an erase operation, the select line voltage during the resume operation is adjusted by lowering the select line voltage used during the resume pulse application period of the resumed erase operation.

[0108] Data programmed into the memory device 1100 may be output through the display 3200 under the control of the memory controller 1200 .

[0109] The radio transceiver 3300 exchanges or communicates radio signals via the antenna ANT. For example, the radio transceiver 3300 converts radio signals received via the antenna ANT into signals processed by the processor 3100. The processor 3100 processes the signals from the radio transceiver 3300 and transmits the processed signals to, for example, the memory controller 1200 or the display 3200. The memory controller 1200 may provide the signals processed by the processor 3100 to the memory device 1100. The radio transceiver 3300 converts the signals output from the processor 3100 into radio signals and transmits the radio signals to an external device via the antenna ANT. The input device 3400 is a device for inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100. For example, it may be a pointing device such as a touchpad or a computer mouse, a keypad, a keyboard, etc. The processor 3100 controls the operation of the display 3200, so that data output from the memory controller 1200, data output from the radio transceiver 3300, and data output from the input device 3400 are output via the display 3200.

[0110] According to an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be a part of the processor 3100 or an integrated circuit chip separate from the processor 3100 .

[0111] Figure 11 It is shown that including, for example, Figure 2 A diagram of an embodiment of a memory system of a memory device is shown.

[0112] Reference Figure 11 The memory system 4000 may be a personal computer (PC), a tablet computer, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, an MP4 player, etc.

[0113] The memory system 4000 includes a memory device 1100 and a memory controller 1200 capable of controlling data processing operations of the memory device 1100. For example, the memory controller 1200 controls the memory device 1100 to perform an erase operation, controls the memory device 1100 to suspend the erase operation in response to a suspend command, and controls the memory device 1100 to perform a resume operation in response to a resume command. When the suspend command is received during a pulse application period of the erase operation, the select line voltage during the resume operation is adjusted by lowering the select line voltage used during the resume pulse application period of the resumed erase operation.

[0114] The processor 4100 outputs data stored in the memory device 1100 via the display 4300 according to data input from the input device 4200. For example, the input device 4200 may be a pointing device such as a touch pad or a computer mouse, a keypad, a keyboard, or the like.

[0115] The processor 4100 controls the overall operation of the memory system 4000 and controls the operation of the memory controller 1200. The memory controller 1200 capable of controlling the operation of the memory device 1100 may be a part of the processor 4100 or an integrated circuit chip separate from the processor 4100.

[0116] Figure 12 It is shown that including, for example, Figure 2 A diagram of an embodiment of a memory system of a memory device is shown.

[0117] Reference Figure 12 The memory system 7000 may be a memory card or a smart card. The memory system 7000 includes a memory device 1100 , a memory controller 1200 , and a card interface 7100 .

[0118] The memory controller 1200 controls data exchange between the memory device 1100 and the card interface 7100. For example, the memory controller 1200 controls the memory device 1100 to perform an erase operation, controls the memory device 1100 to suspend the erase operation in response to a suspend command, and controls the memory device 1100 to perform a resume operation in response to a resume command. When a suspend command is received during the pulse application period of the erase operation, the select line voltage during the resume operation is adjusted by lowering the select line voltage used during the resume pulse application period of the resumed erase operation. The card interface 7100 may be, but is not limited to, a secure digital (SD) card interface or a multimedia card (MMC) interface.

[0119] The card interface 7100 provides an interface for data exchange between the host 6000 and the memory controller 1200 according to the protocol of the host 6000. The card interface 7100 may support a universal serial bus (USB) protocol, an inter-chip (IC) USB protocol, etc. In this example, the card interface may refer to hardware capable of supporting the protocol used by the host 6000, software installed in the hardware, and / or a signal transmission method.

[0120] When the memory system 7000 is connected to the host interface 6200 of a host 6000 such as a PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, digital set-top box, etc., the host interface 6200 communicates data with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100.

[0121] According to the present disclosure, even if a pause operation is repeated multiple times during an erase operation of a memory device, a threshold voltage distribution of a selection transistor can be improved by adjusting a potential difference between an operating voltage and an erase voltage applied to the selection transistor.

Claims

1. A memory device comprising: a memory block comprising a plurality of memory cells; a source line driver that applies an erase voltage to a source line of the memory block during an erase operation; a page buffer group that applies the erase voltage to the bit lines of the memory block during the erase operation; a voltage generating circuit that generates a selection line voltage applied to a selection line of the memory block during the erase operation; as well as a control logic for controlling the source line driver, the page buffer group, and the voltage generating circuit to perform a pause operation in response to a pause command, the pause operation including pausing the erase operation; In which, the control logic controls the voltage generating circuit so that during the rising period in which the erase voltage increases toward the target voltage level in the erase operation, the difference between the erase voltage and the selection line voltage remains at a first voltage difference, and during the pulse application period in which the erase voltage of the target voltage level is applied, the difference between the erase voltage and the selection line voltage remains at a second voltage difference, and the second voltage difference is greater than the first voltage difference.

2. The memory device of claim 1 , wherein: The control logic includes operating a voltage controller, and The operating voltage controller controls the voltage generating circuit to set a voltage level of the selection line voltage and generates the selection line voltage of the voltage level.

3. The memory device according to claim 1, wherein During the rising period, the erase voltage and the select line voltage each increase at a constant slope.

4. The memory device according to claim 1, wherein During the pulse application period, the selection line voltage is maintained at a constant level or gradually decreases over time.

5. The memory device according to claim 1, wherein In response to receiving the suspend command during the rising period, the control logic controls the source line driver, the page buffer group, and the voltage generating circuit so that the erase operation is suspended and a program operation or a read operation is performed. The memory device according to claim 5 , wherein: After the program operation or the read operation is completed, the control logic controls the source line driver, the page buffer group, and the voltage generating circuit so that the suspended erase operation is resumed by starting a second rising period.

7. A memory device comprising: a memory block comprising a plurality of memory cells; a peripheral circuit that applies an erase voltage to a source line or a bit line of the memory block and applies a select line voltage to a select line of the memory block during an erase operation; as well as control logic that controls the peripheral circuit to perform a suspend operation in response to receiving a suspend command and controls the peripheral circuit to perform a resume operation in response to receiving a resume command, wherein the suspend operation includes suspending the erase operation and the resume operation includes resuming the suspended erase operation. When the pause command is received during the pulse application period of the erase voltage of the target voltage level in the erase operation, the control logic resets the selection line voltage during the resume operation by lowering the selection line voltage used during the resume pulse application period of the resumed erase operation.

8. The memory device according to claim 7, wherein The control logic controls the peripheral circuit so that during a rising period in which the erase voltage increases toward a target voltage level in the erase operation, the difference between the erase voltage and the selection line voltage remains at a first voltage difference, and during the pulse application period, the difference between the erase voltage and the selection line voltage remains at a second voltage difference, which is greater than the first voltage difference.

9. The memory device according to claim 7, wherein: In response to receiving the suspend command during a rising period, the control logic controls the peripheral circuit so that the erase operation is suspended and a program operation or a read operation is performed.

10. The memory device according to claim 9, wherein After the program operation or the read operation is completed, the control logic controls the peripheral circuit so that the suspended erase operation is resumed by starting a second rising period.

11. The memory device according to claim 7, wherein: When the suspend command is received during the pulse application period, the control logic determines a previous pulse application period based on a time period in which the erase voltage was last applied before the suspend command was received, and establishes a resume pulse application period for the resume operation by subtracting the previous pulse application period from a predetermined time period of the pulse application period.

12. The memory device of claim 7, wherein: The control logic includes operating a voltage controller, and The operating voltage controller controls the peripheral circuit to set a voltage level of the selection line voltage and generates the selection line voltage of the voltage level.

13. A method of operating a memory device, comprising: During a rising period of an erase operation, applying an erase voltage that increases toward a target voltage level to a source line or a bit line of a memory block; During the rising period, applying a selection line voltage lower than the erase voltage by a first voltage difference to the selection line of the memory block; pausing the erase operation in response to receiving a suspend command during the rising period, and resuming the erase operation in response to receiving a resume command; applying the erase voltage of the target voltage level during a pulse application period of the erase operation after the rising period ends; as well as applying a selection line voltage lower than the erase voltage by a second voltage difference during the pulse application period, Wherein, the second voltage difference is greater than the first voltage difference.

14. The method according to claim 13, wherein During the pulse application period, the selection line voltage is gradually reduced over time.

15. The method according to claim 13, wherein During the rising period, the erase voltage and the select line voltage each increase at a constant slope.

16. The method according to claim 13, further comprising: The erase operation is suspended, and a program operation or a read operation is performed.

17. The method according to claim 13, wherein: Resuming the erase operation includes resuming the erase operation by starting a second rising period.

18. A method of operating a memory device, comprising: During a first rising period of an erase operation, applying an erase voltage that increases toward a target voltage level to a source line or a bit line of a memory block; During the first rising period, applying a selection line voltage lower than the erase voltage by a first voltage difference to the selection line of the memory block; applying the erase voltage of the target voltage level during a pulse application period of the erase operation after the first rising period ends; as well as suspending the erase operation in response to receiving a suspend command during the pulse application period, and resuming the erase operation in response to receiving a resume command; wherein the resumed erase operation includes applying the selection line voltage during the second rising period and applying the erase voltage of the target voltage level during the resume pulse application period; and The selection line voltage during the restoration pulse application period is lower by a voltage difference than the selection line voltage used during the previous pulse application period.

19. The method of claim 18, wherein: The selection line voltage during the rising period is lower than the erase voltage by a first voltage difference, and the selection line voltage during the pulse application period is lower than the erase voltage by a second voltage difference, and The second voltage difference is greater than the first voltage difference.

20. The method of claim 18, further comprising: The previous pulse application period is determined according to a time period during which the erase voltage is last applied before the suspend command is received, and the resume pulse application period is set by subtracting the previous pulse application period from a predetermined time period of the pulse application period.

Images