Memory device, operating method thereof, and memory system

Abstract

The invention provides a memory device, an operating method thereof, and a memory system. The memory device includes at least one memory block; an operating method of the memory device includes performing a first program operation on memory cells coupled to a first word line in the memory block; performing a soft erase operation on a memory cell coupled to the first word line; a virtual read operation is performed on memory cells in the memory block.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a memory device and an operating method thereof, and a memory system. Background Art

[0002] Memory devices are used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become a mainstream product in the memory market due to its high storage density, manageable production costs, and suitable programming and erasing speeds. However, as people's requirements for storage devices continue to increase, memory devices and their systems still have significant room for improvement. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory device and an operating method thereof, and a memory system to solve at least one problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a method for operating a memory device, wherein the memory device includes at least one memory block; the method for operating the memory device includes:

[0006] performing a first programming operation on memory cells coupled to a first word line in the memory block;

[0007] performing a soft erase operation on the memory cells coupled to the first word line;

[0008] A dummy read operation is performed on memory cells in the memory block.

[0009] In an optional implementation, performing a virtual read operation on a storage unit in the storage block includes:

[0010] applying a first turn-on voltage to a top selection line in the memory block, and applying a ground voltage to a bit line connected to the memory block; and / or,

[0011] A second turn-on voltage is applied to a bottom selection line in the memory block, and the ground voltage is applied to a common source connected to the memory block.

[0012] In an optional implementation, performing a virtual read operation on a storage unit in the storage block further includes:

[0013] A third turn-on voltage is applied to all word lines in the memory block.

[0014] In an optional implementation, performing a virtual read operation on a storage unit in the storage block further includes:

[0015] Applying a fourth conduction voltage to word lines coupled to programmed memory cells in the memory block; the word lines coupled to the programmed memory cells include the first word line;

[0016] A fifth turn-on voltage is applied to word lines coupled to unprogrammed memory cells in the memory block; the fifth turn-on voltage is lower than the fourth turn-on voltage.

[0017] In an optional implementation, performing a soft erase operation on a memory cell coupled to the first word line includes:

[0018] applying a first voltage to the first word line;

[0019] Applying a second voltage to a bit line and / or a common source connected to the memory block; the first voltage is lower than the second voltage;

[0020] A top selection line, a bottom selection line, and all word lines except the first word line in the memory block are floated.

[0021] In an optional embodiment, the operating method of the memory device further includes:

[0022] Before performing the first programming operation, performing a second programming operation on memory cells coupled to a second word line in the memory block;

[0023] After performing the dummy read operation, performing a third program operation on the memory cells coupled to the second word line;

[0024] A fourth program operation is performed on memory cells coupled to the first word line.

[0025] In an optional implementation, performing a virtual read operation on a storage unit in the storage block includes:

[0026] The dummy read operation is performed on memory cells in a memory cell string that is first selected in the third program operation.

[0027] In an optional implementation, performing a first programming operation on a memory cell coupled to a first word line in the memory block includes:

[0028] Programming some of the memory cells coupled to the first word line to a first target programming state, wherein a threshold voltage of the memory cells in the first target programming state is greater than or equal to a first verification voltage;

[0029] The performing a fourth programming operation on the memory cells coupled to the first word line includes:

[0030] The memory cell in the first target programming state is programmed to a second target programming state, wherein the threshold voltage of the memory cell in the second target programming state is greater than or equal to a second verification voltage; the second verification voltage is less than the first verification voltage.

[0031] In an optional implementation, performing a first programming operation on a memory cell coupled to a first word line in the memory block further includes:

[0032] Some of the memory cells coupled to the first word line are programmed to a third target program state, wherein a threshold voltage of the memory cells in the third target program state is lower than a threshold voltage of the memory cells in the first target program state.

[0033] In a second aspect, an embodiment of the present disclosure provides a memory device, comprising a memory array and a peripheral circuit coupled to the memory array; the memory array comprises at least one memory block; the memory block comprises a first word line and a memory cell coupled to the first word line; the peripheral circuit is configured as follows:

[0034] performing a first programming operation on memory cells coupled to the first word line;

[0035] performing a soft erase operation on the memory cells coupled to the first word line;

[0036] A dummy read operation is performed on memory cells in the memory block.

[0037] In an optional embodiment, the memory block further includes a top selection line and a bottom selection line; the memory array further includes a bit line and a common source connected to the memory block; and the peripheral circuit is specifically configured as follows:

[0038] When performing the dummy read operation, applying a first turn-on voltage to the top selection line and applying a ground voltage to the bit line; and / or,

[0039] A second turn-on voltage is applied to the bottom selection line, and the ground voltage is applied to the common source.

[0040] In an optional implementation, the peripheral circuit is specifically configured as follows:

[0041] When performing the dummy read operation, a third turn-on voltage is applied to all word lines in the memory block.

[0042] In an optional implementation, the peripheral circuit is specifically configured as follows:

[0043] When performing the dummy read operation, applying a fourth conduction voltage to word lines coupled to programmed memory cells in the memory block; the word lines coupled to the programmed memory cells include the first word line;

[0044] A fifth turn-on voltage is applied to word lines coupled to unprogrammed memory cells in the memory block; the fifth turn-on voltage is lower than the fourth turn-on voltage.

[0045] In an optional implementation, the peripheral circuit is specifically configured as follows:

[0046] When performing the soft erase operation, applying a first voltage to the first word line;

[0047] applying a second voltage to the bit line and / or the common source; wherein the first voltage is less than the second voltage;

[0048] The top select line, the bottom select line, and all word lines except the first word line in the memory block are floated.

[0049] In an optional implementation, the peripheral circuit is further configured as follows:

[0050] Before performing the first programming operation, performing a second programming operation on memory cells coupled to a second word line in the memory block;

[0051] After performing the dummy read operation, performing a third program operation on the memory cells coupled to the second word line;

[0052] A fourth program operation is performed on memory cells coupled to the first word line.

[0053] In an optional implementation, the peripheral circuit is specifically configured as follows:

[0054] The dummy read operation is performed on memory cells in a memory cell string that is first selected in the third program operation.

[0055] In an optional implementation, the peripheral circuit is specifically configured as follows:

[0056] When performing the first programming operation, programming some memory cells among the plurality of memory cells coupled to the first word line to a first target programming state, wherein a threshold voltage of the memory cells in the first target programming state is greater than or equal to a first verification voltage;

[0057] When performing the fourth programming operation, the memory cell in the first target programming state is programmed to a second target programming state, and the threshold voltage of the memory cell in the second target programming state is greater than or equal to a second verification voltage; the second verification voltage is less than the first verification voltage.

[0058] In an optional implementation, the peripheral circuit is specifically configured as follows:

[0059] When performing the first programming operation, some of the multiple memory cells coupled to the first word line are programmed to a third target programming state, and the threshold voltage of the memory cells in the third target programming state is lower than the threshold voltage of the memory cells in the first target programming state.

[0060] In a third aspect, an embodiment of the present disclosure provides a memory system, including:

[0061] At least one memory device according to any one of the above embodiments;

[0062] A controller is coupled to at least one of the memory devices and is configured to control the memory device.

[0063] In the technical solution provided by the present disclosure, a method for operating a memory device includes performing a first programming operation and a soft erase operation on memory cells coupled to a first word line, and performing a dummy read operation on memory cells in a memory block. On the one hand, the soft erase operation can be used to allow charges trapped in shallow energy level traps in the memory cells to be released from the storage layer in advance, thereby improving the data retention performance of the memory device. On the other hand, the dummy read operation can be used to clear the residual potential in the channel, thereby reducing the negative impact of the soft erase operation on the programming operation in subsequent steps, minimizing the reduction of the read window or the unevenness of the read window width, thereby improving the reliability of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A schematic diagram of an exemplary system having a memory system provided for an embodiment of the present disclosure;

[0065] Figure 2 A schematic diagram of an exemplary memory card having a memory system provided for an embodiment of the present disclosure;

[0066] Figure 3 A schematic diagram of an exemplary solid-state drive having a memory system provided in accordance with an embodiment of the present disclosure;

[0067] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuits provided for an embodiment of the present disclosure;

[0068] Figure 5 A schematic diagram of an exemplary memory device including a memory array and peripheral circuits provided for an embodiment of the present disclosure;

[0069] Figure 6 A schematic diagram of word line voltage in a stepped pulse programming method provided by an embodiment of the present disclosure;

[0070] Figure 7 Schematic diagram of the threshold voltage distribution of the memory cell provided in the embodiment of the present disclosure Figure 1 ;

[0071] Figure 8 A schematic diagram of a memory block in a memory device according to an embodiment of the present disclosure;

[0072] Figure 9 A flowchart of an operating method of a memory device according to an embodiment of the present disclosure;

[0073] Figure 10 Schematic diagram of the threshold voltage distribution of the memory cell provided in the embodiment of the present disclosure Figure 2 ;

[0074] Figure 11 A schematic diagram of the structure of a storage unit string provided in an embodiment of the present disclosure;

[0075] Figure 12 Voltage curve 1 for a soft erase operation and a virtual read operation provided in an embodiment of the present disclosure;

[0076] Figure 13 Voltage curve 2 for the soft erase operation and virtual read operation provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0077] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0078] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0079] In the drawings, like reference numerals refer to like elements throughout.

[0080] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0081] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0082] The memory system in the embodiments of the present disclosure includes but is not limited to a memory system including a three-dimensional NAND memory. For ease of understanding, the memory system provided by the present disclosure is described using a memory system including a three-dimensional NAND memory as an example.

[0083] Figure 1 Schematic diagram of an exemplary system with a memory system provided in an embodiment of the present disclosure. In an embodiment of the present disclosure, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1As shown in , system 100 may include a host device 101 and a memory system 102. Memory system 102 may include one or more memory devices 103 and a memory controller 104. Host device 101 may include a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), such as an application processor (AP). Host device 101 may be configured to send data to or receive data from memory system 102.

[0084] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host device 101 and is configured to control the memory device 103. The memory controller 104 can manage data stored in the memory device 103 and communicate with the host device 101. In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as in a secure digital card, a compact flash card (CFC), a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In other embodiments, the memory controller 104 is designed to operate in a high duty cycle environment, such as in a solid-state drive or an embedded multi-media card (eMMC).

[0085] In some embodiments, the memory controller 104 and the one or more memory devices 103 may be integrated into various types of memory devices. That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0086] In such Figure 2 In one example shown in FIG, the memory controller 104 and the single memory device 103 can be integrated into a memory card 201. The memory card 201 can be a compact flash card, a smart media card (Smart Media Card, SMC), a memory stick (Memory Stick, MS), a multimedia card (Multi-Media Card, MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as Mini SD card, Micro SD card, SDHC card, etc., or a universal flash memory card. The memory card 201 can also include a device that connects the memory card 201 to a host device (e.g., Figure 1The host device 101 in FIG. 1 is coupled to the memory card connector 202. Figure 3 In another example shown in , the memory controller 104 and the plurality of memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include a processor that connects the SSD 203 to a host device (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.

[0087] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuits provided in accordance with an embodiment of the present disclosure. The memory device 300 may be Figure 1 3. An example of a memory device 103 in FIG. Memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to memory array 301. Memory array 301 is described as a three-dimensional NAND memory array, wherein memory cells 305 are NAND memory cells, and memory cells 305 are provided in the form of an array of memory strings 304, each memory string 304 extending vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0088] In some embodiments, each memory cell 305 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, for example, a multi-level cell (MLC) that stores two bits per cell, a triple-level cell (TLC) that stores three bits per cell, or a quad-level cell (QLC) that stores four bits per cell.

[0089] like Figure 4As shown in FIG, each memory string 304 may include a bottom select transistor (BST) 307 at its source terminal and a top select transistor (TST) 306 at its drain terminal. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the sources of the memory strings 304 in the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory strings 304 in the same memory block 303 have a common source (Array Common Source, ACS). According to some embodiments, the top select transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, and data can be read from or written to the bit line 311 via an output bus (not shown). In some embodiments, each memory string 304 is configured to be selected or deselected by applying a select voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a select voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0090] like Figure 4 As shown in , the memory string 304 can be organized into a plurality of memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is a basic data unit for an erase operation, that is, all memory cells 305 on the same memory block 303 are erased at the same time. In order to erase the memory cells 305 in a selected memory block, the common source line 310 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage. It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 305 of adjacent memory strings 304 can be coupled by word lines 312, which select which row of memory cells 305 is affected by the read or program operation.

[0091] In some embodiments, the peripheral circuit 302 may include any suitable analog, digital, and mixed-signal circuits for operating the memory array 301 by applying a voltage signal and / or a current signal to each target memory cell 305 through the bit line 311, the word line 312, the common source line 310, the bottom select line 309, and the top select line 308, and sensing a voltage signal and / or a current signal from each target memory cell 305. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology.

[0092] Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, a control logic 405, a register group 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 5 Additional peripheral circuits not shown.

[0093] The page buffer / sense amplifier 401 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to a control signal from the control logic 405. In one example, the page buffer / sense amplifier 401 can store a page of programming data (write data) to be programmed into the memory array 301. In another example, the page buffer / sense amplifier 401 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sense amplifier 401 can also sense a low-power signal from the bit line representing the data bit stored in the memory cell and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 402 can be configured to be controlled by the control logic 405 and select one or more memory strings by applying a bit line voltage generated from the voltage generator 404.

[0094] The row decoder / word line driver 403 can be configured to be controlled by the control logic 405 and to select / deselect memory blocks of the memory array 301 and to select / deselect word lines of the memory blocks. The row decoder / word line driver 408 can also be configured to drive word lines using word line voltages generated from the voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive the bottom select line and the top select line. As described in detail below, the row decoder / word line driver 403 is configured to perform a programming operation on the memory cells coupled to the selected word line(s). The voltage generator 404 can be configured to be controlled by the control logic 405 and to generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0095] The control logic 405 can be coupled to each peripheral circuit described above and is configured to control the operation of each peripheral circuit. The register group 406 can be coupled to the control logic 405 and include a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The flash memory interface 407 can be coupled to the control logic 405 and act as a control buffer to buffer control commands received from a host-side device (not shown) and relay them to the control logic 405, as well as buffer status information received from the control logic 405 and relay it to the memory controller. The flash memory interface 407 can also be coupled to the column decoder / bit line driver 402 via the data bus 408 and act as a data I / O interface and data buffer to buffer data and relay it to the memory array 301 or relay or buffer data from the memory array 301.

[0096] In some embodiments, an Increment Step Pulse Program (ISPP) method is used to program the memory device. Figure 6 This diagram illustrates the word line voltages used in the stepped pulse programming method. During the stepped pulse programming process, a continuously increasing programming voltage, Vpgm, is applied to a selected word line to program the memory cells coupled to the selected word line. The difference ΔV between two adjacent programming voltages Vpgm is the step size of the stepped pulse. Between programming pulses, a program-verify operation is performed, applying a verify voltage, Vvfy, to the selected word line to confirm whether the threshold voltage of the selected memory cell has reached the threshold voltage corresponding to the target programming state. If the selected memory cell fails the program-verify operation, program-verify operations are continued on the selected memory cell until the threshold voltage of the selected memory cell reaches the threshold voltage corresponding to the target programming state.

[0097] In some embodiments, a multi-step programming method is used to perform a programming operation on a memory cell, and the multi-step programming method may include a coarse programming operation and a fine programming operation. In a specific example, Figure 7 Schematic diagram of the distribution of the threshold voltage of the memory cell provided in the embodiment of the present disclosure Figure 1 Here, taking the memory cell as a quad-level cell QLC as an example, after performing a coarse programming operation, the memory cell is programmed to programming states P1 to P15. After performing a fine programming operation, the memory cells in programming states P1 to P15 are respectively programmed to programming states P1' to P15'. It can be seen from the figure that the threshold voltage distribution width of the memory cells in programming states P1 to P15 is greater than the threshold voltage distribution width of the memory cells in programming states P1' to P15'. Both the coarse programming operation and the fine programming operation include performing a programming operation on the memory cell by a step pulse programming method. The difference is that the step size of the step pulse in the coarse programming operation can be larger than the step size of the step pulse in the fine programming operation, and for two corresponding programming states, such as programming state P15 and programming state P15', when the coarse programming operation is performed on the memory cell to program the memory cell to programming state P15, a programming verification operation is performed on the memory cell using a verification voltage Vc, and when the fine programming operation is performed on the memory cell in programming state P15 to program the memory cell to programming state P15', a programming verification operation is performed on the memory cell using a verification voltage Vf, and the verification voltage Vf is greater than the verification voltage Vc, so that the left end of the threshold voltage distribution can be tightened to reduce the width of the threshold voltage distribution.

[0098] While performing programming operations on memory cells using the aforementioned multi-step programming method, which includes a coarse programming operation and a fine programming operation, can improve the efficiency and reliability of programming operations on multi-level memory cells, multi-level memory cells still suffer from the problem of poor data retention performance in memory cells in higher programming states. To address this issue, the present disclosure proposes the following implementations.

[0099] An embodiment of the present disclosure provides an operating method for a memory device. Figure 8 A schematic diagram of a memory block in a memory device according to an embodiment of the present disclosure; Figure 9 A flowchart of an operating method of a memory device according to an embodiment of the present disclosure; Figure 10 Schematic diagram of the threshold voltage distribution of the memory cell provided in the embodiment of the present disclosure Figure 2 ; Figure 11 A schematic diagram of the structure of a storage unit string provided in an embodiment of the present disclosure; Figure 12 Voltage curve 1 for a soft erase operation and a virtual read operation provided in an embodiment of the present disclosure; Figure 13 Voltage curve 2 for the soft erase operation and virtual read operation provided by the embodiment of the present disclosure.

[0100] In the embodiment of the present disclosure, Figure 8 As shown, a memory block includes multiple word lines WL and dummy word lines DWL. The memory block includes multiple memory cell strings indicated by dashed lines. Each memory cell string is connected between a bit line BL and a common source ACS, and each word line WL is coupled to a memory cell in each memory cell string. The memory block also includes a top select line TSL and a bottom select line BSL. Here, an example is used in which each memory cell string includes a top select transistor connected to the top select line TSL and a bottom select transistor connected to the bottom select line BSL. However, the present disclosure is not limited to this, and the present disclosure does not impose any specific restrictions on the top select lines or the number of top select lines.

[0101] In the embodiment of the present disclosure, Figure 9 As shown, the operating method of the memory device includes the following steps:

[0102] Step S10: performing a first programming operation on memory cells coupled to a first word line in the memory block;

[0103] Step S20: performing a soft erase operation on the memory cells coupled to the first word line;

[0104] Step S30: performing a virtual read operation on the storage cells in the storage block.

[0105] The operating method of the memory device provided by the embodiment of the present disclosure will be described in detail below.

[0106] In some embodiments, a method for operating a memory device includes: executing step S10 , performing a first programming operation on memory cells coupled to a first word line.

[0107] It should be noted that, in the embodiment of the present disclosure, the first word line may be any unprogrammed word line in the memory block, and the second word line may be a word line that has been roughly programmed before the first word line is programmed. For ease of explanation, in the following examples, the first word line is used as Figure 8 The second word line is WLn Figure 8 Take WLn-1 in as an example.

[0108] In some embodiments, the specific process of executing step S10 may include: programming some of the multiple memory cells coupled to the first word line WLn to a first target programming state, the threshold voltage of the memory cells in the first target programming state is greater than or equal to the first verification voltage, and programming some of the multiple memory cells coupled to the first word line WLn to a third target programming state, the threshold voltage of the memory cells in the third target programming state is less than the threshold voltage of the memory cells in the first target programming state.

[0109] In some specific examples, such as Figure 10 As shown, the first programming operation can be a coarse programming operation. After the first programming operation is performed on the memory cells coupled to the first word line WLn, the memory cells coupled to the first word line WLn are respectively in the erased state P0a, the programming state P1a to the programming state P15a. Here, the first target programming state in the above steps can be the programming state P13a, the programming state P14a or the programming state P15a. Correspondingly, the first verification voltage can be Vc13, Vc14 or Vc15, and the third target programming state can be one of the programming states P1a to P12a.

[0110] In some embodiments, the operating method of the memory device includes: executing step S20 to perform a soft erase operation on memory cells coupled to the first word line WLn.

[0111] In some specific examples, combined with reference Figures 8 to 12 The specific process of executing step S20 may include: applying a first voltage V1 to the first word line WLn; applying a second voltage V2 to the bit line BL and / or the common source ACS connected to the memory block; the first voltage V1 is less than the second voltage V2; floating the top selection line TSL, the bottom selection line BSL and all word lines except the first word line WLn in the memory block.

[0112] In the embodiment of the present disclosure, Figure 11 As shown, the channel in the memory block includes a channel layer 501, a functional layer 502, and an insulating fill layer 503. The functional layer 502 further includes a tunneling layer 5021, a storage layer 5022, and a barrier layer 5023. The channel can be cylindrical, with the channel layer 501, tunneling layer 5021, storage layer 5022, and barrier layer 5023 arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order. The word line WL, dummy word line DWL, top select line TSL, and bottom select line BSL surround the channel to form a memory cell string including a memory cell, a dummy memory cell, a top select transistor, and a bottom select transistor. The channel layer 501 is connected to a common source ACS and extends vertically into the common source ACS.

[0113] When a programming operation is performed on a memory cell coupled to a selected word line, charges (such as electrons) will be captured in the storage layer 5022 of the memory cell, thereby increasing the threshold voltage of the memory cell. However, part of the charges will be captured in shallow energy level traps in the storage layer 5022 near the tunneling layer 5021. These charges captured in the shallow energy level traps will still increase the threshold voltage of the memory cell. However, after the programming operation is completed, the charges in the shallow energy level traps are easily excited and break free from the constraints of the traps and return to the channel layer 501, causing the threshold voltage of the memory cell to drift negatively, and may even cause errors in the data stored in the memory cell, thereby reducing the data retention performance of the memory device.

[0114] In an embodiment of the present disclosure, after a coarse program operation is performed on memory cells coupled to the first word line WLn, a soft erase operation may be performed on the memory cells coupled to the first word line WLn.

[0115] In some specific examples, the channel layer 501 and the common source ACS are made of the same material. For example, the channel layer 501 and the common source ACS may both include N-type doped polysilicon. Figure 11 and Figure 12 During a soft erase operation, a first voltage V1 is applied to the common source ACS, which can be transferred to the channel layer 501. A second voltage V2 is applied to the first word line WLn. The second voltage V2 is lower than the first voltage V1. In this case, a negative voltage difference is generated between the first word line WLn and the channel layer 501, which can release charges trapped in shallow energy level traps. Furthermore, during a soft erase operation, a first voltage V1 can also be applied to the bit line BL, or the first voltage V1 can be applied to both the common source ACS and the bit line BL. When the first voltage V1 is applied to the bit line BL, the bit line BL can also transfer the first voltage V1 to the channel layer 501.

[0116] Reference Figure 10 After a soft erase operation is performed on the memory cells coupled to the first word line WLn, the memory cells in the higher programming state after the coarse programming operation, for example, the memory cells in programming state P13a, programming state P14a and programming state P15a, are in programming state P13b, programming state P14b and programming state P15b, respectively, after being soft erased. It can be seen from the figure that the threshold voltage of some memory cells in the higher programming state after being soft erased decreases, and the threshold voltage distribution corresponding to the higher programming state becomes wider. This is because for the memory cells in the higher programming state, they experience more program-verification operations during the programming operation and capture more charges, so more charges will be captured in shallow energy level traps. After being soft erased, the charges captured in the shallow energy level traps escape from the storage layer, and the threshold voltage of the memory cell will decrease.

[0117] Combined with reference Figure 11 and Figure 12 When a soft erase operation is performed on the first word line WLn, the word lines other than the first word line WLn, the top select line TSL, and the bottom select line BSL can all be placed in a floating state. The word lines other than the first word line WLn, the top select line TSL, and the bottom select line BSL can be coupled to a voltage close to the first voltage V1 by the channel layer 501, thereby preventing the memory cells coupled to the unselected word lines from being soft erased. Here, before performing the soft erase operation, the voltage on all word lines can be set to the ground voltage Vss, or the word lines other than the first word line WLn can be directly floated from the power supply voltage Vdd.

[0118] In the embodiment of the present disclosure, the soft erase operation has a relatively weaker erasing effect than the erase operation of erasing a memory cell in a programmed state to an erased state. Therefore, after the soft erase operation is performed on the memory cell, only the charges trapped in the shallow energy level traps will be released from the storage layer, without having a significant impact on the charges trapped in the deep energy level traps.

[0119] In some specific examples, a first voltage V1 applied to the bit line BL and / or the common source ACS during a soft erase operation may be lower than an erase voltage applied to the bit line BL and / or the common source ACS during an erase operation on memory cells in the memory block, and a second voltage V2 applied to the first word line WLn during a soft erase operation may be higher than a voltage applied to the word line during an erase operation on memory cells in the memory block. For example, when an erase operation is performed on memory cells in the memory block, the erase voltage applied to the bit line BL and / or the common source ACS may be in a range of 17V to 20V, and the voltage applied to the word line may be in a range of -0.5V to 0.5V; when a soft erase operation is performed on the first word line WLn, the first voltage V1 applied to the bit line BL and / or the common source ACS may be in a range of 12V to 16V, and the second voltage V2 applied to the first word line WLn may be in a range of 0.6V to 1V. That is, when the erase operation is performed on the memory cell, the difference between the erase voltage and the voltage applied to the word line is greater than the difference between the first voltage V1 and the second voltage V2 when the soft erase operation is performed on the memory cell.

[0120] In some specific examples, the application time of the first voltage V1 when performing the soft erase operation may be shorter than the application time of the erase voltage when performing the erase operation on the memory cells in the memory block.

[0121] In some embodiments, the operating method of the memory device also includes: performing a fourth programming operation on the memory cell coupled to the first word line WLn, and the specific process may include: programming the memory cell in the first target programming state to the second target programming state, the threshold voltage of the memory cell in the second target programming state is greater than or equal to the second verification voltage, and the second verification voltage is less than the first verification voltage.

[0122] In some specific examples, refer to Figure 10 The fourth programming operation may be a fine programming operation. When the first target programming state is programming state P13a, the first verification voltage is Vc13, the second target programming state is P13c, and the second verification voltage is Vf13. When the first target programming state is programming state P14a, the first verification voltage is Vc14, the second target programming state is P14c, and the second verification voltage is Vf14. When the first target programming state is programming state P15a, the first verification voltage is Vc15, the second target programming state is P15c, and the second verification voltage is Vf15. In the disclosed embodiment, for memory cells in a higher programming state, the verification voltage in the coarse programming operation may be greater than the verification voltage in the fine programming operation. Therefore, when performing a soft erase operation, a larger first voltage V1 may be applied to the bit line BL and / or the common source ACS, allowing charges trapped in shallow energy level traps to be fully released.

[0123] It should be noted that in the embodiments of the present disclosure, the memory cells in the memory block are quad-level cells (QLCs), and the higher programming states are the three highest programming states among the fifteen programming states of the QLCs, but the present disclosure is not limited thereto. In other embodiments, the memory cells may be multi-level cells such as triple-level cells (TLCs) or five-level cells (PLCs), and the higher programming states may include at least the two highest programming states.

[0124] In the embodiment of the present disclosure, a soft erase operation can be performed between the coarse programming operation and the fine programming operation to allow the charges trapped in the shallow energy level traps to escape from the storage layer in advance, thereby reducing the amount of charges escaped from the shallow energy level traps after the programming operation is completed and optimizing the data retention performance of the memory device.

[0125] In some embodiments, in order to avoid program interference between adjacent word lines, the programming order of adjacent word lines can be set. Figure 8Taking the programming order in a memory block from the word line closest to the bit line BL to the word line closest to the common source ACS as an example, for the first word line WLn and the second word line WLn-1, the programming order may be: performing a second programming operation on the memory cells coupled to the second word line WLn-1, performing a first programming operation on the memory cells coupled to the first word line WLn, performing a third programming operation on the memory cells coupled to the second word line WLn-1, and performing a fourth programming operation on the memory cells coupled to the first word line WLn. The second programming operation and the first programming operation may be coarse programming operations, and the third programming operation and the fourth programming operation may be fine programming operations. Before performing the third programming operation on the memory cells coupled to the second word line WLn-1, a soft erase operation needs to be performed on the memory cells coupled to the first word line WLn.

[0126] Combined with reference Figure 11 and Figure 12 During the voltage drop phase of the soft erase operation, both the top select line TSL and the bottom select line BSL are in a floating state. The voltages on these two lines need to be coupled down through the decreasing voltage trend on the bit line BL and the common source ACS. During this process, the channel layer 501 discharges through the bit line BL and / or the common source ACS. However, before the channel layer 501 discharges to the ground voltage Vss, the top select transistor or the bottom select transistor is turned off, preventing the channel layer 501 from fully discharging and leaving residual potential in the channel layer 501. In this case, if a third programming operation is immediately performed on the memory cell coupled to the second word line WLn-1, the residual potential in the channel layer 501 may prevent the left end of the threshold voltage distribution from being tightened, resulting in a smaller window between two adjacent threshold voltage distributions. Furthermore, because the magnitude of the residual channel potential may vary across different memory cell strings, the window width may also be uneven. Here, the window between two adjacent threshold voltage distributions is the read window. The above situation will lead to problems such as a reduced read window and uneven read window width, which will increase the error rate of the read operation and reduce the reliability of the memory device.

[0127] In some embodiments, the operating method of the memory device includes: executing step S30 to perform a dummy read operation on memory cells in a memory block.

[0128] In some embodiments, the specific process of executing step S30 may include: applying a first turn-on voltage to the top selection line in the storage block and applying a ground voltage to the bit line connected to the storage block; and / or, applying a second turn-on voltage to the bottom selection line in the storage block and applying a ground voltage to the common source connected to the storage block.

[0129] In the embodiments of the present disclosure, refer to Figure 12and Figure 13 , performing a virtual read operation includes applying a first turn-on voltage Vp1 to the top selection line TSL to turn on the top selection transistor coupled to the top selection line TSL, and applying a ground voltage Vss to the bit line BL connected to the storage block, whereby the channel can be discharged in the direction of the bit line BL; and / or, applying a second turn-on voltage Vp2 to the bottom selection line BSL to turn on the bottom selection transistor coupled to the bottom selection line BSL, and applying a ground voltage Vss to the common source ACS connected to the storage block, whereby the channel can be discharged in the direction of the common source ACS.

[0130] In some embodiments, reference Figure 12 , performing a virtual read operation on the memory cells in the memory block, further comprising: applying a third turn-on voltage Vp3 to all word lines in the memory block.

[0131] In the disclosed embodiments, a dummy read operation differs from a data read operation in that the data stored in the memory cells does not need to be read out. Specifically, performing a data read operation may include applying a read voltage to a selected word line and applying a turn-on voltage to unselected word lines to turn on the memory cells connected to the unselected word lines, and determining the data stored in the memory cells based on whether the selected memory cells are turned on. Performing a dummy read operation, on the other hand, may include applying the same turn-on voltage to all word lines to turn on both the memory cells and the dummy memory cells, without further determining the read result. The purpose of the dummy read operation is to turn on the memory cell string so that the channel discharges through the bit line BL and / or ACS direction, thereby clearing the residual potential in the channel.

[0132] In some embodiments, reference Figure 13 , performing a dummy read operation on memory cells in a memory block, further comprising: applying a fourth pass voltage Vp4 to word lines coupled to programmed memory cells in the memory block; the word lines coupled to programmed memory cells include the first word line WLn; applying a fifth pass voltage Vp5 to word lines coupled to unprogrammed memory cells in the memory block; the fifth pass voltage Vp5 being less than the fourth pass voltage Vp4. Here, the word lines coupled to the unprogrammed memory cells include a dummy word line DWL and a word line WL1 among the unselected word lines, which may be a word line located between the first word line WLn and a common source ACS; and the word lines coupled to the programmed memory cells also include a word line WL2 among the unselected word lines, which may be a word line located between the first word line WLn and a bit line BL.

[0133] In the embodiment of the present disclosure, different on-voltages can be applied to programmed word lines and unprogrammed word lines when performing a virtual read operation. Since the threshold voltage of most programmed memory cells is higher than the threshold voltage of unprogrammed memory cells, a relatively small on-voltage is applied to the unprogrammed memory cells. This can avoid the influence of excessive on-voltage on the threshold voltage of the unprogrammed memory cells and can reduce the power consumption of the virtual read operation.

[0134] The above embodiment uses the example of performing a dummy read operation on all memory cells in a memory block before performing the third programming operation on the second word line WLn-1. In other embodiments, the dummy read operation may be performed on only a portion of the memory cells in the memory block. For example, the dummy read operation may be performed on the memory cells in the memory cell string first selected in the third programming operation. In other words, only the channel of the memory cell string first selected in the third programming operation is discharged. It can be understood that the residual channel potential generated during the soft erase operation has the most serious impact on the memory cells coupled to the second word line WLn-1 in the memory cell string first selected in the third programming operation. However, as the number of program-verify operations increases, the residual channel potential in other memory cell strings can be gradually released through the coupling effect. Therefore, the dummy read operation can be performed only on the memory cells in the memory cell string first selected in the third programming operation in the memory block. This improves the efficiency of the dummy read operation and further reduces the power consumption of the dummy read operation.

[0135] In the embodiments of the present disclosure, on the one hand, a soft erase operation can be performed to allow charges trapped in shallow energy level traps to be released from the storage layer in advance, thereby improving the data retention performance of the memory device; on the other hand, a virtual read operation can be performed to clear the residual potential of the channel to reduce the negative impact of the soft erase operation on the programming operation in subsequent steps, thereby avoiding as much as possible the reduction of the read window or the uneven width of the read window, thereby improving the reliability of the memory device.

[0136] Based on a concept similar to the operating method of the above-mentioned memory device, the present disclosure further provides a memory device, Figure 4 and Figure 8 The memory device 300 includes a memory array 301 and a peripheral circuit 302 coupled to the memory array 301; the memory array 301 includes at least one memory block; the memory block includes a first word line WLn and a memory cell coupled to the first word line WLn; the peripheral circuit 302 is configured to execute the operating method of the memory device in any of the above embodiments.

[0137] In some embodiments, in conjunction with reference Figure 4 and Figure 9, the peripheral circuit 302 is configured to: perform a first program operation on the memory cells coupled to the first word line WLn; perform a soft erase operation on the memory cells coupled to the first word line WLn; and perform a dummy read operation on the memory cells in the memory block.

[0138] In some embodiments, in conjunction with reference Figure 8 、 Figure 12 and Figure 13 , the storage block also includes a top selection line TSL and a bottom selection line BSL; the memory array 301 also includes a bit line BL and a common source ACS connected to the storage block; the peripheral circuit 302 is specifically configured to: when performing a virtual read operation, apply a first turn-on voltage Vp1 to the top selection line TSL, and apply a ground voltage Vss to the bit line BL; and / or, apply a second turn-on voltage Vp2 to the bottom selection line BSL, and apply a ground voltage Vss to the common source ACS.

[0139] In some embodiments, reference Figure 12 and Figure 13 The peripheral circuit 302 is specifically configured to: apply a first voltage V1 to the first word line WLn when performing a soft erase operation; apply a second voltage V2 to the bit line BL and / or the common source ACS; the first voltage V1 is less than the second voltage V2; and float the top selection line TSL, the bottom selection line BSL and all word lines except the first word line WLn in the storage block.

[0140] In some embodiments, the peripheral circuit 302 is specifically configured as follows: when executing a first programming operation, some of the multiple memory cells coupled to the first word line WLn are programmed to a first target programming state, and the threshold voltage of the memory cells in the first target programming state is greater than or equal to the first verification voltage; when executing a fourth programming operation, the memory cells in the first target programming state are programmed to a second target programming state, and the threshold voltage of the memory cells in the second target programming state is greater than or equal to the second verification voltage; the second verification voltage is less than the first verification voltage.

[0141] In some embodiments, the peripheral circuit 302 is specifically configured to: when performing a first programming operation, program some of the multiple memory cells coupled to the first word line WLn to a third target programming state, and the threshold voltage of the memory cells in the third target programming state is less than the threshold voltage of the memory cells in the first target programming state.

[0142] In an embodiment of the present disclosure, the peripheral circuitry can be configured to perform a soft erase operation on the memory cells coupled to the first word line WLn after performing a first programming operation on the memory cells. This allows charges trapped in shallow energy level traps in the memory cells to be released from the storage layer in advance, thereby improving the data retention performance of the memory device. Furthermore, for memory cells in a higher programmed state, the first verification voltage used in performing the first programming operation on them can be greater than the second verification voltage used in performing the fourth programming operation on them. This allows a higher first voltage V1 to be applied during the soft erase operation, allowing the charges trapped in the shallow energy level traps to be fully released.

[0143] In some embodiments, reference Figure 12 The peripheral circuit 302 is specifically configured to apply the third turn-on voltage Vp3 to all word lines in the memory block when performing a dummy read operation.

[0144] In some embodiments, reference Figure 13 , the peripheral circuit 302 is specifically configured as follows: when performing a virtual read operation, applying a fourth turn-on voltage Vp4 to the word line coupled to the programmed memory cell in the memory block; the word line coupled to the programmed memory cell includes the first word line WLn; applying a fifth turn-on voltage Vp5 to the word line coupled to the unprogrammed memory cell in the memory block; the fifth turn-on voltage Vp5 is less than the fourth turn-on voltage Vp4.

[0145] In some embodiments, the peripheral circuit 302 is specifically configured to perform a dummy read operation on the memory cells in the memory cell string that is first selected in the third programming operation.

[0146] In some embodiments, the peripheral circuit 302 is further configured to: perform a second programming operation on memory cells coupled to the second word line WLn-1 in the memory block before performing the first programming operation; perform a third programming operation on memory cells coupled to the second word line WLn-1 after performing the dummy read operation; and perform a fourth programming operation on memory cells coupled to the first word line WLn. Here, the first and second programming operations may be coarse programming operations, and the third and fourth programming operations may be fine programming operations.

[0147] In the disclosed embodiment, the peripheral circuitry can be configured to perform a dummy read operation on the memory cells in the memory block before performing a fine programming operation on the memory cells coupled to the second word line WLn-1. This clears any residual potential in the channel, minimizing any negative impact on the fine programming operation on the memory cells coupled to the second word line WLn-1 and preventing a reduction in the read window or uneven read window width. Furthermore, the dummy read operation can be performed only on the memory cells in the memory cell string that is first selected during the fine programming operation, further improving the efficiency of the dummy read operation.

[0148] In the disclosed embodiment, the peripheral circuit is configured to, through a soft erase operation, allow the charges trapped in the shallow energy level traps of the memory cell to escape from the storage layer in advance, thereby improving the data retention performance of the memory device, and through a virtual read operation, clear the residual potential of the channel to reduce the negative impact of the soft erase operation on the programming operation in the subsequent steps, and avoid as much as possible the reduction of the read window or the uneven width of the read window, thereby improving the reliability of the memory device.

[0149] Based on a concept similar to the above-mentioned memory device, the present disclosure further provides a memory system, which includes: at least one memory device according to any of the above-mentioned embodiments; a controller coupled to the at least one memory device and configured to control the memory device. For the specific composition and functional implementation of the memory system, please refer to the above description of the memory system. Figures 1 to 5 For the sake of brevity, the description is not repeated here.

[0150] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0151] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0152] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A method for operating a memory device, characterized in that: The memory device comprises at least one memory block; The operating method of the memory device comprises: performing a first programming operation on memory cells coupled to a first word line in the memory block; performing a soft erase operation on the memory cells coupled to the first word line; A dummy read operation is performed on memory cells in the memory block.

2. The method for operating a memory device according to claim 1, wherein: The performing of a virtual read operation on a storage unit in the storage block includes: applying a first turn-on voltage to a top selection line in the memory block, and applying a ground voltage to a bit line connected to the memory block; and / or, A second turn-on voltage is applied to a bottom selection line in the memory block, and the ground voltage is applied to a common source connected to the memory block.

3. The method for operating a memory device according to claim 2, wherein: The performing of a virtual read operation on the storage cells in the storage block further includes: A third turn-on voltage is applied to all word lines in the memory block.

4. The method for operating a memory device according to claim 2, wherein: The performing of a virtual read operation on the storage cells in the storage block further includes: Applying a fourth conduction voltage to word lines coupled to programmed memory cells in the memory block; the word lines coupled to the programmed memory cells include the first word line; A fifth turn-on voltage is applied to word lines coupled to unprogrammed memory cells in the memory block; the fifth turn-on voltage is lower than the fourth turn-on voltage.

5. The method for operating a memory device according to claim 1, wherein: The performing a soft erase operation on the memory cell coupled to the first word line includes: applying a first voltage to the first word line; Applying a second voltage to a bit line and / or a common source connected to the memory block; the first voltage is lower than the second voltage; A top selection line, a bottom selection line, and all word lines except the first word line in the memory block are floated.

6. The method for operating a memory device according to claim 1, wherein: The operating method of the memory device further includes: Before performing the first programming operation, performing a second programming operation on memory cells coupled to a second word line in the memory block; After performing the dummy read operation, performing a third program operation on the memory cells coupled to the second word line; A fourth program operation is performed on memory cells coupled to the first word line.

7. The method for operating a memory device according to claim 6, wherein: The performing of a virtual read operation on a storage unit in the storage block includes: The dummy read operation is performed on memory cells in a memory cell string that is first selected in the third program operation.

8. The method for operating a memory device according to claim 6, wherein: The performing a first programming operation on the memory cells coupled to the first word line in the memory block includes: Programming some of the memory cells coupled to the first word line to a first target programming state, wherein a threshold voltage of the memory cells in the first target programming state is greater than or equal to a first verification voltage; The performing a fourth programming operation on the memory cells coupled to the first word line includes: The memory cell in the first target programming state is programmed to a second target programming state, wherein the threshold voltage of the memory cell in the second target programming state is greater than or equal to a second verification voltage; the second verification voltage is less than the first verification voltage.

9. The method for operating a memory device according to claim 8, wherein: The performing a first programming operation on the memory cells coupled to the first word line in the memory block further includes: Some of the memory cells coupled to the first word line are programmed to a third target program state, wherein a threshold voltage of the memory cells in the third target program state is lower than a threshold voltage of the memory cells in the first target program state.

10. A memory device, characterized in that: The memory device includes a memory array and a peripheral circuit coupled to the memory array; the memory array includes at least one memory block; the memory block includes a first word line and a memory cell coupled to the first word line; the peripheral circuit is configured to: performing a first programming operation on memory cells coupled to the first word line; performing a soft erase operation on the memory cells coupled to the first word line; A dummy read operation is performed on memory cells in the memory block.

11. The memory device according to claim 10, wherein: The memory block further includes a top selection line and a bottom selection line; the memory array further includes a bit line and a common source connected to the memory block; the peripheral circuit is specifically configured as follows: When performing the dummy read operation, applying a first turn-on voltage to the top selection line and applying a ground voltage to the bit line; and / or, A second turn-on voltage is applied to the bottom selection line, and the ground voltage is applied to the common source.

12. The memory device according to claim 11, wherein: The peripheral circuit is specifically configured as follows: When performing the dummy read operation, a third turn-on voltage is applied to all word lines in the memory block.

13. The memory device according to claim 11, wherein: The peripheral circuit is specifically configured as follows: When performing the dummy read operation, applying a fourth turn-on voltage to a word line coupled to a programmed memory cell in the memory block; The word lines coupled to the programmed memory cells include the first word lines; applying a fifth turn-on voltage to a word line coupled to an unprogrammed memory cell in the memory block; The fifth conduction voltage is lower than the fourth conduction voltage.

14. The memory device according to claim 11, wherein: The peripheral circuit is specifically configured as follows: When performing the soft erase operation, applying a first voltage to the first word line; applying a second voltage to the bit line and / or the common source; wherein the first voltage is less than the second voltage; The top select line, the bottom select line, and all word lines except the first word line in the memory block are floated.

15. The memory device according to claim 10, wherein: The peripheral circuit is further configured to: Before performing the first programming operation, performing a second programming operation on memory cells coupled to a second word line in the memory block; After performing the dummy read operation, performing a third program operation on the memory cells coupled to the second word line; A fourth program operation is performed on memory cells coupled to the first word line.

16. The memory device according to claim 15, wherein: The peripheral circuit is specifically configured as follows: The dummy read operation is performed on memory cells in a memory cell string that is first selected in the third program operation.

17. The memory device according to claim 15, wherein: The peripheral circuit is specifically configured as follows: When performing the first programming operation, programming some memory cells among the plurality of memory cells coupled to the first word line to a first target programming state, wherein a threshold voltage of the memory cells in the first target programming state is greater than or equal to a first verification voltage; When performing the fourth programming operation, the memory cell in the first target programming state is programmed to a second target programming state, and the threshold voltage of the memory cell in the second target programming state is greater than or equal to a second verification voltage; the second verification voltage is less than the first verification voltage.

18. The memory device according to claim 17, wherein: The peripheral circuit is specifically configured as follows: When performing the first programming operation, some of the multiple memory cells coupled to the first word line are programmed to a third target programming state, and the threshold voltage of the memory cells in the third target programming state is lower than the threshold voltage of the memory cells in the first target programming state.

19. A memory system, characterized in that: include: at least one memory device according to any one of claims 10 to 18; A controller is coupled to at least one of the memory devices and is configured to control the memory device.

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