Scan register circuit and memory device including the same

Abstract

The invention provides a scan register circuit and a memory device including the same. The memory device includes: a memory cell array configured to store data; a page buffer circuit configured to store data in the memory cell array or read data stored in the memory cell array; and a scan register circuit configured to receive a pass / fail result of the data from the page buffer circuit and store the pass / fail result in a plurality of scan registers. The scan register circuit acquires information on the scan register in which the failure result is stored by a scan operation, and uses the information on the scan register in which the failure result is stored to determine a number of failed bits and / or a position index indicating positions of the failed bits according to an operation mode.

Description

Technical Field

[0001] Example embodiments of the present disclosure described herein relate to a semiconductor memory device, and more particularly, to a scan register circuit that performs a fail bit count operation or a location search operation depending on an operation mode, and a memory device including the scan register circuit. Background Art

[0002] For example, semiconductor memory can be categorized as either volatile memory or nonvolatile memory. Generally, volatile memory (e.g., dynamic random access memory (DRAM) or static random access memory (SRAM)) can exhibit faster read and / or write speeds compared to nonvolatile memory. However, when power to the volatile memory is turned off, the data stored in the volatile memory may disappear. In contrast, nonvolatile memory can retain data even when power is turned off.

[0003] Flash memory is a representative example of non-volatile memory. Flash memory can be used as a storage device in electronic devices such as, but not limited to, computers, smartphones, and digital cameras. Flash memory can store two or more bits of multi-bit data in a single memory cell. Depending on the threshold voltage distribution, flash memory can have at least one erased state and multiple programmed (e.g., written) states.

[0004] Flash memory may include a page buffer circuit for storing data in a memory cell array or reading data stored in the memory cell array. The flash memory can obtain pass / fail results of the data from the page buffer circuit and correct errors caused by failed bits. The flash memory needs to accurately determine the number and location of failed bits to effectively correct errors caused by failed bits. Summary of the Invention

[0005] Example embodiments of the present disclosure provide a scan register circuit that performs a fail bit counting operation or a position search operation according to an operation mode, and a memory device including the scan register circuit.

[0006] According to an embodiment, a memory device includes: a memory cell array configured to store data; a page buffer circuit configured to store data in the memory cell array or read data stored in the memory cell array; and a scan register circuit configured to receive pass / fail results of the data from the page buffer circuit and store the pass / fail results in a plurality of scan registers. The scan register circuit acquires information about scan registers storing fail results among the plurality of scan registers through a scan operation, and uses the information about the scan registers storing the fail results to determine the number of fail bits and / or a position index indicating the location of the fail bits according to an operation mode.

[0007] According to an embodiment, a scan register circuit of a memory device includes: a scan register array configured to include multiple scan chain units, each scan chain unit having multiple scan registers, each scan register storing a pass / fail result of data; and a fail bit output circuit configured to determine the number of fail bits and / or a position index indicating the location of the fail bit according to an operation mode. The fail bit output circuit obtains information about a scan register storing a fail result among the multiple scan registers through a scan operation of the multiple scan registers, and uses the information of the scan register storing the fail result to determine the number of fail bits or the position index.

[0008] According to an embodiment, a scan register circuit of a memory device includes: a scan register array, which is configured to have multiple scan chain units, each scan chain unit has multiple scan registers, and each scan register stores a pass / fail result of data; a bit counter, which is configured to receive a scan chain output signal of each scan chain unit in a fail bit counting mode and determine the number of fail bits; and a location finder, which is configured to receive a scan chain output signal and a scan register output signal of each scan chain unit in a location search mode and determine a location index indicating the location of the fail bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram illustrating an example embodiment of a storage device according to the present disclosure.

[0011] Figure 2 It is an icon Figure 1 A block diagram of an example embodiment of a memory device is illustrated in FIG.

[0012] Figure 3 It is an icon Figure 2A circuit diagram of an example embodiment of a memory block BLK1 of a memory cell array is illustrated.

[0013] Figure 4 It is an icon Figure 3 Illustrated is a circuit diagram of a cell string selected by a first string selection line SSL1 from among cell strings of a memory block BLK1 .

[0014] Figure 5 It is an icon Figure 4 FIG. 5 is a diagram of an example embodiment of a threshold voltage distribution of a memory cell illustrated in FIG.

[0015] Figure 6 It is an icon Figure 2 A block diagram of an example embodiment of a scan register circuit is shown.

[0016] Figure 7 and Figure 8 It is an icon Figure 6 A circuit diagram of an exemplary embodiment of a first scan chain unit is shown.

[0017] Figure 9 Is used to illustrate Figure 6 A diagram showing the operating mode of the scan register circuit.

[0018] Figure 10 It is an icon Figure 8 FIG. 1 is a circuit diagram of an exemplary embodiment of a method for operating a first scan chain unit in a failed bit counting mode.

[0019] Figure 11 It is illustrated by way of example Figure 6 A conceptual diagram of the failed bit counting operation of the scan register circuit shown in FIG.

[0020] Figures 12 to 14 is a diagram illustrating an example embodiment of a fail bit counting operation during first to third cycles.

[0021] Figure 15 is a timing diagram illustrating an example embodiment of a fail bit counting operation during first to third cycles.

[0022] Figure 16 It is an icon Figure 6 A conceptual diagram of an example embodiment of a location search operation of a scan register circuit is shown.

[0023] Figure 17 Is used to illustrate Figure 16 A block diagram of the location search operation of the scan register circuit is shown.

[0024] Figure 18 and Figure 19 Is used to illustrate Figure 17A diagram showing the operation of a 16x4 encoder and an 8x3 encoder.

[0025] Figure 20 It is an icon Figure 17 A circuit diagram of an example embodiment of a position search mode of a first scan chain unit is shown.

[0026] Figures 21 to 25 It is shown in the figure Figure 17 A diagram of an example embodiment of a position search mode during the first to fifth cycles of a scan register circuit is shown.

[0027] Figure 26 It is shown in the figure Figure 17 FIG. 4 is a timing diagram of a position search mode during the first to fifth cycles of the scan register circuit shown.

[0028] Figure 27 is a diagram illustrating an example embodiment of a memory device having a multi-stack structure.

[0029] Figure 28 is a block diagram illustrating an example of implementing a storage device according to an embodiment of the present disclosure using a solid state drive (SSD). DETAILED DESCRIPTION

[0030] Hereinafter, exemplary embodiments of the present disclosure will be described in detail and clearly to such an extent that a person having ordinary skill in the art can easily implement the inventive concept.

[0031] Figure 1 1 is a block diagram illustrating an example embodiment of a storage device according to the present disclosure. The storage device 1000 may be a flash storage device based on a flash memory. For example, the storage device 1000 may be implemented as a solid state drive (SSD), a universal flash memory (UFS), a memory card, etc.

[0032] refer to Figure 1 , the memory device 1000 may include a memory device 1100 and a memory controller 1200. The memory device 1100 may receive an input / output signal IO from the memory controller 1200 via an input / output line, a control signal CTRL via a control line, and external power PWR via a power line. The memory device 1000 may store data in the memory device 1100 under the control of the memory controller 1200.

[0033] The memory device 1100 may include a memory cell array 1110 and a peripheral circuit 1115. The memory cell array 1110 may have a vertical 3D structure. The memory cell array 1110 may include a plurality of memory cells. Each memory cell may store multiple bits of data.

[0034] In terms of design layout structure, the memory cell array 1110 may be located (eg, disposed) next to or above the peripheral circuit 1115. The structure in which the memory cell array 1110 is located above the peripheral circuit 1115 may be referred to as a cell-on-periphery (COP) structure.

[0035] The memory cell array 1110 may be manufactured as a separate chip from the peripheral circuit 1115. The upper chip including the memory cell array 1110 and the lower chip including the peripheral circuit 1115 may be connected to each other by a bonding method. This structure may be referred to as a chip-to-chip (C2C) structure.

[0036] The peripheral circuit 1115 may include analog circuits and / or digital circuits required to store or read data in the memory cell array 1110. The peripheral circuit 1115 may receive external power PWR through a power line and generate various levels of internal power.

[0037] The peripheral circuit 1115 may receive commands, addresses, and / or data from the memory controller 1200 through an input / output line. The peripheral circuit 1115 may store data in the memory cell array 1110 according to the control signal CTRL. Alternatively or additionally, the peripheral circuit 1115 may read data stored in the memory cell array 1110 and provide the read data to the memory controller 1200.

[0038] The peripheral circuit 1115 may include a scan register circuit 2000. The scan register circuit 2000 may have a fail bit count mode and a position search mode. The scan register circuit 2000 may have multiple scan chain units, and each scan chain unit may have multiple scan registers. The pass / fail result of the data stored in the memory cell array 1110 may be stored in each scan register. The scan register circuit 2000 may determine the number and location of fail bits using the fail bit count mode and / or the position search mode.

[0039] Figure 2 It is an icon Figure 1 A block diagram of an example embodiment of a memory device is shown in FIG. Figure 2 , the memory device 1100 may include a memory cell array 1110 and a peripheral circuit 1115 (see Figure 1 The peripheral circuit 1115 may include an address decoder 1120 , a page buffer circuit 1130 , a data input / output circuit 1140 , a word line voltage generator 1150 , and a control logic 1160 .

[0040] The memory cell array 1110 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may include a plurality of pages. Each page may include a plurality of memory cells. Each memory cell may store multi-bit data (e.g., two or more bits). Each memory block may correspond to an erase unit, and each page may correspond to a read and / or write unit.

[0041] Memory cell array 1110 can be formed perpendicular to the substrate. Gate electrode layers and insulating layers can be alternately deposited on the substrate. Each memory block (e.g., BLK1) can be connected to one or more string select lines SSL, multiple word lines WL1 to WLm, and one or more ground select lines GSL. Word line WLk is the selected word line sWL, and the remaining word lines (WL1 to WLk-1, WLk+1 to WLm) are unselected word lines uWL.

[0042] The address decoder 1120 can be connected to the memory cell array 1110 through the select line SSLGSL and the word lines WL1 to WLm. The address decoder 1120 can select a word line during a program or read operation. The address decoder 1120 can receive a word line voltage VWL from the word line voltage generator 1150 and provide a program voltage or a read voltage to the selected word line.

[0043] The page buffer circuit 1130 may be connected to the memory cell array 1110 via bit lines BL1 to BLz. The page buffer circuit 1130 may temporarily store data to be stored in the memory cell array 1110 or data read from the memory cell array 1110. The page buffer circuit 1130 may include page buffers PB1 to PBz connected to corresponding bit lines. Each page buffer may include a plurality of latches to store or read multi-bit data.

[0044] The input / output circuit 1140 may be internally connected to the page buffer circuit 1130 through data lines, and externally connected to the memory controller 1200 through input / output lines IO1 to Ion (refer to FIG. Figure 1 ). The input / output circuit 1140 may receive program data from the memory controller 1200 during a program operation. Also, the input / output circuit 1140 may provide data read from the memory cell array 1110 to the memory controller 1200 during a read operation.

[0045] The word line voltage generator 1150 may receive internal power from the control logic 1160 and generate a word line voltage VWL required for reading or writing data. The word line voltage VWL may be provided to a selected word line sWL or an unselected word line uWL through the address decoder 1120 .

[0046] The word line voltage generator 1150 may include a program voltage generator 1151 and a pass voltage generator 1152. The program voltage generator 1151 may generate a program voltage Vpgm supplied to a selected word line sWL during a program operation, and the pass voltage generator 1152 may generate a pass voltage Vpass supplied to the selected word line sWL and the unselected word lines uWL.

[0047] The word line voltage generator 1150 may include a read voltage generator 1153 and a read pass voltage generator 1154. The read voltage generator 1153 may generate a select read voltage Vrd supplied to the selected word line sWL during a read operation. The read pass voltage generator 1154 may generate a read pass voltage Vrdps supplied to the unselected word lines uWL. The read pass voltage Vrdps may be a voltage sufficient to turn on the memory cells connected to the unselected word lines uWL during a read operation.

[0048] The control logic 1160 may control operations such as read, write, and erase of the memory device 1100 using a command CMD, an address ADDR, and a control signal CTRL provided from the memory controller 1200. The address ADDR may include a block select address for selecting a memory block, a row address for selecting a page, and a column address for selecting a memory cell.

[0049] The scan register circuit 2000 may receive the pass / fail result P / F[i] from the page buffer circuit 1130 and output a fail bit count signal (FBC) and / or a position index signal (PI). The memory device 1100 according to an embodiment of the present disclosure may use the scan register circuit 2000 to determine the number and position of fail bits.

[0050] Figure 3 It is an icon Figure 2 A circuit diagram of an example embodiment of a memory block BLK1 of a memory cell array is shown. Figure 3 In the memory block BLK1, a plurality of cell strings STR11 to STR8z may be formed between bit lines BL1 to BLz and a common source line CSL. Each cell string includes a string selection transistor SST, a plurality of memory cells MC1 to MCm, and a ground selection transistor GST.

[0051] String selection transistors SST may be connected to string selection lines SSL1 to SSL8 , ground selection transistors GST may be connected to ground selection lines GSL1 to GSL8 , string selection transistors SST may be connected to bit lines BL1 to BLz, and ground selection transistors GST may be connected to a common source line CSL.

[0052] The first to mth word lines WL1 to WLm may be connected to a plurality of memory cells MC1 to MCm in a row direction. The first to zth bit lines BL1 to BLz may be connected to a plurality of memory cells MC1 to MCm in a column direction. The first to zth page buffers PB1 to PBz may be connected to the first to zth bit lines BL1 to BLz.

[0053] The first word line WL1 may be positioned above the first to eighth ground selection lines GSL1 to GSL8. A first memory cell MC1 positioned at the same height from the substrate may be connected to the first word line WL1. The mth word line WLm may be positioned below the first to eighth string selection lines SSL1 to SSL8. The mth memory cell MCm positioned at the same height from the substrate may be connected to the mth word line WLm. Second memory cells MC2 to the (m-1)th memory cell MCm-1 positioned at the same height from the substrate may be connected to the second to (m-1)th word lines WL2 to WLm-1, respectively.

[0054] Figure 4 It is an icon Figure 3 Illustrated is a circuit diagram of a cell string selected by a first string selection line SSL1 from among cell strings of a memory block BLK1 .

[0055] The 11th to 1zth cell strings STR11 to STR1z may be selected by a first string selection line SSL1. The 11th to 1zth cell strings STR11 to STR1z may be connected to the first to zth bit lines BL1 to BLz, respectively. The first to zth page buffers PB1 to PBz may be connected to the first to zth bit lines BL1 to BLz, respectively.

[0056] The 11th cell string STR11 may be connected to a first bit line BL1 and a common source line CSL. The 11th cell string STR11 may include a string selection transistor SST selected by a first string selection line SSL1, first to mth memory cells MC1 to MCm connected to first to mth word lines WL1 to WLm, and a ground selection transistor GST selected by a first ground selection line GSL1. The 12th cell string STR12 may be connected to a second bit line BL2 and a common source line CSL. The 1zth cell string STR1z may be connected to a zth bit line BLz and a common source line CSL.

[0057] The first word line WL1 and the mth word line WLm may be edge word lines (edge ​​WL). The second word line WL2 and the m-1th word line WLm-1 may be edge adjacent word lines. The kth word line WLk may be the selected word line sWL. The k-1th word line WLk-1 and the k+1th word line WLk+1 may be adjacent word lines adjacent to the selected word line. If the kth word line WLk is the selected word line sWL, the remaining word lines WL1 to WLk and WLk+1 to WLm may be unselected word lines uWL.

[0058] The first memory cell MC1 and the mth memory cell MCm may be edge memory cells. The second memory cell MC2 and the m-1th memory cell MCm-1 may be edge-adjacent memory cells. The kth memory cell MCk may be the selected memory cell sMC. The k-1th memory cell MCk-1 and the k+1th memory cell MCk+1 may be memory cells adjacent to the selected memory cell (neighboring MCs). If the kth memory cell MCk is the selected memory cell sMC, the remaining memory cells MC1 to MCk-1, and MCk+1 to MCm may be unselected memory cells uMC.

[0059] A group of memory cells selected by one string select line and connected to one word line can be a page. For example, memory cells selected by the first string select line SSL1 and connected to the kth word line WLk can be a page. For example, eight pages can be configured on the kth word line WLk. Of the eight pages, the page connected to the first string select line SSL1 is a selected page, and the pages connected to the second to eighth string select lines SSL2 to SSL8 are unselected pages.

[0060] The first word line WL1 is a first edge word line (Edge1 WL), and the second word line WL2 is a first edge adjacent word line (Edge1 adjacent WL). The mth word line WLm is a second edge word line (Edge2 WL), and the m-1th word line WLm-1 is a second edge adjacent word line (Edge2 adjacent WL). The word lines between the first edge adjacent word line and the second edge adjacent word line are intermediate word lines. For example, the kth word line WLk (k=3 to m-2) between the second word line WL2 and the m-1th word line WLm-1 is an intermediate word line.

[0061] In a read operation, if the second word line WL2 is the selected word line sWL, the remaining word lines may be unselected word lines uWL. The second word line WL2 may be the first edge adjacent word line (Edge1 adjacent WL). The second memory cell MC2 may be the selected memory cell sMC. The remaining memory cells may be unselected memory cells uMC.

[0062] If the m-1th word line WLm-1 is the selected word line sWL, the remaining word lines may be unselected word lines uWL. The m-1th word line WLm-1 may be the second edge-adjacent word line. The m-1th memory cell MCm-1 may be the selected memory cell sMC. The remaining memory cells may be unselected memory cells uMC.

[0063] Figure 5 It is an icon Figure 4 . The horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of memory cells.

[0064] Figure 5 An example of storing 3 bits of data in one memory cell is shown. Depending on the threshold voltage distribution, the 3-bit memory cell can have one of eight states (E0, P1 to P7). E0 represents the erased state, and P1 to P7 represent the programmed states.

[0065] During a read operation, select read voltages Vrd1 to Vrd7 may be applied to the selected word line sWL, and a pass voltage Vps and / or a read pass voltage Vrdps may be applied to the unselected word line uWL. The pass voltage Vps and / or the read pass voltage Vrdps may be sufficient to turn on the memory cell. For example, the pass voltage Vps may be applied to the adjacent word line WLk±1, and the read pass voltage Vrdps may be applied to the unselected word line other than the adjacent word line.

[0066] The first selection read voltage Vrd1 may be a voltage level between the erase state E0 and the first program state P1. The second selection read voltage Vrd2 may be a voltage level between the first program state P1 and the second program state P2. In this manner, the seventh selection read voltage Vrd7 may be a voltage level between the sixth program state P6 and the seventh program state P7.

[0067] When a first selection read voltage Vrd1 is applied, memory cells in the erased state E0 can be turned on, and memory cells in the first to seventh programming states P1 to P7 can be turned off. When a second selection read voltage Vrd2 is applied, memory cells in the erased state E0 and the first programming state P1 can be turned on, and memory cells in the second to seventh programming states P2 to P7 can be turned off. In this way, when a seventh selection read voltage Vrd7 is applied, memory cells in the erased state E0 and the first to sixth programming states P1 to P6 can be turned on, and memory cells in the seventh programming state P7 can be turned off.

[0068] During a read operation, the kth word line WLk may be selected. A power supply voltage may be applied to the string select line SSL1 and the ground select line GSL1, and the string select transistor SST and the ground select transistor GST may be turned on. In addition, a select read voltage Vrd may be applied to the selected word line sWL, and a read pass voltage Vrdps and / or a pass voltage Vps may be applied to the unselected word lines uWL.

[0069] When the read operation of the kth word line WLk is repeatedly performed, the high voltage read pass voltage Vrdps can be repeatedly provided to the remaining word lines. At this time, read interference may occur in the remaining word lines, and thus the threshold voltage may be distorted. When the select read voltage is provided, the memory cell connected to the kth word line WLk can be an OFF cell. That is, when the threshold voltage of the kth memory cell is higher than the select read voltage, the kth memory cell can be an OFF cell. When the kth memory cell is an OFF cell, the channel can be separated at the kth memory cell. That is, the lower channel of the kth memory cell can receive the ground voltage from the common source line CSL, and the upper channel of the kth memory cell can have a negative channel voltage.

[0070] A channel voltage difference may occur between the lower channel and the upper channel between which the kth memory cell is interposed. Due to the channel voltage difference, hot carrier injection (HCI) may occur in adjacent memory cells MCk+1 and / or MCk-1. As a result, the threshold voltages of memory cells connected to adjacent word lines WLk+1 and / or WLk+1 may be distorted. For example, the threshold voltage of a memory cell in the erased state E0 may rise to enter a programmed state.

[0071] Figure 6 It is an icon Figure 2 A block diagram of an example embodiment of a scan register circuit is shown. Figure 6 The scan register circuit 2000 may include a scan register array 2100 and a fail bit output circuit 2200. The fail bit output circuit 2200 may include a bit counter 2300 and a position finder 2400.

[0072] The scan register array 2100 may include a plurality of scan chain units. For example, the scan register array 2100 may include a first scan chain unit SC01 to a sixteenth scan chain unit SC16. Each scan chain unit may include a pulse gate PG, a scan register, and a priority filter PF.

[0073] For example, the first scan chain unit SC01 may include a first pulse gate PG1, first scan registers 00 to 07, and a first priority filter PF1. The second scan chain unit SC02 may include a second pulse gate PG2, second scan registers 08 to 0F, and a second priority filter PF2. Similarly, the sixteenth scan chain unit SC16 may include a sixteenth pulse gate PG16, sixteenth scan registers 78 to 7F, and a sixteenth priority filter PF16.

[0074] Each scan chain unit can have the same or similar internal configuration and operating principle. Hereinafter, the internal configuration and operating principle of the first scan chain unit SC01 will be described. The first pulse gate PG1 of the first scan chain unit SC01 can receive a clear pulse CP from the control logic 1160 and provide a clock signal to the first scan registers 00 to 07.

[0075] The pass / fail results P / F[i] of the data of the page buffers may be input to the first scan registers 00 to 07. For example, the pass / fail results of the data of the first to eighth page buffers PB1 to PB8 may be input to the first scan registers 00 to 07 of the first scan chain unit SC01. The pass / fail result P / F[1] of the data of the first page buffer PB1 may be input to the scan register 00.

[0076] The pass / fail results of the data of the ninth to sixteenth page buffers PB9 to PB16 can be input to the second scan registers 08 to 0F of the second scan chain unit SC02. The pass / fail results of the data of the seventeenth to twenty-fourth page buffers PB17 to PB24 can be input to the third scan registers 10 to 17 of the third scan chain unit SC03. In this way, the pass / fail results can also be input to the scan register of the sixteenth scan chain unit SC16.

[0077] The bit counter 2300 may receive the scan chain output signal SCO from the first to sixteenth scan chain units SC01 to SC16 and determine a fail bit count FBC. Additionally, the bit counter 2300 may receive the scan chain output signal SCO from the first to sixteenth scan chain units SC01 to SC16 and output a SCO pass signal SCOP.

[0078] The position finder 2400 may receive scan chain output signals SCO and scan register output signals SRO from the first to sixteenth scan chain units SC01 to SC16 and may detect the position of a fail bit and output a position index signal PI[n].

[0079] A scan register circuit of a memory device according to an example embodiment of the present disclosure may include a scan register array 2100 and a fail bit output circuit 2200. The scan register array 2100 may have multiple scan chain units, each of which may have multiple scan registers, and each scan register may store a pass / fail result for data. The fail bit output circuit 2200 may obtain information about the scan registers storing the fail results through a scan operation of the multiple scan registers. The fail bit output circuit 2200 may use the information about the scan registers storing the fail results to determine the number of fail bits according to the operation mode. A position index indicating the position of the fail bit may be determined.

[0080] Figure 7 and Figure 8 It is an icon Figure 6 FIG. 1 is a circuit diagram of an exemplary embodiment of a first scan chain unit. Figure 7 and Figure 8 The first scan chain unit SC01 may include a first pulse gate PG1 , first scan registers 00 to 07 , a first priority filter PF1 , and a scan register output circuit 2110 .

[0081] The first pulse gate PG1 can receive the clear pulse CP and the first scan chain output signal SCO1 and perform an AND logic operation. For example, the first pulse gate PG1 may include a first AND gate AND1. The first AND gate AND1 can receive the clear pulse CP and the first scan chain output signal SCO1 and generate a clock signal. The clock signal can be provided to the first scan registers 00 to 07.

[0082] The scan register 00 may include a first DQ flip-flop DQ1 and a first multiplexer MX1. The first DQ flip-flop DQ1 may include a D terminal, a CK terminal, an R terminal, and a Q terminal. The D terminal may be connected to a power supply terminal, and the CK terminal may be connected to an output terminal of a first pulse gate PG1. The first DQ flip-flop DQ1 may receive a power supply voltage VCC through the D terminal, a clock signal through the CK terminal, and a reset signal through the R terminal. The first DQ flip-flop DQ1 may output an output signal through the Q terminal.

[0083] A first multiplexer MX1 ​​may include a P terminal and an F terminal. The P terminal may be connected to a power supply terminal, and the F terminal may be connected to a Q terminal of a first DQ flip-flop DQ1. The first multiplexer MX1 ​​may receive a first pass / fail result P / F[1], select one of the P terminal and the F terminal, and connect it to a first node N1. For example, if the first pass / fail result P / F[1] is pass, the P terminal may be connected to the first node N1. And if the first pass / fail result P / F[1] is fail, the F terminal may be connected to the first node N1.

[0084] The scan register 01 may include a second DQ flip-flop DQ2 and a second multiplexer MX2. The D terminal of the second DQ flip-flop DQ2 may be connected to the first node N1. The second DQ flip-flop DQ2 may receive a clock signal through the CK terminal and a reset signal through the R terminal. The second DQ flip-flop DQ2 may output an output signal through the Q terminal.

[0085] The P terminal of the second multiplexer MX2 can be connected to the first node N1, and the F terminal can be connected to the Q terminal of the second DQ flip-flop DQ2. The second multiplexer MX2 can receive the second pass / fail result P / F[2], select one of the P terminal and the F terminal, and connect it to the second node N2. For example, if the second pass / fail result P / F[2] is pass, the P terminal can be connected to the second node N2. And if the second pass / fail result P / F[2] is fail, the F terminal can be connected to the second node N2.

[0086] The scan register 07 may include an eighth DQ flip-flop DQ8 and an eighth multiplexer MX8. The D terminal of the eighth DQ flip-flop DQ8 may be connected to the seventh node N7. The eighth DQ flip-flop DQ8 may receive a clock signal through the CK terminal and a reset signal through the R terminal. The eighth DQ flip-flop DQ8 may output an output signal through the Q terminal.

[0087] The P terminal of the eighth multiplexer MX8 can be connected to the seventh node N7, and the F terminal can be connected to the Q terminal of the eighth DQ flip-flop DQ8. The eighth multiplexer MX8 can receive the eighth pass / fail result P / F[8], select one of the P terminal and the F terminal, and connect it to the eighth node N8. For example, if the eighth pass / fail result P / F[8] is pass, the P terminal can be connected to the eighth node N8. And if the eighth pass / fail result P / F[8] is fail, the F terminal can be connected to the eighth node N8.

[0088] The first scan chain unit SC01 may include a first inverter INV1 between an eighth node N8 and a ninth node N9. The first inverter INV1 may invert a result of the eighth node N8 and output a first chain fail signal CF1.

[0089] The first priority filter PF1 may include multiple logic operation circuits. For example, the first priority filter PF1 may include a first OR gate OR1, a second AND gate AND2, and a third AND gate AND3. The first OR gate OR1 may receive a default low priority parameter LWP0 and a mode signal MODE as inputs and provide an OR operation result to the tenth node N10.

[0090] One of the input terminals of the second AND gate AND2 may be connected to the eighth node N8, and the other input terminal may receive the default low priority parameter LWP0 and output the first low priority parameter LWP1. One of the input terminals of the third AND gate AND3 may receive the first chain fail signal CF1 through the ninth node N9, and the other input terminal may be connected to the tenth node N10. The third AND gate AND3 may output the first scan chain output signal SCO1.

[0091] The scan register output circuit 2110 may include an AND logic operation circuit and multiple selection circuits. The selection circuits may be tri-state buffers that selectively output signals based on a switching control signal. For example, the scan register output circuit 2110 may include a fourth AND gate AND4 and first through eighth tri-state buffers TB1 through TB8. The fourth AND gate AND4 may receive the dump signal DUMP and the first scan chain output signal SCO1 and provide a tri-state switching signal TSW to the first through eighth tri-state buffers TB1 through TB8.

[0092] Each of the first through eighth tri-state buffers TB1 through TB8 can have three output states. For example, each tri-state buffer can output logic 1, logic 0, and high resistance (z) based on a tri-state switching signal TSW. If the tri-state switching signal TSW is 0, high resistance (z) can be output regardless of the input. If the tri-state switching signal TSW is 1, the inverted version of the input signal can be output. Each of the first through eighth tri-state buffers TB1 through TB8 can output SRO[7:0].

[0093] Each scan chain unit according to an example embodiment of the present disclosure may include: a pulse gate that receives a clear pulse CP and outputs a clock signal; a plurality of scan registers that perform a scan chain operation in response to the clock signal of the pulse gate; and a priority filter that receives scan chain operation results from the plurality of scan registers and outputs a scan chain output signal.

[0094] Figure 9 Is used to illustrate Figure 6 The diagram shows the operating mode of the scan register circuit. Figure 9 The scan register circuit 2000 may have a fail bit counting mode and a position search mode. In the fail bit counting mode, the mode signal MODE may be 1 and the dump signal DUMP may be 0. In the position search mode, the mode signal MODE may be 0 and the dump signal DUMP may be 1.

[0095] When the operation mode is the failed bit counting mode, the bit counter 2300 (see Figure 6 ) can receive information of a scan register storing a fail result from each scan chain unit and determine the number of fail bits.

[0096] When the operation mode is the location search mode, the location finder 2400 (see Figure 6 ) can receive information of a scan register storing a fail result and information of a scan register in which a fail result is first stored from each scan chain unit, and the location finder 2400 can determine a location index indicating a location of a fail bit.

[0097] Figure 10 It is an icon Figure 8 FIG. 1 is a circuit diagram of an exemplary embodiment of an operation method of the first scan chain unit in a failed bit counting mode. Figure 10 In the example of , the first pass / fail result P / F[1] is 0, the fourth pass / fail result P / F[4] is 1, and the eighth pass / fail result P / F[8] is 0.

[0098] In the fail bit counting mode, the mode signal MODE is 1 and the dump signal DUMP is 0. The first to eighth DQ flip-flops DQ1 to DQ8 can all be reset by the reset signal (see Figure 15 , RST) is initialized. The reset signal RST may be provided to R terminals of the first to eighth DQ flip-flops DQ1 to DQ8.

[0099] If the first pass / fail result P / F[1] is 0, the P terminal of the first multiplexer MX1 ​​may be connected to the first node N1. The first node N1 may have a logic 1 because it is connected to the power supply terminal. If the fourth pass / fail result P / F[4] is 1, the F terminal of the fourth multiplexer MX4 may be connected to the fourth node N4. Since the fourth DQ flip-flop DQ4 is initialized by the reset signal RST, the fourth node N4 may have a logic 0. If the eighth pass / fail result P / F[8] is 0, the P terminal of the eighth multiplexer MX8 may be connected to the seventh node N7. The eighth node N8 may have a logic 0.

[0100] If the dump signal DUMP is 0, the tristate switching signal TSW is 0. If the tristate switching signal TSW is 0, the outputs of the first to eighth tristate buffers TB1 to TB8 may have high resistance (z) regardless of the input. Therefore, the scan register output signal SRO may not be output.

[0101] If the mode signal MODE is 1, the output of the first OR gate OR1 in the first priority filter PF1 is always 1. That is, the tenth node N10 may have a logic 1. Therefore, the output of the third AND gate AND3 may have the same value as the logic value of the ninth node N9. That is, the first scan chain output signal SCO1 may be equal to the first chain fail signal CF1. If the first chain fail signal CF1 is 1, the first scan chain output signal SCO1 may be 1.

[0102] If the default low priority parameter LWP0 is 1, the first low priority parameter LWP1 may be equal to the logic value of the eighth node N8. If the eighth node N8 is logic 0, the first low priority parameter LWP1 may be logic 0.

[0103] Figure 11 It is an icon Figure 6 A conceptual diagram of an example embodiment of a failed bit counting operation of a scan register circuit is shown. Figure 11 , the first scan registers 00 to 07 of the first scan chain unit SC01 may have pass / fail results of 0, 0, 0, 1, 1, 0, 0, 0, respectively. Figure 10 As shown, the first scan chain unit SC01 may have a first chain fail signal CF1 of logic 1. The first scan chain output signal SCO1 of the first priority filter PF1 may be logic 1.

[0104] The second scan registers 08 to 0F of the second scan chain unit SC02 may respectively have pass / fail results of 0, 0, 0, 0, 0, 0, 0, 0. Since all the second scan chain units SC02 are passed, the second chain fail signal CF2 may be logic 0. The second scan chain output signal SCO2 of the second priority filter PF2 may be logic 0.

[0105] The third scan registers 10 to 17 of the third scan chain unit SC03 may respectively have pass / fail results of 0, 1, 0, 0, 0, 1, 0, 0. The third scan chain unit SC03 may have a third chain fail signal CF3 of logic 1. The third scan chain output signal SCO3 of the third priority filter PF3 may be logic 1.

[0106] The fourth scan registers 18 to 1F of the fourth scan chain unit SC04 may have pass / fail results of 0, 0, 0, 0, 0, 0, 1, and 0, respectively. The fourth scan chain unit SC04 may have a fourth chain fail signal CF4 of logic 1. The fourth scan chain output signal SCO4 of the fourth priority filter PF4 may be logic 1. In this manner, the fifth to sixteenth scan chain units SC05 to SC16 may have a chain fail signal of logic 0 and a scan chain output signal of logic 0.

[0107] Figures 12 to 14 is a diagram illustrating an example embodiment of a failed bit counting operation during the first to third cycles. Figures 12 to 14 The bit counter 2300 may include a bitwise counter 2310, an adder 2320, a counting register 2330, and a SCOP output circuit. For example, the SCOP output circuit may be composed of a second OR logic operation circuit OR2.

[0108] refer to Figure 12 In the first cycle of the fail bit counting mode, a fail result value of 1 may be stored in the scan registers 03 and 04 of the first scan chain unit SC01. The first scan chain output signal SCO1 may be 1. The second scan chain unit SC02 may store a pass result value of 0 in the second scan registers 08 to 0F. The second scan chain output signal SCO2 may be 0. A fail result value of 1 may be stored in the scan registers 11 and 15 of the third scan chain unit SC03. The third scan chain output signal SCO3 may be 1. A fail result value of 1 may be stored in the scan register 1E of the fourth scan chain unit SC04. The fourth scan chain output signal SCO4 may be 1. The fifth scan chain output signal SCO5 to the sixteenth scan chain output signal SCO16 may all be 0.

[0109] The bit-by-bit counter 2310 may receive the first to sixteenth scan chain output signals SCO1 to SCO16 and output a first bit count output signal BCO1. The first bit count output signal BCO1 may be the number of 1s in the first to sixteenth scan chain output signals SCO1 to SCO16. The first bit count output signal BCO1 may be 3.

[0110] The adder 2320 may add the first bit count output signal BCO1 to the first output signal CNT1 of the counting register 2330. The adder 2320 may add BCO1 and CNT1 and output 3 as a result. The counting register 2330 may store the output result of the adder 2320.

[0111] The second OR logic operation circuit OR2 may receive the first to sixteenth scan chain output signals SCO1 to SCO16 and output a SCO pass signal SCOP. In the first cycle of the fail bit counting mode, the SCO pass signal SCOP may be 1.

[0112] refer to Figure 13 In the second cycle of the fail bit counting mode, when the clear pulse CP is applied, the first fail result stored in the scan register of each scan chain unit may change from 1 to 0. Since the scan register 03 is the first to store a fail result among the scan registers of the first scan chain unit SC01, the 1 in the scan register 03 may change to 0. The scan register 04 may continue to store the fail result value of 1. The first scan chain output signal SCO1 may be 1.

[0113] Since the second scan chain unit SC02 stores all 0s as qualified results in the second scan registers 08 to 0F, the second scan chain output signal SCO2 may continue to be 0.

[0114] Since the scan register 11 is the first to store the fail result among the scan registers of the third scan chain unit SC03 , the 1 in the scan register 11 may become 0. The scan register 15 may continue to store 1 as the fail result. The third scan chain output signal SCO3 may be 1.

[0115] Since scan register 1E is the first to store a fail result among the scan registers of the fourth scan chain unit SC04, the 1 in scan register 1E may change to 0. Since all scan registers of the fourth scan chain unit SC04 store 0, the fourth scan chain output signal SCO4 may change from 1 to 0.

[0116] The bit-by-bit counter 2310 may receive the first to sixteenth scan chain output signals SCO1 to SCO16 and output a second bit count output signal BCO2. The second bit count output signal BCO2 may be 2. The adder 2320 may add the second bit count output signal BCO2 to the second output signal CNT2 of the counter register 2330. The adder 2320 may add BCO2 and CNT2 and output 5 as a result. The counter register 2330 may store the output result of the adder 2320.

[0117] The second OR logic operation circuit OR2 may receive the first to sixteenth scan chain output signals SCO1 to SCO16 and output a SCO pass signal SCOP. In the second cycle of the fail bit counting mode, the SCO pass signal SCOP may be 1.

[0118] refer to Figure 14 , in the third cycle of the fail bit counting mode, when the clear pulse CP is applied, the first fail result stored in the scan register of each scan chain unit may be changed from 1 to 0.

[0119] Since the scan register 04 is the first to store a fail result among the first scan registers 00 to 07 of the first scan chain unit SC01, the 1 in the scan register 04 may be changed to 0. The first scan chain output signal SCO1 may be 0. Since all 0s are stored as pass results in the second scan registers 08 to 0F of the second scan chain unit SC02, the second scan chain output signal SCO2 may continue to be 0.

[0120] Since the scan register 11 is the first to store a fail result among the third scan registers 10 to 17 of the third scan chain unit SC03, the 1 in the scan register 11 may be changed to 0. The third scan chain output signal SCO3 may be 0. Since all 0s are stored in the fourth scan register of the fourth scan chain unit SC04 as pass results, the fourth scan chain output signal SCO4 may continue to be 0.

[0121] The bit-by-bit counter 2310 may receive the first to sixteenth scan chain output signals SCO1 to SCO16 and output a third bit count output signal BCO3. The third bit count output signal BCO3 may be 0. The adder 2320 may add the third bit count output signal BCO3 to the third output signal CNT3 of the counting register 2330. The adder 2320 may add BCO3 and CNT3 and output 5 as the result. The counting register 2330 may store the output result of the adder 2320. The bit-by-bit counter 2310 may have counted five failed bits in two counting cycles.

[0122] The second OR logic operation circuit OR2 can receive the first scan chain output signal SCO1 to the sixteenth scan chain output signal SCO16 and output the SCO pass signal SCOP. In the third cycle of the fail bit counting mode, since the first scan chain output signal SCO1 to the sixteenth scan chain output signal SCO16 are all 0, the SCO pass signal SCOP can be 0. If the SCO pass signal SCOP is 0, the fail bit counting operation ends.

[0123] Figure 15 is a timing diagram illustrating an example embodiment of a failed bit counting operation during the first to third cycles. Figure 15 , the first cycle may be executed in a time period from T0 to T1, the second cycle may be executed in a time period from T1 to T2, and the third cycle may be executed in a time period from T2 to T3.

[0124] In the first cycle of the fail bit counting mode, the first scan chain output signal SCO1 may be 1, the second scan chain output signal SCO2 may be 0, the third scan chain output signal SCO3 may be 1, and the fourth scan chain output signal SCO4 may be 1. The fifth to sixteenth scan chain output signals SCO5 to SCO16 may all be 0.

[0125] The scan chain output signal SCO[15:0] may be 0000 0000 0000 1101. The first bit count output signal BCO1 may be 3. The adder 2320 may add the first bit count output signal BCO1 to the first output signal CNT1 of the counting register 2330. The adder 2320 may add BCO1 and CNT1 and output 3 as a result.

[0126] In the second cycle of the fail bit counting mode, when the clear pulse CP is applied, the first fail result among the fail results stored in the scan register of each scan chain unit may be changed from 1 to 0. The first scan chain output signal SCO1 is 1, the second scan chain output signal SCO2 is 0, the third scan chain output signal SCO3 is 1, and the fourth scan chain output signal SCO4 is 0. The fifth scan chain output signal SCO5 to the sixteenth scan chain output signal SCO16 may all be 0.

[0127] The scan chain output signal SCO[15:0] may be 0000 0000 0000 0101. The second bit count output signal BCO2 may be 2. The adder 2320 may add BCO2 and CNT2 and output 5 as a result.

[0128] In the third cycle of the fail bit counting mode, when the clear pulse CP is applied, the first fail result among the fail results stored in the scan register of each scan chain unit may change from 1 to 0. The first scan chain output signal SCO1 and the third scan chain output signal SCO3 may be 0.

[0129] Therefore, the first to sixteenth scan chain output signals SCO1 to SCO16 may all be 0. The third bit count output signal BCO3 may be 0. The adder 2320 may add BCO3 and CNT3 and output 5 as a result. The count register 2330 may store the output result of the adder 2320.

[0130] In the fail bit counting mode, multiple scan chain units can operate in parallel. Therefore, in the above example, the scan register circuit 2000 can obtain five fail bits in the first cycle and the second cycle. The scan register circuit 2000 can perform a fail bit counting operation at high speed by operating multiple scan chain units simultaneously in the fail bit counting mode.

[0131] Figure 16 It is an icon Figure 6 A conceptual diagram of an example embodiment of a location search operation of a scan register circuit is shown. Figure 16 , the first scan registers 00 to 07 of the first scan chain unit SC01 may have pass / fail results of 0, 0, 0, 1, 1, 0, 0, 0, respectively. Figure 10 As shown, the first scan chain unit SC01 may have a first chain fail signal CF1 of logic 1. The first scan chain output signal SCO1 of the first priority filter PF1 may be logic 1.

[0132] The second scan registers 08 to 0F of the second scan chain unit SC02 may respectively have pass / fail results of 0, 0, 0, 0, 0, 0, 0, 0. Since all the second scan chain units SC02 are passed, the second chain fail signal CF2 may be logic 0. In the position search mode, the mode signal MODE is 0, and thus the second scan chain output signal SCO2 of the second priority filter PF2 may be logic 0.

[0133] The third scan registers 10 to 17 of the third scan chain unit SC03 may have pass / fail results of 0, 1, 0, 0, 0, 1, 0, 0, respectively. The third scan chain unit SC03 may have a third chain fail signal CF3 of logic 1. In the position search mode, the mode signal MODE is 0, and thus the third scan chain output signal SCO3 of the third priority filter PF3 may be logic 0.

[0134] The fourth scan registers 18 to 1F of the fourth scan chain unit SC04 may respectively have pass / fail results of 0, 0, 0, 0, 0, 0, 1, and 0. The fourth scan chain unit SC04 may have a fourth chain fail signal CF4 of logic 1. In the position search mode, the mode signal MODE is 0, and thus the fourth scan chain output signal SCO4 of the fourth priority filter PF4 may be logic 0.

[0135] In this way, the fifth to sixteenth scan chain units SC05 to SC16 may have chain fail signals of logic 0 and scan chain output signals of logic 0. In the location search operation, only the highest priority scan chain may have logic 1 through the priority filter.

[0136] Figure 17 Is used to illustrate Figure 16 A block diagram of the location search operation of the scan register circuit is shown.

[0137] refer to Figure 17 The scan register circuit 2000 may include a scan register array 2100 and a position finder 2400. The position finder 2400 may receive scan chain output signals SCO and scan register output signals SRO from the first scan chain unit SC01 to the sixteenth scan chain unit SC16 of the scan register array 2100. The position finder 2400 may output a position index PI[n] to detect the position of a failed bit.

[0138] The location finder 2400 may include a scan chain encoder 2412, a priority encoder 2421, a scan register encoder 2422, and an adder 2430. For example, the scan chain encoder 2412 may be a 16x4 encoder. For example, the scan register encoder 2422 may be an 8x3 encoder.

[0139] The scan register array 2100 may store a fail result value of 1 in the scan registers (e.g., 03, 04, 11, 15, and 1E). Since the scan chain cells (SC01, SC03, and SC04) store a fail result value of 1, the chain fail signal CF[15:0] may be 0000 0000 0000 1101.

[0140] The first priority filter PF1 to the sixteenth priority filter PF16 can receive the first to sixteenth chain fail signals CF[15:0] and output the scan chain output signal SCO. The first priority filter PF1 to the sixteenth priority filter PF16 can set all subsequent data to 0 when outputting the first 1. The scan chain output signal SCO[15:0] can be 00000000 0000 0001.

[0141] The scan register array 2100 may output a scan register output signal SRO[7:0] via a scan register output circuit 2110. The scan register output signal SRO[7:0] may be 1111 1000. The priority encoder 2421 of the location finder 2400 may output a scan register priority signal SRP[7:0]. The priority encoder 2421 may cause all subsequent data to be 0 upon outputting the first 1. The scan register priority signal SRP[7:0] may be 0000 1000.

[0142] Figure 18 and Figure 19 Is used to illustrate Figure 17 Table showing the operation of the 16x4 encoder and the 8x3 encoder.

[0143] refer to Figure 18 , the 16x4 scan chain encoder 2412 may receive the scan chain output signal SCO and output a first position index PI1. For example, if the scan chain output signal SCO[15:0] is 0000 0000 0000 0001, the first position index PI1[3:0] may be 0000.

[0144] refer to Figure 19 , the 8x3 scan register encoder 2422 may receive the scan register priority signal SRP and output a second position index PI2. For example, if the scan register priority signal SRP[7:0] is 0000 1000, the second position index PI2[2:0] may be 011.

[0145] Reference again Figure 17 , the adder 2430 may receive the first position index PI1 and the second position index PI2 and output a position index signal PI[n]. For example, if the first position index PI1[3:0] is 0000 and the second position index PI2[2:0] is 011, the adder 2430 may output PI[n], i.e., 0000011.

[0146] Figure 20 It is an icon Figure 17 FIG. 1 is a circuit diagram of an exemplary embodiment of a position search mode of a first scan chain unit. Figure 20 , the first pass / fail result P / F[1] is 0, the fourth pass / fail result P / F[4] is 1, and the eighth pass / fail result P / F[8] is 0. Figure 9 , in the position search mode, the mode signal MODE is 0 and the dump signal DUMP is 1. The first to eighth DQ flip-flops DQ1 to DQ8 may all be initialized by a reset signal supplied to the R terminal.

[0147] If the first pass / fail result P / F[1] is 0, the P terminal of the first multiplexer MX1 ​​can be connected to the first node N1. The first node N1 can be a logic 1 because it is connected to the power supply terminal. If the fourth pass / fail result P / F[4] is 1, the F terminal of the fourth multiplexer MX4 can be connected to the fourth node N4. Since the fourth DQ flip-flop DQ4 can be initialized by the reset signal, the fourth node N4 can be a logic 0. If the eighth pass / fail result P / F[8] is 0, the P terminal of the eighth multiplexer MX8 can be connected to the seventh node N7. The eighth node N8 can be a logic 0.

[0148] If the dump signal DUMP is 1 and the first scan chain output signal SCO1 is 1, the tri-state switching signal TSW is 1. If the tri-state switching signal TSW is 1, the outputs of the first to eighth tri-state buffers TB1 to TB8 may be inverted values ​​of the inputs. For example, since the first node N1 is 1, SRO[0] may be 0. Since the fourth node N4 is 0, SRO[3] may be 1. Since the eighth node N8 is 0, SRO[7] may be 1. The scan register output signals SRO[7:0] of the scan register output circuit 2110 may be 1111 1000.

[0149] If the mode signal MODE is 0, the output of the first OR gate OR1 in the first priority filter PF1 can be determined based on the default low priority parameter LWP0. If the default low priority parameter LWP0 is 1, the tenth node N10 can be logic 1. Therefore, the output of the third AND gate AND3 can have the same value as the logic value of the ninth node N9. In other words, the first scan chain output signal SCO1 can be equal to the first chain fail signal CF1. If the first chain fail signal CF1 is 1, the first scan chain output signal SCO1 can be 1.

[0150] If the default low priority parameter LWP0 is 1, the first low priority parameter LWP1 may be equal to the logic value of the eighth node N8. If the eighth node N8 is logic 0, the first low priority parameter LWP1 may be logic 0.

[0151] Figures 21 to 25 It is shown in the figure Figure 17 FIGURE 1 shows an exemplary embodiment of a position search mode during the first to fifth cycles of a scan register circuit. Figures 21 to 25 , the location finder 2400 may include a 16×4 encoder 2412 , a priority encoder 2421 , an 8×3 encoder 2422 , and an adder 2430 .

[0152] refer to Figure 21In the first cycle of the position search mode, a fail result value of 1 may be stored in the scan registers 03 and 04 of the first scan chain unit SC01, and the first chain fail signal CF1 may be 1. A pass result value of 0 may be stored in the scan registers 08 to 0F of the second scan chain unit SC02, and the second chain fail signal CF2 may be 0. A fail result value of 1 may be stored in the scan registers 11 and 15 of the third scan chain unit SC03, and the third chain fail signal CF3 may be 1. A fail result value of 1 may be stored in the scan register 1E of the fourth scan chain unit SC04, and the fourth chain fail signal CF4 may be 1. The fifth chain fail signal CF5 to the sixteenth chain fail signal CF16 may all be 0.

[0153] In the first cycle of the position search mode, the chain fail signal CF[15:0] may be 0000 0000 00001101. The priority filters PF1 to PF16 may receive the chain fail signal CF[15:0] and output the scan chain output signal SCO[15:0]. The scan chain output signal SCO[15:0] may be 0000 0000 0000 0001.

[0154] Scan register output circuit 2110 (see Figure 20 ) may output a scan register output signal SRO[7:0]. The scan register output signal SRO[7:0] may be 1111 1000. The priority encoder 2421 of the location finder 2400 may output a scan register priority signal SRP[7:0]. The scan register priority signal SRP[7:0] may be 0000 1000.

[0155] The 16x4 encoder 2412 may receive the scan chain output signal SCO[15:0] and output a first position index PI1. If the scan chain output signal SCO[15:0] is 0000 0000 0000 0001, the first position index PI1[3:0] may be 0000. The 8x3 encoder 2422 may receive the scan register priority signal SRP and output a second position index PI2. If the scan register priority signal SRP[7:0] is 0000 1000, the second position index PI2[2:0] may be 011.

[0156] The adder 2430 may receive a first position index PI1 and a second position index PI2 and output a position index signal PI[n]. If the first position index PI1[3:0] is 0000 and the second position index PI2[2:0] is 011, the adder 2430 may output a position index signal PI[n]. The position index signal PI[n] may be 0000011. PI[n] may be a position index indicating the position of the scan register 03 of the scan register array 2100.

[0157] The position of the scan register 03 may be a position where both the scan chain output signal SCO and the scan register priority signal SRP are 1. When the scan operation proceeds from the scan register 00 to the scan register 7F, the scan register 03 may store the first fail bit. The scan register circuit 2000 may output a position index PI[n] indicating the position of the scan register 03 in the first cycle of the position search mode.

[0158] refer to Figure 22 , when the clear pulse CP is applied in the second cycle of the position search mode, the scan register 03 of the first scan chain unit SC01 may be cleared, and the fail result value of 1 stored in the scan register 04 may be maintained. The first chain fail signal CF1 may be 1. The second chain fail signal CF2 may be 0, and the third chain fail signal CF3 and the fourth chain fail signal CF4 may be 1. The fifth chain fail signal CF5 to the sixteenth chain fail signal CF16 may all be 0.

[0159] In the second cycle of the position search mode, the chain fail signal CF[15:0] may be 0000 0000 00001101. The scan chain output signal SCO[15:0] may be 0000 0000 0000 0001. The scan register output signal SRO[7:0] may be 1111 0000. The scan register priority signal SRP[7:0] may be 0001 0000.

[0160] If the scan chain output signal SCO[15:0] is 0000 0000 0000 0001, the first position index PI1[3:0] may be 0000. If the scan register priority signal SRP[7:0] is 0001 0000, the second position index PI2[2:0] may be 100. If the first position index PI1[3:0] is 0000 and the second position index PI2[2:0] is 100, the position index signal may be PI[n]=[0000100]. The position index signal PI[n] may indicate the position of the scan register 04.

[0161] refer to Figure 23, when the clear pulse CP is applied in the third period of the position search mode, the scan register 04 of the first scan chain unit SC01 may be cleared, and the first chain fail signal CF1 may be 0. The second chain fail signal CF2 may be 0, and the third chain fail signal CF3 and the fourth chain fail signal CF4 may be 1. The fifth chain fail signal CF5 to the sixteenth chain fail signal CF16 may all be 0.

[0162] In the third cycle of the position search mode, the chain fail signal CF[15:0] may be 0000 0000 00001100. The scan chain output signal SCO[15:0] may be 0000 0000 0000 0100. The scan register output signal SRO[7:0] may be 1111 1110. The scan register priority signal SRP[7:0] may be 0000 0010.

[0163] If the scan chain output signal SCO[15:0] is 0000 0000 0000 0100, the first position index PI1[3:0] may be 0010. If the scan register priority signal SRP[7:0] is 0000 0010, the second position index PI2[2:0] may be 001. If the first position index PI1[3:0] is 0010 and the second position index PI2[2:0] is 001, the position index signal may be PI[n]=[0010001]. The position index signal PI[n]=[0010001] may indicate the position of the scan register 11.

[0164] refer to Figure 24 , when the clear pulse CP is applied in the fourth cycle of the position search mode, the scan register 11 of the third scan chain unit SC03 may be cleared, and the third chain fail signal CF3 may be 1. The fourth chain fail signal CF4 may be 1. The fifth chain fail signal CF5 to the sixteenth chain fail signal CF16 may all be 0.

[0165] In the fourth cycle of the position search mode, the chain fail signal CF[15:0] may be 0000 0000 00001100. The scan chain output signal SCO[15:0] may be 0000 0000 0000 0100. The scan register output signal SRO[7:0] may be 1110 0000. The scan register priority signal SRP[7:0] may be 0010 0000.

[0166] If the scan chain output signal SCO[15:0] is 0000 0000 0000 0100, the first position index PI1[3:0] may be 0010. If the scan register priority signal SRP[7:0] is 0010 0000, the second position index PI2[2:0] may be 101. If the first position index PI1[3:0] is 0010 and the second position index PI2[2:0] is 101, the position index signal may be PI[n]=[0010101]. The position index signal PI[n]=[0010101] may indicate the position of the scan register 15.

[0167] refer to Figure 25 , when the clear pulse CP is applied in the fifth cycle of the position search mode, the scan register 15 of the third scan chain unit SC03 may be cleared, and the third chain fail signal CF3 may be 0. The fourth chain fail signal CF4 may be 1. The fifth chain fail signal CF5 to the sixteenth chain fail signal CF16 may all be 0.

[0168] In the fifth cycle of the position search mode, the chain fail signal CF[15:0] may be 0000 0000 0000 1000. The scan chain output signal SCO[15:0] may be 0000 0000 0000 1000. The scan register output signal SRO[7:0] may be 1100 0000. The scan register priority signal SRP[7:0] may be 0100 0000.

[0169] If the scan chain output signal SCP[15:0] is 0000 0000 0000 1000, the first position index PI1[3:0] may be 0011. If the scan register priority signal SRP[7:0] is 0100 0000, the second position index PI2[2:0] may be 110. If the first position index PI1[3:0] is 0011 and the second position index PI2[2:0] is 110, the position index signal may be PI[n]=[0011110]. The position index signal PI[n]=[0011110] may indicate the position of the scan register 1E.

[0170] Figure 26 It is shown in the figure Figure 17 FIG. 4 is a timing diagram of a position search mode during the first to fifth cycles of the scan register circuit shown.

[0171] In the first cycle of the position search mode, the chain fail signal CF[15:0] may be 0000 0000 00001101. The scan chain output signal SCO[15:0] may be 0000 0000 0000 0001. The scan register output signal SRO[7:0] may be 1111 1000. The scan register priority signal SRP[7:0] may be 0000 1000. The first position index PI1[3:0] may be 0000. The second position index PI2[2:0] may be 011. The position index signal PI[n] = [0000011] may indicate the position of the scan register 03.

[0172] In the second cycle of the position search mode, the chain fail signal CF[15:0] may be 0000 0000 00001101. The scan chain output signal SCO[15:0] may be 0000 0000 0000 0001. The scan register output signal SRO[7:0] may be 1111 0000. The scan register priority signal SRP[7:0] may be 0001 0000. The first position index PI1[3:0] may be 0000. The second position index PI2[2:0] may be 100. The position index signal PI[n] = [0000100] may indicate the position of the scan register 04.

[0173] In the third cycle of the position search mode, the chain fail signal CF[15:0] may be 0000 0000 00001100. The scan chain output signal SCO[15:0] may be 0000 0000 0000 0100. The scan register output signal SRO[7:0] may be 1111 1110. The scan register priority signal SRP[7:0] may be 0000 0010. The first position index PI1[3:0] may be 0010. The second position index PI2[2:0] may be 001. The position index signal PI[n] = [0010001] may indicate the position of the scan register 11.

[0174] In the fourth cycle of the position search mode, the chain fail signal CF[15:0] may be 0000 0000 00001100. The scan chain output signal SCO[15:0] may be 0000 0000 0000 0100. The scan register output signal SRO[7:0] may be 1110 0000. The scan register priority signal SRP[7:0] may be 0010 0000. The first position index PI1[3:0] may be 0010. The second position index PI2[2:0] may be 101. The position index signal PI[n] = [0010101] may indicate the position of the scan register 15.

[0175] In the fifth cycle of the position search mode, the chain fail signal CF[15:0] may be 0000 0000 00001000. The scan chain output signal SCO[15:0] may be 0000 0000 0000 1000. The scan register output signal SRO[7:0] may be 1100 0000. The scan register priority signal SRP[7:0] may be 0100 0000. The first position index PI1[3:0] may be 0011. The second position index PI2[2:0] may be 110. The position index signal PI[n] = [0011110] may indicate the position of the scan register 1E.

[0176] Figure 27 is a diagram illustrating an example embodiment of a memory device having a multi-stack structure. Figure 27 , the memory device 3000 may have a first stack ST1 and a second stack ST2. The first stack ST1 may be located at the bottom, and the second stack ST2 may be located at the top.

[0177] The pillars of the memory device 3000 can be formed by joining the first stack ST1 and the second stack ST2. A plurality of dummy word lines (e.g., Dummy1 WL and Dummy2 WL) can be included at the junction of the first stack ST1 and the second stack ST2. The first stack ST1 can be located between the common source line CSL and the first dummy word line Dummy1 WL. The second stack ST2 can be located between the second dummy word line Dummy2 WL and the bit line BL.

[0178] The first stack ST1 may include a ground select line GSL, a first edge word line Edge1 WL, and a first stack word line Stack1 WLs. The second stack ST2 may include a second stack word line Stack2 WLs and a second edge word line Edge2 WL. The memory cells connected to the first edge word line Edge1 WL and the second edge word line Edge2 WL may store different bit data than other memory cells. For example, the memory cells connected to the first edge word line Edge1 WL and the second edge word line Edge2 WL may be SLC or MLC, and the memory cells connected to the other word lines may be TLC or QLC.

[0179] The memory device 3000 may include a scan register circuit. The scan register circuit may acquire information about a scan register storing a failure result through a scan operation. The scan register circuit may use the information about the scan register storing the failure result to determine the number of fail bits or generate a location index indicating the location of a fail bit according to an operation mode.

[0180] Figure 28 is a block diagram illustrating an example of implementing a storage device according to an embodiment of the present disclosure using a solid state drive (SSD). Figure 28 , the SSD 4000 may include a plurality of memory devices 4101 to 4104 , and an SSD controller 4200 .

[0181] The first memory device 4101 and the second memory device 4102 can be connected to the SSD controller 4200 via a first channel CH1. The third memory device 4103 and the fourth memory device 4104 can be connected to the SSD controller 4200 via a second channel CH2. The number of channels connected to the SSD controller 4200 can be two or more. The number of memory devices connected to one channel can be two or more.

[0182] The SSD controller 4200 may include a host interface 4201, a memory interface 4202, a buffer interface 4203, a control unit 4210, and a working memory 4220. The SSD controller 4200 may be connected to the host 1500 through the host interface 4201. Based on a request from the host 1500, the SSD controller 4200 may write data to a corresponding memory device or read data from the corresponding memory device.

[0183] The SSD controller 4200 may be connected to a plurality of memory devices 4101 to 4104 through a memory interface 4202, and may be connected to the buffer memory 1300 through a buffer interface 4203. The memory interface 4202 may provide data temporarily stored in the buffer memory 1300 to the memory devices through channels CH1 and CH2. The memory interface 4202 may transfer data read from the memory devices 4101 to 4104 to the buffer memory 1300.

[0184] The control unit 4210 may analyze and process a signal received from the host 1500. The control unit 4210 may control the host 1500 or the memory devices 4101 to 4104 through the host interface 4201 or the memory interface 4202. The control unit 4210 may control operations of the memory devices 4101 to 4104 by using firmware for driving the SSD 4000.

[0185] The SSD controller 4200 may manage data to be stored in the memory devices 4101 to 4104. In the event of a sudden power failure, the SSD controller 4200 may back up data stored in the working memory 4220 or the buffer memory 1300 to the memory devices 4101 to 4104.

[0186] According to the present disclosure, it is possible to reduce the test time taken to perform a margin read test operation and to perform the margin read test operation at a high speed.

[0187] According to embodiments, the semiconductor device, electronic system, or semiconductor package described above may be included in various electronic products including display devices, televisions, computers (e.g., laptop computers), phones (e.g., smart phones), servers, infotainment systems, and the like.

[0188] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A memory device, comprising: a memory cell array configured to store data; a page buffer circuit configured to store data in the memory cell array or read data stored in the memory cell array; as well as a scan register circuit configured to receive pass / fail results of data from the page buffer circuit and store the pass / fail results in a plurality of scan registers, In which, the scanning register circuit obtains information about the scanning register storing the failure results among the multiple scanning registers through a scanning operation, and uses the information about the scanning register storing the failure results to determine the number of failure bits and / or the position index indicating the position of the failure bit according to the operation mode.

2. The memory device according to claim 1, in, The scan register circuit comprises: a scan register array, the scan register array being configured to have a plurality of scan chain units, each scan chain unit having a plurality of scan registers, each scan register storing the pass / fail result of data; and A bit counter is configured to receive information of a scan register storing a fail result from each scan chain unit and determine the number of fail bits when the operation mode is a fail bit counting mode.

3. The memory device according to claim 2, in, The scan register circuit further includes a location finder configured to determine a location index indicating a location of the failed bit when the operation mode is a location search mode, and The location finder receives information of a scan register storing the failure result and information of a scan register storing a first failure result from each scan chain unit, and determines the location index.

4. The memory device according to claim 3, in, Each scan chain unit also includes: a pulse gate configured to receive a clear pulse and output a clock signal, wherein the plurality of scan registers are connected in series and perform a scan chain operation in response to the clock signal of the pulse gate; and A priority filter is configured to receive scan chain operation results from the plurality of scan registers and output a scan chain output signal.

5. The memory device according to claim 4, in, The bit counter comprises: a bit-by-bit counter configured to receive the scan chain output signal from the priority filter and generate a bit count output signal; a counting register configured to store a bit counting result; and An adder is configured to calculate a failed bit count using a previous bit count result stored in the counting register and the bit count output signal of the bit-by-bit counter.

6. The memory device according to claim 4, in, Each scan chain unit also includes: A scan register output circuit is configured to receive information about a scan register storing a fail result among the plurality of scan registers and output a scan register output signal.

7. The memory device according to claim 6, in, The scan register output circuit includes selection circuits connected in series, and the scan register output signal is generated from each selection circuit in the position search mode.

8. The memory device according to claim 7, in, The location finder includes: a first encoder configured to receive the scan chain output signal and output a first position index; a second encoder configured to receive the scan chain register signal and output a second position index; and An adder is configured to output the position index using the first position index and the second position index.

9. The memory device according to claim 8, in, The second encoder comprises: a priority encoder configured to receive the scan chain register signal and generate a scan register priority signal; and A scan register encoder is configured to receive the scan register priority signal and generate the second location index.

10. The memory device according to claim 1, in, The memory device is a flash memory in which memory cells are vertically stacked on a substrate.

11. A scan register circuit of a memory device, the scan register circuit comprising: a scan register array, the scan register array being configured to have a plurality of scan chain units, each scan chain unit having a plurality of scan registers, each scan register storing a pass / fail result of data; as well as a fail bit output circuit configured to determine the number of fail bits and / or a position index indicating the position of the fail bit according to an operation mode, In which, the failure bit output circuit obtains information about the scan register storing the failure result among the multiple scan registers through the scanning operation of the multiple scan registers, and uses the information of the scan register storing the failure result to determine the number of failure bits or the position index.

12. The scan register circuit according to claim 11, in, Each scan chain unit also includes, a pulse gate configured to receive a clear pulse and output a clock signal, wherein the plurality of scan registers are connected in series and perform a scan chain operation in response to the clock signal of the pulse gate; and A priority filter is configured to receive scan chain operation results from the plurality of scan registers and output a scan chain output signal.

13. The scan register circuit according to claim 12, in, The fail bit output circuit comprises: A bit counter is configured to receive information of a scan register storing a fail result from each scan chain unit and determine the number of fail bits when the operation mode is a fail bit counting mode.

14. The scan register circuit according to claim 13, in, The bit counter comprises: a bit-by-bit counter configured to receive the scan chain output signal from the priority filter and generate a bit count output signal; a counting register configured to store a bit counting result; and An adder is configured to calculate a failed bit count using a previous bit count result stored in the counting register and the bit count output signal of the bit-by-bit counter.

15. The scan register circuit according to claim 13, in, The fail bit output circuit further includes a position finder configured to determine a position index indicating a position of the fail bit when the operation mode is a position search mode, and The location finder receives information of a scan register storing the failure result and information of a scan register storing a first failure result from each scan chain unit, and determines the location index.

16. The scan register circuit according to claim 12, in, Each scan chain unit also includes: A scan register output circuit is configured to receive information about a scan register storing a fail result among the plurality of scan registers and output a scan register output signal.

17. The scan register circuit according to claim 16, in, The scan register output circuit includes selection circuits connected in series, and generates the scan register output signal from each selection circuit in a position search mode.

18. The scan register circuit according to claim 11, in, The memory device is a flash memory.

19. A scan register circuit of a memory device, the scan register circuit comprising: a scan register array, the scan register array being configured to have a plurality of scan chain units, each scan chain unit having a plurality of scan registers, each scan register storing a pass / fail result of data; a bit counter configured to receive the scan chain output signal of each scan chain unit in a failed bit counting mode and determine the number of failed bits; as well as A location finder is configured to receive the scan chain output signal and the scan register output signal of each scan chain unit in a location search mode and determine a location index indicating a location of the failed bit.

20. The scan register circuit according to claim 19, in, Each scan chain unit also includes: a pulse gate configured to receive a clear pulse and output a clock signal, wherein the plurality of scan registers are connected in series and perform a scan chain operation in response to the clock signal of the pulse gate; and A priority filter is configured to receive scan chain operation results from the plurality of scan registers and output a scan chain output signal.

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