Multilayer ceramic capacitor and method of manufacturing same

Abstract

The invention provides a multilayer ceramic capacitor and a manufacturing method thereof. The multilayer ceramic capacitor comprises a multilayer ceramic tile, a first terminal electrode and a second terminal electrode. The multi-layer ceramic tile has a first end face and a second end face, and the multi-layer ceramic tile includes a plurality of dielectric layers and a plurality of inner electrode layers. Each of the inner electrode layers includes an inner layer and a first indium isolation layer between the inner layer and one of the dielectric layers, and the dielectric layer includes a plurality of second indium isolation layers. The first end electrode is arranged on the first end face, and the second end electrode is arranged on the second end face. Therefore, the average fault-free time of the multilayer ceramic capacitor can be improved, and the service life of the multilayer ceramic capacitor can be prolonged.

Description

Technical Field

[0001] The present invention relates to a capacitor and a manufacturing method thereof, and in particular to a multilayer ceramic capacitor and a manufacturing method thereof. Background Art

[0002] Multilayer ceramic capacitors (MLCCs) are a type of ceramic capacitor, and their capacitance is proportional to the product's surface area and the number of ceramic film layers. MLCCs can be mounted using surface mount technology (SMT), are easily formed into wafers, and are compact, making them a mainstream product in the capacitor industry and used in a variety of electronic devices.

[0003] Perovskite oxide compounds, as materials for the dielectric layers of multilayer ceramic capacitors, can reduce the cost and improve the performance of multilayer ceramic capacitors. Therefore, perovskite oxide compounds have been widely used in multilayer ceramic capacitors. However, as the number of internal electrode layers in multilayer ceramic capacitors increases, the thickness of the dielectric layer decreases, thereby reducing the insulation resistance between the internal electrode layers, which reduces the reliability and high-temperature load life of the multilayer ceramic capacitors.

[0004] Furthermore, when the thickness of the dielectric layer decreases, the mean time to failure (MTTF) of the conventional multilayer ceramic capacitor decreases, thereby shortening the service life of the multilayer ceramic capacitor.

[0005] Therefore, it is necessary to develop a method for manufacturing a capacitor that can overcome the defects of existing multilayer ceramic capacitors. Summary of the Invention

[0006] One aspect of the present invention is to provide a multilayer ceramic capacitor, which includes a multilayer ceramic tile, a first end electrode and a second end electrode. The multilayer ceramic tile has a first end face and a second end face, the first end face and the second end face are opposite to each other, wherein the multilayer ceramic tile includes multiple dielectric layers and multiple internal electrode layers. The dielectric layer includes multiple perovskite oxides and borosilicate glass, wherein the perovskite oxide includes barium and titanium. The internal electrode layer and the dielectric layer are stacked alternately, wherein each of the internal electrode layers includes an inner layer and a first indium isolation layer. The material of the inner layer includes nickel, the first indium isolation layer is located between the inner layer and one of the dielectric layers, wherein the thickness of the first indium isolation layer is 1nm to 19nm, the dielectric layer includes multiple second indium isolation layers, and the second indium isolation layers are respectively located at multiple grain boundaries of the perovskite oxide. The first end electrode is arranged on the first end face and is electrically connected to a portion of the internal electrode layer. The second end electrode is arranged on the second end face and is electrically connected to another portion of the internal electrode layer.

[0007] According to the multilayer ceramic capacitor described in the preceding paragraph, when the total weight of the perovskite oxide is 100 wt %, the weight of the borosilicate glass may be 0.01 wt % to 5 wt %.

[0008] According to the multilayer ceramic capacitor described in the preceding paragraph, the borosilicate glass may contain boron trioxide, aluminum trioxide, and silicon dioxide.

[0009] According to the multilayer ceramic capacitor described in the previous paragraph, the inner electrode layer is formed by sintering a nickel paste containing indium, and the amount of indium added to the nickel paste can be 0.01 mol % to 5 mol %.

[0010] According to the multilayer ceramic capacitor described in the preceding paragraph, the first indium content of the first indium barrier layer may be greater than the second indium content of each of the second indium barrier layers.

[0011] According to the multilayer ceramic capacitor described in the preceding paragraph, when the sum of the titanium content of the perovskite oxide and the second indium content of the second indium isolation layer is 100 mol %, the second indium content can be 10 -20 mol% to 10 -2 mol%.

[0012] According to the multilayer ceramic capacitor described in the preceding paragraph, the first indium isolation layer may include indium, barium, and titanium.

[0013] According to the multilayer ceramic capacitor described in the preceding paragraph, the second indium barrier layer may include indium, barium, and titanium.

[0014] According to the multilayer ceramic capacitor described in the preceding paragraph, a ratio of the thickness of each of the inner electrode layers to the thickness of each of the dielectric layers may be 0.4 to 0.6.

[0015] Another aspect of the present invention provides a method for manufacturing a multilayer ceramic capacitor, comprising the following steps: forming a plurality of dielectric layers, wherein the dielectric layers comprise a plurality of perovskite oxides and borosilicate glass, and the perovskite oxides comprise barium and titanium; forming a plurality of internal electrode layers; alternately laminating the internal electrode layers and the dielectric layers to form a stack; performing a sintering process to form the stack into a multilayer ceramic tile, wherein the sintering process comprises a low-temperature burnout step and a high-temperature sintering step; and forming a first terminal electrode and a second terminal electrode at respective ends of the multilayer ceramic tile to obtain a multilayer ceramic capacitor.

[0016] According to the method for manufacturing a multilayer ceramic capacitor as described above, when the total weight of the perovskite oxide is 100 wt %, the weight of the borosilicate glass may be 0.01 wt % to 5 wt %.

[0017] According to the method for manufacturing a multilayer ceramic capacitor described in the preceding paragraph, the borosilicate glass may contain boron trioxide, aluminum trioxide, and silicon dioxide.

[0018] According to the manufacturing method of the multilayer ceramic capacitor described in the previous paragraph, the inner electrode layer is formed by sintering a nickel paste containing indium, and the amount of indium added to the nickel paste can be 0.01 mol % to 5 mol %.

[0019] According to the manufacturing method of the multilayer ceramic capacitor described in the previous paragraph, after the sintering process, a first indium isolation layer can be formed at the interface between any one of the internal electrode layers and one of the corresponding dielectric layers, and multiple second indium isolation layers can be formed at multiple grain boundaries of the perovskite oxide, wherein the first indium isolation layer and the second indium isolation layer can be generated simultaneously.

[0020] Thus, the multilayer ceramic capacitor and the method for manufacturing the multilayer ceramic capacitor of the present invention can improve the mean time between failures of the multilayer ceramic capacitor and extend the service life of the multilayer ceramic capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To make the above and other objects, features, advantages and embodiments of the present invention more apparent, the accompanying drawings are described as follows:

[0022] Figure 1 FIG1 is a perspective schematic diagram illustrating a multilayer ceramic capacitor according to one embodiment of the present invention;

[0023] Figure 2 To illustrate the Figure 1 A schematic cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention along section line AA;

[0024] Figure 3 To illustrate the Figure 1 A schematic cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention along section line BB;

[0025] Figure 4 A flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to another embodiment of the present invention;

[0026] Figure 5 An annular dark field image of the multilayer ceramic capacitor of Experimental Example 1 taken by a scanning transmission electron microscope;

[0027] Figure 6 for Figure 5 Lα energy dispersion X-ray image of indium in Experimental Example 1;

[0028] Figure 7 A bright field image of a multilayer ceramic capacitor of Experimental Example 2 taken by a scanning transmission electron microscope;

[0029] Figure 8 for Figure 7 Lα energy dispersion X-ray image of indium in Experimental Example 2;

[0030] Figure 9 for Figure 8 A magnified image of the barium titanate perovskite oxide;

[0031] Figure 10 for Figure 9 Lα energy dispersive X-ray image of indium perovskite oxide of barium titanate; and

[0032] Figure 11 Graph of total dielectric thickness versus mean time between failure in nickel multilayer ceramic capacitors and nickel-indium multilayer ceramic capacitors. DETAILED DESCRIPTION

[0033] The following describes various embodiments of the present invention in greater detail. However, these embodiments may encompass a wide variety of inventive concepts and may be implemented within a variety of specific scopes. The specific embodiments described are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, to simplify the drawings, some conventional structures and components are depicted in simplified schematic form.

[0034] Furthermore, the terms “first”, “second”, etc. in the description are only used to distinguish between components or actions in the same technology, and are not used to indicate a procedural sequence or an arrangement order.

[0035] The spatial relationship between two elements described in the present invention applies not only to the orientations depicted in the drawings but also to orientations not depicted in the drawings, such as an inverted orientation. Furthermore, the terms "connected" or "electrically connected" between two components as used in the present invention are not limited to direct or direct electrical connections between the two components but may also include indirect or indirect electrical connections, as needed.

[0036] In the present invention, a multilayer ceramic capacitor having a "metal" inner electrode layer is referred to as a "metal" multilayer ceramic capacitor (Metal MLCC), such as a nickel multilayer ceramic capacitor (Ni MLCC) or a nickel-indium multilayer ceramic capacitor (Ni-InMLCC). Specifically, a "nickel multilayer ceramic capacitor" represents a multilayer ceramic capacitor having a metal inner electrode layer containing nickel. Similarly, a "nickel-indium multilayer ceramic capacitor" represents a multilayer ceramic capacitor having a metal inner electrode layer containing nickel and indium.

[0037] Please refer to Figures 1 to 3 , Figures 1 to 3 A three-dimensional schematic diagram of a multilayer ceramic capacitor 100 according to an embodiment of the present invention is shown, and Figure 1 Schematic cross-sectional views of a multilayer ceramic capacitor 100 along section line AA and section line BB according to an embodiment of the present invention. The multilayer ceramic capacitor 100 includes a multilayer ceramic tile 200 , a first terminal electrode 300 , and a second terminal electrode 400 .

[0038] For example, the multilayer ceramic tile 200 can be a rectangular parallelepiped or a cube. However, the shape of the multilayer ceramic tile 200 can be designed according to product requirements, and the present invention is not limited thereto. The multilayer ceramic tile 200 has a first end face 202 and a second end face 204, and the first end face 202 and the second end face 204 are opposite to each other. Figures 1 to 3 As can be seen, the multilayer ceramic tile 200 is a rectangular parallelepiped. Therefore, the multilayer ceramic tile 200 may further include a first surface 205, a second surface 206, a third surface 207, and a fourth surface 208. The first surface 205 and the second surface 206 are opposite each other, and the third surface 207 and the fourth surface 208 are opposite each other. The first end surface 202, the second end surface 204, the third surface 207, and the fourth surface 208 are all located between the first surface 205 and the second surface 206. The third surface 207 and the fourth surface 208 are located between the first end surface 202 and the second end surface 204.

[0039] The multilayer ceramic tile 200 includes a plurality of dielectric layers 210 and a plurality of internal electrode layers 220. The dielectric layers 210 and the internal electrode layers 220 are stacked alternately. During the manufacturing process of the multilayer ceramic tile 200, green sheets of the dielectric layer 210 and slurry layers of the internal electrode layer 220 can be stacked alternately to form a stacked structure, and then the stacked structure is sintered. The dielectric layer 210 is a ceramic layer formed by sintering green sheets of perovskite oxide (not shown) and borosilicate glass. Therefore, each of the dielectric layers 210 includes a plurality of perovskite oxides and borosilicate glass. The perovskite oxide includes barium and titanium. In some embodiments, the dielectric layer 210 is made of a perovskite oxide of barium titanate (BaTiO3).

[0040] Borosilicate glass may include boron trioxide (B2O3), aluminum oxide (Al2O3), and silicon dioxide (SiO2). In some embodiments, the weight of the borosilicate glass may be 0.01 wt% to 5 wt% based on 100 wt% of the total weight of the perovskite oxide. For example, the weight of the borosilicate glass may be 0.05 wt%, 0.1 wt%, 0.2 wt%, 0.3 wt%, 0.4 wt%, 0.5 wt%, 0.6 wt%, 0.7 wt%, 0.8 wt%, 0.9 wt%, 1 wt%, 1.5 wt%, 2 wt%, 2.5 wt%, 3 wt%, 3.5 wt%, 4 wt%, or 4.5 wt%. When the weight of the borosilicate glass is within the above ranges, the mean time between failures (MTBF) of the multilayer ceramic capacitor 100 may be improved, thereby extending the service life of the multilayer ceramic capacitor 100.

[0041] like Figure 2 As shown, the internal electrode layer 220 can be divided into two parts. One part of the internal electrode layer 220 extends from the first end surface 202 of the multilayer ceramic tile 200 toward the second end surface 204 and is spaced apart from the second end surface 204. The other part of the internal electrode layer 220 extends from the second end surface 204 toward the first end surface 202 and is spaced apart from the first end surface 202. The two parts of the multilayer ceramic tile 200 are arranged alternately, with the dielectric layer 210 located between adjacent ones of the internal electrode layers 220. The internal electrode layers 220 are substantially parallel to the first surface 205 and the second surface 206 of the multilayer ceramic tile 200.

[0042] Depend on Figure 2 and Figure 3 As can be seen, each of the inner electrode layers 220 includes an inner layer 222 and a first indium barrier layer 224. The inner layer 222 is made of nickel. For example, nickel may be the primary component of the inner layer 222. The first indium barrier layer 224 of each of the inner electrode layers 220 is located between the inner layer 222 and the dielectric layer 210 adjacent to the inner layer 222. Thus, the first indium barrier layer 224 of each of the inner electrode layers 220 separates the inner layer 222 from the surrounding dielectric layer 210.

[0043] The thickness of the first indium isolation layer 224 is 1 nm to 100 nm. For example, the thickness of the first indium isolation layer 224 may be 3 nm, 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm, 19 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, or 90 nm. When the thickness of the first indium isolation layer 224 is within the above range, the mean time between failures of the multilayer ceramic capacitor 100 can be improved, thereby extending the service life of the multilayer ceramic capacitor 100. Please refer to Figure 2 The ratio of the thickness h1 of each of the inner electrode layers 220 to the thickness h2 of each of the dielectric layers 210 may be 0.4 to 0.6. When the ratio is within the above range, the mean time between failures of the multilayer ceramic capacitor 100 may be improved, thereby extending the service life of the multilayer ceramic capacitor 100. Figure 2 In some embodiments, the total thickness H of the dielectric layer 210 ranges from 0.5 μm to 8.4 μm. For example, the total thickness H of the dielectric layer 210 may be 1.2 μm, 3.2 μm, 5 μm, or 6.8 μm.

[0044] The inner electrode layer 220 may be formed by sintering a nickel paste containing indium. Accordingly, the first indium barrier layer 224 may be a concentrated metallic phase layer of indium metal, interposed between the inner layer 222 composed of nickel and the ceramic body of the dielectric layer 210. The dielectric layer 210 may be made of barium titanate, and the first indium barrier layer 224 may include indium, barium, and titanium. The indium addition amount of the nickel paste may be 0.01 mol% to 5 mol%. For example, the indium addition amount of the nickel paste may be 0.05 mol%, 0.1 mol%, 0.2 mol%, 0.3 mol%, 0.4 mol%, 0.5 mol%, 0.6 mol%, 0.7 mol%, 0.8 mol%, 0.9 mol%, 1 mol%, 1.5 mol%, 2 mol%, 2.5 mol%, 3 mol%, 3.5 mol%, 4 mol%, or 4.5 mol%. When the amount of indium added to the nickel paste is within the above range, the mean time between failures of the multilayer ceramic capacitor 100 can be improved, thereby extending the service life of the multilayer ceramic capacitor 100 .

[0045] Due to the addition of indium metal, the material of the inner electrode layer 220 can be sintered in a highly reducing atmosphere. For example, the material of the inner electrode layer 220 can be sintered in an atmosphere with a high hydrogen content. Therefore, the multilayer ceramic capacitor 100 can have stable reliability at higher operating temperatures, such as 105°C or 125°C. Furthermore, the first indium isolation layer 224 can provide a Schottky barrier between the inner layer 222 and the dielectric layer 210, and the Schottky barrier can suppress the leakage current of the multilayer ceramic capacitor 100. Thereby, the multilayer ceramic capacitor 100 has a long high-temperature load life and high reliability.

[0046] Please refer to Figure 1 The first terminal electrode 300 is at least provided on the first end surface 202 of the multilayer ceramic tile 200 and is electrically connected to the internal electrode layer 220 extending from the first end surface 202. The second terminal electrode 400 is at least provided on the second end surface 204 of the multilayer ceramic tile 200 and is electrically connected to the internal electrode layer 220 extending from the second end surface 204. Figure 1 and Figure 2 It can be seen that the first end electrode 300 covers the first end surface 202, and the first surface 205, the second surface 206, the third surface 207, and the fourth surface 208 are adjacent to the first end surface 202. The second end electrode 400 covers the second end surface 204, and the first surface 205, the second surface 206, the third surface 207, and the fourth surface 208 are adjacent to the second end surface 204.

[0047] The first terminal electrode 300 and the second terminal electrode 400 can each have a single-layer structure or a multi-layer structure. Each of the first terminal electrode 300 and the second terminal electrode 400 can have a three-layer structure stacked in sequence, wherein the first layer of the three-layer structure can be made of copper, silver, or a silver-palladium alloy, the second layer of the three-layer structure can be made of nickel, and the third layer of the three-layer structure can be made of tin. The multilayer ceramic capacitor 100 of the present invention can be used in autonomous electric vehicle technology, but is not limited thereto.

[0048] Figure 4 FIG2 is a flowchart illustrating the steps of a method M for manufacturing a multilayer ceramic capacitor 100 according to another embodiment of the present invention. Figure 2 and Figure 4 As shown in step 410 of the manufacturing method M, a plurality of dielectric layers 210 are formed. As shown in step 420 of the manufacturing method M, a plurality of internal electrode layers 220 are formed. As shown in step 430 of the manufacturing method M, the internal electrode layers 220 and the dielectric layers 210 are alternately laminated to form a stack.

[0049] Next, please refer to Figure 2 and Figure 4 As shown in step 440 of manufacturing method M, a sintering process is performed to form the laminated multilayer ceramic tile 200. The sintering process includes a low-temperature burnout step and a high-temperature sintering step. The temperature of the low-temperature burnout step may be 300°C, and the temperature of the high-temperature sintering step may be 1200°C.

[0050] Furthermore, please refer to Figure 2 and Figure 4 As shown in step 450 and step 460 of the manufacturing method M, the first terminal electrode 300 and the second terminal electrode 400 are respectively formed at both ends of the multilayer ceramic tile 200 to obtain the multilayer ceramic capacitor 100.

[0051] The present invention is further illustrated by the following specific examples, which are intended to facilitate those skilled in the art to fully utilize and practice the present invention without excessive interpretation. These examples should not be construed as limiting the scope of the present invention, but are intended to illustrate how to implement the materials and methods of the present invention.

[0052] <Experimental Example 1>

[0053] In Experimental Example 1, the perovskite powder of barium titanate is ball-milled with additives, and the additives may be 3 mol% of dysprosium oxide (Dy2O3), 0.1 mol% of magnesium oxide (MgO) and 0.03 wt% of borosilicate glass powder. The above raw materials are mixed evenly and dried to obtain raw material powder, and the raw material powder is then ground together with an organic solvent to obtain a raw material slurry. The raw material slurry is cast on a plastic film and dried to obtain a ceramic green sheet. Nickel slurry to which 0.05 wt% of indium oxide (In2O3) powder is added is evenly mixed with a three-roller mixer and then printed on the green sheet as an inner layer. Multiple nickel printed sheets are stacked and cut to obtain green sheets of nickel-indium multilayer ceramic capacitor chips. After the organic binder is burned out at 300°C, the green sheet is heated at an oxygen partial pressure of 1×10 -13 Under the conditions of Pa, nickel-indium multilayer ceramic capacitors were fired at 1200°C for 2 hours and then reoxidized at a low temperature. During the sintering process in a reducing atmosphere, indium oxide was converted to metallic indium, forming a nickel-indium alloy. Finally, copper terminal electrodes were formed by heating at 780°C for 20 minutes.

[0054] Next, a highly accelerated life test (HALT) was performed at 140°C and 40V (i.e., four times higher than the rated voltage). The parameters and mean time between failures of Experimental Example 1 are shown in Table 1 below.

[0055] Table 1

[0056]

[0057] Figure 5 FIG. 4 is an annular dark field image of the multilayer ceramic capacitor 100 a of Experimental Example 1 taken by a scanning transmission electron microscope. Figure 6 for Figure 5 The Lα energy dispersion X-ray image of indium in Experiment 1. Figure 5 and Figure 6As can be seen, the inner electrode layer 220 is formed by sintering a nickel paste containing indium. Therefore, the multilayer ceramic capacitor 100a can be referred to as a nickel-indium multilayer ceramic capacitor. The structure of the multilayer ceramic capacitor 100a is substantially the same as that of the multilayer ceramic capacitor 100. The difference between the multilayer ceramic capacitor 100a and the multilayer ceramic capacitor 100 is that the multilayer ceramic capacitor 100a further includes a first indium barrier layer 224 in the inner electrode layer 220, while the dielectric layer 210 of the multilayer ceramic capacitor 100a includes multiple second indium barrier layers 214.

[0058] Specifically, by Figure 5 and Figure 6 As can be seen, the dielectric layer 210 includes a plurality of perovskite oxides 212, and the second indium isolation layer 214 can be formed on a plurality of grain boundaries 212a of the perovskite oxides 212. In other words, the indium metal in the material of the inner electrode layer 220 not only isolates the interface between the inner electrode layer 220 and the corresponding dielectric layer 210, but also diffuses into the dielectric layer 210 and blocks the grain boundaries 212a of the perovskite oxides 212 in the dielectric layer 210.

[0059] Please refer to Figure 5 and Figure 6 , the grains (i.e., grains of barium titanate) can be understood as a core-shell structure, wherein the core region of the grain is barium titanate, and the shell region of the grain is a grain boundary 212a having indium metal (i.e., the second indium isolation layer 214) and a first indium isolation layer 224 having indium metal. In other words, indium metal forms a barrier in the shell region of the core-shell structure. Specifically, the diffused indium (+3) occupies the position of titanium (+4) of the perovskite oxide 212 and acts as an acceptor, and can capture free electrons generated when oxygen vacancies are formed during sintering in a reducing atmosphere. Therefore, the indium isolation in the shell region of the core-shell structure of the barium titanate grains containing the grain boundaries increases the resistivity and reduces the leakage current, thereby improving the mean time between failures of the multilayer ceramic capacitor 100a.

[0060] Nickel forms a liquid phase with the borosilicate glass at the interface between any of the inner electrode layers 220 and the corresponding dielectric layer 210, diffusing into the shell region of the core-shell structure of the barium titanate grains. The co-doping level of the borosilicate glass increases proportionally with the amount of indium added to the nickel paste. The first indium barrier layer 224 and the second indium barrier layer 214 function in conjunction with each other depending on the total thickness of the dielectric layer 210.

[0061] The first indium content of the first indium barrier layer 224 may be greater than the second indium content of each of the second indium barrier layers 214. When the sum of the titanium content of the perovskite oxide 212 and the second indium content of the second indium barrier layer 214 is calculated as 100 mol %, the second indium content may be calculated as 10 -20 mol% to 10 -2mol%. The second indium isolation layer 214 may include indium, barium, and titanium.

[0062] After the sintering process is performed, a first indium isolation layer 224 can be formed at the interface between any one of the internal electrode layers 220 and one of the corresponding dielectric layers 210, and multiple second indium isolation layers 214 can be formed at multiple grain boundaries 212a of the perovskite oxide 212, wherein the first indium isolation layer 224 and the second indium isolation layer 214 can be generated simultaneously.

[0063] <Experimental Examples 2 to 6>

[0064] The manufacturing method of the multilayer ceramic capacitor of Experimental Example 1 is similar to the manufacturing method of the multilayer ceramic capacitors of Experimental Examples 2 to 6 (hereinafter referred to as Experimental Examples 2 to 6). In Experimental Examples 2 to 6, the amount of indium oxide added varies with the total thickness of the dielectric layer of the multilayer ceramic capacitor. The amount of borosilicate glass powder added is substantially proportional to the amount of indium oxide added to promote the diffusion of indium at the grain boundaries of the dielectric layer.

[0065] <Experimental Examples 7 to 14>

[0066] The manufacturing method of the multilayer ceramic capacitor of Experimental Example 1 is similar to the manufacturing method of the multilayer ceramic capacitors of Experimental Examples 7 to 14 (hereinafter referred to as Experimental Examples 7 to 14). In Experimental Examples 7 to 14, the total thickness of the dielectric layer of the multilayer ceramic capacitors is the same, and the addition amount of borosilicate glass powder ranges from 0.01 wt % to 5 wt %, but the addition amount of indium oxide is different.

[0067] <Comparative Examples 1 to 2>

[0068] The manufacturing method of the multilayer ceramic capacitor of Experimental Example 1 is similar to the manufacturing methods of the multilayer ceramic capacitors of Comparative Examples 1 and 2. In Comparative Example 1, indium oxide is not added. In Comparative Example 2, borosilicate glass powder is not added.

[0069] Figure 7 FIG. 1 is a bright field image of the multilayer ceramic capacitor 100 b of Experimental Example 2 taken by a scanning transmission electron microscope. Figure 8 for Figure 7 The Lα energy dispersion X-ray image of indium in Experiment 2. Figure 7 and Figure 8 It can be seen that the multilayer ceramic capacitor 100b is a nickel-indium multilayer ceramic capacitor. Figure 8 As shown, the indium isolation layer (ie, the first indium isolation layer 224 and the second indium isolation layer 214 ) is located at the interface between the inner layer 222 and the dielectric layer 210 , and at the grain boundary 212 a of the perovskite oxide 212 .

[0070] Figure 9for Figure 8 A magnified image of the barium titanate perovskite oxide. Figure 10 for Figure 9 Lα energy dispersive X-ray image of indium oxide in the perovskite of barium titanate. Figure 9 As shown, indium diffuses and isolates within the shell region of the core-shell structure. Indium occupies the titanium position within the barium titanate, and the acceptor function can be extended to the core region of the dielectric layer because the indium is isolated within the shell region, which includes the grain boundaries. The indium isolation within the shell region remains effective even when the dielectric layer thickness increases.

[0071] The results in Table 1 show that the multilayer ceramic capacitor of the present invention has specific contents of borosilicate glass powder and indium oxide, and can improve the mean time between failures compared with the mean time between failures of the multilayer ceramic capacitors of Comparative Examples 1 and 2.

[0072] Figure 11 1100 is a graph showing the total thickness of the dielectric layers versus mean time between failures in nickel multilayer ceramic capacitors and nickel-indium multilayer ceramic capacitors. Figure 11 As shown in Figure 1, as the total thickness of the dielectric layer increases, the mean time between failures (MTBF) of nickel-indium multilayer ceramic capacitors increases, thereby increasing the service life of nickel-indium multilayer ceramic capacitors. Furthermore, compared with nickel multilayer ceramic capacitors, nickel-indium multilayer ceramic capacitors have a better MTBF.

[0073] In summary, the advantage of the present invention is that the inner electrode layer of the multilayer ceramic capacitor includes a nickel inner layer and an indium isolation layer located between the nickel inner layer and the dielectric layer. The indium isolation layer can provide a Schottky barrier between the nickel inner layer and the dielectric layer, and the Schottky barrier can suppress leakage current. Furthermore, due to the addition of indium metal, the multilayer ceramic tile can be sintered in a highly reducing atmosphere. Therefore, the multilayer ceramic capacitor can have stable reliability at higher operating temperatures. Thereby, the high-temperature load life of the multilayer ceramic capacitor can be extended, and the reliability of the multilayer ceramic capacitor can be improved. Compared with the existing multilayer ceramic capacitor, the mean time between failures of the multilayer ceramic capacitor of the present invention is improved, thereby extending the service life of the multilayer ceramic capacitor.

[0074] Although the present invention has been disclosed above in terms of embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0075]

Explanation of symbols

[0076] 100, 100a, 100b: Multilayer ceramic capacitors

[0077] 200:Multi-layer ceramic tiles

[0078] 202: first end surface

[0079] 204: Second end face

[0080] 205: first surface

[0081] 206: Second surface

[0082] 207: Third surface

[0083] 208: Fourth Surface

[0084] 210: dielectric layer

[0085] 212:Perovskite oxide

[0086] 212a: grain boundary

[0087] 214: Second indium isolation layer

[0088] 220: Inner electrode layer

[0089] 222: Inner layer

[0090] 224: first indium isolation layer

[0091] 300: first end electrode

[0092] 400: second terminal electrode

[0093] 410,420,430,440,450,460: Steps

[0094] 1100: Chart

[0095] H: total thickness

[0096] h1,h2: thickness

[0097] M: Manufacturing method.

Claims

1. A multilayer ceramic capacitor, characterized in that Include: A multilayer ceramic tile having a first end surface and a second end surface, the first end surface and the second end surface facing each other, wherein the multilayer ceramic tile comprises: a plurality of dielectric layers comprising a plurality of perovskite oxides and borosilicate glass, wherein the plurality of perovskite oxides comprise barium and titanium; and A plurality of inner electrode layers and the plurality of dielectric layers are alternately stacked, wherein each of the plurality of inner electrode layers comprises: an inner layer, wherein the material of the inner layer comprises nickel; and a first indium isolation layer located between the inner layer and one of the plurality of dielectric layers, wherein the first indium isolation layer has a thickness of 1 nm to 19 nm, the plurality of dielectric layers include a plurality of second indium isolation layers, and the plurality of second indium isolation layers are respectively located at a plurality of grain boundaries of the plurality of perovskite oxides; a first end electrode, disposed on the first end surface and electrically connected to a portion of the plurality of internal electrode layers; and The second end electrode is disposed on the second end surface and is electrically connected to another portion of the plurality of inner electrode layers.

2. The multilayer ceramic capacitor according to claim 1, wherein When the total weight of the plurality of perovskite oxides is 100 wt %, the weight of the borosilicate glass is 0.01 wt % to 5 wt %.

3. The multilayer ceramic capacitor according to claim 1, wherein The borosilicate glass contains boron trioxide, aluminum trioxide and silicon dioxide.

4. The multilayer ceramic capacitor according to claim 1, wherein The plurality of inner electrode layers are formed by sintering a nickel paste containing indium, and the amount of indium added to the nickel paste is 0.01 mol % to 5 mol %.

5. The multilayer ceramic capacitor according to claim 1, wherein A first indium content of the first indium barrier layer is greater than a second indium content of each of the plurality of second indium barrier layers.

6. The multilayer ceramic capacitor according to claim 1, wherein When the sum of the titanium content of the plurality of perovskite oxides and the second indium content of the plurality of second indium isolation layers is 100 mol %, the second indium content is 10 -20 mol% to 10 -2 mol%.

7. The multilayer ceramic capacitor according to claim 1, wherein The first indium isolation layer includes indium, barium and titanium.

8. The multilayer ceramic capacitor according to claim 1, wherein The plurality of second indium isolation layers include indium, barium and titanium.

9. The multilayer ceramic capacitor according to claim 1, wherein A ratio of a thickness of each of the plurality of inner electrode layers to a thickness of each of the plurality of dielectric layers is 0.4 to 0.

6.

10. A method for manufacturing a multilayer ceramic capacitor, characterized in that: Include: forming a plurality of dielectric layers, wherein the plurality of dielectric layers comprises a plurality of perovskite oxides and borosilicate glass, the plurality of perovskite oxides comprising barium and titanium; forming a plurality of inner electrode layers; alternately laminating the plurality of internal electrode layers and the plurality of dielectric layers to form a stack; Performing a sintering process to form the stacked layers into a multilayer ceramic tile, wherein the sintering process comprises: performing a low-temperature burnout step; and performing a high temperature sintering step; as well as A first terminal electrode and a second terminal electrode are respectively formed at both ends of the multilayer ceramic tile to obtain a multilayer ceramic capacitor.

11. The method for manufacturing a multilayer ceramic capacitor according to claim 10, wherein: When the total weight of the plurality of perovskite oxides is 100 wt %, the weight of the borosilicate glass is 0.01 wt % to 5 wt %.

12. The method for manufacturing a multilayer ceramic capacitor according to claim 10, wherein: The borosilicate glass contains boron trioxide, aluminum trioxide and silicon dioxide.

13. The method for manufacturing a multilayer ceramic capacitor according to claim 10, wherein: The plurality of inner electrode layers are formed by sintering a nickel paste containing indium, and the amount of indium added to the nickel paste is 0.01 mol % to 5 mol %.

14. The method for manufacturing a multilayer ceramic capacitor according to claim 10, wherein: After the sintering process is performed, a first indium isolation layer is formed at the interface between any one of the multiple internal electrode layers and one of the multiple dielectric layers corresponding thereto, and multiple second indium isolation layers are formed at multiple grain boundaries of the multiple perovskite oxides, wherein the first indium isolation layer and the multiple second indium isolation layers are generated simultaneously.

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