Preparation method of chip packaging structure and chip packaging structure
By adopting the chip packaging structure method of separately preparing and bonding, the warping and stability problems are solved, the plastic sealing through-hole layer connection with a high aspect ratio is achieved, and the product yield and stability are improved.
Patent Information
- Application Number
- CN202510763218.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-09
- Publication Date
- 2025-09-16
AI Technical Summary
The chip packaging structure is prone to warping during the multi-layer stacking process, which limits the number of layers of modules and redistribution layers. In addition, the height of the plastic-encapsulated through-hole layer made by TMV technology is limited, affecting stability and product yield.
Multiple modules of the chip packaging structure are prepared separately and then bonded together through the first bonding layer and the second bonding layer. The first plastic-sealed through-hole layer and the second plastic-sealed through-hole layer are respectively made on the first circuit layer and the second circuit layer, and the first bonding layer and the second bonding layer are made on the far side thereof to achieve a plastic-sealed through-hole layer connection with a high aspect ratio.
The warping phenomenon is reduced, the product yield is improved, the preparation cost is reduced, and the stability of the chip packaging structure is ensured by the plastic sealing through-hole layer with a high aspect ratio.
Smart Images
Figure CN120656947A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing, and more specifically, to a method for preparing a chip packaging structure and a chip packaging structure. Background Art
[0002] In the field of semiconductor manufacturing, during the current preparation of chip packaging structures, multiple modules of the chip packaging structure are stacked in sequence. This method can easily cause the chip packaging structure to warp, limiting the number of layers that can be stacked in the chip packaging structure, and thus limiting the number of layers that can be made into the redistribution layer. Furthermore, during the production of the multi-layer redistribution layer of the chip packaging structure, defects in any one layer will cause the entire chip packaging structure to be scrapped, thereby affecting the product yield of the chip packaging structure. In addition, if the chip packaging structure uses TMV (Through Molding Via) technology to achieve interconnection between chips, the height of the plastic through-hole layer made by TMV technology in the chip packaging structure is limited, thereby affecting the stability of the chip packaging structure. Summary of the Invention
[0003] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a method for preparing a chip packaging structure, the method comprising: Providing a first circuit layer and a second circuit layer; A first plastic-encapsulated through-hole layer and a second plastic-encapsulated through-hole layer are formed on the first circuit layer and the second circuit layer, respectively, wherein the first plastic-encapsulated through-hole layer includes a first conductive trace that passes through the first plastic-encapsulated through-hole layer, and the second plastic-encapsulated through-hole layer includes a second conductive trace that passes through the second plastic-encapsulated through-hole layer, the first conductive trace is connected to the trace in the first circuit layer, and the second conductive trace is connected to the trace in the second circuit layer; A first bonding layer and a second bonding layer are respectively formed on a side of the first plastic-encapsulated through-hole layer away from the first circuit layer and a side of the second plastic-encapsulated through-hole layer away from the second circuit layer, wherein the first bonding layer includes a third conductive trace penetrating the first bonding layer, and the second bonding layer includes a fourth conductive trace penetrating the second bonding layer, the first conductive trace of the first plastic-encapsulated through-hole layer is connected to the third conductive trace of the first bonding layer, and the second conductive trace of the second plastic-encapsulated through-hole layer is connected to the fourth conductive trace of the second bonding layer; Bonding a side of the first bonding layer facing away from the first circuit layer and a side of the second bonding layer facing away from the second circuit layer, wherein the first conductive trace in the first plastic-encapsulated through-hole layer is connected to the second conductive trace in the second plastic-encapsulated through-hole layer through the third conductive trace and the fourth conductive trace; Arranging at least one chip connected to the wiring in the first circuit layer on the first circuit layer, and manufacturing a packaging layer for at least packaging the chip; A plurality of conductive balls connected to the wiring in the second circuit layer are arranged on the second circuit layer to obtain a chip packaging structure.
[0004] In a possible implementation, the step of providing a first circuit layer and a second circuit layer includes: Providing a first carrier board and a second carrier board; Manufacturing a first circuit layer and a second circuit layer on the first carrier board and the second carrier board respectively; After the step of bonding the side of the first bonding layer facing away from the first circuit layer and the side of the second bonding layer facing away from the second circuit layer, the method further includes: The first carrier board and the second carrier board are removed.
[0005] In a possible implementation, the step of respectively forming a first plastic-sealed through-hole layer and a second plastic-sealed through-hole layer on the first circuit layer and the second circuit layer includes: forming a first conductive layer and a second conductive layer on the first circuit layer and the second circuit layer respectively; The first conductive layer is patterned to obtain a first conductive trace, and the second conductive layer is patterned to obtain a second conductive trace; Forming a first plastic encapsulation layer and a second plastic encapsulation layer on the first conductive trace and the second conductive trace respectively; The first plastic sealing layer and the second plastic sealing layer are patterned to form a first plastic sealing through hole layer and a second plastic sealing through hole layer.
[0006] In a possible implementation, the step of forming the first bonding layer and the second bonding layer on a side of the first plastic-encapsulated through-hole layer away from the first circuit layer and on a side of the second plastic-encapsulated through-hole layer away from the second circuit layer, respectively, includes: Forming a third conductive layer and a fourth conductive layer on a side of the first plastic-encapsulated through-hole layer away from the first circuit layer and a side of the second plastic-encapsulated through-hole layer away from the second circuit layer, respectively; Performing patterning on the third conductive layer to form a third conductive trace, and performing patterning on the fourth conductive layer to form a fourth conductive trace; Forming a first dielectric layer and a second dielectric layer on the third conductive trace and the fourth conductive trace respectively; The first dielectric layer and the second dielectric layer are patterned to form a first bonding layer and a second bonding layer respectively.
[0007] In a possible implementation, the step of forming a third conductive layer and a fourth conductive layer on a side of the first plastic-encapsulated through-hole layer away from the first circuit layer and a side of the second plastic-encapsulated through-hole layer away from the second circuit layer, respectively, includes: Forming a third conductive layer and a fourth conductive layer on a side of the first plastic-encapsulated through-hole layer away from the first circuit layer and a side of the second plastic-encapsulated through-hole layer away from the second circuit layer by physical vapor deposition, respectively, wherein the material of the third conductive layer and the fourth conductive layer comprises copper; The step of forming a first dielectric layer and a second dielectric layer on the third conductive trace and the fourth conductive trace respectively includes: A first dielectric layer and a second dielectric layer are respectively formed on the third conductive trace and the fourth conductive trace by chemical vapor deposition, wherein the materials of the first dielectric layer and the second dielectric layer include low dielectric constant materials, silicon dioxide or silicon nitride.
[0008] Another object of the present application is to provide a chip packaging structure, the chip packaging structure comprising: a first plastic-encapsulated through-hole layer, wherein the first plastic-encapsulated through-hole layer includes a first conductive trace penetrating the first plastic-encapsulated through-hole layer; A first bonding layer is provided on one side of the first plastic-encapsulated through-hole layer, wherein the first bonding layer includes a third conductive trace penetrating the first bonding layer; a second bonding layer, disposed on a side of the first bonding layer away from the first plastic-encapsulated through-hole layer, wherein the second bonding layer includes a fourth conductive trace penetrating the second bonding layer; a second plastic through-hole layer, arranged on a side of the second bonding layer away from the first bonding layer, wherein the second plastic through-hole layer includes a second conductive trace penetrating the second plastic through-hole layer, and the first conductive trace in the first plastic through-hole layer is connected to the second conductive trace in the second plastic through-hole layer through the third conductive trace and the fourth conductive trace; A first circuit layer is provided on a side of the first plastic-encapsulated through-hole layer away from the first bonding layer, wherein the traces in the first circuit layer are connected to the first conductive traces in the first plastic-encapsulated through-hole layer; A second circuit layer is provided on a side of the second plastic-encapsulated through-hole layer away from the second bonding layer, wherein the traces in the second circuit layer are connected to the second conductive traces in the second plastic-encapsulated through-hole layer; A chip is arranged on a side of the first circuit layer away from the first plastic-encapsulated through-hole layer, and the chip is connected to the wiring in the first circuit layer; a packaging layer, at least arranged around the chip; The conductive balls are arranged on a side of the second circuit layer away from the second plastic-encapsulated through-hole layer, and the conductive balls are connected to the traces in the second circuit layer.
[0009] In a possible implementation, the first bonding layer further includes a first dielectric layer, the second bonding layer includes a second dielectric layer, the first dielectric layer is arranged around the third conductive trace of the first bonding layer, and the second dielectric layer is arranged around the fourth conductive trace of the second bonding layer.
[0010] In a possible implementation, the first conductive trace in the first plastic-encapsulated through-hole layer and the third conductive trace in the first bonding layer are correspondingly arranged and interconnected, and the second conductive trace in the second plastic-encapsulated through-hole layer and the fourth conductive trace in the second bonding layer are also correspondingly arranged and interconnected; The third conductive trace in the first bonding layer and the fourth conductive trace in the second bonding layer are correspondingly arranged and connected to each other.
[0011] In a possible implementation, the first circuit layer and the second circuit layer have the same type of circuit layer structure, wherein the type of the circuit layer structure includes a redistribution layer structure.
[0012] In a possible implementation, the first circuit layer includes a plurality of stacked first routing layers and an insulating layer located between adjacent first routing layers, and adjacent first routing layers are connected via insulating layer through-holes; The second circuit layer includes a plurality of stacked second routing layers and an insulating layer between adjacent second routing layers, and adjacent second routing layers are connected via insulating layer through-holes.
[0013] Based on any of the above aspects, embodiments of the present application provide a method for preparing a chip packaging structure and a chip packaging structure. First, a first circuit layer and a second circuit layer are provided. A first plastic-encapsulated via layer and a second plastic-encapsulated via layer are then formed on the first circuit layer and the second circuit layer, respectively. Next, a first bonding layer and a second bonding layer are formed on the side of the first plastic-encapsulated via layer facing away from the first circuit layer and the side of the second plastic-encapsulated via layer facing away from the second circuit layer, respectively. The first bonding layer facing away from the first circuit layer and the second bonding layer facing away from the second circuit layer are then bonded together. Next, at least one chip connected to the traces in the first circuit layer is placed on the first circuit layer, and a packaging layer is formed to encapsulate at least the chip. Finally, a plurality of conductive balls connected to the traces in the second circuit layer are placed on the second circuit layer, resulting in a chip packaging structure. In this manner, the multiple modules of the chip packaging structure are separately prepared and then bonded together via the first bonding layer and the second bonding layer. This reduces warping of the chip packaging structure and allows the separately prepared modules to be individually tested to confirm yield before bonding together, thereby reducing manufacturing costs and improving the product yield of the chip packaging structure. At the same time, the above solution can realize the preparation of a plastic-encapsulated through-hole layer with a relatively high aspect ratio, thereby ensuring the stability of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.
[0015] Figure 1 A step diagram of a method for preparing a chip packaging structure provided in this embodiment; Figure 2a and Figure 2b for Figure 1 Corresponding process flow chart; Figure 3 for Figure 1 Schematic diagram of the sub-step flow of step S120; Figure 4 for Figure 3 One of the corresponding process flow charts; Figure 5 for Figure 3 The corresponding process flow chart 2; Figure 6 for Figure 1 Schematic diagram of the sub-step flow of step S130; Figure 7 for Figure 6 One of the corresponding process flow charts; Figure 8 for Figure 6 The corresponding process flow chart 2; Figure 9 A schematic diagram of a chip packaging structure provided in this embodiment.
[0016] Icons: 1-chip packaging structure; 10-first circuit layer; 20-second circuit layer; 30-first plastic-sealed through-hole layer; 300-first conductive trace; 310-first conductive layer; 320-first plastic-sealed layer; 40-second plastic-sealed through-hole layer; 400-second conductive trace; 410-second conductive layer; 420-second plastic-sealed layer; 50-first bonding layer; 500-third conductive trace; 510-first dielectric layer; 520-third conductive layer; 60-second bonding layer; 600-fourth conductive trace; 610-second dielectric layer; 620-fourth conductive layer; 70-chip; 80-packaging layer; 90-conductive ball; 100-first carrier; 110-second carrier. DETAILED DESCRIPTION
[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.
[0018] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.
[0019] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.
[0020] In the description of this application, it should be noted that the terms "upper" and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or the orientations or positional relationships in which the product of this application is typically placed when in use. These terms are intended solely to facilitate the description of this application and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" and the like are used solely for distinction and should not be construed as indicating or implying relative importance.
[0021] It should be noted that, in the absence of conflict, different features in the embodiments of the present application can be combined with each other.
[0022] In order to solve the technical problems mentioned in the above background technology, the inventors innovatively designed the following technical solutions, and the specific implementation solutions of this application will be described in detail with reference to the accompanying drawings.
[0023] Please refer to Figure 1 、 Figure 2a and Figure 2b , Figure 1 A step diagram of a method for preparing a chip packaging structure 1 provided in this embodiment, Figure 2a and Figure 2b for Figure 1 The corresponding process diagram. Figure 1 、 Figure 2a and Figure 2b The preparation method of the chip packaging structure 1 is described in detail.
[0024] Step S110 , providing a first circuit layer 10 and a second circuit layer 20 .
[0025] In this step, the first circuit layer 10 and the second circuit layer 20 are respectively manufactured on the carrier board to provide a basic electrical connection structure for the chip packaging structure 1 .
[0026] In this embodiment, the first circuit layer 10 and the second circuit layer 20 can be manufactured by photolithography or etching to ensure circuit accuracy and reliability. In addition, the first circuit layer 10 and the second circuit layer 20 can include a multi-layer wiring structure.
[0027] Step S120, making a first plastic-sealed through-hole layer 30 and a second plastic-sealed through-hole layer 40 on the first circuit layer 10 and the second circuit layer 20 respectively, wherein the first plastic-sealed through-hole layer 30 includes a first conductive trace 300 passing through the first plastic-sealed through-hole layer 30, and the second plastic-sealed through-hole layer 40 includes a second conductive trace 400 passing through the second plastic-sealed through-hole layer 40, the first conductive trace 300 is connected to the trace in the first circuit layer 10, and the second conductive trace 400 is connected to the trace in the second circuit layer 20.
[0028] In this embodiment, the first through-molding via layer 30 and the second through-molding via layer 40 may be implemented by through-molding via (TMV) technology.
[0029] In step S130, a first bonding layer 50 and a second bonding layer 60 are respectively formed on a side of the first plastic-encapsulated through-hole layer 30 away from the first circuit layer 10 and a side of the second plastic-encapsulated through-hole layer 40 away from the second circuit layer 20, wherein the first bonding layer 50 includes a third conductive trace 500 passing through the first bonding layer 50, and the second bonding layer 60 includes a fourth conductive trace 600 passing through the second bonding layer 60, the first conductive trace 300 of the first plastic-encapsulated through-hole layer 30 is connected to the third conductive trace 500 of the first bonding layer 50, and the second conductive trace 400 of the second plastic-encapsulated through-hole layer 40 is connected to the fourth conductive trace 600 of the second bonding layer 60.
[0030] In step S140, the side of the first bonding layer 50 facing away from the first circuit layer 10 and the side of the second bonding layer 60 facing away from the second circuit layer 20 are bonded, wherein the first conductive trace 300 in the first plastic-encapsulated through-hole layer 30 is connected to the second conductive trace 400 in the second plastic-encapsulated through-hole layer 40 through the third conductive trace 500 and the fourth conductive trace 600.
[0031] In the related art, the chip packaging structure 1 is prepared by stacking multiple modules in sequence. This method easily causes the chip packaging structure 1 to warp. However, in this embodiment, the multiple modules of the chip packaging structure 1 are prepared separately and then bonded together through the first bonding layer 50 and the second bonding layer 60. On the one hand, this reduces the warping of the chip packaging structure 1. On the other hand, the multiple modules prepared separately can be tested separately to confirm that the yield is normal before being bonded together, which not only reduces the preparation cost but also improves the product yield of the chip packaging structure 1. In addition, in the related art, if the chip packaging structure 1 uses TMV technology to achieve interconnection between chips 70, the current TMV technology is limited by the film material, and the height of the plastic sealing through hole layer produced by it in the chip packaging structure 1 is limited, resulting in a low aspect ratio. In this embodiment, the first plastic sealing through hole layer 30 and the second plastic sealing through hole layer 40 are bonded together through the first bonding layer 50 and the second bonding layer 60, which can achieve the preparation of a plastic sealing through hole layer with a high aspect ratio, thereby improving the stability of the chip packaging structure 1.
[0032] In step S150 , at least one chip 70 connected to the wiring in the first circuit layer 10 is disposed on the first circuit layer 10 , and a packaging layer 80 is manufactured to at least package the chip 70 .
[0033] In this embodiment, the encapsulation layer 80 is used to protect the chip 70 from external environmental influences, such as moisture, dust, or mechanical impact.
[0034] In step S160 , a plurality of conductive balls 90 connected to the wiring in the second circuit layer 20 are provided on the second circuit layer 20 to obtain a chip packaging structure 1 .
[0035] In this embodiment, the conductive balls 90 are used to achieve electrical connection between the chip package structure 1 and other external circuit elements or substrates.
[0036] It is worth noting that the conductive balls 90 can be tin balls.
[0037] Furthermore, step S110 can be implemented in the following manner.
[0038] First, a first carrier board 100 and a second carrier board 110 are provided.
[0039] In this embodiment, the first carrier board 100 and the second carrier board 110 serve as a temporary supporting structure for fixing and supporting the first circuit layer 10 and the second circuit layer 20 .
[0040] It is worth noting that the materials of the first carrier 100 and the second carrier 110 can be silicon, ceramic or metal, etc. The materials of the first carrier 100 and the second carrier 110 are not specifically limited here and need to be selected according to actual conditions.
[0041] Next, the first circuit layer 10 and the second circuit layer 20 are respectively manufactured on the first carrier board 100 and the second carrier board 110 .
[0042] In this embodiment, a first circuit layer 10 and a second circuit layer 20 are typically prepared using processes such as photolithography or etching to achieve electrical connections within the chip packaging structure 1. When a multi-layer circuit structure is required, the first wiring layer and the insulating layer should be repeatedly and alternately prepared to form the first circuit layer 10, and the second wiring layer and the insulating layer should be repeatedly and alternately prepared to form the second circuit layer 20. In this way, this embodiment greatly reduces the warping of the chip packaging structure 1 by separately preparing the multi-layer circuit structure and then bonding the two together, thereby achieving the manufacture of the multi-layer circuit structure of the chip packaging structure 1. In addition, the modules with multi-layer circuit structures prepared separately can be individually tested to confirm that the yield is normal before being bonded together, which not only reduces the preparation cost but also improves the product yield of the chip packaging structure 1.
[0043] In this case, after step S140, the method further includes: Remove the first carrier 100 and the second carrier 110. In this embodiment, after the first plastic-encapsulated through-hole layer 30 and the first bonding layer 50 are prepared on the first carrier 100 carrying the first circuit layer 10, and after the second plastic-encapsulated through-hole layer 40 and the second bonding layer 60 are prepared on the second carrier 110 carrying the second circuit layer 20, it is necessary to remove the first carrier 100 and the second carrier 110, and then the subsequent chips 70 or conductive balls 90 are manufactured on the side of the first circuit layer 10 away from the first plastic-encapsulated through-hole layer 30 and on the side of the second circuit layer 20 away from the second plastic-encapsulated through-hole layer 40.
[0044] For further information, please refer to Figure 3 、 Figure 4 and Figure 5 , Figure 3 for Figure 1 Schematic diagram of the sub-step flow of step S120, Figure 4 for Figure 3 One of the corresponding process flow charts, Figure 5 for Figure 3 Corresponding to the second process flow chart, step S120 can be implemented in the following manner.
[0045] In sub-step S121 , a first conductive layer 310 and a second conductive layer 410 are formed on the first circuit layer 10 and the second circuit layer 20 , respectively.
[0046] In this step, a layer of conductive material may be formed on the first circuit layer 10 to form the first conductive layer 310 and a layer of conductive material may be formed on the second circuit layer 20 to form the second conductive layer 410 by physical vapor deposition, chemical vapor deposition or electroplating.
[0047] In sub-step S122 , the first conductive layer 310 is patterned to obtain the first conductive trace 300 , and the second conductive layer 410 is patterned to obtain the second conductive trace 400 .
[0048] In this step, the patterning method of the first conductive layer 310 and the second conductive layer 410 includes photolithography and etching processes. For example, a pattern is first formed using photoresist and a mask through a photolithography process, and then unnecessary parts are removed through an etching process to form the first conductive trace 300 and the second conductive trace 400.
[0049] It is worth noting that the materials of the first conductive layer 310 and the second conductive layer 410 can be metals, such as copper, aluminum and other materials.
[0050] In sub-step S123 , a first plastic encapsulation layer 320 and a second plastic encapsulation layer 420 are formed on the first conductive trace 300 and the second conductive trace 400 , respectively.
[0051] In this embodiment, the material of the first plastic packaging layer 320 and the second plastic packaging layer 420 may be epoxy resin, which may be formed by injection molding or compression molding.
[0052] In sub-step S124 , the first plastic encapsulation layer 320 and the second plastic encapsulation layer 420 are patterned to form a first plastic encapsulation through hole layer 30 and a second plastic encapsulation through hole layer 40 .
[0053] In this embodiment, the first plastic layer 320 and the second plastic layer 420 are patterned to ensure that the side of the first plastic via layer 30 away from the first circuit layer 10 and the side of the second plastic via layer 40 away from the second circuit layer 20 remain flat.
[0054] Furthermore, step S120 can also be implemented in the following manner.
[0055] First, a first plastic encapsulation layer 320 and a second plastic encapsulation layer 420 are formed on the first circuit layer 10 and the second circuit layer 20, respectively. Next, a first plastic encapsulation through hole and a second plastic encapsulation through hole are formed in the first plastic encapsulation layer 320 and the second plastic encapsulation through hole, respectively. Then, a conductive material is filled in the first plastic encapsulation through hole and the second plastic encapsulation through hole, respectively, to form the first conductive trace 300 and the second conductive trace 400. The first plastic encapsulation through hole and the second plastic encapsulation through hole can be formed in the first plastic encapsulation layer 320 and the second plastic encapsulation through hole, respectively, by laser etching and punching.
[0056] For further information, please refer to Figure 6 、 Figure 7 and Figure 8 , Figure 6 for Figure 1 Schematic diagram of the sub-step flow of step S130, Figure 7 for Figure 6 One of the corresponding process flow charts, Figure 8 for Figure 6 The corresponding second process, step S130 , can be implemented in the following manner.
[0057] In sub-step S131 , a third conductive layer 520 and a fourth conductive layer 620 are respectively formed on a side of the first plastic through hole layer 30 away from the first circuit layer 10 and a side of the second plastic through hole layer 40 away from the second circuit layer 20 .
[0058] In this step, a third conductive layer 520 can be formed on the side of the first plastic-encapsulated through-hole layer 30 away from the first circuit layer 10, and a fourth conductive layer 620 can be formed on the side of the second plastic-encapsulated through-hole layer 40 away from the second circuit layer 20 by physical vapor deposition, chemical vapor deposition or electroplating. The material of the third conductive layer 520 and the fourth conductive layer 620 can be metal, such as copper.
[0059] In sub-step S132 , the third conductive layer 520 is patterned to form the third conductive trace 500 , and the fourth conductive layer 620 is patterned to form the fourth conductive trace 600 .
[0060] In this step, the patterning method of the third conductive layer 520 and the fourth conductive layer 620 includes photolithography and etching processes. For example, a pattern is first formed using photoresist and a mask through a photolithography process, and then unnecessary parts are removed through an etching process to form a third conductive trace 500 and a fourth conductive trace 600.
[0061] In sub-step S133 , a first dielectric layer 510 and a second dielectric layer 610 are formed on the third conductive trace 500 and the fourth conductive trace 600 , respectively.
[0062] In this step, a first dielectric layer 510 may be deposited on the third conductive trace 500 and a second dielectric layer 610 may be deposited on the fourth conductive trace 600 by chemical vapor deposition or atomic layer deposition.
[0063] In sub-step S134 , the first dielectric layer 510 and the second dielectric layer 610 are patterned to form a first bonding layer 50 and a second bonding layer 60 .
[0064] In this step, the first dielectric layer 510 and the second dielectric layer 610 are patterned to ensure that the side of the first bonding layer 50 away from the first plastic via layer 30 and the side of the second bonding layer 60 away from the second plastic via layer 40 remain flat.
[0065] In this embodiment, hybrid bonding is achieved by adding a first bonding layer 50 and a second bonding layer 60 to the first plastic-sealed through-hole layer 30 and the second plastic-sealed through-hole layer 40 respectively. This process is usually carried out in a high-temperature environment, and ultimately electrical connection is achieved between the first circuit layer 10, the first plastic-sealed through-hole layer 30, the first bonding layer 50, the second bonding layer 60, the second plastic-sealed through-hole layer 40 and the second circuit layer 20.
[0066] Furthermore, sub-step S131 can be implemented by the following method: a third conductive layer 520 and a fourth conductive layer 620 are respectively produced on the side of the first plastic-encapsulated through-hole layer 30 away from the first circuit layer 10 and on the side of the second plastic-encapsulated through-hole layer 40 away from the second circuit layer 20 by physical vapor deposition, wherein the material of the third conductive layer 520 and the fourth conductive layer 620 includes copper.
[0067] In this embodiment, physical vapor deposition (PVD) is a technique that converts a material from a solid or liquid state into a gaseous state through a physical process, and then deposits it on a substrate to form a thin film. Common PVD methods include magnetron sputtering, DC magnetron sputtering, and radio frequency magnetron sputtering.
[0068] Sub-step S133 can be achieved by forming a first dielectric layer 510 and a second dielectric layer 610 on the third conductive trace 500 and the fourth conductive trace 600, respectively, by chemical vapor deposition. The materials of the first dielectric layer 510 and the second dielectric layer 610 include, but are not limited to, low-k materials, silicon dioxide, silicon nitride, and the like. In this embodiment, chemical vapor deposition is a technique that converts a gaseous precursor into a solid thin film through a chemical reaction.
[0069] Based on the same inventive concept, another object of this application is to provide a chip packaging structure 1, please refer to Figure 9 , Figure 9 This is a schematic diagram of a chip package structure 1 provided in this embodiment. The chip package structure 1 includes a first plastic encapsulation via layer 30, a first bonding layer 50, a second bonding layer 60, a second plastic encapsulation via layer 40, a first circuit layer 10, a second circuit layer 20, a chip 70, a packaging layer 80, and conductive balls 90.
[0070] The first molded through-hole layer 30 includes a first conductive trace 300 that passes through the first molded through-hole layer 30. The first bonding layer 50 is disposed on one side of the first molded through-hole layer 30, wherein the first bonding layer 50 includes a third conductive trace 500 that passes through the first bonding layer 50. The second bonding layer 60 is disposed on a side of the first bonding layer 50 away from the first molded through-hole layer 30, wherein the second bonding layer 60 includes a fourth conductive trace 600 that passes through the second bonding layer 60. The second molded through-hole layer 40 is disposed on a side of the second bonding layer 60 away from the first bonding layer 50, wherein the second molded through-hole layer 40 includes a second conductive trace 400 that passes through the second molded through-hole layer 40. The first conductive trace 300 in the first molded through-hole layer 30 is connected to the second conductive trace 400 in the second molded through-hole layer 40 via the third conductive trace 500 and the fourth conductive trace 600.
[0071] The first circuit layer 10 is disposed on a side of the first molded through-hole layer 30 away from the first bonding layer 50. The traces in the first circuit layer 10 are connected to the first conductive traces 300 in the first molded through-hole layer 30. The second circuit layer 20 is disposed on a side of the second molded through-hole layer 40 away from the second bonding layer 60. The traces in the second circuit layer 20 are connected to the second conductive traces 400 in the second molded through-hole layer 40. The chip 70 is disposed on a side of the first circuit layer 10 away from the first molded through-hole layer 30. The chip 70 is connected to the traces in the first circuit layer 10. The encapsulation layer 80 is disposed at least around the chip 70. The conductive balls 90 are disposed on a side of the second circuit layer 20 away from the second molded through-hole layer 40. The conductive balls 90 are connected to the traces in the second circuit layer 20.
[0072] In this embodiment, the side of the first bonding layer 50 away from the first plastic through-hole layer 30 and the side of the second bonding layer 60 away from the second plastic through-hole layer 40 are hybrid-bonded to achieve electrical connection between the chip 70, the first circuit layer 10, the first plastic through-hole layer 30, the first bonding layer 50, the second bonding layer 60, the second plastic through-hole layer 40, the second circuit layer 20 and the conductive ball 90.
[0073] In this embodiment, in the direction perpendicular to the plane of the first plastic-sealed through-hole layer 30 and the second plastic-sealed through-hole layer 40, the thickness of the first plastic-sealed through-hole layer 30 is the same as the thickness of the second plastic-sealed through-hole layer 40, the thickness of the first bonding layer 50 is the same as the thickness of the second bonding layer 60, the thickness of the first plastic-sealed through-hole layer 30 is greater than the thickness of the first bonding layer 50, and similarly, the thickness of the second plastic-sealed through-hole layer 40 is greater than the thickness of the second bonding layer 60.
[0074] In addition, the length of the first molded through-hole layer 30 in the direction in which it extends is much greater than the thickness of the first molded through-hole layer 30 in a direction perpendicular to the plane in which the first molded through-hole layer 30 is located. The length of the first bonding layer 50 in the direction in which the first bonding layer 50 extends is much greater than the thickness of the first bonding layer 50 in a direction perpendicular to the plane in which the first bonding layer 50 is located. Similarly, the length of the second molded through-hole layer 40 in the direction in which the second molded through-hole layer 40 extends is much greater than the thickness of the second molded through-hole layer 40 in a direction perpendicular to the plane in which the second molded through-hole layer 40 is located. The length of the second bonding layer 60 in the direction in which the second bonding layer 60 extends is much greater than the thickness of the second bonding layer 60 in a direction perpendicular to the plane in which the second bonding layer 60 is located. In this way, the above-mentioned chip packaging structure 1, in which the two modules are prepared separately and then bonded together, can ensure that the first molded through-hole layer 30 and the second molded through-hole layer 40 achieve a high aspect ratio, thereby ensuring the stability of the chip packaging structure 1. At the same time, the warping phenomenon of the chip packaging structure 1 can also be reduced, thereby ensuring the product yield of the chip packaging structure 1.
[0075] Further, please refer again to Figure 1 The first bonding layer 50 also includes a first dielectric layer 510, and the second bonding layer 60 includes a second dielectric layer 610. The first dielectric layer 510 is arranged around the third conductive trace 500 of the first bonding layer 50, and the second dielectric layer 610 is arranged around the fourth conductive trace 600 of the second bonding layer 60.
[0076] In this embodiment, the first bonding layer 50 is formed by the third conductive trace 500 and the first dielectric layer 510 located therearound. The third conductive layer 520 is a conductive material, and the first dielectric layer 510 is a dielectric material. The second bonding layer 60 is formed by the fourth conductive trace 600 and the second dielectric layer 610 located therearound. The fourth conductive layer 620 is a conductive material, and the second dielectric layer 610 is a dielectric material.
[0077] The two are then mixed and bonded in a high-temperature environment. Under high-temperature conditions, the atoms or molecules between the conductive material and the dielectric material interact with each other to form a stable chemical bond, thereby achieving a connection between the first dielectric layer 510 and the second dielectric layer 610, and a connection between the third conductive trace 500 and the fourth conductive trace 600, thereby achieving an electrical connection between the chip 70, the first circuit layer 10, the first plastic-encapsulated through-hole layer 30, the first bonding layer 50, the second bonding layer 60, the second plastic-encapsulated through-hole layer 40, the second circuit layer 20 and the conductive ball 90.
[0078] Further, please refer again to Figure 1 The first conductive trace 300 in the first plastic-encapsulated through-hole layer 30 and the third conductive trace 500 in the first bonding layer 50 are correspondingly arranged and interconnected, and the second conductive trace 400 in the second plastic-encapsulated through-hole layer 40 and the fourth conductive trace 600 in the second bonding layer 60 are also correspondingly arranged and interconnected.
[0079] The third conductive trace 500 in the first bonding layer 50 and the fourth conductive trace 600 in the second bonding layer 60 are correspondingly arranged and interconnected. In this way, electrical connections are achieved among the first plastic via layer 30, the first bonding layer 50, the second bonding layer 60, and the second plastic via layer 40.
[0080] Furthermore, the first circuit layer 10 and the second circuit layer 20 have the same type of circuit layer structure, wherein the type of circuit layer structure includes a redistribution layer structure (RDL) or an ABF circuit layer structure. The RDL is mainly composed of dielectric materials such as polyimide and copper metal, and the material of the ABF is a composite material mainly composed of epoxy resin, silicon micropowder and curing agent.
[0081] It is worth noting that the first circuit layer 10 and the second circuit layer 20 may also have different types of circuit layer structures. For example, the first circuit layer 10 may be a multi-layer RDL, and the second circuit layer 20 may be a multi-layer ABF. Alternatively, the first circuit layer 10 may be a multi-layer ABF, and the second circuit layer 20 may be a multi-layer RDL.
[0082] Further, please refer again to Figure 1The first circuit layer 10 includes a plurality of stacked first routing layers (not shown in the figure) and an insulating layer (not shown in the figure) located between adjacent first routing layers, and adjacent first routing layers are connected by insulating layer through-holes. The second circuit layer 20 includes a plurality of stacked second routing layers (not shown in the figure) and an insulating layer (not shown in the figure) located between adjacent second routing layers, and adjacent second routing layers are connected by insulating layer through-holes. In this way, the above-mentioned chip packaging structure 1 can realize the production of multiple routing layers of the chip packaging structure 1 by separately preparing multiple layers of first routing layers or multiple layers of second routing layers and then bonding them together, which greatly reduces the warping phenomenon of the chip packaging structure 1 and thereby improves the product yield of the chip packaging structure 1.
[0083] In summary, the present application provides a method for preparing a chip packaging structure and a chip packaging structure. First, a first circuit layer and a second circuit layer are provided. A first plastic-encapsulated via layer and a second plastic-encapsulated via layer are then formed on the first circuit layer and the second circuit layer, respectively. Next, a first bonding layer and a second bonding layer are formed on the side of the first plastic-encapsulated via layer facing away from the first circuit layer and the side of the second plastic-encapsulated via layer facing away from the second circuit layer, respectively. The first bonding layer facing away from the first circuit layer and the second bonding layer facing away from the second circuit layer are then bonded together. Next, at least one chip connected to the traces in the first circuit layer is placed on the first circuit layer, and a packaging layer is formed to encapsulate at least the chip. Finally, a plurality of conductive balls connected to the traces in the second circuit layer are placed on the second circuit layer, resulting in a chip packaging structure. In this manner, the multiple modules of the chip packaging structure are separately prepared and then bonded together via the first bonding layer and the second bonding layer, reducing warping of the chip packaging structure. Furthermore, the separately prepared modules can be individually tested to confirm yield before bonding together, reducing manufacturing costs and improving the product yield of the chip packaging structure. At the same time, the above solution can realize the preparation of a plastic-encapsulated through-hole layer with a relatively high aspect ratio, thereby ensuring the stability of the chip packaging structure.
[0084] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.
Claims
1. A method for preparing a chip packaging structure, characterized in that: The method comprises: Providing a first circuit layer and a second circuit layer; A first plastic-encapsulated through-hole layer and a second plastic-encapsulated through-hole layer are formed on the first circuit layer and the second circuit layer, respectively, wherein the first plastic-encapsulated through-hole layer includes a first conductive trace that passes through the first plastic-encapsulated through-hole layer, and the second plastic-encapsulated through-hole layer includes a second conductive trace that passes through the second plastic-encapsulated through-hole layer, the first conductive trace is connected to the trace in the first circuit layer, and the second conductive trace is connected to the trace in the second circuit layer; A first bonding layer and a second bonding layer are respectively formed on a side of the first plastic-encapsulated through-hole layer away from the first circuit layer and a side of the second plastic-encapsulated through-hole layer away from the second circuit layer, wherein the first bonding layer includes a third conductive trace penetrating the first bonding layer, and the second bonding layer includes a fourth conductive trace penetrating the second bonding layer, the first conductive trace of the first plastic-encapsulated through-hole layer is connected to the third conductive trace of the first bonding layer, and the second conductive trace of the second plastic-encapsulated through-hole layer is connected to the fourth conductive trace of the second bonding layer; Bonding a side of the first bonding layer facing away from the first circuit layer and a side of the second bonding layer facing away from the second circuit layer, wherein the first conductive trace in the first plastic-encapsulated through-hole layer is connected to the second conductive trace in the second plastic-encapsulated through-hole layer through the third conductive trace and the fourth conductive trace; Arranging at least one chip connected to the wiring in the first circuit layer on the first circuit layer, and manufacturing a packaging layer for at least packaging the chip; A plurality of conductive balls connected to the wiring in the second circuit layer are arranged on the second circuit layer to obtain a chip packaging structure.
2. The method for preparing a chip packaging structure according to claim 1, wherein: The step of providing a first circuit layer and a second circuit layer includes: Providing a first carrier board and a second carrier board; Manufacturing a first circuit layer and a second circuit layer on the first carrier board and the second carrier board respectively; After the step of bonding the side of the first bonding layer facing away from the first circuit layer and the side of the second bonding layer facing away from the second circuit layer, the method further includes: The first carrier board and the second carrier board are removed.
3. The method for preparing a chip packaging structure according to claim 1, wherein: The step of respectively forming a first plastic-sealed through-hole layer and a second plastic-sealed through-hole layer on the first circuit layer and the second circuit layer comprises: forming a first conductive layer and a second conductive layer on the first circuit layer and the second circuit layer respectively; The first conductive layer is patterned to obtain a first conductive trace, and the second conductive layer is patterned to obtain a second conductive trace; Forming a first plastic encapsulation layer and a second plastic encapsulation layer on the first conductive trace and the second conductive trace respectively; The first plastic sealing layer and the second plastic sealing layer are patterned to form a first plastic sealing through hole layer and a second plastic sealing through hole layer.
4. The method for preparing a chip packaging structure according to claim 1, wherein: The step of respectively forming a first bonding layer and a second bonding layer on a side of the first plastic-encapsulated through-hole layer away from the first circuit layer and a side of the second plastic-encapsulated through-hole layer away from the second circuit layer comprises: Forming a third conductive layer and a fourth conductive layer on a side of the first plastic-encapsulated through-hole layer away from the first circuit layer and a side of the second plastic-encapsulated through-hole layer away from the second circuit layer, respectively; Performing patterning on the third conductive layer to form a third conductive trace, and performing patterning on the fourth conductive layer to form a fourth conductive trace; Forming a first dielectric layer and a second dielectric layer on the third conductive trace and the fourth conductive trace respectively; The first dielectric layer and the second dielectric layer are patterned to form a first bonding layer and a second bonding layer respectively.
5. The method for preparing a chip packaging structure according to claim 4, wherein: The step of forming a third conductive layer and a fourth conductive layer on a side of the first plastic-encapsulated through-hole layer away from the first circuit layer and a side of the second plastic-encapsulated through-hole layer away from the second circuit layer, respectively, comprises: Forming a third conductive layer and a fourth conductive layer on a side of the first plastic-encapsulated through-hole layer away from the first circuit layer and a side of the second plastic-encapsulated through-hole layer away from the second circuit layer by physical vapor deposition, respectively, wherein the material of the third conductive layer and the fourth conductive layer comprises copper; The step of forming a first dielectric layer and a second dielectric layer on the third conductive trace and the fourth conductive trace respectively includes: A first dielectric layer and a second dielectric layer are respectively formed on the third conductive trace and the fourth conductive trace by chemical vapor deposition, wherein the materials of the first dielectric layer and the second dielectric layer include low dielectric constant materials, silicon dioxide or silicon nitride.
6. A chip packaging structure, characterized in that: The chip packaging structure includes: a first plastic-encapsulated through-hole layer, wherein the first plastic-encapsulated through-hole layer includes a first conductive trace penetrating the first plastic-encapsulated through-hole layer; A first bonding layer is provided on one side of the first plastic-encapsulated through-hole layer, wherein the first bonding layer includes a third conductive trace penetrating the first bonding layer; a second bonding layer, disposed on a side of the first bonding layer away from the first plastic-encapsulated through-hole layer, wherein the second bonding layer includes a fourth conductive trace penetrating the second bonding layer; a second plastic through-hole layer, arranged on a side of the second bonding layer away from the first bonding layer, wherein the second plastic through-hole layer includes a second conductive trace penetrating the second plastic through-hole layer, and the first conductive trace in the first plastic through-hole layer is connected to the second conductive trace in the second plastic through-hole layer through the third conductive trace and the fourth conductive trace; A first circuit layer is provided on a side of the first plastic-encapsulated through-hole layer away from the first bonding layer, wherein the traces in the first circuit layer are connected to the first conductive traces in the first plastic-encapsulated through-hole layer; A second circuit layer is provided on a side of the second plastic-encapsulated through-hole layer away from the second bonding layer, wherein the traces in the second circuit layer are connected to the second conductive traces in the second plastic-encapsulated through-hole layer; A chip is arranged on a side of the first circuit layer away from the first plastic-encapsulated through-hole layer, and the chip is connected to the wiring in the first circuit layer; a packaging layer, at least arranged around the chip; The conductive balls are arranged on a side of the second circuit layer away from the second plastic-encapsulated through-hole layer, and the conductive balls are connected to the traces in the second circuit layer.
7. The chip packaging structure according to claim 6, wherein: The first bonding layer further includes a first dielectric layer, and the second bonding layer includes a second dielectric layer. The first dielectric layer is arranged around the third conductive trace of the first bonding layer, and the second dielectric layer is arranged around the fourth conductive trace of the second bonding layer.
8. The chip packaging structure according to claim 6, wherein: The first conductive trace in the first plastic-encapsulated through-hole layer and the third conductive trace in the first bonding layer are correspondingly arranged and interconnected, and the second conductive trace in the second plastic-encapsulated through-hole layer and the fourth conductive trace in the second bonding layer are also correspondingly arranged and interconnected; The third conductive trace in the first bonding layer and the fourth conductive trace in the second bonding layer are correspondingly arranged and connected to each other.
9. The chip packaging structure according to claim 6, wherein: The first circuit layer and the second circuit layer have the same type of circuit layer structure, wherein the type of the circuit layer structure includes a redistribution layer structure.
10. The chip packaging structure according to claim 6, wherein: The first circuit layer includes a plurality of stacked first routing layers and an insulating layer located between adjacent first routing layers, and adjacent first routing layers are connected via insulating layer through-holes; The second circuit layer includes a plurality of stacked second routing layers and an insulating layer between adjacent second routing layers, and adjacent second routing layers are connected via insulating layer through-holes.