A method for manufacturing a shallow trench isolation structure and a shallow trench isolation structure

Abstract

The application discloses a manufacturing method of a shallow trench isolation structure and the shallow trench isolation structure. The manufacturing method of the shallow trench isolation structure comprises the following steps: forming a hard mask layer with a protection structure on a semiconductor layer; forming a trench penetrating through the hard mask layer and extending into the semiconductor layer; forming an isolation medium in the trench, the protection structure being adjacent to the isolation medium in the trench; and removing the hard mask layer to form the shallow trench isolation structure; wherein during the process of removing the hard mask layer, the protection structure protects the sidewall of the isolation medium in the trench to prevent a gap from being formed between the semiconductor layer and the sidewall of the isolation medium.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a manufacturing method of a shallow trench isolation structure and the shallow trench isolation structure. BACKGROUND

[0002] Shallow Trench Isolation (STI) is an important isolation technology in semiconductor process, which is used to provide isolation between active devices to prevent interference and crosstalk between different devices. With the continuous progress of integrated circuit manufacturing process, the requirement for device isolation is also getting higher and higher, and STI is widely used because of its good isolation performance and the advantage of being suitable for sub-micron and nanometer level process.

[0003] In the traditional semiconductor process, a hard mask layer is formed in the semiconductor layer, and the semiconductor layer is etched through the hard mask layer to form a trench in the semiconductor layer. After filling the isolation medium in the trench and removing the hard mask layer, the STI structure is formed.

[0004] In the STI structure formed by the traditional process, a divot is formed between the sidewalls of the semiconductor layer and the isolation medium. In the subsequent process, conductive material may be left in the divot, causing edge leakage and other defects, reducing the reliability of the semiconductor device. SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a manufacturing method of a shallow trench isolation structure and the shallow trench isolation structure, which solves the problem of forming a divot between the sidewalls of the semiconductor layer and the isolation medium in the prior art.

[0006] According to an aspect of the present application, a manufacturing method of a shallow trench isolation structure is provided, comprising: forming a hard mask layer with a protection structure on a semiconductor layer; forming a trench extending through the hard mask layer and into the semiconductor layer; forming an isolation medium in the trench, the protection structure being adjacent to the isolation medium in the trench; and removing the hard mask layer to form a shallow trench isolation structure; wherein during the process of removing the hard mask layer, the protection structure protects the sidewall of the isolation medium in the trench to prevent a divot from being formed between the semiconductor layer and the sidewall of the isolation medium.

[0007] Optionally, the method of forming a hard mask layer with a protection structure on a semiconductor layer comprises: forming a first hard mask layer on the surface of the semiconductor layer; forming a protection area in the first hard mask layer, the area of the first hard mask layer other than the protection area being a non-protection area.

[0008] Optionally, the method for forming a hard mask layer with a protection structure on a semiconductor layer comprises: forming a second hard mask layer on the first hard mask layer, wherein the thickness of the second hard mask layer on the protection region is greater than the thickness of the second hard mask layer on the non-protection region, and the second hard mask layer on the protection region forms a protection protrusion, and the protection protrusion and the protection region constitute a protection structure; and forming a third hard mask layer on the second hard mask layer, wherein the part of the third hard mask layer covering the protection protrusion forms a protruding part correspondingly.

[0009] Optionally, the method for forming a protection region in the first hard mask layer comprises: forming a patterned resist mask layer on the first hard mask layer; and performing ion implantation on the first hard mask layer through the opening of the resist mask layer to form a doped region in the first hard mask layer, and the doped region is the protection region.

[0010] Optionally, the second hard mask layer is formed by using a SACVD process, and the thickness of the second hard mask layer above the protection region is greater than the thickness of the second hard mask layer above the non-protection region, and the second hard mask layer above the protection region forms a protection protrusion.

[0011] Optionally, the method for forming an isolation medium in the trench comprises: forming an isolation medium filling the trench and covering the surface of the third hard mask layer; and removing the isolation medium covering the surface of the third hard mask layer, and the isolation medium filling the trench is retained; wherein, the protruding part of the third hard mask layer is removed together when the isolation medium covering the surface of the third hard mask layer is removed, and the top of the isolation medium is flush with the surface of the remaining hard mask layer.

[0012] Optionally, the first hard mask layer and the second hard mask layer are oxide layers, and the third hard mask layer is a nitride layer.

[0013] Optionally, the third hard mask layer is removed by using a wet etching process; and the second hard mask layer and the first hard mask layer are removed by using a wet etching process, and the protection structure protects the sidewall of the isolation medium in the process of removing the second hard mask layer and the first hard mask layer.

[0014] Optionally, in the process of removing the first hard mask layer, the etching rate of the protection region is lower than the etching rate of the non-protection region.

[0015] According to another aspect of the present application, there is provided a shallow trench isolation structure formed by using the manufacturing method of any one of the above shallow trench isolation structures, the isolation structure comprising a trench formed in a semiconductor layer and an isolation medium filling the trench, wherein there is no gap between the semiconductor layer and the sidewall of the isolation medium.

[0016] The unexpected technical effect of the present application is:

[0017] In the embodiment, a hard mask layer with a protection structure is formed, wherein the protection structure protects the sidewall of the isolation medium in the trench during the etching back of the isolation medium, so as to prevent the formation of a gap between the semiconductor layer and the sidewall of the isolation medium.

[0018] Further, the protection structure is formed during the formation of the hard mask layer and is removed at the same time during the removal of the hard mask layer, so that no additional steps are needed.

[0019] In the preferred embodiment, a patterned resist mask layer is formed on the surface of the first hard mask layer, and ion implantation is performed on the first hard mask layer through the openings of the resist mask layer to form a protection region in the first hard mask layer; during the formation of the second hard mask layer, the second hard mask layer above the protection region forms a protection protrusion, and the protection protrusion and the protection region jointly constitute the protection structure. The embodiment utilizes the influence of the doped first mask layer on the deposition rate of the subsequent second mask layer to form the protection protrusion, avoiding the use of etching process, thereby avoiding the damage of the etching process to the semiconductor layer, and at the same time avoiding the introduction of too many etching auxiliary structure layers.

[0020] In the preferred embodiment, the SACVD deposition process is used to form the second hard mask layer, and the SACVD process has high sensitivity to the doped first hard mask layer, so that during the formation of the second hard mask layer, the deposition rate of the second hard mask layer above the protection region is higher than that of the second hard mask layer above the non-protection region, and therefore, through the same deposition step, the thickness of the second hard mask layer above the protection region is greater than that of the second hard mask layer above the non-protection region.

[0021] In the preferred embodiment, the third hard mask layer is removed by wet etching, which utilizes the different etching selectivity between the third hard mask layer and the second hard mask layer and between the third hard mask layer and the isolation medium. Compared with dry etching, which needs to use photolithography process, the embodiment process is simpler and at least saves one photolithography step.

[0022] In the preferred embodiment, the second hard mask layer and the first hard mask layer are removed by wet etching. Since the protection protrusion covers the sidewall of the isolation medium, the protection protrusion is removed first than the isolation medium. Further, the thickness of the protection protrusion is greater than that of the rest of the second hard mask layer, so that when the rest of the second hard mask layer is removed, the protection protrusion still remains a part, and the isolation medium adjacent to the protection protrusion is protected from contacting the etchant. When the first hard mask layer is removed, the remaining protection protrusion continues to protect the sidewall of the isolation medium.

[0023] Further, when the protection protrusions are removed, the non-protection area of the first hard mask layer has been removed by a part, the remaining thickness of the protection area is greater than the remaining thickness of the non-protection area, and the etching rate of the doped protection area is lower than the etching rate of the non-protection area, so that the non-protection area is removed prior to the protection area, and the isolation medium adjacent to the protection area is protected from the etchant. BRIEF DESCRIPTION OF DRAWINGS

[0024] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0025] Figures la to le schematic cross-sectional views of various stages in the process of forming an STI structure in the prior art, in which:

[0026] Figure la a schematic view of forming a hard mask layer on a semiconductor layer in the prior art is shown;

[0027] Figure lb a schematic view of forming a trench in a semiconductor layer in the prior art is shown;

[0028] Figure lc a schematic view of forming an isolation medium filling the trench and covering the surface of the hard mask layer in the prior art is shown;

[0029] Figure Id a schematic view of removing the second hard mask layer in the prior art is shown;

[0030] Figure le a schematic view of removing the first hard mask layer to form a shallow trench isolation structure in the prior art is shown;

[0031] Figure 2 a flow chart of the manufacturing method of the shallow trench isolation structure provided by the embodiments of the present application is shown;

[0032] Figures 3a to 3j schematic cross-sectional views of various stages in the manufacturing process of the semiconductor device of the embodiments of the present application are shown, in which:

[0033] Figure 3a a schematic view of forming a first hard mask layer on the surface of a semiconductor layer in the embodiments of the present application is shown;

[0034] Figure 3b a schematic view of forming a protection area in the first hard mask layer in the embodiments of the present application is shown;

[0035] Figure 3c a schematic view of forming a second hard mask layer on the first hard mask layer in the embodiments of the present application is shown;

[0036] Figure 3d A schematic diagram of forming a third hard mask layer on the second hard mask layer is shown;

[0037] Figure 3e A schematic diagram of forming a trench through the hard mask layer and the semiconductor layer is shown;

[0038] Figure 3f A schematic diagram of forming an isolation medium filling the trench and covering the surface of the hard mask layer is shown;

[0039] Figure 3g A schematic diagram of removing the portion of the isolation medium on the surface of the hard mask layer is shown;

[0040] Figure 3h A schematic diagram of removing the third hard mask layer is shown;

[0041] Figure 31 A schematic diagram of removing the second hard mask layer and the non-protected region of the first hard mask layer while keeping the protected region of the first hard mask layer is shown;

[0042] Figure 3j A schematic diagram of removing the protected region of the first hard mask layer is shown.

[0043] BRIEF DESCRIPTION OF DRAWINGS DETAILED DESCRIPTION

[0044] The present application will be described in more detail with reference to the drawings, in which:

[0045] In describing the structure of the device, when a layer or a region is referred to as being "on" or "above" another layer or another region, it can mean that it is directly on or above the other layer or the other region, or it can contain other layers or regions therebetween. Also, if the device is flipped, the layer or the region will be "below" or "under" the other layer or the other region.

[0046] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0047] This application may be presented in various forms, some of which will be described below.

[0048] Figures la to le Schematic cross-sectional views of the various stages in the formation of an STI (Shallow Trench Isolation) structure in the prior art are shown.

[0049] like Figure la As shown, a mask layer 120 is formed on the first semiconductor layer 110, and a patterned resist mask layer PR1 is formed on the mask layer 120. In this embodiment, the mask layer 120 includes a stacked first mask layer 121, a second mask layer 122, and a third mask layer 123, wherein the first mask layer 121 is an oxide layer (e.g., a SiO2 layer), the second mask layer 122 is a nitride layer (e.g., a SiN layer), and the third mask layer 123 is, for example, a composite layer of a carbon layer and a nitride layer (e.g., a SION layer).

[0050] like Figure lb As shown, the pattern of the resist mask layer PR1 is transferred to the mask layer 120 and the first semiconductor layer 110 by etching the patterned resist mask layer PR1, thereby forming a first trench 130 in the first semiconductor layer 110. After the first trench 130 is formed, the third mask layer 123 is removed.

[0051] like Figure lc As shown, for example, a dielectric layer 140 is formed by a deposition process to fill the first trench 130 and cover the surface of the mask layer 120. The dielectric layer 140 is, for example, an oxide layer (e.g., a SiO2 layer), but is not limited thereto.

[0052] like Figure Id As shown, for example, the dielectric layer 140 covering the surface of the mask layer 120 is removed using a CMP (Chemical Mechanical Planarization) process, and the second mask layer 122 is removed using a wet etching process.

[0053] like Figure leAs shown, a wet etching process is used to remove the first mask layer 121 to form the shallow trench isolation structure. After the second mask layer 122 is removed, the sidewall of the top of the dielectric layer 140 is exposed. During the process of removing the first mask layer 121, the etchant contacts the top surface and the sidewall of the top of the dielectric layer 140, and a portion of the sidewall of the dielectric layer 140 is corroded by the etchant, thereby forming a gap 150 between the first semiconductor layer 110 and the sidewall of the dielectric layer 140. In the subsequent process, conductive material may be left in the gap 150, resulting in edge leakage and other defects, and reducing the reliability of the semiconductor device.

[0054] In view of this, the embodiments of the present application provide a manufacturing method of a shallow trench isolation structure, Figure 2 A flow chart of the manufacturing method of the shallow trench isolation structure provided by the embodiments of the present application is shown, and the manufacturing method will be described in detail with reference to Figure 2 The manufacturing method comprises the following steps.

[0055] S10: forming a hard mask layer with a protection structure on a semiconductor layer;

[0056] S20: forming a trench penetrating through the hard mask layer and reaching the inside of the semiconductor layer;

[0057] S30: forming an isolation medium in the trench, and the protection structure is adjacent to the isolation medium in the trench; and

[0058] S40: removing the hard mask layer to form a shallow trench isolation structure;

[0059] In the embodiments, the hard mask layer with the protection structure is formed, wherein the protection structure protects the sidewall of the isolation medium in the trench during the process of removing the hard mask layer, so as to prevent the formation of a gap between the semiconductor layer and the sidewall of the isolation medium. Further, the protection structure is formed during the process of forming the hard mask layer, and is removed at the same time during the process of removing the hard mask layer, so that no additional steps are needed.

[0060] Figures 3a to 3j Cross-sectional diagrams of various stages in the manufacturing process of the semiconductor device of the embodiments of the present application are shown, and the manufacturing method of the semiconductor device of the embodiments of the present application will be described below in combination with Figure 2 and Figures 3a to 3j .

[0061] In step S10, the hard mask layer with the protection structure is formed on the semiconductor layer, as shown in Figures 3a to 3d .

[0062] As shown in Figure 3a , the first hard mask layer 221 is formed on the surface of the second semiconductor layer 210.

[0063] In this step, a first hard mask layer 221 is formed on the surface of the second semiconductor layer 210, for example by using a deposition process. The second semiconductor layer 210 can be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer, and the second semiconductor layer 210 can also have a semiconductor device formed therein, such as a MOS transistor, a diode, a triode, etc. In this embodiment, the first hard mask layer 221 is an oxide layer, for example a silicon oxide (SiO2) layer.

[0064] As shown in FIG. 2B, a protection region 221a is formed in the first hard mask layer 221. Figure 3b

[0065] In this step, a patterned photoresist mask layer PR21 is formed on the surface of the first hard mask layer 221, and ions are implanted into the first hard mask layer 221 through the openings of the photoresist mask layer PR21 to form a doped region in the first hard mask layer 221, wherein the doped first hard mask layer forms the protection region 221a, and the non-doped first hard mask layer 221 forms a non-protection region 221b. In one embodiment, for example, nitrogen ions are implanted into the first hard mask layer 221 to perform nitrogen (N) doping on the first hard mask layer 221, but the application is not limited thereto.

[0066] As shown in FIG. 2C, a second hard mask layer 222 is formed on the first hard mask layer 221. Figure 3c

[0067] In this embodiment, the second hard mask layer 222 is an oxide layer, for example a silicon oxide (SiO2) layer. The second hard mask layer 222 is formed by using a SACVD (Sub Atmospheric Chemical Vapor Deposition) process. The SACVD process has high sensitivity to the doped first hard mask layer 221, specifically, the SACVD process has high sensitivity to the doped first hard mask layer 221 is embodied in that, during the process of forming the second hard mask layer 222, the deposition rate of the second hard mask layer 222 above the protection region 221a is higher than the deposition rate of the second hard mask layer 222 above the non-protection region 221b, and therefore, through the same deposition step, the thickness of the second hard mask layer 222 above the protection region 221a is greater than the thickness of the second hard mask layer 222 above the non-protection region 221b, the second hard mask layer 222 above the protection region 221a forms a protection protrusion 222a, and the protection protrusion 222a and the protection region 221a jointly form a protection structure.

[0068] As shown in FIG. 2D, a third hard mask layer 223 is formed on the second hard mask layer 222. Figure 3d

[0069] ​​​In this step, a third hard mask layer 223 is formed, for example, by a deposition process. The third hard mask layer 223 conformally covers the second hard mask layer 222 and the protection protrusions 222a, so that the portions of the third hard mask layer 223 covering the protection protrusions 222a correspondingly form protrusions 223a. In this embodiment, the third hard mask layer 223 is a nitride layer, for example, a silicon nitride (SiN) layer.

[0070] In step S20, trenches are formed through the hard mask layers and into the semiconductor layer, wherein the trenches are formed between the protection structures, as shown in Figure 3e

[0071] In this step, a patterned resist mask layer is formed on the surface of the hard mask layer (specifically, the third hard mask layer 233), and the hard mask layer and the second semiconductor layer 210 are etched through the openings of the resist mask layer, so that the pattern of the resist mask layer is transferred to the hard mask layer and the second semiconductor layer 210, to form second trenches 230 extending through the hard mask layer and into the second semiconductor layer 210. After the second trenches 230 are formed, the resist mask layer is removed.

[0072] The openings of the resist mask layer define the positions of the second trenches 230. In this embodiment, the openings of the resist mask layer are opposite to the regions between the protrusions 223a, so that the second trenches 230 are formed between the protrusions 223a and between the protection structures. In other words, the protrusions 223 and the protection structures are respectively adjacent to the sidewalls of the second trenches 230. As shown in Figure 3e Figure 3e , the protection structures are adjacent to the first side (e.g., the left side in Figure 3e ) and the second side (e.g., the right side in Figure 3e ) of the second trenches 230, and correspondingly, the protrusions 223 are adjacent to the first side (e.g., the left side in Figure 3e ) and the second side (e.g., the right side in

[0073] Although Figure 3e only the first side sidewall and the second side sidewall of the second trenches 230 are shown in the cross-sectional view, it should be understood that the protection structures are adjacent to any sidewall of the second trenches 230. For example, when the horizontal cross-sectional shape of the second trenches 230 is circular, square, or the like, the protection structures are around the second trenches 230 and adjacent to the sidewalls of the second trenches 230. When the horizontal cross-sectional shape of the second trenches 230 is annular, the protection structures are adjacent to the outer sidewall and the inner sidewall of the second trenches 230.

[0074] In step S30, an isolation medium 240 is formed in the second trenches 230, and the protection structures are adjacent to the isolation medium 240 in the second trenches 230, as shown in​​Figures 3f to 3g As shown.

[0075] Specifically, such as Figure 3f As shown, for example, a deposition process is used to form an isolation medium 240, which fills the second trench 230 and covers the surface of the hard mask layer (specifically, the third hard mask layer 233). In this embodiment, the isolation medium 240 is, for example, an oxide layer, such as a silicon oxide (SiO2) layer. In other embodiments, the isolation medium 240 can be made of other materials as needed, such as a nitride layer.

[0076] Next, as Figure 3g As shown, the portion of the isolation medium 240 located on the surface of the hard mask layer is removed using CMP (Chemical Mechanical Planarization) or etching processes, while the isolation medium 240 filling the second trench 230 is retained. During the removal of the portion of the isolation medium 240 located on the surface of the hard mask layer, the protrusion 223a of the third hard mask layer 223 is simultaneously removed, making the top of the isolation medium 240 flush with the top of the third hard mask layer 223.

[0077] In step S40, the hard mask layer is removed to form a shallow trench isolation structure, such as... Figures 3h to 31 As shown.

[0078] Specifically, such as Figure 3h As shown, the third hard mask layer 223 is removed. In this step, for example, wet etching is used to remove the third hard mask layer 223. The third hard mask layer (nitride layer) 223 and the isolation medium (oxide layer) 240 have different etching selectivity ratios. By selecting the etchant used in wet etching, the third hard mask layer 223 is removed, while the isolation medium 240 is retained. Simultaneously, the third hard mask layer (nitride layer) 223 and the second hard mask layer (oxide layer) 222 have different etching selectivity ratios. By selecting the etchant used in wet etching, the third hard mask layer 223 is removed, while the second hard mask layer 222 is retained.

[0079] Next, as Figure 31 and Figure 3j As shown, the second hard mask layer 222 and the first hard mask layer 221 are removed. During the removal of the second hard mask layer 222 and the first hard mask layer 221, the protective structure protects the sidewalls of the isolation medium 240 in the second trench 230 to prevent the formation of gaps between the second semiconductor layer 210 and the sidewalls of the isolation medium 240.

[0080] Specifically, the second hard mask layer 222 and the first hard mask layer 221 are removed, for example, by using a wet etching process. In the embodiment, the second hard mask layer 222, the first hard mask layer 221 and the isolation medium 240 are all oxide layers. In the same etching step, the etchant of the wet etching process contacts the exposed surface, and then the etching process is implemented. When the second hard mask layer 222 is removed, the protective protrusion 222a adjacent to the isolation medium 240 protects the sidewall of the isolation medium 240. Since the sidewall of the isolation medium 240 is covered by the protective protrusion 222a, the protective protrusion 222a contacts the etchant of the wet etching process. The protective protrusion 222a is etched preferentially to the sidewall of the isolation medium 240. Further, the thickness of the protective protrusion 222a is greater than the thickness of the rest of the second hard mask layer 222. When the rest of the second hard mask layer 222 is removed, a part of the protective protrusion 222a remains.

[0081] Then, the first hard mask layer 221 is continuously removed. When the first hard mask layer 221 is removed, the remaining protective protrusion 222a continues to protect the sidewall of the isolation medium 240. Further, when the protective protrusion 222a is completely removed, the protective region 221a continues to protect the sidewall of the isolation medium 240. Specifically, when the protective protrusion 222a is removed, the non-protective region 221b of the first hard mask layer 221 has been removed partially. The remaining thickness of the protective region 221a is greater than the remaining thickness of the non-protective region 221b. The etching rate of the doped protective region 221a is lower than the etching rate of the non-protective region 221b. Therefore, the non-protective region 221b is etched faster than the protective region 221a.

[0082] After the above steps, the top of the isolation medium 240 is removed partially, and the sidewall of the part of the isolation medium 240 beyond the second semiconductor layer 210 can also be removed partially. However, no gap appears between the second semiconductor layer 210 and the sidewall of the isolation medium 240.

[0083] Corresponding to the manufacturing method of the shallow trench isolation structure provided in the above embodiment, another embodiment of the present application further provides a shallow trench isolation structure manufactured by any of the manufacturing methods provided in the above embodiments. Figure 3j The structure shown is an exemplary structure of the shallow trench isolation structure provided in the embodiment of the present application. The shallow trench isolation structure provided in the embodiment of the present application is protected by the protective structure adjacent to the isolation medium. No gap appears between the second semiconductor layer 210 and the sidewall of the isolation medium 240. The introduction of conductive material between the second semiconductor layer 210 and the sidewall of the isolation medium 240 in the subsequent deposition of the conductive layer is prevented. Further, the edge leakage and other defects of the shallow trench isolation structure are prevented, and the reliability of the semiconductor device is ensured.

[0084] The unexpected technical effects of the present application are:

[0085] In the present embodiment, a hard mask layer with a protection structure is formed, wherein the protection structure protects the sidewall of the isolation medium in the trench during the etching back of the isolation medium, so as to prevent the formation of a gap between the semiconductor layer and the sidewall of the isolation medium.

[0086] Further, the protection structure is formed during the formation of the hard mask layer and is removed simultaneously during the removal of the hard mask layer, so that no additional steps are needed.

[0087] In a preferred embodiment, a patterned resist mask layer is formed on the surface of the first hard mask layer, and ion implantation is performed on the first hard mask layer through the openings of the resist mask layer to form a protection region in the first hard mask layer; during the formation of the second hard mask layer, the second hard mask layer above the protection region forms a protection protrusion, and the protection protrusion and the protection region jointly constitute the protection structure. The present embodiment utilizes the influence of the doped first mask layer on the deposition rate of the subsequent second mask layer to form the protection protrusion, avoiding the use of etching process, thereby avoiding the damage to the semiconductor layer caused by the etching process, and avoiding the introduction of too many etching auxiliary structure layers.

[0088] In a preferred embodiment, the SACVD deposition process is used to form the second hard mask layer, and the SACVD process has high sensitivity to the doped first hard mask layer, so that during the formation of the second hard mask layer, the deposition rate of the second hard mask layer above the protection region is higher than the deposition rate of the second hard mask layer above the non-protection region, and therefore, through the same deposition step, the thickness of the second hard mask layer above the protection region is greater than the thickness of the second hard mask layer above the non-protection region.

[0089] In a preferred embodiment, the third hard mask layer is removed by wet etching, which utilizes the different etching selectivity between the third hard mask layer and the second hard mask layer and between the third hard mask layer and the isolation medium. Compared with dry etching, which needs to use photolithography process, the present embodiment process is simpler and at least saves one photolithography step.

[0090] In a preferred embodiment, the second hard mask layer and the first hard mask layer are removed by wet etching. Since the protection protrusion covers the sidewall of the isolation medium, the protection protrusion is removed first, and further, the thickness of the protection protrusion is greater than the thickness of the remaining region of the second hard mask layer, so that when the remaining region of the second hard mask layer is removed, the protection protrusion still remains a part, and the isolation medium adjacent to the protection protrusion is protected from contacting the etchant. When the first hard mask layer is removed, the remaining protection protrusion continues to protect the sidewall of the isolation medium.

[0091] Further, when the protection bump is removed, the non-protection area of the first hard mask layer has been removed by a part, the remaining thickness of the protection area is greater than the remaining thickness of the non-protection area, and the etching rate of the doped protection area is lower than the etching rate of the non-protection area, so that the non-protection area is removed prior to the protection area, and the isolation medium adjacent to the protection area is protected from the etchant.

[0092] In accordance with the embodiments of the present application as described above, these embodiments are not described in detail with all of the possible modifications and alterations. It is apparent that many modifications and changes of the embodiments are possible in light of the above description. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well use the present application and make modifications and uses on the basis of the present application. The present application is limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a shallow trench isolation structure, comprising: forming a hard mask layer with a protection structure on a semiconductor layer; forming a trench through the hard mask layer and extending into the semiconductor layer; forming an isolation medium in the trench, the protection structure being adjacent to the isolation medium in the trench; and removing the hard mask layer to form a shallow trench isolation structure; wherein the protection structure protects the sidewall of the isolation medium in the trench during the removal of the hard mask layer to prevent a gap between the semiconductor layer and the sidewall of the isolation medium; the method for forming a hard mask layer with a protection structure on a semiconductor layer comprises: forming a first hard mask layer on a surface of the semiconductor layer; forming a protection region in the first hard mask layer, the first hard mask layer excluding the protection region being a non-protection region; forming a second hard mask layer on the first hard mask layer, wherein the thickness of the second hard mask layer on the protection region is greater than the thickness of the second hard mask layer on the non-protection region, the second hard mask layer on the protection region forming a protection protrusion, the protection protrusion and the protection region constituting a protection structure; and forming a third hard mask layer on the second hard mask layer, wherein the part of the third hard mask layer covering the protection protrusion forms a protruding part correspondingly.

2. The method of manufacturing a shallow trench isolation structure according to claim 1, wherein, the method for forming a protection region in the first hard mask layer comprises: forming a patterned resist mask layer on the first hard mask layer; ion implantation is performed on the first hard mask layer through the opening of the resist mask layer to form a doped region in the first hard mask layer, the doped region being the protection region.

3. The method of manufacturing a shallow trench isolation structure of claim 1, wherein, The second hard mask layer is formed by SACVD process, the thickness of the second hard mask layer above the protection region is greater than the thickness of the second hard mask layer above the non-protection region, and the second hard mask layer above the protection region forms a protection protrusion.

4. The method of manufacturing a shallow trench isolation structure of claim 1, wherein, the method for forming an isolation medium in the trench comprises: forming an isolation medium filling the trench and covering the surface of the third hard mask layer; removing the isolation medium covering the surface of the third hard mask layer, the isolation medium filling the trench is retained; wherein the protruding part of the third hard mask layer is removed together with the isolation medium covering the surface of the third hard mask layer, the top of the isolation medium is flush with the surface of the remaining hard mask layer.

5. The method of manufacturing a shallow trench isolation structure of claim 1, wherein, The first hard mask layer and the second hard mask layer are oxide layers, and the third hard mask layer is a nitride layer.

6. The method of manufacturing a shallow trench isolation structure of claim 5, wherein, The third hard mask layer is removed by wet etching process, and the second hard mask layer and the first hard mask layer are removed by wet etching, the protection structure protects the sidewall of the isolation medium during the removal of the second hard mask layer and the first hard mask layer.

7. The method of manufacturing a shallow trench isolation structure of claim 6, wherein, During the removal of the first hard mask layer, the etching rate of the protection region is lower than the etching rate of the non-protection region.

8. A shallow trench isolation structure formed by the method of any of claims 1-7, the isolation structure comprising a trench formed in a semiconductor layer, and an isolation medium filling the trench, wherein, There is no gap between the semiconductor layer and the sidewall of the isolation medium.

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