Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a substrate on which an active device is formed; forming an interlayer dielectric layer covering the active device on the substrate; forming an interconnection contact hole penetrating through the interlayer dielectric layer at the top of the active device, wherein the interconnection contact hole is exposed out of the top surface of the active device; forming barrier layers on the side walls and the bottoms of the interconnection contact holes; removing partial thickness of the barrier layer at the bottom of the interconnection contact hole; and filling a conductive layer in contact with the barrier layer in the residual space of the interconnection contact hole, wherein the conductive layer and the barrier layer serve as an interconnection structure. According to the semiconductor structure, the barrier layer with partial thickness is removed, so that the thickness of the barrier layer can be reduced, the distance between the conductive layer and the active device is reduced, the electron transmission distance between the conductive layer and the active device is reduced, the resistance between the conductive layer and the active device is reduced, and the performance of the semiconductor structure is further improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the semiconductor device fabrication process, interconnect contact holes—vertical vias connecting the transistor active area to the first metal layer—play a crucial role. As device dimensions in integrated circuits continue to shrink, the size of interconnect contact holes also decreases, making the resistance of interconnect contact holes increasingly significant in affecting circuit performance. The formation of interconnect contact holes requires multiple complex process steps, including dielectric deposition, photolithography, etching, barrier layer deposition, and filler material deposition. Failures in any of these steps can lead to defects in the interconnect contact holes, impacting the performance and reliability of the entire chip.

[0003] Currently, the performance of semiconductor structures still needs to be improved. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which an active device is formed; forming an interlayer dielectric layer covering the active device on the substrate; forming an interconnection contact hole penetrating the interlayer dielectric layer on top of the active device, with the interconnection contact hole exposing the top surface of the active device; forming a barrier layer on the sidewalls and bottom of the interconnection contact hole; removing a portion of the thickness of the barrier layer at the bottom of the interconnection contact hole; and filling the remaining space of the interconnection contact hole with a conductive layer in contact with the barrier layer.

[0006] Optionally, the step of removing a portion of the thickness of the barrier layer at the bottom of the interconnect contact hole includes: forming a barrier material layer on the top of the interlayer dielectric layer and the bottom and sidewalls of the interconnect contact hole; and etching away a portion of the thickness of the barrier layer at the bottom of the interconnect contact hole.

[0007] Optionally, the process of etching and removing a portion of the barrier layer at the bottom of the interconnect contact hole includes a plasma dry etching process.

[0008] Optionally, the etching gas used in the plasma dry etching process includes one or more of CHF 3 , Cl 2 and CF 4 .

[0009] Optionally, the process parameters of the plasma dry etching process include: etching gas flow rate between 10 sccm and 60 sccm; chamber pressure between 5 mTorr and 20 mTorr; bias power between 30 W and 100 W; and etching time between 5 S and 60 S.

[0010] Optionally, the step of forming the barrier layer includes: forming a barrier material layer on the top of the interlayer dielectric layer, the bottom and sidewalls of the interconnection contact hole, and using the barrier material layer on the bottom and sidewalls of the interconnection contact hole as the barrier layer.

[0011] Optionally, the process of forming the barrier material layer includes a metal organic chemical vapor deposition process.

[0012] Optionally, the material of the barrier layer includes one or both of titanium nitride and tantalum nitride.

[0013] Optionally, after forming the interconnection contact hole and before forming the barrier layer, the method further includes: forming an adhesion layer on the bottom and sidewall of the interconnection contact hole; in the step of forming the barrier layer, the barrier layer covers the adhesion layer.

[0014] Optionally, the step of forming the adhesion layer includes: forming an adhesion material layer on the top of the interlayer dielectric layer, the bottom and sidewalls of the interconnection contact hole, and coating the adhesion material layer on the bottom and sidewalls of the interconnection contact hole.

[0015] Optionally, the material of the adhesion layer includes titanium.

[0016] Optionally, the step of forming a conductive layer includes: forming a conductive material layer on the top of the interlayer dielectric layer and in the interconnect contact hole; using the top of the interlayer dielectric layer as a stopping position, removing the conductive material layer above the top of the interlayer dielectric layer, and using the remaining conductive material layer located in the interconnect contact hole as the conductive layer.

[0017] Optionally, in the step of providing the substrate, the active device includes a gate structure and source / drain doped layers located on both sides of the gate structure; and in the step of forming the interconnection contact hole, the interconnection contact hole exposes the top surface of the source / drain doped layers.

[0018] Optionally, the step of forming the interconnect contact hole includes: forming a patterned mask layer on top of the interlayer dielectric layer; using the patterned mask layer as a mask, patterning the interlayer dielectric layer to form an interconnect contact hole penetrating the interlayer dielectric layer, and the interconnect contact hole exposes the top surface of the active device.

[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0020] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein an interconnect contact hole is formed on top of an active device, penetrating an interlayer dielectric layer, and exposing the top surface of the active device through the interconnect contact hole; a barrier layer is formed on the sidewalls and bottom of the interconnect contact hole; a portion of the barrier layer at the bottom of the interconnect contact hole is removed; and a conductive layer in contact with the barrier layer is filled in the remaining space of the interconnect contact hole. That is, the distance between the conductive layer and the active device is the thickness of the barrier layer. Accordingly, by removing a portion of the barrier layer, the thickness of the barrier layer can be reduced, and the distance between the conductive layer and the active device can be reduced, thereby reducing the electron transmission distance between the conductive layer and the active device, and reducing the resistance between the conductive layer and the active device, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 4 A schematic structural diagram corresponding to each step of a method for forming a semiconductor structure is shown;

[0022] Figures 5 to 11 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0023] Currently, the performance of semiconductor structures still needs to be improved. The reasons why the performance needs to be improved are analyzed in conjunction with a method for forming a semiconductor structure.

[0024] in, Figures 1 to 4 A structural schematic diagram corresponding to each step of a method for forming a semiconductor structure is shown.

[0025] refer to Figure 1 , providing a substrate 10, on which an active device 15 is formed, and on which an interlayer dielectric layer 11 covering the active device 15 is formed;

[0026] refer to Figure 2 , forming an interconnection contact hole 20 penetrating the interlayer dielectric layer 11 on the top of the active device 15, and the interconnection contact hole 20 exposes the top surface of the active device 15;

[0027] refer to Figure 3 , forming a barrier layer 26 on the sidewalls and bottom of the interconnection contact hole 20;

[0028] refer to Figure 4 , the remaining space of the interconnection contact hole 20 is filled with a conductive layer 30 in contact with the barrier layer 26 .

[0029] Research has found that during the formation of the barrier layer 26 on the sidewalls and bottom of the interconnect contact hole 20, the reaction gas has a longer transmission path on the sidewalls and a lower concentration of gas molecules reaching the sidewalls, resulting in a slower deposition rate. However, the reaction gas concentration at the bottom of the interconnect contact hole 20 is higher and the deposition rate is faster, resulting in a thinner barrier layer 26 on the sidewalls of the interconnect contact hole 20 and a thicker barrier layer 26 at the bottom of the interconnect contact hole 20. After the conductive layer 30 is subsequently formed, the distance between the conductive layer 30 and the active device 15 is the thickness of the barrier layer 26. Since the barrier layer 26 at the bottom of the interconnect contact hole 20 is thicker, the electron transmission distance between the conductive layer 30 and the active device 15 becomes shorter, and the electron transmission distance is positively correlated with the resistance, which means that the resistance between the conductive layer 30 and the active device 15 is larger, thereby affecting the performance of the semiconductor structure.

[0030] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which an active device is formed; forming an interlayer dielectric layer covering the active device on the substrate; forming an interconnection contact hole penetrating the interlayer dielectric layer on top of the active device, with the interconnection contact hole exposing the top surface of the active device; forming a barrier layer on the sidewall and bottom of the interconnection contact hole; removing a portion of the thickness of the barrier layer at the bottom of the interconnection contact hole; and filling the remaining space of the interconnection contact hole with a conductive layer in contact with the barrier layer.

[0031] The method for forming a semiconductor structure provided by an embodiment of the present invention forms an interconnect contact hole penetrating an interlayer dielectric layer on top of an active device, wherein the interconnect contact hole exposes the top surface of the active device, forms a barrier layer on the sidewalls and bottom of the interconnect contact hole, removes a portion of the thickness of the barrier layer at the bottom of the interconnect contact hole, and fills the remaining space of the interconnect contact hole with a conductive layer in contact with the barrier layer. That is, the distance between the conductive layer and the active device is the thickness of the barrier layer. Accordingly, by removing a portion of the thickness of the barrier layer, the thickness of the barrier layer can be reduced, and the distance between the conductive layer and the active device can be reduced, thereby reducing the electron transmission distance between the conductive layer and the active device, and reducing the resistance between the conductive layer and the active device, thereby improving the performance of the semiconductor structure.

[0032] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] in, Figures 5 to 11 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0034] refer to Figure 5 , providing a substrate 101, on which an active device 100 is formed.

[0035] Specifically, the substrate 101 provides a process platform for a subsequent method of forming a semiconductor structure.

[0036] In this embodiment, the material of the substrate 101 is silicon. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0037] It should be noted that the active device 100 is used in the semiconductor structure to control or process electrical signals.

[0038] As an example, the active device 100 includes a transistor.

[0039] In this embodiment, in the step of providing the substrate 101 , the active device 100 includes a gate structure 102 and source / drain doped layers 106 located on both sides of the gate structure 102 .

[0040] Specifically, the gate structure 102 is used to control the on and off of the conductive channel.

[0041] In this embodiment, the material of the gate structure 102 includes polysilicon.

[0042] In other embodiments, the gate structure may also be a metal gate structure, and the material of the gate structure is not limited herein.

[0043] It should be noted that the source-drain doped layer 106 is used as the source region and the drain region of the transistor.

[0044] In this embodiment, when forming an NMOS transistor, the source / drain doping layer 106 includes a stress layer doped with N-type ions, that is, the first-type ions are N-type ions.

[0045] Specifically, the material of the stress layer is Si or SiC, and the stress layer provides tensile stress to the channel region of the NMOS transistor, thereby facilitating improvement of the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions.

[0046] When forming a PMOS transistor, the source-drain doped layer 106 includes a stress layer doped with P-type ions, that is, the second type ions are P-type ions.

[0047] The material of the stress layer is Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, thereby facilitating improvement of the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions or In ions.

[0048] refer to Figure 6, an interlayer dielectric layer 110 is formed on the substrate 101 to cover the active device 100 .

[0049] It should be noted that the interlayer dielectric layer 110 provides a process basis for the subsequent formation of interconnect contact holes. At the same time, the interlayer dielectric layer 110 also electrically isolates adjacent active devices 100 and adjacent conductive layers formed subsequently, reducing the risk of leakage between them.

[0050] In this embodiment, the process of forming the interlayer dielectric layer 110 includes a chemical vapor deposition process.

[0051] As an example, the steps of forming the interlayer dielectric layer 110 include: forming an interlayer dielectric material layer covering the active device 100 on top of the substrate 101 ; planarizing the interlayer dielectric material layer, and using the remaining interlayer dielectric material layer as the interlayer dielectric layer 110 .

[0052] Specifically, during the process of forming the interlayer dielectric layer 110 , the interlayer dielectric layer 110 covers the gate structure 102 and the source / drain doped layer 106 .

[0053] As an example, the material of the interlayer dielectric layer 110 includes silicon oxide.

[0054] refer to Figure 7 An interconnection contact hole 120 is formed on the top of the active device 100 and penetrates the interlayer dielectric layer 110 , and the interconnection contact hole 120 exposes the top surface of the active device 100 .

[0055] Specifically, the interconnection contact hole 120 provides a spatial location for the subsequent formation of an adhesion layer, a barrier layer, and a conductive layer.

[0056] In this embodiment, the steps of forming the interconnection contact hole 120 include: forming a patterned mask layer on top of the interlayer dielectric layer 110; using the patterned mask layer as a mask, patterning the interlayer dielectric layer 110 to form the interconnection contact hole 120 penetrating the interlayer dielectric layer 110, and the interconnection contact hole 120 exposing the top surface of the active device 100.

[0057] In this embodiment, the process of patterning the interlayer dielectric layer 110 includes a dry etching process.

[0058] It should be noted that the dry etching process is an anisotropic dry etching process, which has the characteristics of high graphic transfer accuracy and good sidewall morphology formation quality. The interconnect contact hole 120 is formed by graphic processing through the dry etching process, providing a better deposition interface for the subsequent formation of the adhesion layer.

[0059] As an example, in the step of forming the interconnection contact hole 120 , the interconnection contact hole 120 exposes the top surface of the source-drain doped layer 106 .

[0060] Specifically, the interconnection contact hole 120 exposes the source-drain doped layer 106 , enabling a subsequently formed conductive layer to be electrically connected to the source-drain doped layer 106 .

[0061] It should be noted that after the adhesion layer and the barrier layer are subsequently formed, the electrons in the conductive layer can still flow through the adhesion layer and the barrier layer to form an electrical connection with the source-drain doped layer 106 .

[0062] refer to Figure 8 , an adhesion layer 126 is formed on the bottom and sidewalls of the interconnection contact hole 120 .

[0063] Specifically, the adhesion layer 126 is used to enhance the adhesion between the interlayer dielectric layer 110 and the subsequently formed barrier layer and conductive layer, and to enhance the adhesion between the source / drain doped layer 106 and the subsequently formed barrier layer and conductive layer, thereby reducing the risk of the subsequently formed barrier layer and conductive layer falling off during other formation processes.

[0064] In this embodiment, the step of forming the adhesion layer 126 includes: forming an adhesion material layer on the top of the interlayer dielectric layer 110 and the bottom and sidewalls of the interconnection contact hole 120, and using the adhesion material layer on the bottom and sidewalls of the interconnection contact hole 120 as the adhesion layer 126.

[0065] As an example, the process of forming the adhesion material layer includes a plasma enhanced chemical vapor deposition process.

[0066] Specifically, the plasma enhanced chemical vapor deposition process has high film deposition quality, which can reduce the risk of gaps between the adhesion material layer and the interlayer dielectric layer 110, and between the adhesion material layer and the source / drain doping layer 106, thereby improving the adhesion between the adhesion layer 126 and the interlayer dielectric layer 110 and the source / drain doping layer 106.

[0067] In this embodiment, the material of the adhesion layer 126 includes titanium.

[0068] Specifically, titanium has high adhesion, which can improve the adhesion between the adhesion layer 126 and the interlayer dielectric layer 110 and the source-drain doped layer 106. At the same time, titanium has high conductivity, which can reduce the resistance between the conductive layer and the source-drain doped layer 106, thereby further improving the performance of the semiconductor structure.

[0069] refer to Figure 9 , a barrier layer 130 is formed on the sidewalls and bottom of the interconnection contact hole 120 .

[0070] It should be noted that by forming the barrier layer 130, the risk of metal atoms in the subsequently formed conductive layer diffusing into the source / drain doped layer 106 and the interlayer dielectric layer 110 can be reduced, thereby reducing the risk of defects in the source / drain doped layer 106 and the interlayer dielectric layer 110 and improving the performance of the semiconductor structure.

[0071] In this embodiment, the step of forming the barrier layer 130 includes: forming a barrier material layer on the top of the interlayer dielectric layer 110 and the bottom and sidewalls of the interconnection contact hole 120, and using the barrier material layer on the bottom and sidewalls of the interconnection contact hole 120 as the barrier layer 130.

[0072] As an example, the process of forming the barrier material layer includes a metal organic chemical vapor deposition process.

[0073] Specifically, during the formation of the barrier material layer, the deposition rate of the barrier material layer is fastest at the top of the interlayer dielectric layer 110 , so that the thickness of the barrier material layer at the top of the interlayer dielectric layer is greater than the thickness of the barrier material layer at the bottom of the interconnection contact hole 120 .

[0074] In this embodiment, the material of the barrier layer 130 includes one or both of titanium nitride and tantalum nitride.

[0075] Specifically, titanium nitride and tantalum nitride have high conductivity and good chemical stability, and have good compatibility with the material of the conductive layer. In addition, titanium nitride and tantalum nitride can prevent metal atoms in the conductive layer from diffusing into the source / drain doped layer 106 and the interlayer dielectric layer 110 .

[0076] refer to Figure 10 , a portion of the barrier layer 130 at the bottom of the interconnection contact hole 120 is removed.

[0077] It should be noted that a portion of the barrier layer 130 at the bottom of the interconnect contact hole 120 is removed, and the remaining space of the interconnect contact hole 120 is subsequently filled with a conductive layer in contact with the barrier layer 130. That is, the distance between the conductive layer and the active device 100 is the thickness of the barrier layer 130 plus the thickness of the adhesion layer 126. Accordingly, by removing a portion of the barrier layer 130, the thickness of the barrier layer 130 can be reduced, and the distance between the conductive layer and the active device 100 can be reduced, thereby reducing the electron transmission distance between the conductive layer and the active device 100. Since resistance is positively correlated with the electron transmission distance, the electron transmission distance between the conductive layer and the active device 100 is reduced, and the resistance between the conductive layer and the active device 100 is reduced, thereby improving the performance of the semiconductor structure.

[0078] In this embodiment, the step of removing a portion of the barrier layer 130 at the bottom of the interconnection contact hole 120 includes: etching to remove a portion of the barrier layer 130 at the bottom of the interconnection contact hole 120 .

[0079] In this embodiment, the process of etching and removing a portion of the barrier layer 130 at the bottom of the interconnection contact hole 120 includes a plasma dry etching process.

[0080] It should be noted that the plasma dry etching process is an anisotropic dry etching process with high pattern transfer accuracy. By etching away a portion of the thickness of the barrier layer 130 at the bottom of the interconnect contact hole 120 through the plasma dry etching process, the risk of damaging other film layers (such as the barrier layer 130 on the side wall of the interconnect contact hole 120) can be reduced.

[0081] Specifically, in the process of etching away a portion of the barrier layer 130 at the bottom of the interconnect contact hole 120 using a plasma dry etching process, a polymer is formed on the side of the barrier layer 130 on the side wall of the interconnect contact hole 120. The polymer protects the barrier layer 130 on the side wall of the interconnect contact hole 120 and reduces the probability of damage to the barrier layer 130 on the side wall of the interconnect contact hole 120.

[0082] It should be noted that, in the process of removing a portion of the barrier layer 130 at the bottom of the interconnection contact hole 120 , a portion of the barrier material layer at the top of the interlayer dielectric layer 110 will also be consumed and removed.

[0083] As an example, the etching gas used in the plasma dry etching process includes one or more of CHF 3 , Cl 2 and CF 4 .

[0084] It should be noted that the etching gas flow rate in the plasma dry etching process should not be too high or too low. If the etching gas flow rate is too high, it can easily lead to an excessively fast etching rate, making it difficult to control the etching depth, increasing the risk of over-etching the barrier layer 130 and affecting the performance of the semiconductor structure. If the etching gas flow rate is too low, it can easily lead to a prolonged etching time, affecting process production efficiency. Therefore, in this embodiment, the etching gas flow rate in the plasma dry etching process is between 10 sccm and 60 sccm.

[0085] It should also be noted that the chamber pressure during the plasma dry etching process should not be too high or too low. If the chamber pressure is too high, the movement of ions and free electrons in the plasma will become more random, resulting in reduced etching anisotropy, increased lateral etching, and a greater risk of etching and consumption of the barrier layer 130 on the sidewalls of the interconnect contact hole 120, thereby affecting the performance of the semiconductor structure. If the chamber pressure is too low, it can easily lead to a reduced etching rate, which in turn reduces etching efficiency and affects process throughput. For this reason, in this embodiment, the chamber pressure during the plasma dry etching process is between 5mTorr and 20mTorr.

[0086] Specifically, the bias power in the plasma dry etching process should not be too large or too small. If the bias power in the plasma dry etching process is too large, it is easy to cause the ion energy in the plasma to increase significantly, and the high-energy ions bombard the surface of the barrier layer 130, which is easy to cause excessive defects on the surface of the remaining barrier layer 130 (for example, increased surface roughness), affecting the electrical properties of the semiconductor structure; if the bias power in the plasma dry etching process is too small, it is easy to cause insufficient RF power, resulting in lower ion energy in the plasma, which is easy to cause the etching rate to decrease, which also reduces the etching efficiency and affects the process capacity. For this reason, in this embodiment, the bias power in the plasma dry etching process is between 30W and 100W.

[0087] It should be noted that the etching time in the plasma dry etching process should not be too long or too short. If the etching time in the plasma dry etching process is too long, it is difficult to control the etching depth, which increases the risk of over-etching the barrier layer 130 and affects the performance of the semiconductor structure; if the etching time in the plasma dry etching process is too short, it is easy to cause the thickness of the barrier layer 130 removed to not meet the process requirements, resulting in the electron transmission distance between the conductive layer and the active device 100 being reduced too little. Since resistance is positively correlated with electron transmission distance, if the electron transmission distance between the conductive layer and the active device 100 is reduced too little, the resistance between the conductive layer and the active device 100 will be reduced too little, thereby failing to improve the performance of the semiconductor structure. For this reason, in this embodiment, the etching time in the plasma dry etching process is between 5S and 60S.

[0088] In this embodiment, in the step of forming the barrier layer 130 , the barrier layer 130 covers the adhesion layer 126 .

[0089] refer to Figure 11 , a conductive layer 160 in contact with the barrier layer 130 is filled in the remaining space of the interconnection contact hole 120 .

[0090] Specifically, the conductive layer 160 is used to form an electrical connection with the active device 100 , so that the active device 100 can be electrically connected to the back-end circuit structure through the conductive layer 160 .

[0091] In this embodiment, the step of forming the conductive layer 160 includes: forming a conductive material layer on the top of the interlayer dielectric layer 110 and in the interconnection contact hole 120; using the top of the interlayer dielectric layer 110 as a stopping position, removing the conductive material layer above the top of the interlayer dielectric layer 110, and using the remaining conductive material layer located in the interconnection contact hole 120 as the conductive layer 160.

[0092] It should be noted that, with the top of the interlayer dielectric layer 110 as the stopping position, the process of removing the conductive material layer above the top of the interlayer dielectric layer 110 also includes removing the adhesion material layer and the barrier material layer above the top of the interlayer dielectric layer 110 .

[0093] As an example, with the top of the interlayer dielectric layer 110 as a stop position, the process of removing the conductive material layer above the top of the interlayer dielectric layer 110 includes a chemical mechanical polishing process.

[0094] In this embodiment, the material of the conductive layer 160 includes one or more of cobalt, tungsten and ruthenium.

[0095] In other embodiments, the conductive layer may be made of other types of materials, which are not limited here.

[0096] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate on which active devices are formed; forming an interlayer dielectric layer covering the active device on the substrate; forming an interconnection contact hole penetrating the interlayer dielectric layer on top of the active device, wherein the interconnection contact hole exposes the top surface of the active device; forming a barrier layer on the sidewall and bottom of the interconnection contact hole; removing a portion of the barrier layer at the bottom of the interconnection contact hole; A conductive layer in contact with the barrier layer is filled in the remaining space of the interconnection contact hole.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of removing a portion of the barrier layer at the bottom of the interconnection contact hole comprises: etching and removing a portion of the barrier layer at the bottom of the interconnection contact hole.

3. The method for forming a semiconductor structure according to claim 2, wherein: The process of etching and removing a portion of the thickness of the barrier layer at the bottom of the interconnection contact hole includes a plasma dry etching process.

4. The method for forming a semiconductor structure according to claim 3, wherein: The etching gas used in the plasma dry etching process includes one or more of CHF3, Cl2 and CF4.

5. The method for forming a semiconductor structure according to claim 3, wherein: The process parameters of the plasma dry etching process include: etching gas flow rate ranging from 10 sccm to 60 sccm; chamber pressure ranging from 5 mTorr to 20 mTorr; bias power ranging from 30 W to 100 W; and etching time ranging from 5 s to 60 s.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the barrier layer includes: forming a barrier material layer on the top of the interlayer dielectric layer, the bottom and sidewalls of the interconnection contact hole, and using the barrier material layer on the bottom and sidewalls of the interconnection contact hole as the barrier layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The process of forming the barrier material layer includes a metal organic chemical vapor deposition process.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the barrier layer includes one or both of titanium nitride and tantalum nitride.

9. The method for forming a semiconductor structure according to claim 1, wherein: After forming the interconnection contact hole and before forming the barrier layer, the method further includes: forming an adhesion layer on the bottom and sidewall of the interconnection contact hole; In the step of forming the barrier layer, the barrier layer covers the adhesion layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming the adhesion layer includes: forming an adhesion material layer on the top of the interlayer dielectric layer, the bottom and sidewalls of the interconnection contact hole, and using the adhesion material layer on the bottom and sidewalls of the interconnection contact hole as the adhesion layer.

11. The method for forming a semiconductor structure according to claim 9, wherein: The material of the adhesion layer includes titanium.

12. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming the conductive layer include: forming a conductive material layer on the top of the interlayer dielectric layer and in the interconnection contact hole; using the top of the interlayer dielectric layer as a stopping position, removing the conductive material layer above the top of the interlayer dielectric layer, and using the remaining conductive material layer located in the interconnection contact hole as the conductive layer.

13. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, the active device includes a gate structure and source and drain doped layers located on both sides of the gate structure; In the step of forming the interconnection contact hole, the interconnection contact hole exposes the top surface of the source-drain doped layer.

14. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming the interconnection contact hole include: forming a patterned mask layer on top of the interlayer dielectric layer; using the patterned mask layer as a mask, patterning the interlayer dielectric layer to form an interconnection contact hole penetrating the interlayer dielectric layer, and the interconnection contact hole exposes the top surface of the active device.

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