Semiconductor device and memory system

Abstract

The invention provides a semiconductor device and a memory system, the semiconductor device comprises a semiconductor structure and a protection structure, and the protection structure is stacked with the semiconductor structure in a first direction; the protection structure comprises a first protection layer, a second protection layer and a first stress guiding piece, the second protection layer is located on the side, away from the semiconductor structure, of the first protection layer, the second protection layer and the first protection layer are arranged in a spaced mode, and the first stress guiding piece is located between the first protection layer and the second protection layer and connected with the first protection layer and the second protection layer; and the plurality of first stress guiding pieces are annularly distributed at intervals. According to the semiconductor device and the memory system, the failure risk of the key module of the semiconductor device can be reduced, and the mechanical performance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a memory system. Background Art

[0002] Chips generally require packaging to reduce mechanical impact from the outside world. Existing technologies often use packaging layers to encapsulate chips to form semiconductor devices. Under various mechanical impacts, the packaging layer and chip often experience fractures (possibly fractures in the packaging layer, the chip, or both), or delamination (possibly between the chip and the packaging layer, or between multi-layer chips), leading to chip failure and poor mechanical performance of the semiconductor device. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor device and a memory system that can reduce the risk of chip failure and improve the mechanical properties of the semiconductor device.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, the present application provides a semiconductor device comprising: a semiconductor structure and a protective structure, the protective structure being stacked with the semiconductor structure in a first direction; the protective structure comprising a first protective layer, a second protective layer and a first stress guiding member, the second protective layer being located on a side of the first protective layer away from the semiconductor structure, the second protective layer being spaced apart from the first protective layer, the first stress guiding member being located between the first protective layer and the second protective layer and connecting the first protective layer and the second protective layer; a plurality of first stress guiding members being distributed in a ring-shaped pattern.

[0006] In some embodiments, the semiconductor structure includes a key module; a first protective layer covers the key module, and a first stress guide is spaced around the key module; a connection point between the first stress guide and the first protective layer is a first connection point, and a connection point between the first stress guide and the second protective layer is a second connection point;

[0007] In the first direction, orthographic projections of at least some of the first connection points of the first stress guiding member on the semiconductor structure fall outside the critical module.

[0008] In some embodiments, the first stress guiding member is inclined relative to the first protective layer and the second protective layer; in the first direction, the orthographic projection of the second connection point of the first stress guiding member on the semiconductor structure falls on a side of the orthographic projection of the first connection point of the first stress guiding member on the semiconductor structure close to the key module.

[0009] In some embodiments, an orthographic projection of the second connection point of the first stress guide on the semiconductor structure falls outside the critical module or falls on the critical module.

[0010] In some embodiments, the first stress guiding member is perpendicular to the first protective layer and the second protective layer; in the first direction, the orthographic projection of the second connection point of the first stress guiding member on the semiconductor structure falls on the orthographic projection of the first connection point of the first stress guiding member on the semiconductor structure.

[0011] In some embodiments, an orthographic projection of the second connection point of the first stress guide on the semiconductor structure falls outside the critical module.

[0012] In some embodiments, a size of a first end of the first stress guide connected to the first protective layer is equal to, larger than, or smaller than a size of a second end of the first stress guide connected to the second protective layer.

[0013] In some embodiments, a size of a middle section of the first stress guide between the first end and the second end is equal to or greater than a size of the first end or the second end.

[0014] In some embodiments, the protective structure also includes a third protective layer and a second stress guiding member, the third protective layer is located on a side of the second protective layer away from the first protective layer and is spaced apart from the second protective layer, the second stress guiding member is located between the third protective layer and the second protective layer and connects the third protective layer and the second protective layer; wherein the second stress guiding member is spaced around the key module, the connection point between the second stress guiding member and the third protective layer is a third connection point, and in the first direction, the orthographic projection of the third connection point of the second stress guiding member on the semiconductor structure falls on the side of the orthographic projection of the second connection point of the first stress guiding member on the semiconductor structure close to the key module.

[0015] In some embodiments, a vertical distance between the second connection points of two first stress guides on opposite sides of the critical module is greater than a vertical distance between the third connection points of two second stress guides on opposite sides of the critical module.

[0016] In some embodiments, the connection point between the second stress guide and the second protective layer is a fourth connection point; in the first direction, the orthographic projection of the fourth connection point of the second stress guide on the semiconductor structure falls on the orthographic projection of the second connection point of the first stress guide on the semiconductor structure or falls on a side of the orthographic projection of the second connection point of the first stress guide on the semiconductor structure close to the key module.

[0017] In some embodiments, a minimum vertical distance between first connection points of two first stress guides on opposite sides of the critical module is greater than a minimum vertical distance between fourth connection points of two second stress guides on opposite sides of the critical module.

[0018] In some embodiments, a minimum vertical distance between the second connection points of two first stress guides on opposite sides of the critical module is greater than a minimum vertical distance between the fourth connection points of two second stress guides on opposite sides of the critical module.

[0019] In some embodiments, the second stress guide is inclined or perpendicular to the second protective layer and the third protective layer.

[0020] In some embodiments, a size of the third end of the second stress guide connected to the second protective layer is equal to, larger than, or smaller than a size of the fourth end of the second stress guide connected to the third protective layer.

[0021] In some embodiments, a size of a middle section of the second stress guide between the third end and the fourth end is equal to or greater than a size of the third end or the fourth end.

[0022] In some embodiments, the material of the protection structure is at least one of stainless steel, metal, ceramic, and silicide.

[0023] In some embodiments, the semiconductor structure further includes a substrate, and the key module is located on the substrate.

[0024] In some embodiments, the semiconductor device further includes a packaging layer, which is located on the substrate and covers the key module, and the first protection layer is located on the packaging layer.

[0025] A second aspect of the present application further provides a memory system, comprising: at least one semiconductor device as described above; and a controller configured to control the semiconductor device.

[0026] The semiconductor device and memory system provided by the present application form a protection structure on one side of the semiconductor structure, and the protection structure includes a first protective layer, a second protective layer and a first stress guiding member. The first protective layer is located on the side of the semiconductor structure close to the key module, the second protective layer is located on the side of the first protective layer away from the semiconductor structure, the second protective layer is spaced apart from the first protective layer, and the first stress guiding member is located between the first protective layer and the second protective layer and connects the first protective layer and the second protective layer; multiple first stress guiding members are distributed in a ring-shaped manner. When the semiconductor device is subjected to various mechanical shocks, the first stress guiding member of the protection structure can change the position and direction of the stress exerted on the semiconductor device to guide the stress exerted on the semiconductor device to fall outside the key module, thereby reducing the risk of chip failure and improving the mechanical properties of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A cross-sectional view of a semiconductor device provided in some embodiments of the present application.

[0029] Figure 2 for Figure 1 An enlarged view of the protection structure of the semiconductor device is shown.

[0030] Figure 3 for Figure 1 Schematic diagram of the positional relationship between the stress guide and key modules of a semiconductor device.

[0031] Figure 4 Cross-sectional views of semiconductor devices provided in accordance with other embodiments of the present application.

[0032] Figure 5 for Figure 4 Schematic diagram of the positional relationship between the stress guide and key modules of a semiconductor device.

[0033] Figure 6 Cross-sectional views of semiconductor devices provided in some further embodiments of the present application.

[0034] Figure 7 for Figure 6 Schematic diagram of the positional relationship between the stress guide and key modules of a semiconductor device.

[0035] Figure 8 Cross-sectional views of semiconductor devices provided in some further embodiments of the present application.

[0036] Figure 9 Cross-sectional views of semiconductor devices provided for some other embodiments of the present application.

[0037] Figure 10 A schematic diagram of a module of a memory system provided in this application. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings of some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0039] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0040] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0041] The present application addresses the technical problem that semiconductor device chips are prone to failure and have poor mechanical properties when subjected to various mechanical shocks. A protective structure is formed on one side of the semiconductor structure, and the protective structure includes a first protective layer, a second protective layer and a first stress guiding member. The first protective layer is located on a side of the semiconductor structure close to a key module, the second protective layer is located on a side of the first protective layer away from the semiconductor structure, the second protective layer is spaced apart from the first protective layer, and the first stress guiding member is located between the first protective layer and the second protective layer and connects the first protective layer and the second protective layer; multiple first stress guiding members are distributed in a ring-shaped manner. When the semiconductor device is subjected to various mechanical shocks, the first stress guiding member of the protective structure can change the position and direction of the stress exerted on the semiconductor device to guide the stress exerted on the semiconductor device to fall outside the key module, thereby reducing the risk of chip failure and improving the mechanical properties of the semiconductor device.

[0042] See also Figures 1 to 3 Some embodiments of the present application provide a semiconductor device 100, comprising a semiconductor structure 110 and a protection structure 120, wherein the protection structure 120 is stacked with the semiconductor structure 110 in a first direction Z. The protection structure 120 comprises a first protection layer 11, a second protection layer 12, and a first stress guide 21. The first protection layer 11 is located on the semiconductor structure 110, the second protection layer 12 is located on a side of the first protection layer 11 away from the semiconductor structure 110, and the second protection layer 12 is spaced apart from the first protection layer 11. The first stress guide 21 is located between and connects the first protection layer 11 and the second protection layer 12. A plurality of first stress guides 21 are distributed in an annular pattern.

[0043] Please refer again Figure 2 and Figure 3 In some embodiments, a semiconductor structure 110 includes a critical module 30, a first protective layer 11 covers the critical module 30, and first stress guides 21 are spaced apart around the critical module 30. The connection points between the first stress guide 21 and the first protective layer 11 are first connection points 211, and the connection points between the first stress guide 21 and the second protective layer 12 are second connection points 212. In a first direction Z, orthographic projections of at least some of the first connection points 211 of the first stress guide 21 on the semiconductor structure 110 fall outside the critical module 30, and orthographic projections of the second connection points 212 of the first stress guide 21 on the semiconductor structure 110 fall outside or on the critical module 30.

[0044] Please refer again Figure 2 and Figure 3 In some embodiments, the protective structure 120 further includes a third protective layer 13 and a second stress guide 22. The third protective layer 13 is located on a side of the second protective layer 12 away from the first protective layer 11 and is spaced apart from the second protective layer 12. The second stress guide 22 is located between the third protective layer 13 and the second protective layer 12 and connects the third protective layer 13 and the second protective layer 12. The plurality of second stress guides 22 are spaced apart in a ring-shaped pattern and are spaced apart in a ring-shaped pattern around the key module 30.

[0045] The connection point between the second stress guide 22 and the third protective layer 13 is a third connection point 221, and the connection point between the second stress guide 22 and the second protective layer 12 is a fourth connection point 222. In the first direction Z, the orthographic projection of the third connection point 221 of the second stress guide 221 on the semiconductor structure 110 falls on a side of the orthographic projection of the second connection point 212 of the first stress guide 21 on the semiconductor structure 110 close to the key module 30. The orthographic projection of the fourth connection point 222 of the second stress guide 22 on the semiconductor structure 110 falls on the orthographic projection of the second connection point 212 of the first stress guide 21 on the semiconductor structure 110 or falls on a side of the orthographic projection of the second connection point 212 of the first stress guide 21 on the semiconductor structure 110 close to the key module 30.

[0046] In this embodiment, the orthographic projection of the second stress transmission member 22 on the semiconductor structure 110 falls on the key module 30 .

[0047] In other embodiments, the orthographic projection of the second stress-transmitting member 22 on the semiconductor structure 110 at least partially falls on the key module 30 .

[0048] Please refer again Figure 1When the key module 30 is subjected to various mechanical shocks and stress F is generated, the stress F will first enter the outermost protective layer (the third protective layer 13), and then transmit the stress F from the third protective layer 13 to the second protective layer 12 through the second stress transmission component 22, and then transmit the stress F from the second protective layer 12 along the first stress guiding component 21 to the first protective layer 11. Since the first stress guiding component 21 can change the position and direction of the stress exerted on the semiconductor device 100, it can guide the stress exerted on the semiconductor device 100 to fall outside the key module 30, thereby reducing the failure risk of the key module 30 (for example, chip) and improving the mechanical properties of the semiconductor device 100.

[0049] The orthographic projections of the first connection points 211 of the first stress guide 21 on the semiconductor structure 110 onto the key module 30 fall on two different locations. In the first location, all of the orthographic projections of the first connection points 211 of the first stress guide 21 on the semiconductor structure 110 fall outside the key module 30 in the first direction Z. In the second location, only a portion of the orthographic projections of the first connection points 211 of the first stress guide 21 on the semiconductor structure 110 fall outside the key module 30 in the first direction Z, while the remaining portion of the orthographic projections of all of the first connection points 211 of the first stress guide 21 on the semiconductor structure 110 fall on the key module 30 in the first direction Z. Naturally, the stress-guiding effect of the first stress guide 21 in the first location is greater than that in the second location.

[0050] In this embodiment, the first stress transmitting member 21 and the second stress transmitting member 22 are arranged obliquely relative to the first protective layer 11 and the second protective layer 12, respectively. That is, the first stress transmitting member 21 and the second stress transmitting member 22 extend radially from the third protective layer 13 toward the first protective layer 11, and the orthographic projection of at least a portion of the first connection point 211 of the first stress guiding member 21 on the semiconductor structure 110 falls outside the key module 30. This can change the transmission direction of the stress F and transmit at least a portion of the stress F to the outside of the key module 30 layer by layer, thereby reducing the stress F directly acting on the key module 30, lowering the failure risk of the key module 30 (e.g., chip), and improving the mechanical properties of the semiconductor device 100.

[0051] See also Figure 1 and Figure 2 In some embodiments, in a second direction X perpendicular to the first direction Z, a size of the first end of the first stress guide 21 connected to the first protective layer 11 (i.e., the first connection point 211) is equal to, smaller than, or larger than a size of the second end of the first stress guide 21 connected to the second protective layer 12 (i.e., the second connection point 212), and a size of a middle section of the first stress guide 21 between the first end and the second end is equal to or different from a size of the first end or the second end.

[0052] In this embodiment, the first stress guide 21 is arranged obliquely and has a rectangular cross section in the second direction X.

[0053] The shape, inclination angle, etc. of the second stress guide 22 may be the same as or different from the shape, inclination angle, etc. of the first stress guide 21 .

[0054] See also Figure 1 and Figure 2 In some embodiments, in a second direction X perpendicular to the first direction Z, a size of the third end of the second stress guide 22 connected to the second protective layer 12 (i.e., the fourth connection point 222) is equal to, smaller than, or larger than a size of the fourth end of the second stress guide 22 connected to the third protective layer 13 (i.e., the third connection point 221), and a size of a middle section of the second stress guide 22 between the third end and the fourth end is equal to or different from a size of the first end or the second end.

[0055] In this embodiment, the second stress guide 22 is arranged obliquely and has a diamond-shaped cross section in the second direction X.

[0056] Please refer again Figure 2 In some embodiments, a vertical distance d2 between the second connection points 212 of the two first stress guides 21 located on opposite sides of the key module 30 is greater than a vertical distance d3 between the third connection points 221 of the two second stress guides 22 located on opposite sides of the key module 30 .

[0057] The minimum vertical distance d1 between the first connection points 211 of the two first stress guides 21 on opposite sides of the key module 30 is greater than the minimum vertical distance d4 between the fourth connection points 222 of the two second stress guides 22 on opposite sides of the key module 30 .

[0058] The minimum vertical distance d2 between the second connection points 212 of the two first stress guides 21 on opposite sides of the key module 30 is greater than the minimum vertical distance d4 between the fourth connection points 222 of the two second stress guides 22 on opposite sides of the key module 30 .

[0059] In some embodiments, the material of the protection structure 120 is at least one of high-strength materials such as stainless steel, metal, ceramic, and silicide. That is, the material selection of the protection structure 120 of the present application is diverse and is not limited to the listed materials.

[0060] In some embodiments, the key module 30 can be at least one of a bare chip, a package structure with a packaging layer, a stand-alone module (e.g., an electronic component), etc. That is, the semiconductor device of the present application has diverse applications and is not limited to chip packaging structures, etc., and can also be other semiconductor devices.

[0061] In this embodiment, the key module 30 is a bare chip. In this embodiment, the semiconductor structure 110 further includes a packaging layer 50 and a substrate 40. The key module 30 is located on the substrate 40. The packaging layer 50 is located on the substrate 40 and covers the key module 30. The first protection layer 11 is located on the packaging layer 50.

[0062] In other embodiments, the protection structure 120 of the semiconductor device 100 may also serve as a sacrificial layer and may be removed or replaced when necessary.

[0063] See also Figure 4 and Figure 5 The present application provides a semiconductor device 200 having substantially the same structure as the semiconductor device 100, except that the semiconductor device 200 only includes a first protective layer 11, a second protective layer 12, and a first stress guide 21. In a first direction Z, the orthographic projection of a first connection point 211 of the first stress guide 21 on the semiconductor structure 110 falls outside the critical module 30, while the orthographic projection of a second connection point 212 of the first stress guide 21 on the semiconductor structure 110 falls on the critical module 30.

[0064] See also Figure 6 and Figure 7 The present application provides a semiconductor device 300. The structure of the semiconductor device 300 is basically the same as that of the semiconductor device 200. The difference is that in the first direction Z, the orthographic projection of the first connection point 211 of the first stress guiding member 21 of the semiconductor device 300 on the semiconductor structure 110 falls outside the key module 30, and the orthographic projection of the second connection point 212 of the first stress guiding member 21 of the semiconductor device 300 on the semiconductor structure 110 falls outside the key module 30.

[0065] See also Figure 8 The present application provides a semiconductor device 400. The structure of semiconductor device 400 is substantially the same as that of semiconductor device 100. The difference lies in that the inclination angle of first stress guide 21 of semiconductor device 400 is different from that of first stress guide 21 of semiconductor device 100. First stress guide 21 of semiconductor device 400 is perpendicular to first protective layer 11 and second protective layer 12. The cross-sections of first stress guide 21 and second stress guide 22 along a second direction X are rectangular.

[0066] See also Figure 9The present application provides a semiconductor device 500. The structure of semiconductor device 500 is basically the same as that of semiconductor device 400. The difference is that the shapes of first stress guiding member 21 and second stress guiding member 22 of semiconductor device 500 are different from the shapes of first stress guiding member 21 and second stress guiding member 22 of semiconductor device 400. The cross-section of first stress guiding member 21 and second stress guiding member 22 of semiconductor device 500 in the second direction X is spherical or part of a sphere.

[0067] Of course, in other embodiments, the cross-sectional shapes of the first stress guide 21 and the second stress guide 22 in the second direction X are not limited to the aforementioned rectangle, diamond, circle or semicircle, and may also be set to other shapes according to actual conditions.

[0068] Of course, in other embodiments, the protective structure 120 may further include a fourth protective layer, a fifth protective layer, etc., and accordingly, the protective structure 120 may further include a third stress guide, a fourth stress guide, etc. That is, the number of protective layers of the protective structure 120 may be two or more, the number of stress guides may be one or more, and the distance between two stress guides located on opposite sides of the key module 30 gradually increases in the first direction.

[0069] See also Figure 10 The present application also provides a memory system 1000, which includes one or more semiconductor devices 100 / 200 / 300 / 400 / 500 as described above and a controller 600, wherein the controller 600 is connected to the semiconductor devices 100 / 200 / 300 / 400 / 500, and the controller 600 is configured to control the semiconductor devices 100 / 200 / 300 / 400 / 500.

[0070] The memory system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller may be configured to control operations of the semiconductor device, such as read, erase, and program operations.

[0071] In some embodiments, the controller 600 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0072] In some embodiments, the controller 600 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0073] The semiconductor device and memory system provided herein comprise a protective structure formed on one side of a semiconductor structure, the protective structure comprising a first protective layer, a second protective layer, and a first stress guide. The first protective layer is located on a side of the semiconductor structure proximal to a critical module, the second protective layer is located on a side of the first protective layer distal to the semiconductor structure, the second protective layer is spaced apart from the first protective layer, and the first stress guide is located between and connects the first and second protective layers. A plurality of first stress guides are arranged in an annular pattern, spaced apart, and arranged around the critical module. The connection points between the first stress guides and the first protective layer are first connection points, and the connection points between the first stress guides and the second protective layer are second connection points. In a first direction, the orthographic projections of at least some of the first connection points of the first stress guides on the semiconductor structure fall outside the critical module. When the semiconductor device is subjected to various mechanical shocks, the first stress guides of the protective structure can change the location and direction of the stress acting on the semiconductor device, thereby directing the stress acting on the semiconductor device outside the critical module, thereby reducing the risk of chip failure and improving the mechanical performance of the semiconductor device.

[0074] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: semiconductor structures; and a protection structure stacked on the semiconductor structure in a first direction; In which, the protective structure includes a first protective layer, a second protective layer and a first stress guiding member, the first protective layer is located on the semiconductor structure, the second protective layer is located on the side of the first protective layer away from the semiconductor structure, the second protective layer is spaced apart from the first protective layer, the first stress guiding member is located between the first protective layer and the second protective layer and connects the first protective layer and the second protective layer; multiple first stress guiding members are distributed in a ring-shaped manner.

2. The semiconductor device according to claim 1, wherein The semiconductor structure includes a key module; the first protective layer covers the key module, and the first stress guide is spaced around the key module; the connection point between the first stress guide and the first protective layer is a first connection point, and the connection point between the first stress guide and the second protective layer is a second connection point; In the first direction, orthographic projections of at least some of the first connection points of the first stress guiding member on the semiconductor structure fall outside the critical module.

3. The semiconductor device according to claim 2, wherein The first stress guide is inclined relative to the first protective layer and the second protective layer; In the first direction, an orthographic projection of the second connection point of the first stress guide on the semiconductor structure falls on a side of the orthographic projection of the first connection point of the first stress guide on the semiconductor structure close to the key module.

4. The semiconductor device according to claim 3, wherein An orthographic projection of the second connection point of the first stress guide on the semiconductor structure falls outside the critical module or falls on the critical module.

5. The semiconductor device according to claim 2, wherein The first stress guide is perpendicular to the first protective layer and the second protective layer; In the first direction, an orthographic projection of the second connection point of the first stress guide on the semiconductor structure falls on an orthographic projection of the first connection point of the first stress guide on the semiconductor structure.

6. The semiconductor device according to claim 5, wherein An orthographic projection of the second connection point of the first stress guide on the semiconductor structure falls outside the critical module.

7. The semiconductor device according to claim 3 or 5, wherein: In a second direction X perpendicular to the first direction Z, a size of a first end of the first stress guide connected to the first protective layer is equal to, greater than, or smaller than a size of a second end of the first stress guide connected to the second protective layer.

8. The semiconductor device according to claim 7, wherein In a second direction X perpendicular to the first direction Z, a size of a middle section of the first stress guide between the first end and the second end is equal to or larger than a size of the first end or the second end.

9. The semiconductor device according to any one of claims 2 to 6, wherein: The protective structure further includes a third protective layer and a second stress guide, wherein the third protective layer is located on a side of the second protective layer away from the first protective layer and is spaced apart from the second protective layer, and the second stress guide is located between the third protective layer and the second protective layer and connects the third protective layer and the second protective layer; The second stress guiding members are spaced around the key module, and the connection point between the second stress guiding member and the third protective layer is a third connection point. In the first direction, the orthographic projection of the third connection point of the second stress guiding member on the semiconductor structure falls on a side of the orthographic projection of the second connection point of the first stress guiding member on the semiconductor structure close to the key module.

10. The semiconductor device according to claim 9, wherein A vertical distance between the second connection points of two first stress guides located on opposite sides of the key module is greater than a vertical distance between the third connection points of two second stress guides located on opposite sides of the key module.

11. The semiconductor device according to claim 9, wherein The connection point between the second stress guide and the second protective layer is a fourth connection point; In the first direction, an orthographic projection of the fourth connection point of the second stress guide on the semiconductor structure falls on an orthographic projection of the second connection point of the first stress guide on the semiconductor structure or falls on a side of the orthographic projection of the second connection point of the first stress guide on the semiconductor structure close to the key module.

12. The semiconductor device according to claim 11, wherein A minimum vertical distance between the first connection points of two first stress guides located on opposite sides of the key module is greater than a minimum vertical distance between the fourth connection points of two second stress guides located on opposite sides of the key module.

13. The semiconductor device according to claim 12, wherein A minimum vertical distance between the second connection points of two first stress guides located on opposite sides of the key module is greater than a minimum vertical distance between the fourth connection points of two second stress guides located on opposite sides of the key module.

14. The semiconductor device according to claim 9, wherein The second stress guide is inclined or perpendicular to the second protection layer and the third protection layer.

15. The semiconductor device according to claim 14, wherein A size of a third end of the second stress guide connected to the second protective layer is equal to, larger than, or smaller than a size of a fourth end of the second stress guide connected to the third protective layer.

16. The semiconductor device according to claim 15, wherein A size of a middle section of the second stress guide between the third end and the fourth end is equal to or larger than a size of the third end or the fourth end.

17. The semiconductor device according to claim 1, wherein The material of the protection structure is at least one of stainless steel, metal, ceramic and silicide.

18. The semiconductor device according to claim 2, wherein The semiconductor structure further includes a substrate, and the key module is located on the substrate.

19. The semiconductor device according to claim 18, wherein The semiconductor device further includes a packaging layer, which is located on the substrate and covers the key module, and the first protection layer is located on the packaging layer.

20. A memory system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 19; and A controller is configured to control the semiconductor device.

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