Packaging substrate structure and manufacturing method thereof

Abstract

The invention discloses a packaging substrate structure and a manufacturing method thereof, and the packaging substrate structure comprises a glass core plate which is provided with one or more conductive through holes which are communicated with a first surface and a second surface of the glass core plate; the first redistribution structure is arranged on the glass core plate and electrically connected with the conductive through hole, and the first redistribution structure is provided with at least one cavity; the at least one glass interconnection module is embedded into the cavity; a first high-density wiring structure is arranged on the surface of one side of the glass interconnection module; the second high-density wiring structure is arranged on the first rewiring structure and the first high-density wiring structure and is electrically connected with the first rewiring structure and the first high-density wiring structure; and the second redistribution structure is arranged on the second surface of the glass core plate and is electrically connected with the conductive through hole. The glass interconnection module is embedded into the added layer, high-density interconnection, low signal loss, high thermal mechanical reliability, low warping and low cost are achieved, flexible adjustment can be achieved according to chip I / O requirements, and the high-density interconnection requirements of different packaging scenes are met.

Description

Technical Field

[0001] The present invention relates to the field of advanced semiconductor packaging, and in particular to a packaging substrate structure and a manufacturing method thereof. Background Art

[0002] With the rapid development of high-performance computing (HPC), artificial intelligence (AI), and 5G communications, the continuous improvement of chip integration has put forward higher requirements for packaging substrates, especially in terms of high-density interconnection and low warpage performance. Traditional organic substrates are prone to warping due to their high coefficient of thermal expansion (CTE) (10-15 ppm / °C) and insufficient rigidity. It is difficult to achieve high-density interconnection with a line width / spacing of ≤2 μm. At the same time, the signal loss is large under high-frequency conditions (dielectric constant 6-8, loss factor D f =0.02-0.03). Silicon interposers can support submicron interconnects, but their fabrication cost is high (approximately five times that of glass substrates), and the CTE of silicon (2-3 ppm / °C) is significantly mismatched with that of organic substrates, leading to reliability issues caused by thermomechanical stress, such as microcracking or delamination. Glass interposers offer low CTE (3-8 ppm / °C) and high flatness, but their processing complexity and high cost limit their widespread application. Therefore, a new packaging substrate structure is urgently needed that can achieve high-density interconnects, low signal loss, and low warpage while reducing costs.

[0003] The interconnection module of the glass packaging substrate in the related art cannot be flexibly adjusted according to the chip I / O requirements, and cannot adapt to the high-density interconnection requirements of different packaging scenarios. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems in the above-mentioned technologies to a certain extent. To this end, the purpose of the present invention is to propose a packaging substrate structure and a manufacturing method thereof, which embeds a glass interconnect module into a build-up layer, utilizes the glass interconnect module itself to achieve high-density interconnection in local key areas, combines the low CTE characteristics of the glass core board to form a "dual low CTE" architecture to ensure low warpage, and finally constructs a redistribution layer (RDL) to achieve an increase in overall interconnection density, achieving high-density interconnection, low signal loss, high thermomechanical reliability, low warpage, low cost, and flexible adjustment according to chip I / O requirements, reducing dependence on the overall processing accuracy of the substrate, and adapting to the high-density interconnection requirements of different packaging scenarios.

[0005] To achieve the above objectives, the present invention provides, in one aspect, a package substrate structure, comprising: a glass core board having a first surface and a second surface opposite to each other and one or more conductive through-holes connecting the first surface and the second surface; A first redistribution structure is provided on the first surface of the glass core board and is electrically connected to the conductive vias, the first redistribution structure having at least one cavity extending from a side surface of the first redistribution structure to a portion of the thickness of the first redistribution structure; At least one glass interconnect module is embedded in the cavity; one side surface of the glass interconnect module has a first high-density wiring structure; a second high-density wiring structure, disposed on the first redistribution structure and the first high-density wiring structure, and electrically connecting the first redistribution structure and the first high-density wiring structure; The second redistribution structure is disposed on the second surface of the glass core board and is electrically connected to the conductive through hole.

[0006] According to a packaging substrate structure of the present invention, a high-density local interconnection is achieved through a first high-density wiring structure prefabricated by a glass interconnect module, and combined with a second high-density wiring structure, an I / O density of 1800 / mm can be achieved. 2 and 35 μm pitch; the CTE (3-8ppm / °C) of the glass core board and glass interconnect module is highly matched with the silicon chip (2-3 ppm / °C), which reduces the warpage of the entire package to <50 μm, ensuring the alignment accuracy and reliability of high-density interconnection; the glass core board provides a low dielectric constant (about 4-6) and low-loss signal transmission channel, combined with the fine wiring of the high-density wiring structure, effectively reducing high-frequency signals to D f <0.01, improving signal integrity; the glass interconnect module is embedded in the rewiring structure and can be flexibly adjusted according to the chip I / O requirements, reducing the dependence on the overall processing accuracy of the substrate and adapting to the high-density interconnection requirements of different packaging scenarios; the packaging substrate structure supports large-size packaging and panel-level packaging processes, which can realize large-size, multi-chip integration, significantly improve production efficiency, and reduce unit chip packaging costs.

[0007] In addition, the package substrate structure proposed above according to the present invention may also have the following additional technical features: Optionally, the line specifications of the first high-density wiring structure are smaller than the line specifications of the second high-density wiring structure, the line specifications of the first rewiring structure are the same as the line specifications of the second rewiring structure, and the line specifications of the second high-density wiring structure are smaller than the line specifications of the first rewiring structure.

[0008] Furthermore, the circuit specifications are line width and / or line spacing, and the line width / spacing of the first high-density wiring structure is ≤2 μm.

[0009] Optionally, the bottom of the cavity has a partial circuit layer, and a surface of the glass interconnect module opposite to the first high-density wiring structure is attached to the bottom of the cavity by an adhesive.

[0010] Optionally, it also includes a first outer layer and a second outer layer, the first outer layer is arranged on the second high-density wiring structure, and the first outer layer has electroplated columns electrically connected to the second high-density wiring structure; the second outer layer is arranged on the second heavy wiring structure.

[0011] To achieve the above object, a second aspect of the present invention provides a method for manufacturing a package substrate structure, which comprises the following steps: Providing a glass core board, making conductive through-holes on the glass core board, and making a first circuit layer electrically connected through the conductive through-holes on a first surface and a second surface opposite to the glass core board; Adding wiring layers on the first circuit layer of the first surface to produce a first redistribution structure, and adding wiring layers on the first circuit layer of the second surface to produce a second redistribution structure; At least one cavity is formed in the first redistribution structure, extending from a side surface of the first redistribution structure to a portion of the thickness thereof; Providing at least one glass interconnect module, and embedding the glass interconnect module into the cavity, wherein one side surface of the glass interconnect module has a first high-density wiring structure; Laminating a dielectric layer on the first redistribution structure and the first high-density wiring structure, and flattening the dielectric layer using multi-zone low-stress chemical mechanical polishing to expose the wiring layer of the first redistribution structure and the conductive blocks of the first high-density wiring structure; A second high-density wiring structure is manufactured on the flattened first redistribution structure and the first high-density wiring structure.

[0012] According to a method for manufacturing a package substrate structure of the present invention, a high-density local interconnection is achieved by prefabricating a first high-density wiring structure through a glass interconnect module, and combined with a second high-density wiring structure, an I / O density of 1800 / mm can be achieved. 2 and 35 μm pitch; the CTE (3-8ppm / °C) of the glass core board and glass interconnect module is highly matched with the silicon chip (2-3 ppm / °C), which reduces the warpage of the entire package to <50 μm, ensuring the alignment accuracy and reliability of high-density interconnection; the glass core board provides a low dielectric constant (about 4-6) and low-loss signal transmission channel, combined with the fine wiring of the high-density wiring structure, effectively reducing high-frequency signals to D f<0.01, improving signal integrity. The glass interconnect module is embedded in the rewiring structure, allowing for flexible adjustment based on chip I / O requirements, reducing reliance on overall substrate processing accuracy and adapting to the high-density interconnect requirements of various packaging scenarios. This packaging substrate structure supports large-scale packaging and panel-level packaging processes, enabling large-scale, multi-chip integration, significantly improving production efficiency and reducing unit chip packaging costs. Furthermore, the embedded glass interconnect module ensures flatness through multi-zone low-stress CMP. Coplanarity is ensured by combining a prefabricated first high-density wiring structure with conductive blocks embedded in the first rewiring structure. The hybrid dielectric stack overcomes ABF limitations, achieving submicron interconnects while remaining highly compatible with existing packaging processes, facilitating industrialization.

[0013] In addition, the method for manufacturing a package substrate structure proposed above in the present invention may also have the following additional technical features: Optionally, the method further includes fabricating a first outer layer on the second high-density wiring structure, and fabricating electroplating columns on the first outer layer that are electrically connected to the second high-density wiring structure.

[0014] Optionally, the method further includes manufacturing a second outer layer on the second redistribution structure and performing surface treatment on the second outer layer.

[0015] Optionally, an adhesive is provided on a surface of the glass interconnect module opposite to the first high-density wiring structure. After the glass interconnect module is embedded in the cavity, a heat pressing process is performed to adhere the glass interconnect module to the bottom of the cavity through the adhesive.

[0016] Furthermore, the adhesive is a DAF film containing 5-15 wt% graphene.

[0017] Optionally, the multi-zone low-stress chemical mechanical polishing is performed using a silicon dioxide-based slurry zone pressure, wherein the pressure in the first high-density wiring structure area is 2-4 psi, and the pressure in the first heavy wiring structure area is 4-6 psi, and the polishing is terminated by online optical endpoint detection of a reflectivity >65%. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic cross-sectional view of a package substrate structure according to an embodiment of the present invention; Figure 2 A schematic diagram of a process for manufacturing a packaging substrate structure according to an embodiment of the present invention; Figure 3-Figure 12 Schematic cross-sectional view of a substrate in each step of a method for manufacturing a package substrate structure according to an embodiment of the present invention; Figure 13 is a schematic diagram of a glass interconnect module according to an embodiment of the present invention; Description of labels: Glass core board 100, first surface 100a, second surface 100b; Conductive via 200; A first redistribution structure 300, a cavity 310, and a first circuit layer 320; Glass interconnect module 400, first high-density wiring structure 410, conductive blocks 411, adhesive 420; A second high-density wiring structure 500; A second redistribution structure 600 and a first circuit layer 610; First outer layer 700, electroplating column 710; The second outer layer 800 . DETAILED DESCRIPTION

[0019] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0020] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0021] Please refer to Figure 1 , Figure 1 A schematic diagram of a packaging substrate structure provided for one embodiment of the present invention, the packaging substrate structure comprising: a glass core board 100 having a first surface 100a and a second surface 100b opposite to each other and one or more conductive through-holes 200 connecting the first surface 100a and the second surface 100b; a first rewiring structure 300 disposed on the first surface 100a of the glass core board 100 and electrically connected to the conductive through-holes 200, the first rewiring structure 300 having at least one cavity 310 extending from a side surface of the first rewiring structure 300 to a portion of the thickness of the first rewiring structure 300; at least one glass interconnect module 400 embedded in the cavity 310; a first high-density wiring structure 410 being provided on one side surface of the glass interconnect module 400; a second high-density wiring structure 500 disposed on the first rewiring structure 300 and the first high-density wiring structure 410 and electrically connecting the first rewiring structure 300 and the first high-density wiring structure 410; and a second rewiring structure 600 disposed on the second surface of the glass core board 100 and electrically connected to the conductive through-holes 200.

[0022] That is to say, the packaging substrate structure is to embed the glass interconnect module 400 on the build-up layer of the first rewiring structure 300, and the number of glass interconnect modules 400 and cavities 310 can be set according to the core particles that need to be packaged; embedding the glass interconnect module 400 on the build-up layer of the first rewiring structure 300 can be flexibly adjusted according to the chip I / O requirements, reducing the dependence on the overall processing accuracy of the substrate, and can support panel-level packaging technology, realize large-size, multi-core particle integration, significantly improve production efficiency, and reduce unit chip packaging costs.

[0023] Therefore, according to the packaging substrate structure provided by the embodiment of the present invention, high-density local interconnection is achieved through the first high-density wiring structure prefabricated by the glass interconnect module, that is, high-density interconnection of local key areas is achieved by using the glass interconnect module itself; combined with the second high-density wiring structure, an I / O density of 1800 / mm can be achieved. 2 and 35 μm pitch; the CTE (3-8ppm / °C) of the glass core board and glass interconnect module is highly matched with the silicon chip (2-3 ppm / °C), which reduces the warpage of the entire package to <50 μm. In other words, the low CTE characteristics of the glass interconnect module 400 and the glass core board 100 form a "double low CTE" architecture to ensure low warpage and ensure the alignment accuracy and reliability of high-density interconnection; the glass core board provides a low dielectric constant (about 4-6) and low-loss signal transmission channel, combined with the fine wiring of the high-density wiring structure, effectively reducing high-frequency signals to D f <0.01, improving signal integrity; the glass interconnect module is embedded in the rewiring structure and can be flexibly adjusted according to the chip I / O requirements, reducing the dependence on the overall processing accuracy of the substrate and adapting to the high-density interconnection requirements of different packaging scenarios; the packaging substrate structure supports large-size packaging and panel-level packaging processes, which can realize large-size, multi-chip integration, significantly improve production efficiency, and reduce unit chip packaging costs.

[0024] As an example, Figure 1 As shown, the line specifications of the first high-density wiring structure 410 are smaller than the line specifications of the second high-density wiring structure 500, the line specifications of the first rewiring structure 300 are the same as the line specifications of the second rewiring structure 600, and the line specifications of the second high-density wiring structure 500 are smaller than the line specifications of the first rewiring structure 300.

[0025] Specifically, the line specification is line width and / or line spacing; preferably, the line width / spacing of the first high-density wiring structure 410 is ≤2 μm; and the line width / spacing of the second high-density wiring structure 500 is ≤5 μm.

[0026] As an example, the bottom of the cavity 310 has a partial wiring layer, and the surface of the glass interconnect module 400 opposite to the first high-density wiring structure 410 is attached to the bottom of the cavity 310 via adhesive 420. This ensures that the glass interconnect module 400 is securely embedded in the cavity 310.

[0027] As an example, Figure 1 As shown, the package substrate structure also includes a first outer layer 700 and a second outer layer 800. The first outer layer 700 is provided on the second high-density wiring structure 500 and has electroplated pillars 710 electrically connected to the second high-density wiring structure 500. The second outer layer 800 is provided on the second redistribution structure 600. In this way, the first outer layer 700 protects the second high-density wiring structure 500, and its electroplated pillars 710 can be used for flip-chip die. The second outer layer 800 protects the second redistribution structure 600.

[0028] The following describes the manufacturing process of the above-mentioned packaging substrate structure. The embodiment described in this application provides a manufacturing method of the above-mentioned packaging substrate structure. Please refer to Figure 2 , which is a process flow chart of the manufacturing method, comprising the following steps: S1: providing a glass core board, forming conductive through-holes on the glass core board, and forming a first circuit layer electrically connected through the conductive through-holes on a first surface and a second surface opposite to the glass core board; S2: adding wiring layers on the first circuit layer of the first surface to produce a first redistribution structure, and adding wiring layers on the first circuit layer of the second surface to produce a second redistribution structure; S3: forming at least one cavity of the first redistribution structure extending from a side surface of the first redistribution structure to a portion of the thickness thereof; S4: providing at least one glass interconnect module, and embedding the glass interconnect module into the cavity, wherein one side surface of the glass interconnect module has a first high-density wiring structure; S5: Laminating a dielectric layer on the first redistribution structure and the first high-density wiring structure, and flattening the dielectric layer using multi-zone low-stress chemical mechanical polishing to expose the wiring layer of the first redistribution structure and the conductive blocks of the first high-density wiring structure; S6: Fabricating a second high-density wiring structure on the flattened first redistribution structure and the first high-density wiring structure.

[0029] The method begins by fabricating conductive vias 200 and a first wiring layer on a glass core substrate 100. The first wiring layer is the first layer of wiring in the redistribution structure, also known as the inner wiring layer. Layers are then added to the first wiring layer to create a first redistribution structure 300 and a second redistribution structure 600. After adding layers, a cavity 310 with one end open is formed on one side of the first redistribution structure 300, i.e., the outermost layer. Once cavity 310 is formed, a prefabricated glass interconnect module 400 is inserted into the cavity and then leveled.

[0030] Thus, the first high-density wiring structure 410 prefabricated by the glass interconnect module 400 realizes high-density local interconnection, and combined with the second high-density wiring structure 500, an I / O density of 1800 / mm can be achieved. 2 and 35 μm pitch; the CTE (3-8ppm / °C) of the glass core board 100 and the glass interconnect module 400 is highly matched with the silicon chip (2-3 ppm / °C), which reduces the warpage of the entire package to <50 μm, ensuring the alignment accuracy and reliability of high-density interconnection; the glass core board 100 provides a low dielectric constant (about 4-6) and low-loss signal transmission channel, combined with the fine wiring of the high-density wiring structure, effectively reducing high-frequency signals to D f <0.01, improving signal integrity. The glass interconnect module 400 is embedded in the redistribution structure, allowing for flexible adjustments based on chip I / O requirements, reducing reliance on overall substrate processing accuracy and adapting to the high-density interconnect requirements of various packaging scenarios. This packaging substrate structure supports large-scale packaging and panel-level packaging processes, enabling large-scale, multi-die integration, significantly improving production efficiency and reducing unit chip packaging costs. Furthermore, the embedded glass interconnect module ensures flatness through multi-zone low-stress CMP. Coplanarity is ensured by prefabricating the first high-density wiring structure 410 and embedding conductive blocks in the build-up layer of the first redistribution structure 300.

[0031] For details, please refer to Figures 3 to 12 Schematic cross-sectional view of a packaging substrate showing each step of the method for manufacturing the packaging substrate structure.

[0032] First, refer to Figure 3 , perform step S1, provide a glass core board 100, and make conductive through-holes 200 on the glass core board 100, and make a first circuit layer electrically connected through the conductive through-holes 200 on the first surface 100a and the second surface 100b opposite to each other of the glass core board 100.

[0033] Specifically: select glass materials such as alkali-free glass, aluminosilicate glass or borosilicate glass with a thermal expansion coefficient (CTE) of 3-8 ppm / °C as the core board material. The thickness of the glass core board 100 is 0.2 mm-1.6 mm, which supports panel-level packaging ≥515 mm×510 mm.

[0034] like Figure 4 As shown, based on the glass core board 100, TGV holes 110 are fabricated by methods such as plasma etching, laser ablation, laser-induced etching, and focused discharge. In this embodiment, laser-induced etching combined with a deep etching process is used to fabricate the TGV holes 110, with a diameter >30 μm. The TGV holes 110 penetrate the glass core board 100. The laser process uses a nanosecond, picosecond, or femtosecond laser to form a modified area, followed by etching with hydrofluoric acid or an alkaline solution to form uniform, microcrack-free through-holes with a verticality deviation of <5° and an adjustable aspect ratio, meeting the requirements of high-density interconnection.

[0035] like Figure 5 As shown, based on the glass core board 100 in which the TGV hole 110 is formed as described above, a conductive material is filled in the TGV hole 110 to form a conductive through-hole 200. The conductive material includes a seed layer and a metal conductive layer. The seed layer can be formed by a variety of process methods, including but not limited to metal sintering, polymer-assisted metallization, and physical vapor deposition (PVD) sputtering. In this embodiment, PVD sputtering is used to sputter a double-sided seed layer on the glass core board after the glass through-hole is made. Specifically, a Ti / Cu seed layer (titanium thickness>50 nm, copper thickness greater than titanium, thickness deviation<5%) is deposited on the inner wall and upper and lower surfaces (first surface 100a and second surface 100b) of the TGV hole 110 by PVD. Then, a metal conductive layer is made on the surface of the seed layer, and the metal conductive layer completely fills the TGV hole 110 and covers the seed layer on the upper and lower surfaces of the glass core board 100. The metal conductive layer can be formed by methods such as electroplating to fill the holes or by filling the holes with a conductive metal paste. In this embodiment, electroplating is used to fill the through-holes and cover the surface to form the metal conductive layer. The metal conductive layer is then thinned to <15 μm (using CMP or chemical etching, with a surface flatness of <1 μm). The conductive material can be copper, nickel, tin, or their alloys. CMP uses a polishing solution containing abrasives and an oxidizing agent, while chemical etching uses a sulfuric acid and hydrogen peroxide solution to ensure uniform thickness.

[0036] like Figure 6As shown, based on the above-mentioned glass core board 100, the first circuit layers 320 and 610 are manufactured by a subtractive process; the subtractive process includes dry film pasting → exposure (using a g-line or i-line ultraviolet light source) → development (strong alkaline solution such as sodium hydroxide, sodium carbonate or sodium carbonate solution) → etching (one or more of NaOH, NaHCO3, Na2CO3, HCl, H3PO4, H2O2) → film removal, forming an inner layer circuit (i.e., the first circuit layer 320, 610) with a line width / spacing of 8 / 8 μm. The first circuit layers 320 and 610 are electrically connected to the conductive through-hole 200 to meet the high-density interconnection requirements.

[0037] Then, step S2 is performed to build up wiring on the first circuit layer 320 of the first surface 100a to produce a first redistribution structure 300 , and to build up wiring on the first circuit layer 320 of the second surface 100b to produce a second redistribution structure 600 .

[0038] Specifically, Figure 7 As shown, the wiring is increased by a semi-additive process; the process of the semi-additive process includes laminating ABF film → laser drilling → desmearing + chemical copper deposition → dry film application → exposure → development → electroplating → film stripping and flash etching; the ABF film has low CTE, low dielectric loss and high mechanical strength, which supports fine circuit production.

[0039] The laser drilling process is to form a blind hole structure on the surface of the ABF film through laser processing technology. The processed blind hole must meet the precision requirements of aperture ≤60 μm and disk diameter ≤80 μm. Laser drilling can be carried out by UV laser, CO2 laser machine or ultrafast laser. After the laser drilling is completed, a chemical copper deposition process is used to form a conductive metal layer on the inner wall and surface of the blind hole. The thickness of the conductive metal layer is 5 μm-15 μm. The plating solution contains copper sulfate, potassium sodium tartrate, sodium hydroxide and formaldehyde. The backlight level is ≥9. The coating is uniform and there is no obvious oxidation, fiber, fingerprint and other defects on the surface. The coating should be a uniform, dense and shiny orange-red copper layer to ensure good conductivity and bonding. After the conductive metal layer is formed by chemical copper plating, the dry film, exposure and development, electroplating and film stripping flash etching processes are carried out in sequence to complete the circuit layer wiring, that is, to produce it. Figure 7 In the first rewiring structure 300 and the second rewiring structure 600, the build-up wiring layer of the first rewiring structure is electrically connected to the first wiring layer 320, and the build-up wiring layer of the second rewiring structure is electrically connected to the first wiring layer 610. The line width spacing of the wiring layers of the first rewiring structure 300 and the second rewiring structure 600 can reach 8 / 8 μm. Figure 7 As shown, after the first build-up layer is completed, the same process can be used to manufacture the remaining build-up layers on the first build-up layer. The number of build-up layers can be adjusted according to actual needs.

[0040] Then, if Figure 8 As shown, step S3 is performed to form at least one cavity 310 extending from a side surface of the first redistribution structure 300 to a portion of the thickness of the first redistribution structure 300 .

[0041] In this embodiment, the manufacturing of the cavity 310 includes: first, on one side surface of the first redistribution structure 300 formed above ( Figure 7 A layer of ABF film is laminated on the glass interconnect module 300a), and then a cavity 310 is formed by laser or etching. The depth of the cavity 310 matches the thickness of the glass interconnect module 400, and the width of the cavity 310 is greater than the width of the glass interconnect module 400, and is at least 50 μm larger than the single side of the glass interconnect module 400. Finally, laser drilling, dry film application, exposure and development, electroplating, and film stripping and flash etching are performed on the ABF film containing the cavity 310 to complete the build-up wiring of the topmost circuit layer with the cavity 310. Figure 8 As shown, the bottom of the cavity 310 of the first redistribution structure 300 including the cavity 310 has a portion of the circuit layer.

[0042] In addition, if Figure 8 As shown, an outermost circuit layer is also formed on the second redistribution structure 600 .

[0043] Then, if Figure 9 As shown, step S4 is performed to provide at least one glass interconnect module 400 , and embed the glass interconnect module 400 into the cavity 310 . A first high-density wiring structure 410 is formed on one side surface of the glass interconnect module 400 .

[0044] In this embodiment, the glass interconnect module 400 is independently manufactured in advance. Figure 13 As shown, the glass interconnect module 400 comprises a glass core board. A first high-density wiring structure 410 is fabricated on the top surface (TOP) of the glass core board. Conductive blocks 411 (e.g., copper bumps) are fabricated on the top surface of the first high-density wiring structure 410, which are electrically connected to the first high-density wiring structure 410. The number of wiring layers in the first high-density wiring structure 410 can be adjusted as needed, with the line width / spacing of the wiring layers being ≤2 μm. An adhesive is applied to the bottom surface (Bottom) of the glass core board. The adhesive can be a DAF film. In this embodiment, a DAF film containing 5-15 wt% graphene (thermal conductivity >6 W / m·K) is used. The DAF film is treated with oxygen plasma (30-60 s) before placement in the cavity 310.

[0045] Afterwards, the glass interconnect module 400 is placed into the cavity 310, and the bottom DAF film is activated by hot pressing at 150-200°C and 0.5-1 MPa, completing the hot pressing attachment of the glass interconnect module 400. In this embodiment, the width of the cavity 310 is greater than that of the glass interconnect module 400, to facilitate placement of the glass interconnect module 400 within the cavity 310.

[0046] Then, if Figure 10 As shown, step S5 is performed to laminate a dielectric layer on the first redistribution structure 300 and the first high-density wiring structure 410, and use multi-partition low-stress chemical mechanical polishing to flatten the dielectric layer to expose the circuit layer of the first redistribution structure 300 and the conductive block 411 of the first high-density wiring structure 410.

[0047] Specifically, an ABF film is laminated on the first redistribution structure 300 and the first high-density wiring structure 410. The ABF film covers the Figure 9 The outermost wiring layer of the first redistribution structure 300 and the conductive bumps 411 on the first high-density wiring structure 410 are polished, filling the gap between the glass interconnect module 400 and the inner wall of the cavity 310. The ABF film is then removed using multi-zone low-stress CMP, exposing the top surface of the conductive bumps 411 and the outermost wiring layer. Coplanarity is ≤ 0.1 μm and roughness Ra < 10 nm. In this embodiment, multi-zone low-stress CMP is performed using a silica-based slurry (60 ± 5 wt%, pH 9-11). The pressure is zoned for polishing: 2-4 psi for the glass interconnect module area and 4-6 psi for the first redistribution structure area. The polishing is terminated by in-line optical endpoint detection (reflectivity > 65%) and ultrasonic cleaning is performed to ensure a cleanliness level of < 0.1 particles / cm². This completes the leveling of the first high-density wiring structure 410 and the first redistribution structure 300, ensuring coplanarity.

[0048] Then, if Figure 11 As shown, a second outer layer 800 may be fabricated on the second redistribution structure 600 first.

[0049] Specifically, a photosensitive medium layer is laminated or coated onto the outermost wiring layer (bottom surface) of the second redistribution structure 600. The photosensitive medium layer is available in liquid or dry film forms. For dry film, vacuum lamination is used; for liquid, wet slit coating is used. This embodiment preferably uses photosensitive polyimide (PID (dry film)) or PSPI (liquid) with excellent thermal stability, mechanical strength, and structural stability. The photosensitive medium layer undergoes exposure, development, and post-curing to create windows. A dry film is then applied to the surfaces (top surface) of the first redistribution structure 300 and the first high-density wiring structure 410 for protection. The windowed areas are then subjected to ENEPIG pre-treatment, ENEPIG metallization, and dry film stripping on the top surface, completing the fabrication of the second outer layer 800. The exposure, development, post-curing, ENEPIG pre-treatment, ENEPIG metallization, and dry film stripping of the photosensitive medium layer all utilize existing processes and are not described in detail here.

[0050] Then, if Figure 12 As shown, step S6 is executed to manufacture the second high-density wiring structure 500 on the flattened first redistribution structure 300 and the first high-density wiring structure 410 .

[0051] Specifically, the second high-density wiring structure 500 is fabricated on the top surface (top surface) of the first redistribution structure 300 and the first high-density wiring structure 410 using a damascene process. The damascene process involves laminating or coating a first photosensitive dielectric layer, then exposing it, developing it, and then post-curing it to form blind vias with a hole diameter ≥ 5 μm and a pad diameter ≥ 10 μm. This allows for vertical interconnection between the second high-density wiring structure 500, the first redistribution structure 300, and the first high-density wiring structure 410. A second photosensitive dielectric layer is then laminated or coated, followed by exposure, development, post-curing, PVD, electroplating, copper thinning, and Ti / Cu etching to form the pads and wiring layers for horizontal interconnection. Fine wiring with a line / space width of ≤ 5 / 5 μm is achieved. The number of layers in the second high-density wiring structure 500 can be adjusted to meet high-density interconnect requirements. The photosensitive dielectric layer is preferably made of photosensitive polyimide (PID (dry film)) with good thermal stability, mechanical strength, and structural stability, namely, PID (dry film) or PSPI (liquid film).

[0052] Finally, if Figure 1As shown, a first outer layer 700 is fabricated on the second high-density wiring structure 500. The first outer layer 700 is formed by laminating or coating a photosensitive dielectric layer. Blind vias are formed through exposure, development, and post-curing. PVD, dry film lamination, exposure, development, electroplating of copper pillars / nickel / tin, stripping, Ti / Cu etching, and reflow soldering are then performed to form electroplated pillars 710 on the first outer layer 700 that are electrically connected to the second high-density wiring structure 500. The exposure, development, post-curing, PVD, electroplating of copper pillars / nickel / tin, stripping, Ti / Cu etching, and reflow soldering of the photosensitive dielectric layer are all based on existing processes and are not described in detail here.

[0053] So far, the production Figure 1 The package substrate structure shown in FIG. The package substrate structure can be connected to the chip on the electroplating column 710 to perform flip-chip packaging of the chip.

[0054] In summary, the package substrate structure and the manufacturing method thereof proposed in the embodiments of the present invention have the following benefits: 1) High-density interconnection and low warpage: The glass interconnect module achieves local interconnection with a line width / spacing of ≤2 μm through prefabricated RDL. Combined with the second highest density structure of the core board, it can achieve an I / O density of 1800 / mm 2 The CTE of the glass core board and glass interconnect module (3-8 ppm / °C) is highly matched to that of the silicon chip (2-3 ppm / °C), reducing warpage to <50 μm, ensuring alignment accuracy and reliability for high-density interconnects.

[0055] 2) Low transmission loss: The glass core board provides a low dielectric constant (approximately 4-6) and low-loss signal transmission channel. Combined with the fine wiring (≤2 μm) of the photosensitive medium RDL, it effectively reduces high-frequency signals to Df<0.01, thereby improving signal integrity.

[0056] 3) Process innovation and compatibility: The embedded glass interconnect module ensures flatness through multi-zone low-stress CMP; the ABF build-up layer is embedded through pre-fabricated RDL and conductive blocks, and the combination ensures coplanarity; the hybrid dielectric stack breaks through the ABF limitations and achieves sub-micron interconnection. At the same time, it is highly compatible with existing packaging processes and easy to industrialize.

[0057] 4) Cost reduction: The cost of the glass core board is only 1 / 5 of the cost of the silicon interposer. The high-precision process is concentrated on the small-area glass interconnect module. The core board circuit is simplified, and the ABF build-up layer replaces part of the RDL, which significantly reduces the manufacturing cost and is suitable for mass production.

[0058] 5) Improve market competitiveness: Low-cost, high-performance substrate structures can be widely used in fields such as AI chips, server chips and 5G equipment, meeting the needs of cost-sensitive markets and creating higher market share and economic returns for enterprises.

[0059] 6) Support for Large-Size Packaging: This glass packaging substrate supports panel-level packaging processes, enabling large-size, multi-chip integration, significantly improving production efficiency and reducing unit chip packaging costs. Panel-level processes offer higher material utilization rates. In addition to their shape advantages, the panel size is much larger than the wafer, resulting in significant economies of scale. This allows for the simultaneous processing of several times the number of chips on a wafer in a single process flow, thereby reducing the packaging cost per chip.

[0060] 7) Promote the development of high-performance computing industry: This application meets the needs of artificial intelligence, 5G communication and high-performance computing (HPC) for high bandwidth and multi-chip integration by achieving high-density interconnection and low warpage performance with line width / spacing ≤ 2 μm, promotes chip architecture innovation, promotes the advancement of information and communication technology, and provides technical support for industries such as intelligent manufacturing, cloud computing and the Internet of Things.

[0061] 8) Promote green manufacturing: Use glass core boards and glass interconnect modules, combined with panel-level packaging technology, to reduce dependence on high-energy-consuming silicon interposer processes, reduce energy consumption and carbon emissions in the production process, and meet the social needs of sustainable development.

[0062] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0063] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0064] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0065] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0066] In the description of this specification, reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0067] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A packaging substrate structure, characterized in that: include: a glass core board having a first surface and a second surface opposite to each other and one or more conductive through-holes connecting the first surface and the second surface; A first redistribution structure is provided on the first surface of the glass core board and is electrically connected to the conductive vias, the first redistribution structure having at least one cavity extending from a side surface of the first redistribution structure to a portion of the thickness of the first redistribution structure; at least one glass interconnect module embedded in the cavity; One side surface of the glass interconnect module has a first high-density wiring structure; a second high-density wiring structure, disposed on the first redistribution structure and the first high-density wiring structure, and electrically connecting the first redistribution structure and the first high-density wiring structure; The second redistribution structure is disposed on the second surface of the glass core board and is electrically connected to the conductive through hole.

2. The packaging substrate structure according to claim 1, wherein: The line specifications of the first high-density wiring structure are smaller than those of the second high-density wiring structure, the line specifications of the first rewiring structure are the same as those of the second rewiring structure, and the line specifications of the second high-density wiring structure are smaller than those of the first rewiring structure.

3. The package substrate structure according to claim 2, wherein: The line specifications are line width and / or line spacing, and the line width / spacing of the first high-density wiring structure is ≤2 μm.

4. The packaging substrate structure according to claim 1, wherein: The bottom of the cavity is provided with a partial circuit layer, and a surface of the glass interconnect module opposite to the first high-density wiring structure is attached to the bottom of the cavity by an adhesive.

5. The packaging substrate structure according to claim 1, wherein: It also includes a first outer layer and a second outer layer, the first outer layer is arranged on the second high-density wiring structure, and the first outer layer has electroplated columns electrically connected to the second high-density wiring structure; the second outer layer is arranged on the second heavy wiring structure.

6. A method for manufacturing a packaging substrate structure, characterized in that: The following steps are involved: Providing a glass core board, making conductive through-holes on the glass core board, and making a first circuit layer electrically connected through the conductive through-holes on a first surface and a second surface opposite to the glass core board; Adding wiring layers on the first circuit layer of the first surface to produce a first redistribution structure, and adding wiring layers on the first circuit layer of the second surface to produce a second redistribution structure; At least one cavity is formed in the first redistribution structure, extending from a side surface of the first redistribution structure to a portion of the thickness thereof; Providing at least one glass interconnect module, and embedding the glass interconnect module into the cavity, wherein one side surface of the glass interconnect module has a first high-density wiring structure; Laminating a dielectric layer on the first redistribution structure and the first high-density wiring structure, and flattening the dielectric layer using multi-zone low-stress chemical mechanical polishing to expose the wiring layer of the first redistribution structure and the conductive blocks of the first high-density wiring structure; A second high-density wiring structure is manufactured on the flattened first redistribution structure and the first high-density wiring structure.

7. The method for manufacturing a package substrate structure according to claim 6, wherein: The method further includes forming a first outer layer on the second high-density wiring structure, and forming electroplating columns on the first outer layer that are electrically connected to the second high-density wiring structure.

8. The method for manufacturing a package substrate structure according to claim 6, wherein: The method further includes manufacturing a second outer layer on the second redistribution structure and performing surface treatment on the second outer layer.

9. The method for manufacturing a package substrate structure according to claim 6, wherein: An adhesive is provided on a surface of the glass interconnect module opposite to the first high-density wiring structure. After the glass interconnect module is embedded in the cavity, a heat pressing process is performed to adhere the glass interconnect module to the bottom of the cavity through the adhesive.

10. The method for manufacturing a package substrate structure according to claim 9, wherein: The adhesive is a DAF film containing 5-15 wt% graphene.

11. The method for manufacturing a package substrate structure according to claim 6, wherein: The multi-zone low-stress chemical mechanical polishing is performed using a silicon dioxide-based slurry with zoned pressure, wherein the pressure in the first high-density wiring structure zone is 2-4 psi, and the pressure in the first heavy wiring structure zone is 4-6 psi, and is terminated when the reflectivity is greater than 65% through online optical endpoint detection.

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