Operational amplifier

Abstract

The embodiment of the invention relates to an operational amplifier. An electronic device includes: a pair of first transistors, each first transistor coupled to a first node through a conductive terminal; a pair of second transistors, each second transistor coupled to a second node through a conductive terminal; and a third transistor coupling the first node and the second node, a control terminal of the third transistor being coupled to an output of an operational amplifier, the operational amplifier being coupled at its input to the first node and a node to which a reference voltage is applied.

Description

[0001] This application is a divisional application of the invention patent application with the application date of August 30, 2021 (the earliest priority date is August 31, 2020), the Chinese national application number 202111007148.4, and the name "Operational Amplifier". Technical Field

[0002] The present disclosure relates generally to electronic devices and, more particularly, to operational amplifiers. Background Art

[0003] An operational amplifier is a differential amplifier. In other words, an operational amplifier is an electronic amplifier that amplifies the potential difference present at its input.

[0004] Originally, operational amplifiers were designed to perform mathematical operations in analog devices; they enabled basic mathematical operations such as addition, subtraction, integration, differentiation, and other operations to be easily implemented.

[0005] Today, operational amplifiers are used in many other applications such as motor control, voltage regulation, current sources or oscillators. Summary of the Invention

[0006] One embodiment overcomes all or some of the disadvantages of known operational amplifiers.

[0007] One embodiment provides an electronic device comprising: a pair of first transistors, each coupled to a first node via a conductive terminal; a pair of second transistors, each coupled to a second node via a conductive terminal; and a third transistor coupled to the first node and the second node, a control terminal of the third transistor being coupled to an output of an operational amplifier, the operational amplifier being coupled at its input to the first node and a node to which a reference voltage is applied.

[0008] According to one embodiment, the device is an operational amplifier.

[0009] According to one embodiment, the third transistor is coupled to the second node via a current mirror.

[0010] According to one embodiment, the device includes an inverting input, a non-inverting input, and two power supply inputs.

[0011] According to one embodiment, the control terminal of one of the first transistors and the control terminal of one of the second transistors is coupled to the non-inverting input, and the control terminal of the other of the first transistors and the control terminal of the other of the second transistors is coupled to the inverting input.

[0012] According to one embodiment, the first node is coupled to the first power supply input via a current source.

[0013] According to one embodiment, the second node is coupled to the second power supply input via a conduction terminal of the fourth transistor.

[0014] According to one embodiment, a conduction terminal of the third transistor is coupled to the first node, and a conduction terminal of the third transistor is coupled to a first conduction terminal of a fifth transistor, a second conduction terminal of the fifth transistor is coupled to the second power supply input, and a control terminal of the fifth transistor is coupled to the first conduction terminal of the fifth transistor and to the control terminal of the fourth transistor.

[0015] According to one embodiment, a non-inverting input of an operational amplifier included in the device is coupled to the first power supply input through a resistor and to the second power supply input through a current source.

[0016] According to one embodiment, the first transistor is coupled to the first node via its source, and the second transistor is coupled to the second node via its source.

[0017] According to one embodiment, the surface area of ​​the third transistor is at least smaller than one fifth of the surface areas of the first transistor and the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above features and advantages and others will be more fully described in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0019] Figure 1 An operational amplifier is schematically shown;

[0020] Figure 2 In more detail, the Figure 1 An embodiment of the operational amplifier in; and

[0021] Figure 3 Shown Figure 2 An example of current variation in an embodiment of FIG. DETAILED DESCRIPTION

[0022] In different figures, the same features have been designated by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions and material properties.

[0023] For clarity, only the steps and elements that are useful for understanding the embodiments described herein are illustrated and described in detail.

[0024] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intermediate elements other than conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled through one or more other elements.

[0025] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as terms "front", "back", "up", "down", "left", "right", etc., or relative position qualifiers, such as terms "above", "below", "higher", "lower", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figures.

[0026] Unless otherwise indicated, "about," "approximately," "substantially," and "on the order of" mean within 10%, preferably within 5%.

[0027] Figure 1 An operational amplifier 10 is shown schematically.

[0028] The amplifier 10 includes four inputs 102 , 104 , 106 , 108 and one output 110 .

[0029] Input 102 is a non-inverting input (+) and receives an input signal INP. Input 104 is an inverting input (-) and receives an input signal INN.

[0030] Inputs 106 and 108 are power inputs. The power inputs of operational amplifier 10 are passed between inputs 106 and 108. In other words, node 106 is coupled to, and preferably connected to, node or rail 112. Node 112 is coupled to, and preferably connected to, a voltage source that passes a voltage, such as power supply voltage Vcc. Node 108 is coupled to, and preferably connected to, node or rail 114. Node 114 is coupled to, and preferably connected to, a voltage source that passes a reference voltage (GND) (e.g., ground). Thus, power supply voltage Vcc is passed between nodes 106 and 108.

[0031] The output 110 delivers an output signal OUT in accordance with the difference between the input signals INN and INP. More generally, the value of the output voltage VOUT depends on the difference between the voltage received on the non-inverting input and the voltage received on the inverting input.

[0032] Operational amplifier 10 is a rail-to-rail input operational amplifier, that is, it can ideally amplify the potential difference between inputs 102 and 104. The potential received at the input of the operational amplifier can have a value between the voltage value on node 114 and node 112.

[0033] Thus, amplifier 10 delivers an output voltage OUT that can have a range from the voltage provided on node 108 to the voltage provided on node 106 , depending on the difference between input voltage INN and input voltage INP.

[0034] Operational amplifier 10 includes three stages (not shown) between inputs 102 and 104 and output 110: a differential amplification input stage, an intermediate amplification stage or intermediate stage, and an output stage.

[0035] Figure 2 In more detail, Figure 1 More specifically, Figure 2 An example of an input differential stage of the operational amplifier 10 is shown.

[0036] Operational amplifier 10 is a precision amplifier. Therefore, amplifier 10 is primarily used in applications where the accuracy of the amplification performed is important.

[0037] The amplifier 10 includes a first pair of transistors 116a and 116b. Preferably, the transistors 116a and 116b are MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistors. The transistors 116a and 116b are preferably P-type transistors.

[0038] exist Figure 2 In the embodiment of FIG. 1 , transistors 116 a and 116 b are coupled in a common source type configuration. In other words, the sources of transistors 116 a and 116 b are coupled to, and preferably connected to, each other. In other words, the source of transistor 116 a is coupled to, and preferably connected to, node 118, and the source of transistor 116 b is coupled to, and preferably connected to, node 118.

[0039] The other conductive terminal (here, the drain) of each of transistors 116a and 116b is coupled, preferably connected, to another stage of the operational amplifier, for example, an intermediate stage (not shown). Preferably, the drains of transistors 116a and 116b (drain 120a and drain 120b, respectively) are coupled to a node of the intermediate stage, with drains 120a and 120b being coupled to different nodes. The drains of transistors 116a and 116b are preferably not connected to each other.

[0040] In other words, transistor 116a is coupled via its conductive terminal between node 118 and a first node (not shown) of the intermediate stage. Similarly, transistor 116b is coupled via its conductive terminal between node 118 and a second node (not shown) of the intermediate stage.

[0041] Transistors 116a and 116b are controlled by input signals of operational amplifier 10. Transistor 116a is controlled by signal INP. In other words, the control terminal or gate of transistor 116a is coupled to, and preferably connected to, input node 102. Similarly, transistor 116b is controlled by signal INN. In other words, the control terminal or gate of transistor 116b is coupled to, and preferably connected to, input node 104.

[0042] Node 118 is coupled to rail 112 to which voltage Vcc is applied. Node 118 is coupled to rail 112 via current source 122, which delivers current I0. Thus, current source 122 is coupled to rail 112 via one terminal, preferably connected thereto, and is coupled via another terminal, preferably connected thereto, to node 118.

[0043] The operational amplifier 10 further includes a second pair of transistors 124a and 124b. Preferably, the transistors 124a and 124b are MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistors. The transistors 124a and 124b are preferably N-type transistors.

[0044] Transistors 124a and 124b are coupled in a common source type configuration. In other words, the sources of transistors 124a and 124b are coupled to, and preferably connected to, each other. In other words, the source of transistor 124a is coupled to, and preferably connected to, node 126, and the source of transistor 124b is coupled to, and preferably connected to, node 126.

[0045] The other conductive terminal (here, the drain) of each of transistors 124a and 124b is coupled, preferably connected, to another stage of the operational amplifier, such as an intermediate stage (not shown). Preferably, the drains of transistors 116a and 116b (drain 128a and drain 128b, respectively) are coupled to a node of the intermediate stage, with drains 128a and 128b coupled to different nodes. The drains of transistors 124a and 124b are preferably not connected to each other.

[0046] In other words, transistor 124a is coupled via its conductive terminal between node 126 and the third node of the intermediate stage. Similarly, transistor 124b is coupled via its conductive terminal between node 126 and the fourth node of the intermediate stage. Preferably, the third and fourth nodes of the intermediate stage are different from the first and second nodes of the intermediate stage.

[0047] Node 126 is coupled to rail 114 to which reference voltage GND is applied. Node 126 is coupled to rail 114 via transistor 127. Preferably, transistor 127 is a MOSFET transistor. More specifically, transistor 127 is coupled (preferably connected) to rail 114 via a conductive terminal (e.g., its source) and is coupled (preferably connected) to node 126 via another conductive terminal (e.g., its drain).

[0048] Transistors 124a and 124b are controlled by the input signal of operational amplifier 10. Transistor 124a is controlled by signal INP. In other words, the control terminal or gate of transistor 124a is coupled to, and preferably connected to, input node 102. Similarly, transistor 124b is controlled by signal INN. In other words, the control terminal or gate of transistor 124b is coupled to, and preferably connected to, input node 104.

[0049] Operational amplifier 10 also includes a pass transistor 130. Transistor 130 is, for example, a MOSFET transistor, preferably a P-type transistor. Transistor 130 is preferably smaller than transistors 116a, 116b, 124a, and 124b. For example, the surface area of ​​each of transistors 116a, 116b, 124a, and 124b is at least five times, and preferably eight times, the surface area of ​​transistor 130.

[0050] The operational amplifier 10 further comprises a transistor 132 , for example of the MOSFET type, coupled, preferably connected, between a conducting terminal of the transistor 130 and the track 114 .

[0051] Thus, node 118 is coupled to rail 114 through transistor 130 and transistor 132, which are coupled in series. More specifically, transistor 130 is coupled, preferably connected to node 118, through a conductive terminal, such as a source. Transistor 130 is also coupled, preferably connected to node 134, through another conductive terminal, such as a drain. Transistor 132 is also coupled, preferably connected to node 134, through a first conductive terminal, such as a drain, and is also coupled, preferably connected to rail 114, through another conductive terminal, such as a source.

[0052] Transistors 127 and 132 are coupled in a current mirror configuration. In other words, the drain and gate of transistor 132 are coupled, preferably connected to each other, and the gate of transistor 132 is coupled, preferably connected, to the gate of transistor 127. The current flowing through transistor 127, in other words, the current reaching node 126, is also substantially equal to the current flowing through transistors 130 and 132.

[0053] Operational amplifier 10 includes a resistor 136 having a value Rref and a current source 138 that delivers a current Rref. Resistor 136 and current source 138 are coupled in series between rail 112 and rail 114. More specifically, resistor 136 is coupled to, preferably connected to, rail 112 via a first terminal and is coupled to, preferably connected to node 140 via another terminal. Current source 138 is coupled to, preferably connected to node 140 via a first terminal and is coupled to, preferably connected to rail 114 via another terminal.

[0054] Operational amplifier 10 further includes operational amplifier 144. Node 140 is coupled to, preferably connected to, an input, preferably a non-inverting input, of operational amplifier 144. Another input, preferably an inverting input, of operational amplifier 144 is coupled to, preferably connected to, node 118.

[0055] During operation of operational amplifier 10, a signal representing voltage INP is passed to the second, intermediate stage by transistor 116a or transistor 124a. Similarly, a signal representing voltage INN is passed to the second, intermediate stage by transistor 116b or transistor 124b.

[0056] For voltages INN and INP, which correspond to the input voltages of the operational amplifier in common mode between the voltage of rail 114 and threshold TH, transistors 116a and 116b are turned on and transistors 124a and 124b are turned off. Common mode refers to a configuration in which the inverting and non-inverting inputs of operational amplifier 10 are coupled to each other. Signals INP and INN are therefore substantially equal.

[0057] The voltage representing the voltage between input nodes 102 and 104 is passed to the intermediate stage by transistors 116 a and 116 b, with voltages INN and INP corresponding to the input voltage of the operational amplifier in common mode between the voltage of rail 114 and a threshold TH. Threshold TH is between the voltage of rail 114 and the voltage of rail 112, for example, between ground and power supply voltage Vcc, for example, between 0 V and 5 V.

[0058] For voltages INN and INP corresponding to the input voltage of the operational amplifier in the common node between the threshold TH and the voltage of the rail 112, transistors 124a and 124b are turned on and transistors 116a and 116b are turned off. Therefore, for voltages INN and INP corresponding to the input voltage of the operational amplifier in common mode between the threshold TH and the voltage of the rail 112, a voltage representing the voltage between the input nodes 102 and 104 is passed to the intermediate stage by transistors 124a and 124b.

[0059] The value of voltage Vref is selected so that transistor 130 turns on when voltages INP and INN reach a value corresponding to the input voltage of the operational amplifier in common mode equal to threshold TH. Value Vref is determined by the value Rref of resistor 136 and the value Iref of current source 138.

[0060] Figure 3 An example of current variation is shown. More specifically, Figure 3 Shown Figure 2 The current (current (A)) in the embodiment of FIG. 1 varies according to the input voltage (voltage (V)) of the operational amplifier 10 in the common mode, and similarly to Figure 2 Devices of the device (with Figure 2 Unlike the embodiment of FIG. 1 , there is no change in the current (Current (A)) in the operational amplifier 144 ) in the device, and the gate of the transistor 130 is coupled, preferably connected, to the node 140 . Figure 3 The first curve 204 is shown in FIG. Figure 2 The second curve 206 shows the change of the current flowing through the transistor 116a in the embodiment of Figure 2 a third curve 200 showing the change in current flowing through transistor 116a in a device that does not include the operational amplifier 144; and a fourth curve 202 showing the change in current flowing through transistor 124a in a device that does not include the operational amplifier 144.

[0061] Consider that in common mode, the current flowing through transistor 116a is substantially equal to the current flowing through transistor 116b, and the current flowing through transistor 124a is substantially equal to the current flowing through transistor 124b. Therefore, changes in the currents flowing through transistors 116a and 124a also correspond to changes in the currents flowing through transistors 116b and 124b.

[0062] Figure 3 Three consecutive phases A1 , A2 and A3 of operation of the device excluding amplifier 144 are shown.

[0063] During the first phase A1, transistors 124a and 124b are turned off and transistors 116a and 116b are turned on. Therefore, the current flowing through transistors 124a and 124b has a first value C1 that is substantially equal to zero. Figure 3 In the example shown, the current flowing through transistors 116a and 116b is substantially equal to value C2. Value C2 is non-zero and preferably substantially constant throughout phase A1. For example, value C2 is substantially equal to -134 μA. Therefore, curves 200 and 202 are substantially constant during phase A1.

[0064] When the common-mode input voltage reaches the threshold TH1, phase A1 ends. Figure 3 In the example shown in FIG. 4 , the value of the threshold TH1 is substantially equal to 3.58 V. When the common-mode input voltage reaches the threshold TH1 , the second phase A2 begins.

[0065] Phase A2 is a transition phase. During phase A2, the current flowing through transistors 116a and 116b changes from value C2 to value C1, and the current flowing through transistors 124a and 124b changes from value C1 to value C2. Therefore, the current flowing through transistors 116a and 116b is substantially equal to C2 at the beginning of the second phase A2 and is substantially equal to C1 at the end of the second phase A2. Similarly, the current flowing through transistors 124a and 124b is substantially equal to C1 at the beginning of the second phase A2 and is substantially equal to C2 at the end of the second phase A2. Figure 3 In the example of FIG. 2 , during phase A2 , curve 200 rises and curve 202 falls.

[0066] During the third phase A3, transistors 124a and 124b are turned on, and transistors 116a and 116b are turned off. Therefore, the current flowing through transistors 116a and 116b has a first value C1 that is substantially equal to zero. Figure 3 In the example of FIG, the current flowing through transistors 124a and 124b is substantially equal to value C2. Therefore, curves 200 and 202 are substantially constant in phase A3.

[0067] Figure 3 Shown Figure 1 and Figure 2 The embodiment of the device 10 has three successive phases of operation B1 , B2 and B3 .

[0068] The curves 204 and 206 vary similarly to the corresponding curves 200 and 202. In other words, during phase B1, the curves 204 and 206 are substantially constant and substantially equal to the corresponding values ​​C2 and C1. Phase B1 ends when the common-mode input voltage reaches the threshold TH2.

[0069] During phase B2, curve 204 changes from a value C2 at the start of phase B2 to a value C1 at the end of phase B2. Similarly, curve 206 changes to transition from a value C1 at the start of phase B2 to a value C2 at the end of phase B2.

[0070] During phase B3 , curves 204 and 206 are substantially constant and substantially equal to respective values ​​C1 and C2 .

[0071] The variation of curves 204 and 206 differs from the variation of curves 200 and 202 in that the fall of curve 206 and the rise of curve 204 are significantly faster, particularly before the intersection of curves 204 and 206. Consequently, transition phase B2 is shorter than transition phase A2. Thus, a value for threshold TH2 can be selected that is greater than the value of threshold TH1, while keeping phase B3 long enough to allow for high values ​​while maintaining substantially constant curves 204 and 206. Value TH2 is between value TH1 and the voltage value of rail 112.

[0072] An advantage of the described embodiment is that the transition window between the P-type transistor and the N-type transistor (in other words, phase B2) of the embodiment is narrower than the transition window (in other words, phase a2) without the operational amplifier 144. This allows the range of voltage values ​​that the operational amplifier 10 can accurately handle to be increased.

[0073] Another advantage of the described embodiment is that, compared to a device without operational amplifier 144, variations between two different devices regarding phase B2, its width, and its value are less significant. In particular, these variations depend only on temperature and process-related dispersion. This allows the value of current source I0 to be reduced, thereby miniaturizing the device.

[0074] Another advantage of the described embodiment is that the value of threshold TH2 is higher than the value TH1. In other words, phase B1 begins at a value lower than the value of B2, and phase A2 is greater than phase A1. Since phases A1 and A2 are the range of values ​​in which operational amplifier 10 has the best accuracy, increasing the lowest value of the transition window in the embodiment allows the accuracy of operational amplifier 10 to be improved.

[0075] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art.

[0076] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. An electronic device comprising: a pair of first transistors, a first one of the pair of first transistors having a control terminal coupled to the non-inverting input, a second one of the pair of first transistors having a control terminal coupled to the inverting input, and a source terminal of each of the pair of first transistors coupled to a current source via a first node; a pair of second transistors, a first one of the pair of second transistors having a control terminal coupled to the non-inverting input, a second one of the pair of second transistors having a control terminal coupled to the inverting input, and a source terminal of each of the pair of second transistors coupled to a second node; an operational amplifier having a first input coupled to a reference voltage and a second input coupled to the first node; as well as A third transistor has a source terminal coupled to the first node and a control terminal coupled to the output of the operational amplifier.

2. The electronic device of claim 1, wherein the device is an operational amplifier device. 3 . The electronic device of claim 1 , wherein the third transistor is coupled to the second node through a current mirror. 4 . The electronic device of claim 1 , wherein the second node is coupled to a second power supply input through a conduction terminal of a fourth transistor.

5. The electronic device of claim 4 , wherein a conductive terminal of the third transistor is coupled to a first conductive terminal of a fifth transistor, a second conductive terminal of the fifth transistor is coupled to the second power supply input, and a control terminal of the fifth transistor is coupled to the first conductive terminal of the fifth transistor and to the control terminal of the fourth transistor. 6 . The electronic device according to claim 1 , wherein a surface area of ​​the third transistor is at least smaller than one fifth of a surface area of ​​the first transistor and the second transistor.

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