A rail-to-rail amplifier circuit

Abstract

The application provides a rail-to-rail amplifier circuit, comprising: a detection unit configured to generate a feedback control voltage based on respective voltages of a first driving signal and a second driving signal in response to a power supply voltage, a substrate potential generation unit configured to generate a first potential signal and a second potential signal according to the feedback control voltage and a preset voltage, and an amplification unit having a first differential module, a second differential module and an amplification module, wherein the first differential module is configured to output a first differential signal according to the first driving signal, the second driving signal and the first potential signal, the second differential module is configured to output a second differential signal according to the first driving signal, the second driving signal and the second potential signal, and the amplification module is configured to amplify the first differential signal or the second differential signal. The above technical scheme can ensure the flatness of the gain in the entire input voltage range.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a rail-to-rail amplifier circuit. BACKGROUND

[0002] Rail-to-rail operational amplifier can process signals in the entire power supply voltage range, which is crucial in low-voltage, single power supply system.

[0003] However, the input stage or output stage of the rail-to-rail amplifier often causes significant changes in open-loop gain when switching the operating area under different common-mode input voltages or load conditions. This non-constant gain introduces non-linear errors, which seriously affect the signal amplification accuracy. Therefore, achieving constant high gain throughout the input / output range is a core challenge and key requirement for high-performance rail-to-rail amplifier design. SUMMARY

[0004] Therefore, the present application provides a rail-to-rail amplifier circuit, which can ensure the flatness of the gain throughout the input voltage range and improve the linearity and accuracy of the device using the rail-to-rail amplifier circuit.

[0005] The present application provides a rail-to-rail amplifier circuit, comprising:

[0006] The detection unit is configured to generate a feedback control voltage based on the respective voltages of the first drive signal and the second drive signal when selected in response to the power supply voltage, the first drive signal and the second drive signal.

[0007] The substrate potential generation unit is coupled to the detection unit and is configured to generate a first potential signal and a second potential signal according to the feedback control voltage and a preset voltage, wherein the preset voltage is determined by the power supply voltage.

[0008] The amplification unit is coupled to the substrate potential generation unit and has a first differential module, a second differential module and an amplification module. The first differential module is configured to output a first differential signal to the amplification module according to the first drive signal, the second drive signal and the first potential signal. The second differential module is configured to output a second differential signal to the amplification module according to the first drive signal, the second drive signal and the second potential signal. The amplification module is configured to generate an amplified signal and output the amplified signal based on the first differential signal or the second differential signal.

[0009] Optionally, the detection unit comprises: a common-mode input module, a first input end of the common-mode input module inputs the first drive signal, a second input end of the common-mode input module inputs the second drive signal, and a differential current signal is generated when being selected;

[0010] a mirror module, coupled with the common-mode input module and inputting the power voltage and a first bias voltage, configured to mirror process the differential current signal;

[0011] a conversion module, coupled with the mirror module and the common-mode input module respectively, configured to convert the type of the differential current signal to generate the feedback control voltage;

[0012] a tail current source providing module, coupled with the common-mode input module, configured to provide a tail current corresponding to a second bias voltage to the common-mode input module.

[0013] Optionally, the detection unit satisfies one or more of the following:

[0014] the common-mode input module comprises: a first transistor and a second transistor, a control end of the first transistor inputs the first drive signal, a first end of the first transistor is coupled with the mirror module and the conversion module respectively, a second end of the first transistor is coupled with the tail current source providing module, a third end of the first transistor is coupled with a third end of the second transistor and grounded; a control end of the second transistor inputs the second drive signal, a first end of the second transistor is coupled with the mirror module and the conversion module respectively, a second end of the second transistor is coupled with the tail current source providing module;

[0015] the mirror module comprises a third transistor and a fourth transistor, a control end of the third transistor is coupled with a control end of the fourth transistor and inputs the first bias voltage, a first end and a third end of the third transistor are coupled with a first end and a third end of the fourth transistor and input the power voltage, a second end of the third transistor is coupled with the common-mode input module and the conversion module respectively; a second end of the fourth transistor is coupled with the common-mode input module and the conversion module respectively;

[0016] the conversion module comprises a first resistor and a second resistor, a first end of the first resistor is coupled with the mirror module and the common-mode input module respectively, a second end of the first resistor and a second end of the second resistor are coupled and serve as an output end; a first end of the second resistor is coupled with the mirror module and the common-mode input module respectively;

[0017] The tail current source providing module comprises a fifth transistor, a control end of the fifth transistor inputs the second bias voltage, a first end of the fifth transistor is coupled with the common-mode input module, a second end and a third end of the fifth transistor are coupled and grounded.

[0018] Optionally, the substrate potential generating unit comprises:

[0019] The first comparison module is coupled with the detection unit and the first differential module respectively, and is configured to generate the first potential signal according to the feedback control voltage and a first preset voltage determined by the power supply voltage.

[0020] The second comparison module is coupled with the detection unit and the second differential module respectively, and is configured to generate the second potential signal according to the feedback control voltage and a second preset voltage determined by the power supply voltage.

[0021] The first preset voltage and the second preset voltage are the same and are the preset voltage.

[0022] Optionally, the first comparison module comprises a first voltage division branch composed of a third resistor and a fourth resistor, and a first comparator, a first end of the third resistor inputs the power supply voltage, a second end of the third resistor and a first end of the fourth resistor and a first input end of the first comparator are coupled respectively, a second end of the fourth resistor is grounded, a second input end of the first comparator inputs the feedback control voltage, an output end of the first comparator outputs the first potential signal, and the third resistor and the fourth resistor have the same resistance value.

[0023] The second comparison module comprises a second voltage division branch composed of a fifth resistor and a sixth resistor, and a second comparator, a first end of the fifth resistor inputs the power supply voltage, a second end of the fifth resistor and a first end of the sixth resistor and a first input end of the second comparator are coupled respectively, a second end of the sixth resistor is grounded, a second input end of the second comparator inputs the feedback control voltage, and an output end of the second comparator outputs the second potential signal, and the fifth resistor and the sixth resistor have the same resistance value.

[0024] Optionally, the first differential module and the second differential module adopt transistors of different types, and the first differential module and the second differential module are turned on at different times within the working range of the amplification unit.

[0025] Optionally, the first differential module comprises a sixth transistor, a seventh transistor and an eighth transistor, a control terminal of the sixth transistor inputs the first driving signal, a first terminal of the sixth transistor is coupled with the amplification unit, a second terminal of the sixth transistor is coupled with a second terminal of the seventh transistor and a first terminal of the eighth transistor respectively, a third terminal of the sixth transistor is coupled with a third terminal of the seventh transistor and inputs the first potential signal; a control terminal of the seventh transistor inputs the second driving signal, a first terminal of the seventh transistor is coupled with the amplification unit; an input terminal of the eighth transistor inputs the third bias voltage, a second terminal of the eighth transistor is coupled with the third terminal and grounded.

[0026] The second differential module comprises a ninth transistor, a tenth transistor and an eleventh transistor, a control terminal of the ninth transistor inputs the second driving signal, a first terminal of the ninth transistor is coupled with a second terminal of the eleventh transistor and a first terminal of the tenth transistor respectively, a second terminal of the ninth transistor is coupled with the amplification unit, a third terminal of the ninth transistor is coupled with a third terminal of the tenth transistor and inputs the second potential signal; a control terminal of the tenth transistor inputs the first driving signal, a second terminal of the tenth transistor is coupled with the amplification unit; a control terminal of the eleventh transistor inputs the fourth bias voltage, a first terminal and a third terminal of the eleventh transistor are coupled and input the power supply voltage.

[0027] Optionally, the sixth transistor, the seventh transistor and the eighth transistor are one of PMOS transistors and NMOS transistors, and the ninth transistor, the tenth transistor and the eleventh transistor are the other of PMOS transistors and NMOS transistors.

[0028] Optionally, the amplification module comprises:

[0029] a first amplification branch coupled with the first differential module and configured to amplify the first differential signal to generate the amplification signal when the first differential module is selected;

[0030] a second amplification branch coupled with the second differential module and configured to amplify the second differential signal to generate the amplification signal when the second differential module is selected; wherein the second amplification branch and the first amplification branch share an output node.

[0031] Optionally, the first amplification branch comprises a first common-source common-gate structure circuit composed of a twelfth transistor and a thirteenth transistor, a second common-source common-gate structure circuit composed of a fourteenth transistor and a fifteenth transistor, control ends of the twelfth transistor and the thirteenth transistor are coupled and input a fifth bias voltage, first ends and third ends of the twelfth transistor and the thirteenth transistor are coupled and coupled with third ends of the fourteenth transistor and the fifteenth transistor, a second end of the twelfth transistor is coupled with a first end of the fourteenth transistor and an output end of the first differential module, a second end of the thirteenth transistor is coupled with a first end of the fifteenth transistor and the output end of the first differential module, control ends of the fourteenth transistor and the fifteenth transistor are coupled and input a sixth bias voltage, a second end of the fourteenth transistor is coupled with the second amplification branch, and a second end of the fifteenth transistor serves as the output node.

[0032] The second amplification branch comprises a third common-source common-gate structure circuit composed of a sixteenth transistor and a seventeenth transistor, a fourth common-source common-gate structure circuit composed of an eighteenth transistor and a nineteenth transistor, control ends of the sixteenth transistor and the seventeenth transistor are coupled and input a seventh bias voltage, a first end of the sixteenth transistor is coupled with the first amplification branch, control ends of the eighteenth transistor and the nineteenth transistor, a second end of the sixteenth transistor is coupled with a first end of the eighteenth transistor and an output end of the second differential module, and is coupled with third ends of the eighteenth transistor, the nineteenth transistor and the seventeenth transistor, and second ends of the eighteenth transistor and the nineteenth transistor, and is grounded, a first end of the seventeenth transistor serves as the output node, and a second end of the seventeenth transistor is coupled with a first end of the nineteenth transistor and the output end of the second differential module.

[0033] Compared with the prior art, the technical scheme of the embodiment of the application has the following advantages:

[0034] The rail-to-rail amplifier circuit provided by the embodiment of the application can generate a feedback control voltage to the substrate potential generating unit in real time in response to the respective voltages of the first drive signal and the second drive signal. In this way, the substrate potential generating unit can adjust the potentials of the first potential signal and the second potential signal in real time. The first differential module and the second differential module are based on the first drive signal, the second drive signal, the first potential signal and the second potential signal, so that the first potential signal and the second potential signal can act on the amplification process. This feedback mechanism can ensure the flatness of the gain in the entire input voltage range and improve the linearity and accuracy of the device applied to the rail-to-rail amplifier circuit. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the description of the embodiments or the prior art. Obviously, the drawings in the following description only illustrate the embodiments of the present application, and for those skilled in the field, other drawings can be obtained based on the provided drawings without any creative effort.

[0036] Figure 1 A structure diagram of a rail-to-rail amplifier is shown;

[0037] Figure 2 A gain diagram of a rail-to-rail amplifier is shown;

[0038] Figure 3 A structure diagram of a rail-to-rail amplifier circuit in an embodiment of the present application is shown;

[0039] Figure 4 A structure diagram of a detection unit in an embodiment of the present application is shown;

[0040] Figure 5 A structure diagram of a substrate potential generation unit in an embodiment of the present application is shown;

[0041] Figure 6 A change diagram of an output signal of a substrate potential generation unit in an embodiment of the present application is shown;

[0042] Figure 7 A specific structure diagram of an amplification unit in an embodiment of the present application is shown;

[0043] Figure 8 A gain diagram of a rail-to-rail amplifier circuit in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0044] Various embodiments of the present application will be described in detail with reference to the drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, each part in the drawings is not drawn to scale.

[0045] It should be understood that, in the following description, "circuitry" can include a single or multiple combinations of hardware circuitry, programmable circuitry, state machine circuitry, and / or elements that can store instructions for execution by the programmable circuitry. When an element or circuitry is referred to as being "connected to" another element or "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements between the elements, and the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that the two are connected without any intervening elements.

[0046] In the present application, the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first end, a second end and a control end, in the on state of the MOSFET, current flows from the first end to the second end. The first current end, the second current end and the control end of the P-type MOSFET are the source, the drain and the gate respectively, and the third end is the substrate. The first current end, the second current end and the control end of the N-type MOSFET are the drain, the source and the gate respectively, and the third end is the substrate.

[0047] As described in the background, the gain of the existing rail-to-rail amplifier has non-constancy, which introduces nonlinear error and seriously affects the signal amplification accuracy.

[0048] Referring to Figure 1 , a structure diagram of a rail-to-rail amplifier is shown, as Figure 1 , as Figure 1 , the rail-to-rail amplifier in the existing scheme is based on the traditional PMOS input pair (i.e. PMOS transistors PM1, PM2 and PM3), and additionally adds an NMOS input pair (i.e. NMOS transistors NM1, NM2 and NM3). Among them, the PMOS input pair controls two groups of common-gate common-source circuits composed of NMOS transistors NM4, NM5, NM6 and NM7, and the NMOS input pair controls two groups of common-gate common-source circuits composed of PMOS transistors M4, M5, M6 and M7, to realize time-sharing output of the amplification voltage Vout.

[0049] However, referring to Figure 2 , a gain diagram of a rail-to-rail amplifier is shown, as Figure 2 , due to the overlapping of the gain (for example, the gain gmn of the NMOS transistor and the gain gmp of the PMOS transistor) of the amplification region of the NMOS transistor and the PMOS transistor near VDD / 2, the gain of the amplifier is not flat.

[0050] To solve the above technical problems, the present application provides a rail-to-rail amplifier circuit, a detection unit can generate a feedback control voltage to a substrate potential generating unit in real time in response to the respective voltages of the first driving signal and the second driving signal. In this way, the substrate potential generating unit can adjust the potential of the first potential signal and the second potential signal in real time. And the first differential module and the second differential module are based on the first driving signal, the second driving signal, the first potential signal and the second potential signal, so that the first potential signal and the second potential signal can act on the amplification process. This feedback mechanism can ensure the flatness of the gain in the entire input voltage range, and improve the linearity and accuracy of the device applied to the rail-to-rail amplifier circuit.

[0051] For those skilled in the art to better understand and implement the present disclosure, the following refers to the drawings, and the specific schemes of the present application are described in detail through specific examples, principles, advantages and effects, etc.

[0052] Referring to Figure 3 The structure diagram of a rail-to-rail amplifier circuit in an embodiment of the present application is shown in FIG. 1. Figure 3 As shown in FIG. 1, the rail-to-rail amplifier circuit can include:

[0053] The detection unit 110 is configured to, in response to the power supply voltage VDD, the first driving signal Vp and the second driving signal Vn, generate a feedback control voltage Vc based on the respective voltages of the first driving signal Vp and the second driving signal Vn when being gated.

[0054] The substrate potential generation unit 120 is coupled with the detection unit 110 and is configured to generate a first potential signal S1 and a second potential signal S2 according to the feedback control voltage Vc and a preset voltage Vth, wherein the preset voltage Vth is determined by the power supply voltage VDD.

[0055] The amplification unit 130 is coupled with the substrate potential generation unit 120 and has a first differential module 131, a second differential module 132 and an amplification module 133. The first differential module 131 is configured to output a first differential signal to the amplification module 133 according to the first driving signal Vp, the second driving signal Vn and the first potential signal S1. The second differential module 132 is configured to output a second differential signal to the amplification module according to the first driving signal Vp, the second driving signal Vn and the second potential signal S2. The amplification module 133 is configured to generate an amplification signal Vout and output it by amplifying the first differential signal or the second differential signal.

[0056] In combination with Figure 3 , the working principle of the rail-to-rail amplifier circuit in this scheme is briefly described as follows:

[0057] The detection unit 110 can generate a feedback control voltage Vc to the substrate potential generation unit 120 in real time in response to the respective voltages of the first driving signal Vp and the second driving signal Vn.

[0058] The substrate potential generation unit 120 can adjust the potentials of the first potential signal S1 and the second potential signal S2 in real time. The first differential module 131 is gated based on the first driving signal Vp, the second driving signal Vn, and the first potential signal S1, and the second differential module 132 is gated based on the first driving signal Vp, the second driving signal Vn, and the second potential signal S2, so that the first potential signal S1 and the second potential signal S2 can act on the amplification process in time division.

[0059] In this way, when the first differential module 131 is gated, the amplification module 133 can amplify the first differential signal; and when the second differential module 132 is gated, the amplification module 133 can amplify the second differential signal to generate and output the amplification signal Vout.

[0060] In this way, through the feedback adjustment mechanism, the flatness of the gain in the entire input voltage range can be ensured, and the linearity and accuracy of the device applied to the rail-to-rail amplifier circuit are improved.

[0061] In some embodiments, in combination Figure 3 , see Figure 4 The structure of a detection unit in an embodiment of the application is shown in FIG. 11. As shown in FIG. 11, the detection unit 110 can include: Figure 4

[0062] The common-mode input module 111 inputs the first driving signal Vp at a first input end and inputs the second driving signal Vn at a second input end, and generates a differential current signal when gated;

[0063] The mirror module 112 is coupled to the common-mode input module 111 and inputs the power supply voltage VDD and the first bias voltage V bias11 , and is configured to mirror process the differential current signal;

[0064] The conversion module 113 is coupled to the mirror module 112 and the common-mode input module 111, respectively, and is configured to convert the type of the differential current signal to generate the feedback control voltage Vc;

[0065] The tail current source providing module 114 is coupled to the common-mode input module 111 and is configured to provide a tail current corresponding to the second bias voltage V bias12 to the common-mode input module.

[0066] In some embodiments, the detection unit 110 can determine the feedback control voltage Vc through the input first driving signal Vp and the second driving signal Vn.

[0067] ​The feedback control voltage Vc can be half of the sum of the voltages corresponding to the first driving signal Vp and the second driving signal Vn.

[0068] In some embodiments, the detection unit 110 can satisfy one or more of the following:

[0069] The common-mode input module 111 includes a first transistor NM11 and a second transistor NM12. The control end of the first transistor NM11 inputs the first driving signal Vp. The first end of the first transistor NM11 is coupled with the mirror module 112 and the conversion module 113, respectively. The second end of the first transistor NM11 is coupled with the tail current source providing module 114. The third end of the first transistor NM11 is coupled with the third end of the second transistor NM12 and grounded. The control end of the second transistor NM12 inputs the second driving signal Vn. The first end of the second transistor NM12 is coupled with the mirror module 112 and the conversion module 113, respectively. The second end of the second transistor NM12 is coupled with the tail current source providing module 114.

[0070] In other words, the first transistor NM11 and the second transistor NM12 act as differential input tubes.

[0071] The mirror module 112 can include a third transistor PM11 and a fourth transistor PM12. The control end of the third transistor PM11 is coupled with the control end of the fourth transistor PM12 and grounded. The first end and the third end of the third transistor PM11 are coupled with the first end and the third end of the fourth transistor PM12 and grounded. The second end of the third transistor PM11 is coupled with the common-mode input module 111 and the conversion module 113, respectively. bias11 The second end of the fourth transistor PM14 is coupled with the common-mode input module 111 and the conversion module 113, respectively.

[0072] In other words, the third transistor PM11 and the fourth transistor PM12 act as mirror current.

[0073] The conversion module 113 can include a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is coupled with the mirror module 112 and the common-mode input module 111, respectively. The second end of the first resistor R1 and the second end of the second resistor R2 are coupled and serve as an output end. The first end of the second resistor R2 is coupled with the mirror module 112 and the common-mode input module 111, respectively.

[0074] In other words, the first resistor R1 and the second resistor R2 can convert the mirror current into the feedback control voltage Vc.

[0075] In some embodiments, the resistance values ​​of the first resistor R1 and the second resistor R2 can be the same.

[0076] The tail current source providing module 114 may include a fifth transistor NM13, the control terminal of which receives the second bias voltage V. bias12 The first terminal of the fifth transistor NM13 is coupled to the common-mode input module 111, and the second and third terminals of the fifth transistor NM13 are coupled and grounded.

[0077] The differential pair total current provided by the fifth transistor NM13 enables the first transistor NM11 and the second transistor NM112 to operate at the quiescent operating point.

[0078] In some embodiments, combined with Figure 3 See Figure 5 The diagram shown is a structural schematic of a substrate potential generation unit in an embodiment of the present invention. Figure 5 As shown, the substrate potential generation unit 120 may include:

[0079] The first comparison module 121 is coupled to the detection unit 110 and the first differential module 131 respectively, and is configured to generate the first potential signal S1 according to the feedback control voltage Vc and the first preset voltage Vth1, wherein the first preset voltage Vth1 is determined by the power supply voltage VDD.

[0080] The second comparison module 122 is coupled to the detection unit 110 and the second differential module 132 respectively, and is configured to generate the second potential signal S2 according to the feedback control voltage Vc and the second preset voltage Vth2, wherein the second preset voltage Vth2 is determined by the power supply voltage VDD.

[0081] In other words, by setting up a substrate potential generation unit 120 with a first comparison module 121 and a second comparison module 122, a first potential signal S1 and a second potential signal S2 can be output respectively to drive the amplification unit 130 in a time-division manner.

[0082] In some embodiments, the first preset voltage Vth1 and the second preset voltage Vth2 are the same, and are the preset voltage.

[0083] In some embodiments, the first comparison module 121 can include: a first voltage division branch composed of a third resistor R3 and a fourth resistor R4, a first end of the third resistor R3 inputting the power supply voltage VDD, a second end of the third resistor R3 and a first end of the fourth resistor R4 being coupled with a first input end of the first comparator 1211 respectively; a second end of the fourth resistor R4 being grounded; a second input end of the first comparator 1211 inputting the feedback control voltage Vc, and an output end of the first comparator outputting the first potential signal S1.

[0084] Wherein, the third resistor R3 and the fourth resistor R4 have the same resistance value, i.e. Vth1 = 0.5VDD.

[0085] The second comparison module 122 can include: a second voltage division branch composed of a fifth resistor R5 and a sixth resistor R6, a first end of the fifth resistor R5 inputting the power supply voltage VDD, a second end of the fifth resistor R5 and a first end of the sixth resistor R6 being coupled with a first input end of the second comparator 1221 respectively; a second end of the sixth resistor R6 being grounded; a second input end of the second comparator 1221 inputting the feedback control voltage Vc, and an output end of the second comparator 1221 outputting the second potential signal S2.

[0086] Wherein, the fifth resistor R5 and the sixth resistor R6 have the same resistance value, i.e. Vth2 = 0.5VDD.

[0087] Further, referring to Figure 6 the output signal change diagram of the substrate potential generation unit in the embodiment of the application, as shown in Figure 6 When the amplitude of the feedback control voltage Vc is low, the feedback control voltage Vc is less than the first preset voltage Vth1, and the amplitude of the first potential signal S1 output by the substrate potential generation unit is high, which will result in the decrease of the gm of the NMOS tube in the first differential module 131; when the feedback control voltage Vc is greater than the first preset voltage Vth1, the amplitude of the first potential signal S1 decreases slowly.

[0088] When the amplitude of the feedback control voltage Vc is low, the feedback control voltage Vc is less than the second preset voltage Vth2, and the amplitude of the second potential signal S2 output by the substrate potential generation unit is high, which will result in the decrease of the gm of the PMOS tube in the second differential module 132; when the feedback control voltage Vc is greater than the second preset voltage Vth2, the amplitude of the second potential signal S1 decreases rapidly.

[0089] In some embodiments, the first differential module 131 and the second differential module 132 employ transistors of different types, and within the operating range of the amplification unit 130, the first differential module 131 and the second differential module 132 are turned on in a time-division manner.

[0090] Specifically, the first differential module 131 is composed of NMOS transistors and the second differential module 131 is composed of PMOS transistors; or, the first differential module 131 is composed of PMOS transistors and the second differential module 131 is composed of NMOS transistors.

[0091] In some embodiments, combined with Figure 3 See Figure 7 The schematic diagram shown in this embodiment of the invention illustrates the specific structure of an amplification unit, as follows: Figure 7 As shown, the first differential module 131 may include:

[0092] The sixth transistor NM14, the seventh transistor NM15, and the eighth transistor NM16 are connected. The control terminal of the sixth transistor NM14 receives the first drive signal Vp. The first terminal of the sixth transistor NM14 is coupled to the amplification module 133. The second terminal of the sixth transistor NM14 is coupled to the second terminal of the seventh transistor NM15 and the first terminal of the eighth transistor NM16, respectively. The third terminal of the sixth transistor NM14 is coupled to the third terminal of the seventh transistor NM15 and connected to the first potential signal S1. The control terminal of the seventh transistor NM15 receives the second drive signal Vn. The first terminal of the seventh transistor NM15 is coupled to the amplification module 133. The input terminal of the eighth transistor NM16 receives the third bias voltage V. bias13 The second terminal of the eighth transistor NM16 is coupled to the third terminal and grounded.

[0093] The second differential module 132 may include: a ninth transistor PM13, a tenth transistor PM14, and an eleventh transistor PM15. The control terminal of the ninth transistor PM13 receives the second drive signal Vn. The first terminal of the ninth transistor PM13 is coupled to the second terminal of the eleventh transistor PM15 and the first terminal of the tenth transistor PM14, respectively. The second terminal of the ninth transistor PM13 is coupled to the amplification module 133, and the third terminal of the ninth transistor PM13 is coupled to the third terminal of the tenth transistor PM14, and receives the second potential signal S2. The control terminal of the tenth transistor PM14 receives the first drive signal Vp, and the second terminal of the tenth transistor PM14 is coupled to the amplification module 133. The control terminal of the eleventh transistor PM14 receives a fourth bias voltage V. bias14The first end and the third end of the eleventh transistor PM15 are coupled, and the power supply voltage VDD is input.

[0094] In some embodiments, the sixth transistor NM14, the seventh transistor NM15 and the eighth transistor NM16 are one of PMOS transistors and NMOS transistors, and the ninth transistor PM13, the tenth transistor PM14 and the eleventh transistor PM15 are the other one of PMOS transistors and NMOS transistors.

[0095] In the present application, the sixth transistor NM14, the seventh transistor NM15 and the eighth transistor NM16 are NMOS transistors, and the ninth transistor PM13, the tenth transistor PM14 and the eleventh transistor PM15 are NMOS transistors.

[0096] Next, referring to Figure 7 The amplification module 133 can include: a first amplification branch (not identified) coupled with the first differential module 131 and configured to perform amplification processing on the first differential signal to generate the amplified signal Vout when the first differential module 131 is gated; Figure 7 The first amplification branch and the second amplification branch share an output node.

[0097] A second amplification branch (not identified) coupled with the second differential module 132 and configured to perform amplification processing on the second differential signal to generate the amplified signal Vout when the second differential module 132 is gated. Figure 7 The first amplification branch and the second amplification branch share an output node.

[0098] In some embodiments, the first amplification branch includes a first common-source common-gate structure circuit composed of a twelfth transistor PM16 and a thirteenth transistor PM17, and a second common-source common-gate structure circuit composed of a fourteenth transistor PM18 and a fifteenth transistor PM19. bias15 The first end and the third end of the twelfth transistor PM16, the thirteenth transistor PM17 and the third end of the fourteenth transistor PM18 and the fifteenth transistor PM19 are coupled, and the second end of the twelfth transistor PM16 and the first end of the fourteenth transistor PM18 and the output end of the first differential module 131 are coupled. The second end of the thirteenth transistor PM17 and the first end of the fifteenth transistor PM19 and the output end of the first differential module 131 are respectively coupled. The control ends of the fourteenth transistor PM18 and the fifteenth transistor PM19 are coupled, and a sixth bias voltage Vbias6 is input. bias16The second terminal of the fourteenth transistor PM18 is coupled to the second amplification branch; the second terminal of the fifteenth transistor PM19 serves as the output node.

[0099] The second amplification branch includes a third cascode structure circuit composed of the sixteenth transistor NM17 and the seventeenth transistor NM18, and a fourth cascode structure circuit composed of the eighteenth transistor NM19 and the nineteenth transistor NM20. The control terminals of the sixteenth transistor NM17 and the seventeenth transistor NM18 are coupled together and input with a seventh bias voltage V. bias17 The first terminals of the sixteenth transistor NM17 and the seventeenth transistor NM18 are respectively coupled to the control terminals of the first amplification branch, the eighteenth transistor NM19, and the nineteenth transistor NM20. The second terminal of the sixteenth transistor NM17 is respectively coupled to the first terminal of the eighteenth transistor NM19 and the output terminal of the second differential module 132. The third terminals of the sixteenth transistor NM17, the eighteenth transistor NM19, the nineteenth transistor NM20, and the seventeenth transistor NM18, as well as the second terminals of the eighteenth transistor NM19 and the nineteenth transistor NM20, are respectively coupled and grounded. The first terminal of the seventeenth transistor NM18 serves as an output node, and the second terminal of the seventeenth transistor NM18 is respectively coupled to the first terminal of the nineteenth transistor NM20 and the output terminal of the second differential module 132.

[0100] Therefore, by using the rail-to-rail amplifier circuit in the above example, it is possible to ensure flat gain across the entire input voltage range, thereby improving the linearity and accuracy of devices applied to this rail-to-rail amplifier circuit.

[0101] For example, see Figure 8 The diagram shown is a gain schematic of a rail-to-rail amplifier circuit in an embodiment of the present invention. Figure 8 As shown, the amplifier gain is flatter because the gain of the NMOS transistor and the PMOS transistor overlaps less near VDD / 2 (e.g., the gain gmn of the NMOS transistor and the gain gmp of the PMOS transistor).

[0102] It is understood that the above description provides multiple embodiment solutions, and the optional methods described in each embodiment solution can be combined with each other and cross-referenced without conflict, thereby extending to a variety of possible embodiment solutions, all of which can be considered as the embodiment solutions disclosed in this disclosure.

[0103] Although the present disclosure discloses the above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be limited by the scope defined by the claims.

Claims

1. A rail-to-rail amplifier circuit, characterized by, The application relates to a substrate potential generation unit, an amplification unit and a detection unit. The detection unit is configured to generate a feedback control voltage based on the respective voltage of the first driving signal and the second driving signal when being selected, in response to a power supply voltage, the first driving signal and the second driving signal; The substrate potential generation unit is coupled with the detection unit and is configured to generate a first potential signal and a second potential signal according to the feedback control voltage and a preset voltage, wherein the preset voltage is determined by the power supply voltage; the substrate potential generation unit comprises a first comparison module and a second comparison module, wherein the first comparison module is coupled with the detection unit and a first differential module respectively and is configured to generate the first potential signal according to the feedback control voltage and a first preset voltage, the first preset voltage is determined by the power supply voltage; the second comparison module is coupled with the detection unit and a second differential module respectively and is configured to generate the second potential signal according to the feedback control voltage and a second preset voltage, the second preset voltage is determined by the power supply voltage; wherein the amplitude variation range of the first potential signal and the second potential signal is different. The amplification unit is coupled with the substrate potential generation unit and comprises a first differential module, a second differential module and an amplification module, wherein the first differential module is configured to output a first differential signal to the amplification module according to the first driving signal, the second driving signal and the first potential signal; the second differential module is configured to output a second differential signal to the amplification module according to the first driving signal, the second driving signal and the second potential signal; the amplification module is configured to generate an amplification signal and output the amplification signal according to the first differential signal or the second differential signal; the first differential module and the second differential module adopt different types of transistors, and the first differential module and the second differential module are turned on at different times within the working range of the amplification unit.

2. The rail-to-rail amplifier circuit of claim 1, wherein, The detection unit comprises: A common-mode input module, wherein a first input end of the common-mode input module inputs the first driving signal, a second input end of the common-mode input module inputs the second driving signal, and a differential current signal is generated when being selected; A mirror module is coupled with the common-mode input module and inputs the power supply voltage and a first bias voltage and is configured to mirror process the differential current signal; A conversion module is coupled with the mirror module and the common-mode input module respectively and is configured to convert the type of the differential current signal to generate the feedback control voltage; A tail current source providing module is coupled with the common-mode input module and is configured to provide a tail current corresponding to a second bias voltage to the common-mode input module.

3. The rail-to-rail amplifier circuit of claim 2, wherein, The detection unit satisfies one or more of the following conditions: The common-mode input module comprises a first transistor and a second transistor, a control end of the first transistor inputs the first drive signal, a first end of the first transistor is coupled with the mirror module and the conversion module respectively, a second end of the first transistor is coupled with the tail current source providing module, a third end of the first transistor is coupled with a third end of the second transistor and grounded, a control end of the second transistor inputs the second drive signal, a first end of the second transistor is coupled with the mirror module and the conversion module respectively, a second end of the second transistor is coupled with the tail current source providing module; The mirror module comprises a third transistor and a fourth transistor, a control end of the third transistor is coupled with a control end of the fourth transistor and inputs the first bias voltage, a first end and a third end of the third transistor are coupled with a first end and a third end of the fourth transistor and input the power supply voltage, a second end of the third transistor is coupled with the common-mode input module and the conversion module respectively; a second end of the fourth transistor is coupled with the common-mode input module and the conversion module respectively; The conversion module comprises a first resistor and a second resistor, a first end of the first resistor is coupled with the mirror module and the common-mode input module respectively, a second end of the first resistor and a second end of the second resistor are coupled and serve as an output end; a first end of the second resistor is coupled with the mirror module and the common-mode input module respectively; The tail current source providing module comprises a fifth transistor, a control end of the fifth transistor inputs the second bias voltage, a first end of the fifth transistor is coupled with the common-mode input module, a second end and a third end of the fifth transistor are coupled and grounded.

4. The rail-to-rail amplifier circuit according to claim 1, wherein the first preset voltage and the second preset voltage are the same and are the preset voltage. The first comparison module comprises a first voltage division branch composed of a third resistor and a fourth resistor and a first comparator, a first end of the third resistor inputs the power supply voltage, a second end of the third resistor and a first end of the fourth resistor and a first input end of the first comparator are coupled respectively; a second end of the fourth resistor is grounded; a second input end of the first comparator inputs the feedback control voltage, an output end of the first comparator outputs the first potential signal; the third resistor and the fourth resistor have the same resistance value; 5. The rail-to-rail amplifier circuit of claim 1, wherein, The second comparison module comprises a second voltage division branch composed of a fifth resistor and a sixth resistor and a second comparator, a first end of the fifth resistor inputs the power supply voltage, a second end of the fifth resistor and a first end of the sixth resistor and a first input end of the second comparator are coupled respectively; a second end of the sixth resistor is grounded; a second input end of the second comparator inputs the feedback control voltage, an output end of the second comparator outputs the second potential signal; the fifth resistor and the sixth resistor have the same resistance value. ​ 6. The rail-to-rail amplifier circuit of claim 1, wherein, The first differential module comprises a sixth transistor, a seventh transistor and an eighth transistor, the control end of the sixth transistor inputs the first drive signal, the first end of the sixth transistor is coupled with the amplification unit, the second end of the sixth transistor is coupled with the second end of the seventh transistor and the first end of the eighth transistor respectively, the third end of the sixth transistor is coupled with the third end of the seventh transistor and is connected to the first potential signal; the control end of the seventh transistor inputs the second drive signal, the first end of the seventh transistor is coupled with the amplification unit; the input end of the eighth transistor inputs a third bias voltage, the second end of the eighth transistor is coupled with the third end and is grounded. The second differential module comprises a ninth transistor, a tenth transistor and an eleventh transistor, the control end of the ninth transistor inputs the second drive signal, the first end of the ninth transistor is coupled with the second end of the eleventh transistor and the first end of the tenth transistor respectively, the second end of the ninth transistor is coupled with the amplification unit, the third end of the ninth transistor is coupled with the third end of the tenth transistor and inputs the second potential signal; the control end of the tenth transistor inputs the first drive signal, the second end of the tenth transistor is coupled with the amplification unit; the control end of the eleventh transistor inputs a fourth bias voltage, the first end and the third end of the eleventh transistor are coupled and input the power supply voltage.

7. The rail-to-rail amplifier circuit of claim 6, wherein, The sixth transistor, the seventh transistor and the eighth transistor are one of PMOS transistors and NMOS transistors, and the ninth transistor, the tenth transistor and the eleventh transistor are the other of PMOS transistors and NMOS transistors.

8. The rail-to-rail amplifier circuit of claim 1, wherein, The amplification module comprises: a first amplification branch coupled with the first differential module and configured to amplify the first differential signal to generate the amplification signal when the first differential module is selected; a second amplification branch coupled with the second differential module and configured to amplify the second differential signal to generate the amplification signal when the second differential module is selected; wherein the second amplification branch and the first amplification branch share an output node.

9. The rail-to-rail amplifier circuit of claim 8, wherein, The first amplification branch comprises a first common-source common-gate structure circuit composed of a twelfth transistor and a thirteenth transistor, and a second common-source common-gate structure circuit composed of a fourteenth transistor and a fifteenth transistor, control ends of the twelfth transistor and the thirteenth transistor are coupled and input a fifth bias voltage, first ends and third ends of the twelfth transistor and the thirteenth transistor are coupled and coupled with third ends of the fourteenth transistor and the fifteenth transistor, a second end of the twelfth transistor is coupled with a first end of the fourteenth transistor and an output end of the first differential module; a second end of the thirteenth transistor is coupled with a first end of the fifteenth transistor and the output end of the first differential module respectively; control ends of the fourteenth transistor and the fifteenth transistor are coupled and input a sixth bias voltage; a second end of the fourteenth transistor is coupled with the second amplification branch; and a second end of the fifteenth transistor serves as the output node; The second amplification branch comprises a third common-source common-gate structure circuit composed of a sixteenth transistor and a seventeenth transistor, and a fourth common-source common-gate structure circuit composed of an eighteenth transistor and a nineteenth transistor, control ends of the sixteenth transistor and the seventeenth transistor are coupled and input a seventh bias voltage, a first end of the sixteenth transistor is coupled with the first amplification branch, control ends of the eighteenth transistor and the nineteenth transistor respectively, a second end of the sixteenth transistor is coupled with a first end of the eighteenth transistor and an output end of the second differential module respectively, and is coupled with third ends of the eighteenth transistor, the nineteenth transistor and the seventeenth transistor, and second ends of the eighteenth transistor and the nineteenth transistor respectively, and is grounded; a first end of the seventeenth transistor serves as the output node, and a second end of the seventeenth transistor is coupled with a first end of the nineteenth transistor and the output end of the second differential module respectively.

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