Circuits, devices and methods related to dual gate transistor arrangements

Abstract

Circuits, devices, and methods related to dual gate transistor arrangements are provided. The circuit comprises an input node (10) configured to receive a gate control signal for controlling the dual-gate transistor arrangement (14), a first output node (11) configured to be coupled to a first gate node (G1) of the dual-gate transistor arrangement (14); a first switch (S1) coupled between the input node (10) and the first output node (11); a second output node (12) configured to be coupled to a second gate node (G2) of the dual-gate transistor arrangement (14) and to the input node (10). Furthermore, the control circuit (15) is configured to open the first switch (S1) for a first predefined period of time upon detecting that the gate control signal is indicative of turning off the dual-gate transistor arrangement (14), and to close the first switch (S1) after the first predefined period of time.

Description

Technical Field

[0001] The present application relates to circuits, systems, and methods related to dual-gate transistor arrangements. Background Art

[0002] Transistors like insulated gate bipolar transistors (IGBTs) are typically three-terminal devices, meaning that they have two load nodes, which in the case of an IGBT are the collector and emitter, and a control node for providing an electrical control potential, which in the case of an IGBT is the gate node.

[0003] IGBT is a bipolar device. This means that in the conduction mode, i.e. when the IGBT is conducting, the saturation voltage between the collector and emitter (usually abbreviated as V CEsat There is a relationship between the conduction loss ( saturation voltage) and the turn-off energy required to control the IGBT to change its state from conduction mode to blocking mode when it is turned off. During conduction mode, a large number of electron-hole pairs are created and stored in the IGBT, resulting in high conductivity. When the IGBT is turned off, all electron-hole pairs must be removed so that the IGBT can provide a blocking voltage, which results in turn-off losses. During the IGBT design phase, the design is adjusted according to the requirements of the target application. During this design process, low conduction losses (low saturation voltage) are often traded off against high turn-off energy, and vice versa. To alleviate the necessity of this trade-off, dual-gate transistor arrangements have been developed. In the case of a dual-gate IGBT, for example, in a single device, two gate electrodes act on different channel regions on the same IGBT chip die. Each gate electrode of the IGBT is controlled separately. In normal conduction mode, both gates are in the on state, and the entire device behaves like a device with a low saturation voltage. In the event of a turn-off event, the two gates are turned off sequentially, reducing turn-off energy losses. With such devices, low turn-off energy and low saturation voltage can be achieved, leading to faster switching. On the other hand, the need to control two gate terminals requires additional work, such as a gate driver with two outputs and corresponding control methods, which increases the complexity of such systems. Summary of the Invention

[0004] According to an embodiment, a circuit is provided, comprising: an input node configured to receive a gate control signal for controlling a dual-gate transistor arrangement; a first output node configured to be coupled to a first gate node of the dual-gate transistor arrangement; a first switch coupled between the input node and the first output node; and a second output node configured to be coupled to a second gate node of the dual-gate transistor arrangement and to the input node. Furthermore, the circuit comprises a control circuit configured to, upon detecting that the gate control signal indicates turning off the dual-gate transistor arrangement, open the first switch for a first predefined time period, and close the first switch after the first predefined time period.

[0005] According to another embodiment, a device is provided, comprising the above circuit and a dual-gate transistor arrangement.

[0006] According to another embodiment, there is provided a method comprising:

[0007] receiving a gate control signal instructing to turn off the dual-gate transistor arrangement; and

[0008] A first gate node of the dual-gate transistor arrangement is decoupled from the gate control signal for a first predefined time period.

[0009] The foregoing summary constitutes only a brief overview of some embodiments and is not intended to be limiting in any way, as other embodiments may include different features. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a device according to an embodiment.

[0011] Figure 2 is a block diagram of a device according to another embodiment.

[0012] Figure 3A and Figure 3B An example of a transistor arrangement is shown.

[0013] Figure 4 is a timing diagram illustrating the operation of some embodiments.

[0014] Figure 5 A device according to another embodiment is shown.

[0015] Figures 6A to 6E The use of a bidirectional switch in some embodiments is shown.

[0016] Figure 7 is a flowchart illustrating a method according to an embodiment.

[0017] Figure 8is a flow chart illustrating a method according to another embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, various embodiments will be described with reference to the accompanying drawings. These embodiments are given by way of example only and should not be construed as limiting. Details or variations described in connection with one embodiment are also applicable to other embodiments and will therefore not be described again. Features from different embodiments may be combined to form additional embodiments.

[0019] As used herein, the terms "open," "off," "turned off," "shut down," or "blocking" are used synonymously with respect to a switch or transistor in which the switch or transistor does not substantially conduct between its load nodes (except for possible undesirable leakage current). In contrast, "closed," "open," "turned on," "conducting," or "on" relate to a state in which the transistor or switch conducts with a low resistance (commonly referred to as on-resistance) between its load terminals.

[0020] Turning now to the accompanying drawings, Figure 1 is a block diagram of a device according to an embodiment. Figure 1 The device comprises a dual-gate transistor arrangement 14 and a circuit comprising a first switch S1 , an input node 10 , a first output node 11 , a second output node 12 and a control circuit 15 .

[0021] The dual-gate transistor arrangement 14 has a first gate node G1 and a second gate node G2. Figure 1 1 , but the dual-gate transistor arrangement 14 includes at least two load terminals, such as a collector terminal and an emitter terminal in the case of an insulated gate bipolar transistor (IGBT) dual-gate transistor arrangement. To turn on the dual-gate transistor arrangement 14, corresponding control signals can be applied to both the first gate node G1 and the second gate node G2.

[0022] The input node 10 is configured to receive a gate control signal for the dual-gate transistor arrangement 14. The gate control signal may be a signal with two possible voltage levels (high and low) for switching the dual-gate transistor arrangement 14 on and off.

[0023] As shown, the input node 10 is coupled to a first output node 11 via a first switch S1 and directly to a second output node 12. The first output node 11 is coupled to a first gate node G1 of a dual-gate transistor arrangement 14, and the second output node 12 is coupled to a second gate node G2 of the dual-gate transistor arrangement 14.

[0024] In steady-state operation, i.e., outside of switching events of the dual-gate transistor arrangement 14, the first switch S1 is closed, so that the gate control signal applied to the input node 10 is provided to both the gate node G1 and the gate node G2 to keep the transistor on or off. In some embodiments, the first switch S1 can be a normally-on switch, i.e., a switch that is on when no control signal is applied to the first switch S1. This means that in the steady-state operation described above, no control signal needs to be applied to the first switch S1.

[0025] When the dual-gate transistor arrangement 14 is to be changed from the off-state to the on-state, ie turned on, the switch S1 remains closed so that the transition of the gate control signal applied to the input node 10 is applied simultaneously to both gate nodes G1 , G2 .

[0026] When the dual-gate transistor arrangement 14 is to be turned off, for example, when the gate control signal applied to the input node 10 transitions from a logic high level to a logic low level, the transition is detected by the control circuit 15. For example, the control circuit 15 can detect the transition once the gate control signal falls below a predefined threshold value, which is lower than the high level by a certain margin. The margin is selected to account for fluctuations in the gate control signal during steady-state operation. Upon detecting that the gate control signal indicates to turn off the dual-gate transistor arrangement 14, the control circuit 15 controls the first switch S1 to be open for a first predefined time period, for example, between 1 μs and 50 μs or between 5 μs and 20 μs. Therefore, the control circuit 15 is configured to control the switching state of the first switch S1 between the open state and the closed state, and is configured to receive a gate control signal indication signal (here the gate control signal itself, but it can also be a signal derived from the gate control signal), which gate control signal indication signal indicates whether the gate control signal indicates the on-state of the transistor or the off-state of the transistor, and wherein, if the indication signal indicates a transition from the on-state to the off-state (i.e., turning off), the control circuit 15 is configured to open the first switch S1 for a first predefined time period.

[0027] During this first predefined time period, the second gate node G2 is set to a potential given by the gate control signal, e.g., a low level. In this case, the second gate node G2 is discharged. After the first predefined time period, the switch S1 is closed again, and the first gate node G1 is also set to a corresponding low level, i.e., discharged. This gradual discharge of the gate node reduces the turn-off energy, as explained further below.

[0028] exist Figure 1In some embodiments, the switch S1 blocks at least the current from the first gate node G1 to the input node 10 when it is off, so as to prevent the first gate node G1 from discharging. Therefore, S1 can be a unidirectional switch that blocks only the current in the direction from the first gate node G1 to the input terminal 10 when it is off. In other embodiments, the first switch S1 can be a bidirectional switch that blocks the current in both directions when it is off. Details on the use of bidirectional and unidirectional switches will be referred to below. Figures 6A to 6E Further explanation.

[0029] Figure 2 A device according to another embodiment is shown, which is Figure 1 Variants of the device. Figure 1 In comparison, a second switch S2 is additionally provided between the input node 10 and the second output node 12. The second switch S2 may also be a normally-on switch. In operation, after a first predefined time period during which the first switch S1 is disconnected has elapsed, i.e., after the first switch S1 is closed again after the first predefined time period has expired, the control circuit 15 disconnects the second switch S2 for a second predefined time period. The second predefined time period may have a duration in the range given above for the first predefined time period, and may be equal to or different from the duration of the first predefined time period. When disconnected, the second switch S2 at least blocks the current from the input node 10 to the second output node 12 or (which is the same current direction) from the first output node 11 to the second output node 12. To this end, the second switch S2 may be a unidirectional switch. In other embodiments, the second switch S2 may be a bidirectional switch. As mentioned above, reference will be made below to Figures 6A to 6E Further explain the details about one-way switches and two-way switches.

[0030] By disconnecting for a second predefined period of time, Figure 2 In the embodiment, the second switch S2 may prevent the second gate node G2 from being recharged by the charge flowing from the first gate node G1 and thereby avoid an unintended turn-on event at the second gate node G2.

[0031] Figure 1 or Figure 2 The device can be implemented as an integral device in a single housing, wherein the dual-gate transistor arrangement 14 can be implemented, for example, on a first chip die, and the circuit including the control circuit 15 and the switches S1, S2 can be implemented in another chip die. Such a housing can have a single gate terminal coupled to the input node 10, and thus the device only requires a conventional single-channel gate driver. Furthermore, such a housing can have a collector and an emitter terminal. Thus, unlike some conventional solutions, two gate drivers or a dual-channel gate driver are not required. In other embodiments, Figure 1 and Figure 2 The device can be implemented on a single chip die. In addition, such a housing can have a second emitter terminal connected to the emitter node of the dual-gate transistor arrangement in the housing and providing a return path for the gate driver.

[0032] Figure 3A and Figure 3B Shown for implementation Figure 1 and Figure 2 Different possibilities of dual-gate transistor arrangements 14 are provided.

[0033] Figure 3A A first implementation example is shown with a single dual-gate IGBT 30. This dual-gate IGBT 30 has two gates acting on essentially the same active area or region. They share the same emitter and collector nodes, which may also be referred to as emitter and collector, and act on the same semiconductor volume. When both gates are on, two channels are formed in parallel, which in turn means high channel conductivity and high carrier confinement in the body region below the corresponding IGBT cell. This carrier confinement leads to a higher concentration of bipolar charge carriers and, therefore, good conductivity. This good conductivity corresponds to a low collector-emitter voltage drop when on, and in particular a low saturation voltage.

[0034] When the dual-gate IGBT 30 is as reference Figure 1 When the IGBT 30 is turned off as explained above, one channel (coupled to the second gate node G2 in the above example) is first turned off. During a first predefined time period, the load current is divided into a first portion, which continues to flow via the channel associated with the first gate node G1, while a second portion is fed by bipolar charge carriers stored in the channel associated with the second gate node G2. Since the gate-emitter voltage between the second gate node G2 and the emitter is zero or negative, meaning that the associated channel region is closed, holes in this region of the IGBT 30 can flow out, which reduces the number of carriers trapped in the body region. The voltages involved in this phase are not very high (typically up to a few volts) because one channel is still conducting and, therefore, the collector-emitter voltage remains much lower than in the off state. This reduction in carrier accumulation enables relatively low switching losses. At the end of the first predefined time period, the initial carrier accumulation has been significantly reduced.

[0035] When, after the first predefined time period, the other channel is now also turned off (the first switch S1 is closed again, so that the first gate node G1 is now also set to the corresponding voltage for turning off the dual-gate IGBT 30), the collector-emitter voltage rises towards the corresponding applied blocking voltage. With this higher collector-emitter voltage applied, which would cause a typical IGBT tail current to flow through the device, the remaining charge carriers now need to be removed. However, since the charge carrier accumulation and thus the tail current are reduced, the overall losses during turn-off of the dual-gate transistor arrangement 14 are lower than those in a conventional single-gate transistor.

[0036] Figure 3B An alternative implementation of a dual-gate transistor arrangement is shown, in which two IGBT transistors 31, 32 are coupled in parallel, i.e. their collectors are coupled together and their emitters are coupled together. A first gate node G1 is coupled to the gate of IGBT 31 and a second gate node G2 is coupled to the gate of IGBT 32.

[0037] IGBT 31, IGBT 32 may be integrated on the same chip die, such as monolithic integration, or may be provided on separate chip dies. IGBT 31, IGBT 32 may be nominally identical (i.e., identical by design, with only deviations due to manufacturing tolerances or aging). In this case, the operation and effects are similar to Figure 3A The situation is similar. Figure 3B In this implementation, the effect of combining low saturation voltage with low switching loss can be even enhanced by designing IGBTs 31 and 32 differently. For example, IGBT 32, which is turned off first in the above scheme, can be optimized for low conduction losses in the on-state, i.e., a low collector-emitter saturation voltage. As explained in the background section, this typically results in higher switching losses. However, because IGBT 32 is turned off first while IGBT 31 is still on and the voltage drop across the dual-gate transistor arrangement is relatively low, switching losses are still reduced. IGBT 31 is then turned off at a higher collector-emitter voltage when the blocking voltage is established, allowing IGBT 31 to be optimized for low switching losses.

[0038] Figure 3A and Figure 3B The implementation is only used as an example.

[0039] Figure 4 Shown Figure 1 and Figure 2 The curve 40 shows that the Figure 110. At time t0, the first switch S1 and the second switch S2 (if provided) are closed. Therefore, as shown by the curve 41 of the first gate node G1 and the curve 42 of the second gate node G2, the potential at the gate node is also low.

[0040] At time t1, the gate control signal of curve 40 transitions to a high level to turn on the dual-gate transistor arrangement 14. When switch S1 (and switch S2 if provided) is closed, this also sets the gate nodes G1, G2 to a high potential as shown by curves 41 and 42, thereby turning on the dual-gate transistor arrangement 14.

[0041] At t2, the dual gate transistor arrangement 14 will be turned off again and the gate control signal according to curve 40 transitions to a low level. In response to detecting the transition of the gate control signal, the control circuit 15 opens the switch S1 for a first predefined time period, as described above. Figure 4 In the example of t2 to t3, the duration between t2 and t3 may be in the range of 1 μs to 20 μs, but is not limited thereto. During this time, the second output node 12 and thus the second gate node G2 (at Figure 1 directly or in Figure 2 The gate node G1 is electrically coupled to the input node 10 via the closed second switch S2. Therefore, as shown by the curve 42, the voltage at the second gate node G2 also drops to a low level at t2, while the voltage at the first gate node G1 shown by the curve 41 substantially maintains its level until it also drops at t3. Figure 2 If a second switch S2 is provided as shown, then after the first predefined time period, the second switch S2 can be opened for a second predefined time period, which prevents the second gate node G2 from being charged by the first gate node G1 when the first switch S1 is closed again. The next switching event can be performed after a certain time that the system needs to stabilize, for example, after t4. The duration between t3 and t4 can be in the range of 0.5μs to 5μs, but is not limited thereto. Figure 4 The transistor arrangement 14 remains open, ie turned off, until t5, which is Figure 4 The last time shown in .

[0042] It should be noted that Figure 4 The waveform shown in is an idealized waveform with substantially vertical edges. In a real system, the rise and fall of the signal may not occur immediately, but rather occur over a certain period of time, and also due to propagation delays, for example, curves 41 and 42 may lag slightly behind curve 40. Therefore, Figure 4 They are to be considered schematic diagrams illustrating principles of operation rather than precisely measured waveforms.

[0043] In addition to switching in normal operation, protection against faults is often required. Figure 5 A case where additional error protection is provided is shown.

[0044] Figure 5 is a diagram of a device 51 according to another embodiment, which includes circuitry 52 and a dual-gate insulated gate bipolar transistor 50. The insulated gate bipolar transistor 50 is an example of a dual-gate transistor arrangement and may also be used, for example, with respect to Figure 3A and Figure 3B Other dual gate transistor arrangements discussed. In device 51, reference has been made to Figure 1 and Figure 2 Parts and elements discussed have the same reference numerals and will not be discussed again in detail.

[0045] Device 51 may be provided in a housing having a gate terminal G coupled to input node 10, a collector terminal C coupled to the collector of dual-gate IGBT 50, and an emitter terminal E coupled to the emitter of dual-gate IGBT 50. Circuit 52 includes the circuitry already described with reference to Figure 1 and Figure 2 The switches S1 and S2 discussed above and the control circuit 55. During normal operation, as long as no overcurrent is detected as further described below, the control circuit 55 is as described above with respect to Figure 1 、 Figure 2 and Figure 4 The switches S1 and S2 are controlled as described above.

[0046] Circuit 52 may be implemented on a separate chip die from dual-gate IGBT 50 , or may be implemented on the same chip die.

[0047] As mentioned above Figure 1 and Figure 2 As explained in the embodiment of FIG, a single gate terminal G accessible from outside the housing is provided, and thus a single gate driver is sufficient to control the device 51.

[0048] In addition, the circuit 52 includes an overcurrent detection mechanism. To this end, the control circuit 55 is configured to measure the current through the dual-gate IGBT 50. Figure 5 In the embodiment shown, for this purpose, the dual-gate IGBT 50 comprises a measuring resistor R coupled to the S Auxiliary emitter terminal E S Then, across the measuring resistor R SThe voltage drop across φ indicates the collector-emitter current through the dual-gate IGBT 50 and is measured by the control circuit 55. Other current measurement methods can also be used. For example, the current can also be measured without an auxiliary emitter terminal directly between the dual-gate IGBT 50 and the emitter terminal E, for example using a measuring resistor or also using a magnetic field measurement method using, for example, a magnetoresistive element.

[0049] Furthermore, circuit 52 includes a third switch S3, a first diode D1, and a second diode D2. First output node 11 is coupled to the emitter of dual-gate IGBT 50 via first diode D1 and third switch S3, and second output node 12 is coupled to the emitter via second diode D2 and third switch S3. In other embodiments, two third switches may be provided: one for connecting first output node 11 to the emitter, and one for connecting second output node 12 to the emitter.

[0050] When the control circuit 55 determines that the sensed current exceeds a predefined threshold (an overcurrent condition, such as due to a short circuit), it controls switches S1 and S2 to open and switches S3 to close. Switch S3 may be a normally-off switch. This couples the first and second gate nodes G1 and G2 to the emitter of the dual-gate IGBT 50, which reduces the gate-emitter voltage to near zero and thereby turns off the dual-gate IGBT 50, shutting off the overcurrent. When switches S1 and S2 are open, the gate control signal at the input node 10 is decoupled from the gate nodes G1 and G2, so that the dual-gate IGBT 50 is not kept off by the gate control signal.

[0051] Figure 2 The control circuit 15 and Figure 5 The control circuit 55 can be implemented as any suitable logic. It can be supplied with power from the outside or can be supplied with power based on the voltage between the input node 10 and the emitter terminal E. Such a voltage can, for example, charge a buffer capacitor that supplies power to the control circuit 55. Due to the logic that controls the disconnection of the switches S1 and S2 when the transistor arrangement is turned off, this disconnection follows the high state of the voltage at the input node 10 (see Figure 4 ), and overcurrent protection is only required when the gate control signal is high so that the dual-gate transistor arrangement is closed, i.e., conducting, which supplies power to the control circuit 15 or 55 when needed. When the dual-gate transistor arrangement is turned off in any way, and there is no high voltage at the input node 10, the control circuit 15 or 55 is also not required to operate at this time, and thus no power needs to be supplied to it.

[0052] exist Figure 5In the embodiment, switches S1 and S2 can be implemented as bidirectional switches. Switch S3 can be implemented as a unidirectional switch, which blocks the current from the first output node 11 and the second output node 12 to the emitter terminal E when it is off, while diodes D1 and D2 block the current in the opposite direction, or switch S3 can be a bidirectional switch. Figures 6A to 6E The operation and implementation of switches S1 and S2 as bidirectional switches will be explained.

[0053] Switches are typically implemented using transistors such as MOSFETs or insulated gate bipolar transistors. Such transistors typically have a body diode or freewheeling diode similar to Figure 5 The diode shown for the dual-gate IGBT 50 in FIG. This means that, for example, a single MOSFET is often used as a unidirectional switch, because current can always flow in one direction through the body diode even when the transistor is off. To implement a bidirectional switch, for example, two MOSFET transistors can be coupled in series with body diodes of opposite polarity.

[0054] Figures 6A to 6E An example implementation of a first switch S1 and a second switch S2 in such a configuration is shown, wherein the switch S1 is shown as comprising a first unidirectional switch S 1V and the second one-way switch S 1R , and the switch S2 is shown to include a first unidirectional switch S 2V and the second one-way switch S 2R Each of the unidirectional switches is depicted as a switch having a body diode and may be implemented, for example, using a MOSFET transistor. 1V and switch S 1R The body diodes of the switches have opposite polarity and the 2V and switch S 2R The body diode of the Figures 6A to 6E shown.

[0055] Figure 6A The quasi-static state of the switch is shown, which is used outside of overcurrent conditions and outside of turning off the double-gate transistor arrangement, e.g. Figure 4 Between time t0 and time t2 and between Figure 4 Here, all switches S 1V , switch S 1R , switch S 2V , switch S 2R In this state, the voltages at the first gate node G1 and the second gate node G2 substantially correspond to the voltages provided by the gate control signal at the input node 10 .

[0056] Figure 6BThe following figure shows the situation when the control circuit 15 or 55 detects the falling edge of the gate control signal, that is, detects that the dual-gate IGBT 50 is to be turned off. In this case, at least the switch S 1R is turned off for a first predefined time, which prevents the first gate node G1 from discharging. Note that the switch S 1V can also be disconnected (for example, if a common control signal is used to switch S 1V , switch S 1R ), or it can remain closed.

[0057] Figure 6C An example case where the second switch is open for a second predefined time period after the first switch is closed again is shown, as shown in FIG. Figure 2 Here, at least switch S 2V The switch S is turned off, thereby preventing the second gate node G2 from being charged by the discharge of the first gate node G1. 2R It can also be open, or it can remain closed.

[0058] Figure 6B and Figure 6C Also shown is the reference Figure 1 and Figure 2 The switch S1 and the switch S2 can also be unidirectional switches, which means that only the switch S 1R and switch S 2V .

[0059] In about Figure 5 In the case of overcurrent detection explained, the first gate node G1 and the second gate node G2 must be decoupled from the gate control signal at the node 10. Therefore, in this case, at least the switch S 1V and switch S 2V Disconnect. This Figure 6D Alternatively, in this case, all four switches S 1V , switch S 1R , switch S 2V , switch S 2R Are disconnected, such as Figure 6E shown.

[0060] based on Figure 6B 、 Figure 6C and Figure 6D If provided with respect to Figure 2 In order to realize the functions of shutting down and overvoltage protection explained above, the first switch S1 needs to be realized as a bidirectional switch to be able to provide Figure 6B and Figure 6D Both possibilities, while the second switch S2 can only use the switch S 2V implemented as a unidirectional switch to provide Figure 6C and Figure 6D It should be noted that although Figures 6A to 6E Two unidirectional switches are used to implement bidirectional switching, but switches that provide blocking of current in both directions in other ways may also be used.

[0061] Figure 7 A method for controlling a double-gate transistor arrangement according to an embodiment is shown. Figure 7 The method shows reference Figure 1 、 Figure 2 and Figure 4 The functions explained herein will be described with reference to these drawings to avoid repetition.

[0062] At 70, the method includes receiving a gate control signal input, for example at input node 10, indicating a turn-off of a dual-gate transistor arrangement, such as dual-gate transistor arrangement 14. At 71, the method includes decoupling a first gate node of the dual-gate transistor arrangement from the gate control signal input, for a first predefined time, for example by opening switch S1. Figure 1 After the first predefined time, the first gate node is coupled to the gate control signal input again, i.e., here the decoupling occurs only during the first predefined time. Optionally, after the gate control signal input is coupled to the first gate node again, at 72, the method includes decoupling the second gate node from the gate control signal input for a second predefined time, for example by opening the second switch S2, as described with reference to Figure 2 Explained.

[0063] Apart from Figure 7 In addition to the method, error detection can be used, such as Figure 5 Explained. Figure 8 The corresponding method is shown in .

[0064] At 81, the method includes detecting an error condition, such as referring to Figure 5 At 82, in response to the overcurrent condition, the method includes, for example, disconnecting Figure 5 The switches S1 and S2 are opened and the switch S3 is closed to decouple the first and second gate nodes from the gate control signal input and couple the first and second gate nodes to the emitter of the dual-gate transistor arrangement.

[0065] Some embodiments are defined by the following examples:

[0066] Example 1. A circuit comprising:

[0067] an input node configured to receive a gate control signal for controlling the dual-gate transistor arrangement,

[0068] a first output node configured to be coupled to a first gate node of the dual-gate transistor arrangement;

[0069] a first switch coupled between the input node and the first output node;

[0070] a second output node configured to be coupled to a second gate node of the dual-gate transistor arrangement and to the input node;

[0071] A control circuit configured to:

[0072] Upon detecting that the gate control signal indicates to turn off the dual-gate transistor arrangement, the first switch is opened for a first predefined time period, and the first switch is closed after the first predefined time period.

[0073] Example 2. The circuit of Example 1, wherein the first switch is a normally-on switch.

[0074] Example 3. The circuit of Example 1, wherein the first switch blocks at least current flow from the first output node to the input node when open.

[0075] Example 4. The circuit of Example 3, wherein the first switch is a bidirectional switch.

[0076] Example 5. The circuit of any of Examples 1 to 4, further comprising a second switch coupled between the input node and the second output node.

[0077] Example 6. The circuit of Example 5, wherein the control circuit is configured to, upon detecting that the gate control signal indicates turning off the dual-gate transistor arrangement and closing the first switch after opening the first switch, open the second switch for a second predefined time period, and close the second switch after the second predefined time period.

[0078] Example 7. The circuit of Example 5 or 6, wherein the second switch is a normally-on switch.

[0079] Example 8. The circuit of any of Examples 5 to 7, wherein the second switch at least blocks current flow from the input node to the second output node when open.

[0080] Example 9. The circuit of Example 8, wherein the second switch is a bidirectional switch.

[0081] Example 10. The circuit of any of Examples 1 to 9, further comprising: a further node configured to be connected to an emitter node of the dual-gate transistor arrangement;

[0082] at least one third switch coupling the first output node and the second output node to the other node;

[0083] Wherein, the control circuit is configured to close the at least one third switch in response to detecting an error condition.

[0084] Example 11. The circuit of Example 10, further comprising: a first diode coupled between the first output node and the at least one third switch; and a second diode coupled between the second output node and the at least one third switch.

[0085] Example 12. The circuit of any one of Examples 10 or 11 and Examples 5 to 9, wherein the control circuit is further configured to open the first switch and the second switch in response to detecting an error condition.

[0086] Example 13. A device comprising:

[0087] The circuit of any of Examples 1 to 12; and

[0088] A dual-gate transistor arrangement includes the first gate node and the second gate node, wherein the first gate node is coupled to a first output node of the circuit and the second gate node is coupled to a second output node of the circuit.

[0089] Example 14. The device according to Example 13,

[0090] wherein the device comprises a collector terminal, an emitter terminal, and a gate terminal coupled to an input node of the circuit;

[0091] Wherein the dual-gate transistor arrangement comprises: a collector node coupled to a collector terminal of the device; and an emitter node coupled to an emitter terminal of the device.

[0092] Example 15. The device according to Example 13 or 14,

[0093] Wherein the dual-gate transistor arrangement comprises a monolithic dual-gate insulated gate bipolar transistor having the first gate node and the second gate node.

[0094] Example 16. The device according to Example 13 or 14,

[0095] Wherein, the dual-gate transistor arrangement includes a first insulated gate bipolar transistor having the first gate node and a second insulated gate bipolar transistor having the second gate node.

[0096] Example 17. A device according to Example 16, wherein the emitter of the first insulated gate bipolar transistor is coupled to the emitter of the second insulated gate bipolar transistor, and wherein the collector of the first insulated gate bipolar transistor is coupled to the collector of the second insulated gate bipolar transistor.

[0097] Example 18. The device of Example 16 or 17, wherein the first insulated gate bipolar transistor is designed identically to the second insulated gate bipolar transistor.

[0098] Example 19. The device of Example 16 or 17, wherein the first insulated gate bipolar transistor has a lower saturation voltage than the second insulated gate bipolar transistor.

[0099] Example 20. A method comprising:

[0100] receiving a gate control signal input instructing to turn off the dual-gate transistor arrangement; and

[0101] decoupling a first gate node of the dual-gate transistor arrangement from the gate control signal input for a first predefined period of time; and

[0102] After the first predefined time period has elapsed, the first gate node is coupled to the gate control signal input.

[0103] Example 21. The method of Example 20, further comprising:

[0104] After the first predefined time period has elapsed, the second gate node of the dual-gate transistor arrangement is decoupled from the gate control signal input for a second predefined time period.

[0105] Example 22. The method of example 20 or 21, further comprising:

[0106] At times other than during the off period of the dual-gate transistor arrangement, both the first gate node and the second gate node are coupled to the gate control signal input.

[0107] Example 23. The method of any one of Examples 20 to 22, further comprising:

[0108] Detect error conditions; and

[0109] In response to detecting an error condition, both the first gate node and the second gate node are decoupled from the gate control signal input and both the first gate node and the second gate node are coupled to an emitter node of the dual-gate transistor arrangement.

[0110] Although specific embodiments have been shown and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any changes or modifications to the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A circuit (52) for a dual-gate transistor arrangement (14), comprising: an input node (10) configured to receive a gate control signal for controlling the dual-gate transistor arrangement (14), a first output node (11) configured to be coupled to a first gate node (G1) of the dual-gate transistor arrangement (14); a first switch (S1), the first switch (S1) being coupled between the input node (10) and the first output node (11); a second output node (12) configured to be coupled to a second gate node (G2) of the dual-gate transistor arrangement (14) and to the input node (10); A control circuit (15, 55), wherein the control circuit (15, 55) is configured to: Upon detecting that the gate control signal indicates turning off the dual-gate transistor arrangement (14), the first switch (S1) is opened for a first predefined time period and the first switch (S1) is closed after the first predefined time period.

2. The circuit (52) of claim 1, wherein: The first switch (S1) is a normally-on switch.

3. The circuit (52) of claim 1, wherein: The first switch (S1) blocks at least the current from the first output node (11) to the input node (10) when the switch is turned off.

4. The circuit (52) of claim 3, wherein: The first switch (S1) is a bidirectional switch.

5. The circuit (52) according to any one of claims 1 to 4, further comprising a second switch (S2) coupled between the input node (10) and the second output node (12).

6. The circuit (52) of claim 5, wherein: The control circuit (15, 55) is configured to, upon detecting that the gate control signal indicates turning off the dual-gate transistor arrangement (14) and closing the first switch (S1) after opening the first switch (S1), open the second switch (S2) for a second predefined time period, and close the second switch (S2) after the second predefined time period.

7. A circuit (52) according to claim 5 or 6, wherein The second switch (S2) is a normally-on switch.

8. The circuit (52) according to any one of claims 5 to 7, wherein The second switch (S2) blocks at least the current from the input node (10) to the second output node (12) when the switch is turned off.

9. The circuit (52) of claim 8, wherein: The second switch (S2) is a bidirectional switch.

10. The circuit (52) according to any one of claims 5 to 9, further comprising: a further node configured to be connected to an emitter node of the dual-gate transistor arrangement (14); at least one third switch (S3), the at least one third switch (S3) coupling the first output node (11) and the second output node (12) to the other node; Wherein the control circuit (15, 55) is configured to close the at least one third switch (S3) in response to detecting an error condition.

11. The circuit (52) of claim 10, further comprising: a first diode coupled between the first output node (11) and the at least one third switch (S3); and a second diode coupled between the second output node (12) and the at least one third switch (S3).

12. The circuit (52) according to claim 10 or 11, wherein The control circuit (15, 55) is further configured to open the first switch (S1) and the second switch (S2) in response to detecting the error condition.

13. A device (51), comprising: A circuit (52) according to any one of claims 1 to 12; and The dual-gate transistor arrangement (14) includes a first gate node (G1) and a second gate node (G2), wherein the first gate node (G1) is coupled to a first output node (11) of the circuit (52) and the second gate node (G2) is coupled to a second output node (12) of the circuit (52).

14. The device (51) according to claim 13, in, The device (51) includes a collector terminal (C), an emitter terminal (E), and a gate terminal (G) coupled to an input node (10) of the circuit (52); The dual-gate transistor arrangement (14) comprises a collector node coupled to a collector terminal (C) of the device (51) and an emitter node coupled to an emitter terminal (E) of the device (51).

15. The device (51) according to claim 13 or 14, in, The dual-gate transistor arrangement (14) includes a monolithic dual-gate insulated gate bipolar transistor (30, 50) having the first gate node (G1) and the second gate node (G2).

16. The device (51) according to claim 13 or 14, in, The dual-gate transistor arrangement (14) includes a first insulated gate bipolar transistor (31) having the first gate node (G1) and a second insulated gate bipolar transistor (32) having the second gate node (G2).

17. The device (51) according to claim 16, wherein The emitter of the first insulated gate bipolar transistor (31) is coupled to the emitter of the second insulated gate bipolar transistor (32), and wherein the collector of the first insulated gate bipolar transistor (31) is coupled to the collector of the second insulated gate bipolar transistor (32).

18. A method for a dual-gate transistor arrangement (14), comprising: receiving a gate control signal input instructing to turn off the dual-gate transistor arrangement (14); decoupling a first gate node (G1) of the dual-gate transistor arrangement (14) from the gate control signal input for a first predefined period of time; as well as After the first predefined time period has elapsed, the first gate node (G1) is coupled to the gate control signal input.

19. The method according to claim 18, further comprising: After the first predefined time period has elapsed, a second gate node (G2) of the dual-gate transistor arrangement (14) is decoupled from the gate control signal input for a second predefined time period.

20. The method according to claim 19, further comprising: Detect error conditions; as well as In response to detecting the error condition, both the first gate node (G1) and the second gate node (G2) are decoupled from the gate control signal input and both the first gate node (G1) and the second gate node (G2) are coupled to the emitter node of the dual-gate transistor arrangement (14).

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