Method and apparatus for operating buffer stage in amplifier circuitry

Abstract

The embodiment of the invention relates to a method and an apparatus for operating a buffer stage in amplifier circuitry. An example apparatus includes first buffer circuitry (230) having an input and an output; a second buffer circuitry (220) having an input and an output; a resistor (225) having a first terminal and a second terminal, the first terminal of the resistor coupled to the output of the first buffer circuitry, the second terminal of the resistor coupled to the output of the second buffer circuitry; a third buffer circuitry (235) having an input and an output, the input of the third buffer circuitry coupled to the input of the first buffer circuitry; and switching circuitry (240) having a first terminal and a second terminal, the first terminal of the switching circuitry coupled to the input of the second buffer circuitry, and the second terminal of the switching circuitry coupled to the output of the third buffer circuitry.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 564,629, filed on March 13, 2024, and U.S. Provisional Patent Application No. 63 / 564,637, filed on March 13, 2024, each of which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] The present description relates generally to amplifiers and, more particularly, to methods and apparatus for operating a buffer stage in amplifier circuitry. Background Art

[0004] Amplifier circuitry generates a relatively high-power signal at its output in response to a relatively low-power signal at its input. In some devices, the amplifier circuitry regulates the power supply to the circuitry. In other devices, the amplifier circuitry allows relatively low-power circuitry to interface with relatively high-power circuitry. Amplifier circuitry utilizes increasingly complex circuitry to support higher output voltages, output currents, and operating speeds. This circuitry allows the amplifier circuitry to safely support a wide range of operating conditions. Summary of the Invention

[0005] An example apparatus for operating a buffer stage in an amplifier circuit system includes a method and apparatus for operating a buffer stage in an amplifier circuit system, including a first buffer circuit system having an input and an output; a second buffer circuit system having an input and an output; a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the output of the first buffer circuit system and the second terminal of the resistor being coupled to the output of the second buffer circuit system; a third buffer circuit system having an input and an output, the input of the third buffer circuit system being coupled to the input of the first buffer circuit system; and a switch circuit system having a first terminal and a second terminal, the first terminal of the switch circuit system being coupled to the input of the second buffer circuit system and the second terminal of the switch circuit system being coupled to the output of the third buffer circuit system. Other examples are described.

[0006] An example apparatus for operating a buffer stage in an amplifier circuit system includes an input stage circuit system having an output; an opposing buffer stage circuit system having a first input, a second input, and an output; an output stage circuit system having an input coupled to the output of the opposing buffer stage circuit system; a buffer circuit system having an input and an output, the input of the buffer circuit system coupled to the first input of the opposing buffer stage circuit system; and a switch circuit system having a first terminal and a second terminal, the first terminal of the switch circuit system coupled to the output of the buffer circuit system and the second terminal of the switch circuit system coupled to the output of the input stage circuit system and the second input of the opposing buffer stage circuit system. Other examples are described.

[0007] An example apparatus for operating a buffer stage in an amplifier circuit system includes an opposing buffer stage circuit system having a first input and a second input; a transistor having a first terminal and a second terminal; a current mirror circuit system having an input and an output, the output of the current mirror circuit system being coupled to the first terminal of the transistor; a switch circuit system having a first terminal and a second terminal, the first terminal of the switch circuit system being coupled to the input of the current mirror circuit system; and a buffer circuit system having an input, an output, and a power supply terminal, the input of the buffer circuit system being coupled to the first input of the opposing buffer stage circuit system, the output of the buffer circuit system being coupled to the second input of the opposing buffer stage circuit system and the second terminal of the transistor, and the power supply terminal of the buffer circuit system being coupled to the second terminal of the switch circuit system. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an example amplifier circuit system having an input stage, an opposed buffer stage, and an output stage.

[0009] Figure 2 is included Figure 1 An example of an opposing buffer stage, Figure 1 Schematic diagram of example amplifier circuitry with example output stages and example control signal generation circuitry.

[0010] Figure 3 The invention includes an example buffer circuit system and an example switch circuit system. Figure 1 and 2 Schematic diagram of an example opposing buffer stage.

[0011] Figure 4 is included Figure 3 An example buffer circuit system and Figure 3 Example of a switching circuit system Figure 1 、 2 Schematic diagrams of example opposing buffer stages of 3.

[0012] Figure 5 is included Figure 3 and 4 An example buffer circuit system of Figure 3 and 4 Example switching circuit systems and example current mirror circuit systems Figure 1 、 2 , 3 and 4 are schematic diagrams of example opposing buffer stages.

[0013] Figure 6 is included Figure 1 An example input stage and Figure 1 、 2 , 3, 4 and 5 are schematic diagrams of example amplifier circuit systems of example opposing buffer stages.

[0014] Figure 7A yes Figure 2 Schematic diagram of an example control signal generating circuit system.

[0015] Figure 7B yes Figure 2 and 7A 1 is a timing diagram of an example operation of the control signal generating circuit system.

[0016] Figure 8 is a flowchart representing example machine-readable instructions or example operations that may be used Figure 1 、 2 , 3, 4, 5 and 6 opposing buffer stages, Figure 2 and 7A control signal generating circuitry or more generally Figure 1 and 2 to perform, instantiate, and / or implement an example embodiment of the amplifier circuit system.

[0017] Figure 9 yes Figure 1 、 2 , 3, 4, 5 and 6 opposing buffer stages, Figure 2 and 7A control signal generating circuitry or more generally Figure 1 and 2 A timing diagram of an example operation of the amplifier circuit system.

[0018] Figure 10 is included Figure 1 The opposing buffer stage and Figure 1Schematic diagram of an example amplifier circuit system with an example of an output stage.

[0019] Figure 11 is included Figure 1 and 10 The opposing buffer stage and Figure 1 and 10 Schematic diagram of an example amplifier circuit system with an example of an output stage.

[0020] Figure 12 is included Figure 1 、 10 and 11 opposing buffer stages and Figure 1 、 10 1 and 11 are schematic diagrams of example amplifier circuit systems of examples of output stages.

[0021] Figure 13 is included Figure 1 、 10 , 11 and 12 opposing buffer stages and Figure 1 、 10 Schematic diagram of an example amplifier circuit system of an example of the output stages of 11 and 12.

[0022] Figure 14 is a flowchart representing example machine-readable instructions or example operations that may be used Figure 1 、 10 , opposing buffer stages 11, 12, and 13, Figure 1 、 10 , 11, 12 and 13 output stages or more generally Figure 1 、 10 , 11, 12 and 13 are performed, instantiated and / or implemented in accordance with an exemplary embodiment of the amplifier circuit system.

[0023] The drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and the present specification refer to the same or similar (functionally and / or structurally) features and / or components. Although the drawings show regions with distinct lines and boundaries, some or all of these lines and boundaries may be idealized. In practice, boundaries or lines may not be observable, may be blended, or may be irregular. DETAILED DESCRIPTION

[0024] Amplifier circuitry generates a relatively high-power signal at its output in response to a relatively low-power signal at its input. In some devices, the amplifier circuitry regulates the power supply to the circuitry. In other devices, the amplifier circuitry allows relatively low-power circuitry to interface with relatively high-power circuitry. Amplifier circuitry utilizes increasingly complex circuitry to support higher output voltages, output currents, and operating speeds. This circuitry allows the amplifier circuitry to safely support a wide range of operating conditions.

[0025] In some embodiments, the amplifier circuit system has a first input (also referred to as a non-inverting input), a second input (also referred to as an inverting input), and an output. The amplifier circuit system generates an output voltage in response to the difference between the voltages at the first and second inputs. In some systems, the amplifier circuit system amplifies the voltage at the input in response to an external feedback path between the inverting input and the output. In such systems, it is advantageous to implement an amplifier circuit system that is power efficient, area efficient, supports wide bandwidth, and is capable of linear operation. One such type of amplifier circuit system is a three-stage amplifier circuit system.

[0026] The three-stage amplifier circuit system includes an input stage, an opposing buffer stage, and an output stage. The input stage receives an input voltage at the first and second inputs of the amplifier circuit system. Some input stages use a transconductance circuit system to set the first and second inputs to high-impedance inputs. In some amplifier circuit systems, the input stage generates inverting and non-inverting input voltages in response to the current of the transconductance circuit system. In such amplifier circuit systems, the input stage supplies the inverting and non-inverting input voltages to the opposing buffer stage. In other amplifier circuit systems, the input stage generates an input stage voltage in response to the current of the transconductance circuit system. In such amplifier circuit systems, the input stage provides the input stage voltage at the first input of the opposing buffer stage, and the second input of the opposing buffer stage is set to a reference voltage.

[0027] In an example, an opposing buffer stage includes a first buffer circuit system and a second buffer circuit system. The first buffer circuit system has an input coupled to a first output of an input stage, the input stage supplying one of a non-inverting input voltage or a reference voltage. The second buffer circuit system has an input coupled to a second output of the input stage, the input stage supplying one of an inverting input voltage or an input stage voltage. In some examples, such as for a single-output input stage, one of the first or second inputs of the opposing buffer stage is coupled to a reference voltage. The output of the first buffer circuit system is coupled to the output of the second buffer circuit system via a resistor. This configuration of the first and second buffer circuit systems may be referred to as an opposing buffer or opposing buffer circuit system. In operation, the first buffer circuit system generates an inverting sinking current at a first power supply terminal and a non-inverting sourcing current at a second power supply terminal in response to a voltage at the input of the opposing buffer stage. Similarly, the second buffer circuit system generates a non-inverting sinking current at the first power supply terminal and an inverting sourcing current at the second power supply terminal in response to a voltage at the input of the opposing buffer stage. In such operation, the difference between the inverting and non-inverting sink currents and the inverting and non-inverting source currents represents the voltage difference between the inputs of the second and first buffer circuitry. The opposing buffer stage circuitry supplies inverting and non-inverting source currents to the output stage and sinks inverting and non-inverting sink currents from the output stage.

[0028] In an example, the output stage includes a first current mirror circuit system, a second current mirror circuit system, a first gate bias circuit system, a second gate bias circuit system, a class AB control circuit system, and an output driver circuit system. The first current mirror circuit system mirrors the inverting sink current to supply a non-inverting sink current to an opposing buffer stage. The first current mirror circuit system routes the difference between the inverting and non-inverting sink currents to the class AB control circuit system and the output driver circuit system. Similarly, the second current mirror circuit system mirrors the non-inverting source current to sink the inverting source current from the opposing buffer stage. The second current mirror circuit system routes the difference between the non-inverting and inverting source currents to the class AB control circuit system and the output driver circuit system.

[0029] The first gate bias circuitry uses a first bias current to generate a first gate bias voltage referenced to a power supply voltage. The second gate bias circuitry uses a second bias current to generate a second gate bias voltage referenced to a common potential (e.g., ground, VSS, etc.). The class AB control circuitry uses the first and second gate bias voltages to drive a pair of transistors of the output driver circuitry in a linear region. The class AB control circuitry linearly operates the pair of transistors (also referred to as a high-side transistor and a low-side transistor) by conducting the remaining portions of the inverting and non-inverting source and sink currents from the first and second current mirror circuitry. However, to continue operating in the linear region when the inverting and non-inverting sink currents are substantially similar (e.g., a relatively low voltage at the input of the amplifier circuitry), the class AB control circuitry uses third and fourth bias currents. The third bias current increases the current at the output of the first current mirror circuitry, and the fourth bias current increases the current at the output of the second current mirror circuitry. The third and fourth bias currents increase the likelihood that the class AB control circuitry will linearly control the transistors of the output driver circuitry. To support the operation of the amplifier circuit system, the system on chip (SoC) includes four additional current sources to generate the first, second, third and fourth bias currents. Such additional current sources increase power consumption, system on chip size, complexity, cost, etc.

[0030] Some output stages further include a first switch and a second switch. The first switch is coupled between the gate and source terminals of the high-side transistor of the output driver circuitry. The second switch is coupled between the gate and source terminals of the low-side transistor of the output driver circuitry. In operation, in response to shorting the gate and source terminals of the high-side and low-side transistors, closing the first and second switches disables the output of the amplifier circuitry. This operation is referred to as a power-off state or standby state. In the power-off state, the first and second switches prevent the output driver circuitry from generating a voltage at the output of the amplifier circuitry.

[0031] Furthermore, in the power-off state, the first switch shorts the outputs of the class AB control circuitry and the first current mirror circuitry to the supply voltage. Similarly, the second switch shorts the outputs of the class AB control circuitry and the second current mirror circuitry to a common potential. In this state, the first and second switches disable the output stage, which prevents the amplifier circuitry from forming an external feedback loop. Without an external feedback loop, the voltage at the input of the opposing buffer stage increases, which saturates the current at the outputs of the first and second current mirror circuitry. However, during the transition from the power-off state to normal operation, in which the first and second switches are open, the relatively large difference between the non-inverting and inverting source currents or the non-inverting and inverting sink currents begins to drive the high-side and low-side transistors. In response to the saturation current, the output driver circuitry generates a transient voltage at the output of the amplifier circuitry. In some devices, this transient voltage may damage or inaccurately drive circuitry coupled to the output of the amplifier circuitry.

[0032] Examples described herein include methods and apparatus for operating an opposing buffer stage in amplifier circuitry. In some examples, the opposing buffer stage further includes first buffer circuitry, second buffer circuitry, third buffer circuitry, and switch circuitry. The first and second buffer circuitry are configured as opposing buffers and have inputs configured to couple to an input stage. The third buffer circuitry and switch circuitry are coupled between the input of the first buffer circuitry and the input of the second buffer circuitry.

[0033] When in the power-off state, the switch circuitry closes to cause the buffer circuitry to set the input of the second buffer circuitry to be equal to the input of the first buffer circuitry. Furthermore, during power-off operation, the first and second switches of the output stage close to disable (e.g., turn off, no longer conduct, etc.) the high-side and low-side transistors. In such an example, the first and second switches prevent the high-side and low-side transistors from driving the output of the amplifier circuitry. During the transition from the power-off state to normal operation, the first and second switches are opened at a first time. At the first time, the switch circuitry remains closed to continue causing the third buffer circuitry to drive the input of the second buffer based on the input of the first buffer, thereby reducing the difference between the non-inverting and inverting source and sink currents. At a second time, after the amplifier has stabilized, the switch circuitry is opened to no longer drive the input of the second buffer circuitry. Advantageously, the third buffer circuitry and the switch circuitry reduce voltage transients at the output of the amplifier circuitry during the transition from the power-off state to normal operation.

[0034] In some described examples, the first buffer circuitry and the second buffer circuitry further include a first transistor, a second transistor, a third transistor, and a fourth transistor. Control terminals of the first and second transistors are coupled to an input of the buffer circuitry that supplies an input voltage. The first transistor controls the third transistor by shifting the input voltage. The voltage shift of the first transistor is responsive to a first bias current. The third transistor conducts one of an inverting or non-inverting sink current in response to the voltage of the first transistor. Similarly, the second transistor controls the fourth transistor by shifting the input voltage. The voltage shift of the second transistor is responsive to a second bias current. The fourth transistor conducts one of an inverting or non-inverting source current in response to the voltage of the second transistor. The third and fourth transistors use the conducted currents to set the output of the buffer circuitry.

[0035] In such a described example, a first transistor is coupled to one of the first current mirror circuitry or the first gate bias circuitry of the output stage. The first transistor supplies a first bias current to one of the first current mirror circuitry or the first gate bias circuitry. Similarly, a second transistor is coupled to one of the second current mirror circuitry or the second gate bias circuitry of the output stage. The second transistor sinks a second bias current from one of the second current mirror circuitry or the second gate bias circuitry.

[0036] Advantageously, the output stage uses first and second bias currents from the first and second transistors to bias the class AB control circuitry and the output driver circuitry. Advantageously, the first and second transistors reduce the amount of bias current required by the output stage in response to reusing the first and second bias currents. Advantageously, as further described below, the buffer circuitry may include additional transistors to further reduce the amount of bias current required by the output stage.

[0037] Figure 1 is a block diagram of an example amplifier circuit system 100. Figure 1 In the example shown, the amplifier circuit system 100 includes an example input stage 110, an example opposing buffer stage 120, and an example output stage 130. The amplifier circuit system 100 includes a first input, a second input, and an output. The first input (also referred to as the non-inverting input) of the amplifier circuit system 100 is configured to be coupled to an external circuit system that supplies a non-inverting input signal (V IN+ The second input (also referred to as the inverting input) of the amplifier circuitry 100 is configured to be coupled to an external circuitry that supplies the inverting input signal (V IN- The output of amplifier circuitry 100 is configured to be coupled to downstream circuitry that receives the output signal (V OUT ).

[0038] Input stage 110 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of input stage 110 is coupled to a first input of amplifier circuitry 100, which supplies a non-inverting input signal. The second terminal of input stage 110 is coupled to a second input of amplifier circuitry 100, which supplies an inverting input signal. The third and fourth terminals of input stage 110 are coupled to opposing buffer stage 120. In some instances, input stage 110 has a single output coupled to opposing buffer stage 120. In such instances, input stage 110 may have only three terminals, with the third terminal coupled to opposing buffer stage 120. Figure 6 、 10 , 11, 12 and 13 further illustrate and describe such examples. Figure 6 An example of input stage 110 is further shown and described.

[0039] The opposing buffer stage 120 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first and second terminals of the opposing buffer stage 120 are coupled to the input stage 110. In some examples, the opposing buffer stage 120 has a first terminal coupled to the input stage 110 and a second terminal coupled to a reference terminal that supplies a reference voltage. Figure 6 、 10 , 11, 12 and 13 further illustrate and describe such an example. The third, fourth, fifth and sixth terminals of the opposing buffer stage 120 are coupled to the output stage 130. Figure 2 、 3 , 4, 5, 6, 10, 11, 12 and 13 further illustrate and describe examples of opposing buffer stages 120.

[0040] The output stage 130 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first, second, third, and fourth terminals of the output stage 130 are coupled to the opposing buffer stage 120. The fifth terminal of the output stage 130 is coupled to the output of the amplifier circuit system 100. Figure 2 、 10 , 11 , 12 , and 13 further illustrate and describe an example of the output stage 130 .

[0041] In example operation, the input stage 110 receives an inverting and non-inverting input signal. The input stage 110 sets the first and second inputs of the amplifier circuitry as high impedance inputs and generates inverting and non-inverting opposing buffer stage input voltages based on the difference between the voltages of the inverting and non-inverting input signals. In some examples, for example, Figure 6 、 10, 11, 12, and 13, the input stage 110 generates a single-ended output voltage based on the inverting and non-inverting input signals. The opposing buffer stage 120 converts the inverting and non-inverting opposing buffer stage input voltages into source current and sink current. The opposing buffer stage 120 supplies the source current and sink current to the output stage 130. In some examples, the opposing buffer stage 120 further provides a bias current to the output stage 130 or sinks a bias current from the output stage. The output stage 130 sets the output of the amplifier circuit system 100 in response to the source current and sink current of the opposing buffer stage 120. Figure 8 and 14 Example operations of the amplifier circuit system 100 are further shown and described.

[0042] Figure 2 is a schematic diagram of an amplifier circuit system 200 including an example opposed buffer stage 205 (which is Figure 1 ), an example output stage 210 (which is an example of an opposing buffer stage 120 of Figure 1 An example of an output stage 130 of FIG. 1 and an example control signal generating circuit system 215 . Figure 2 The example opposing buffer stage 205 includes a first example buffer circuitry 220 , an example resistor 225 , a second example buffer circuitry 230 , a third example buffer circuitry 235 , and an example switch circuitry 240 . Figure 2 The example output stage 210 includes a first example current mirror circuit system 245, a second example current mirror circuit system 250, an example class AB control circuit system 255, a first example switching circuit system 260, a second example switching circuit system 265, a first example transistor 270 and a second example transistor 275.

[0043] The amplifier circuit system 200 has a first input, a second input, and an output. The first input of the amplifier circuit system 200 is configured to be coupled to Figure 1 The input stage 110 supplies the inverting input voltage (V IN_STAGE- The second input of the amplifier circuitry 200 is configured to be coupled to the input stage 110, which supplies a non-inverting input voltage (V IN_STAGE+ In some examples, the second input of the amplifier circuit system 200 is configured to be coupled to a reference input that supplies a reference voltage (V REF The output of amplifier circuitry 200 is configured to be coupled to downstream circuitry that receives the output voltage (V OUT ).exist Figure 2 In the example of , amplifier circuit system 200 includes opposing buffer stage 205 and output stage 210. However, in some examples, amplifier circuit system 200 includes additional stages, such as Figure 1 The input stage 110.

[0044] Opposing buffer stage 205 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal. The first terminal of opposing buffer stage 205 is coupled to a first input of amplifier circuitry 200, which supplies an inverting input voltage. The second terminal of opposing buffer stage 205 is coupled to a second input of amplifier circuitry 200, which supplies a non-inverting input voltage. The third terminal of opposing buffer stage 205 is coupled to control signal generating circuitry 215. The fourth, fifth, sixth, and seventh terminals of opposing buffer stage 205 are coupled to output stage 210. Figure 3 、 4 , 5, 6, 10, 11, 12 and 13 further illustrate and describe additional examples of opposing buffer stages 205.

[0045] Output stage 210 (also known as a Monticelli output stage) has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal. The first, second, third, and fourth terminals of output stage 210 are coupled to opposing buffer stage 205. The fifth and sixth terminals of output stage 210 are coupled to control signal generation circuitry 215. The seventh terminal of output stage 210 is coupled to the output of amplifier circuitry 200, which supplies an output voltage to downstream circuitry. Figure 10 、 11 , 12 and 13 further illustrate and describe additional examples of output stage 210.

[0046] The control signal generating circuit system 215 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the control signal generating circuit system 215 are coupled to the output stage 210. The third and fourth terminals of the control signal generating circuit system 215 are coupled to the opposing buffer stage 205. Figure 7A An example of control signal generation circuitry 215 is further shown and described.

[0047] Buffer circuit system 220 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of buffer circuit system 220 is coupled to switch circuit system 240 and a first input of amplifier circuit system 200, which supplies the inverting input voltage. The second terminal of buffer circuit system 220 is coupled to resistor 225. The third terminal of buffer circuit system 220 is coupled to current mirror circuit system 245. The fourth terminal of buffer circuit system 220 is coupled to current mirror circuit system 250. Figure 3 、 4, 5, 6, 10, 11, 12 and 13 further illustrate and describe examples of the buffer circuit system 220.

[0048] Resistor 225 has a first terminal and a second terminal. The first terminal of resistor 225 is coupled to buffer circuitry 220. The second terminal of resistor 225 is coupled to buffer circuitry 230.

[0049] Buffer circuitry 230 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of buffer circuitry 230 is coupled to buffer circuitry 235 and a second input of amplifier circuitry 200, which supplies a non-inverting input voltage. The second terminal of buffer circuitry 230 is coupled to resistor 225. The third terminal of buffer circuitry 230 is coupled to current mirror circuitry 245, class AB control circuitry 255, switch circuitry 260, and transistor 270. The fourth terminal of buffer circuitry 230 is coupled to current mirror circuitry 250, class AB control circuitry 255, switch circuitry 265, and transistor 275. Figure 3 、 4 , 5, 6, 10, 11, 12 and 13 further illustrate and describe examples of buffer circuit system 230.

[0050] Buffer circuitry 235 has a first terminal and a second terminal. The first terminal of buffer circuitry 235 is coupled to buffer circuitry 230 and a second input of amplifier circuitry 200, which supplies the non-inverting input voltage. The second terminal of buffer circuitry 235 is coupled to switch circuitry 240. Figure 3 、 4 , 5 and 6 further illustrate and describe an example of the buffer circuit system 235.

[0051] Switching circuitry 240 has a first terminal, a second terminal, a first control terminal, and a second control terminal. The first terminal of switching circuitry 240 is coupled to buffer circuitry 235. The second terminal of switching circuitry 240 is coupled to buffer circuitry 220 and a first input of amplifier circuitry 200, which supplies an inverting input voltage. The first and second control terminals of switching circuitry 240 are coupled to control signal generating circuitry 215, which supplies a second control signal (V OFF2 ) and the second inverting control signal (~V OFF2 ). Combined Figure 3 、 4 , 5 and 6 further illustrate and describe an example of the switching circuit system 240.

[0052] Current mirror circuitry 245 has a first terminal, a second terminal, and a third terminal. The first terminal of current mirror circuitry 245 is coupled to buffer circuitry 220. The second terminal of current mirror circuitry 245 is coupled to buffer circuitry 230, class AB control circuitry 255, switch circuitry 260, and transistor 270. The third terminal of current mirror circuitry 245 is coupled to a power supply terminal that supplies a power supply voltage (V DD ). Combined Figure 10 、 11 , 12, and 13 further illustrate and describe an example of the current mirror circuit system 245.

[0053] Current mirror circuitry 250 has a first terminal, a second terminal, and a third terminal. The first terminal of current mirror circuitry 250 is coupled to buffer circuitry 220. The second terminal of current mirror circuitry 250 is coupled to buffer circuitry 230, class AB control circuitry 255, switch circuitry 265, and transistor 275. The third terminal of current mirror circuitry 250 is coupled to a common terminal that supplies a common voltage (e.g., ground, AVSS, V SS ). Combined Figure 10 、 11 , 12 and 13 further illustrate and describe an example of the current mirror circuit system 250.

[0054] Class AB control circuitry 255 has a first terminal and a second terminal. The first terminal of class AB control circuitry 255 is coupled to buffer circuitry 230, current mirror circuitry 245, switch circuitry 260, and transistor 270. The second terminal of class AB control circuitry 255 is coupled to buffer circuitry 230, current mirror circuitry 250, switch circuitry 265, and transistor 275. Figure 10 、 11 , 12 and 13 further illustrate and describe an example of a class AB control circuit system 255.

[0055] Switching circuitry 260 has a first terminal, a second terminal, and a control terminal. The first terminal of switching circuitry 260 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of switching circuitry 260 is coupled to buffer circuitry 230, current mirror circuitry 245, class AB control circuitry 255, and transistor 270. The control terminal of switching circuitry 260 is coupled to control signal generating circuitry 215, which supplies a first inverted control signal (V OFF1 ).

[0056] Switching circuitry 265 has a first terminal, a second terminal, and a control terminal. The first terminal of switching circuitry 265 is coupled to buffer circuitry 230, current mirror circuitry 250, class AB control circuitry 255, and transistor 275. The second terminal of switching circuitry 265 is coupled to a common terminal, which supplies a common potential. The control terminal of switching circuitry 265 is coupled to control signal generating circuitry 215, which supplies a first control signal (V OFF1 ).exist Figure 2 In an example of , the inverted control signal is an inverted (or 180 degree phase shifted) version of the first control signal. In such an example, the first control signal and the inverted control signal turn the switching circuit systems 260, 265 on and off synchronously.

[0057] Transistor 270 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 270 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 270 is coupled to transistor 275 and the output of amplifier circuitry 200, which supplies an output voltage to downstream circuitry. The control terminal of transistor 270 is coupled to buffer circuitry 230, current mirror circuitry 245, class AB control circuitry 255, and switch circuitry 260.

[0058] Transistor 275 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 275 is coupled to transistor 270 and to the output of amplifier circuitry 200, which supplies an output voltage to downstream circuitry. The second terminal of transistor 275 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 275 is coupled to buffer circuitry 230, current mirror circuitry 250, class AB control circuitry 255, and switch circuitry 265.

[0059] exist Figure 2 In the example of , transistor 275 is an n-channel metal oxide semiconductor field effect transistor (MOSFET). Alternatively, transistor 275 can be an n-channel field effect transistor (FET), an n-channel insulated gate bipolar transistor (IGBT), an n-channel junction field effect transistor (JFET), an NPN bipolar junction transistor (BJT), or a slightly modified p-type equivalent device. Figure 2In the example of FIG, transistor 270 is a p-channel MOSFET. Alternatively, transistor 270 may be a p-channel FET, a p-channel IGBT, a p-channel JFET, a PNP BJT, or a slightly modified n-type equivalent device. Transistors 270 and 275 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structure transistors. Furthermore, transistors 270 and 275 may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0060] Figure 3 is a schematic diagram of an example opposing buffer stage 300, which is Figure 1 and 2 Instances of opposing buffer stages 120, 205. Figure 3 In the example of , opposing buffer stage 300 includes first buffer circuitry 305 , resistor 310 , second buffer circuitry 315 , third buffer circuitry 320 , and switch circuitry 325 . Figure 3 The example buffer circuitry 305 includes a first example voltage source circuitry 330 , a second example voltage source circuitry 335 , a first example transistor 340 , and a second example transistor 345 . Figure 3 The example buffer circuitry 315 includes a first example voltage source circuitry 350 , a second example voltage source circuitry 355 , a first example transistor 360 , and a second example transistor 365 . Figure 3 The example buffer circuitry 320 includes a first example transistor 370 and a second example transistor 375 . Figure 3 The example switching circuitry 325 includes a first example transistor 380 and a second example transistor 385 .

[0061] The opposing buffer stage 300 has a first input, a second input, a third input, a fourth input, a first output, a second output, a third output, and a fourth output. The first input of the opposing buffer stage 300 is configured to be coupled to Figure 1 The input stage 110 supplies the inverting input voltage (V IN_STAGE- The second input of the opposing buffer stage 300 is configured to be coupled to the input stage 110, which supplies the non-inverting input voltage (V IN_STAGE+ In some examples, the second input of the opposing buffer stage 300 is configured to be coupled to a reference input that supplies a reference voltage (V REF ). The third input of the opposing buffer stage 300 is configured to be coupled to Figure 2 The control signal generating circuit system 215 generates a second control signal (V OFF2The fourth input of the opposing buffer stage 300 is configured to be coupled to the control signal generation circuitry 215, which supplies a second inverted control signal (~V OFF2 ).exist Figure 3 In the example of , the second inverted control signal is an inverted version of the second control signal. The first output of the opposing buffer stage 300 is configured to be coupled to Figure 1 and 2 The output stage 130, 210 supplies an inverting sink current (I SNK- The second output of the opposing buffer stage 300 is configured to be coupled to the output stage 130, 210, which receives a non-inverting source current (I SRC+ The third output of the opposing buffer stage 300 is configured to be coupled to an output stage 130, 210 that supplies a non-inverting sink current (I SNK+ The fourth output of the opposing buffer stage 300 is configured to be coupled to the output stage 130, 210, which receives the inverting source current (I SRC- ).

[0062] Buffer circuit system 305 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of buffer circuit system 305 is coupled to switch circuit system 325 and a first input of opposing buffer stage 300, which supplies an inverting input voltage. The second terminal of buffer circuit system 305 is coupled to resistor 310. The third terminal of buffer circuit system 305 is coupled to a first output of opposing buffer stage 300, which supplies an inverting sink current. The fourth terminal of buffer circuit system 305 is coupled to a second output of opposing buffer stage 300, which supplies a non-inverting source current. Buffer circuit system 305 is Figure 2 An example of a buffer circuit system 220 is shown in FIG. Figure 4 、 5 , 6, 10, 11, 12 and 13 further illustrate and describe other examples of buffer circuit system 305.

[0063] Resistor 310 has a first terminal and a second terminal. The first terminal of resistor 310 is coupled to buffer circuitry 305. The second terminal of resistor 310 is coupled to buffer circuitry 315. Resistor 310 is Figure 2 An example of resistor 225.

[0064] The buffer circuit system 315 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of the buffer circuit system 315 is coupled to the second input of the opposing buffer stage 300, which supplies the non-inverting input voltage (V IN_STAGE+). A second terminal of buffer circuitry 315 is coupled to resistor 310. Third and fourth terminals of buffer circuitry 315 are coupled to buffer circuitry 320. A fifth terminal of buffer circuitry 315 is coupled to a third output of opposing buffer stage 300, which supplies a non-inverting sink current. A sixth terminal of buffer circuitry 315 is coupled to a fourth output of opposing buffer stage 300, which supplies an inverting source current. Buffer circuitry 315 is Figure 2 An example of a buffer circuit system 230 is shown in FIG. Figure 4 、 5 , 6, 10, 11, 12 and 13 further illustrate and describe other examples of buffer circuit systems 315.

[0065] Buffer circuit system 320 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first and second terminals of buffer circuit system 320 are coupled to buffer circuit system 315. The third terminal of buffer circuit system 320 is coupled to switch circuit system 325. The fourth terminal of buffer circuit system 320 is coupled to a power supply terminal, which supplies a power supply voltage. The fifth terminal of buffer circuit system 320 is coupled to a common terminal, which supplies a common potential. Buffer circuit system 320 is Figure 2 An example of a buffer circuit system 235 is shown in FIG. Figure 4 、 5 Other examples of buffer circuitry 320 are further shown and described in FIG. 6 .

[0066] Switching circuitry 325 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of switching circuitry 325 is coupled to buffer circuitry 320. The second terminal of switching circuitry 325 is coupled to buffer circuitry 305 and to a first input of opposing buffer stage 300, which supplies an inverted input voltage. The third terminal of switching circuitry 325 is coupled to a third input of opposing buffer stage 300, which supplies a second control signal. The fourth terminal of switching circuitry 325 is coupled to a fourth input of opposing buffer stage 300, which supplies a second inverted control signal. In some examples, switching circuitry 325 is referred to as a transmission gate. Switching circuitry 325 is Figure 2 An example of the switching circuit system 240. Figure 4 、 5 Other examples of switching circuitry 325 are further shown and described in FIG6 .

[0067] Voltage source circuitry 330 has a first terminal and a second terminal. The first terminal of voltage source circuitry 330 is coupled to transistor 340. The second terminal of voltage source circuitry 330 is coupled to voltage source circuitry 335, transistors 380, 385, and a first input of opposing buffer stage 300, which supplies the inverting input voltage.

[0068] Voltage source circuitry 335 has a first terminal and a second terminal. The first terminal of voltage source circuitry 335 is coupled to voltage source circuitry 330, transistors 380, 385, and a first input of opposing buffer stage 300, the first input supplying the inverting input voltage. The second terminal of voltage source circuitry 335 is coupled to transistor 345. In some examples, voltage source circuitry 330, 335 is implemented using transistors and bias current source circuitry. Figure 6 、 10 , 11, 12 and 13 further illustrate and describe such examples.

[0069] Transistor 340 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 340 is coupled to the first output of opposing buffer stage 300, which sinks an inverted current. The second terminal of transistor 340 is coupled to resistor 310 and transistor 345. The control terminal of transistor 340 is coupled to voltage source circuitry 330.

[0070] Transistor 345 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 345 is coupled to resistor 310 and transistor 340. The second terminal of transistor 345 is coupled to the second output of opposing buffer stage 300, which supplies a non-inverting source current. The control terminal of transistor 345 is coupled to voltage source circuitry 335.

[0071] Voltage source circuitry 350 has a first terminal and a second terminal. The first terminal of voltage source circuitry 350 is coupled to transistors 360, 370. The second terminal of voltage source circuitry 350 is coupled to voltage source circuitry 355 and a second input of opposing buffer stage 300, which supplies the non-inverting input voltage.

[0072] Voltage source circuitry 355 has a first terminal and a second terminal. The first terminal of voltage source circuitry 355 is coupled to voltage source circuitry 350 and to a second input of opposing buffer stage 300, which supplies a non-inverting input voltage. The second terminal of voltage source circuitry 355 is coupled to transistors 365, 375. In some examples, voltage source circuitry 350, 355 is implemented using transistors and bias current source circuitry. Figure 6 、 10, 11, 12 and 13 further illustrate and describe such examples.

[0073] Transistor 360 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 360 is coupled to the third output of opposing buffer stage 300, which sinks a non-inverting current. The second terminal of transistor 360 is coupled to resistor 310 and transistor 365. The control terminal of transistor 360 is coupled to voltage source circuitry 350 and transistor 370.

[0074] Transistor 365 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 365 is coupled to resistor 310 and transistor 360. The second terminal of transistor 365 is coupled to the fourth output of opposing buffer stage 300, which supplies an inverted source current. The control terminal of transistor 365 is coupled to voltage source circuitry 355 and transistor 375.

[0075] Transistor 370 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 370 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of transistor 370 is coupled to transistors 375, 380, and 385. The control terminal of transistor 370 is coupled to voltage source circuitry 350 and transistor 360.

[0076] Transistor 375 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 375 is coupled to transistors 370, 380, and 385. The second terminal of transistor 375 is coupled to a common terminal that supplies a common potential. The control terminal of transistor 375 is coupled to voltage source circuitry 355 and transistor 365.

[0077] Transistor 380 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 380 is coupled to voltage source circuitry 330, 335, transistor 385, and a first input of opposing buffer stage 300, which supplies the inverting input voltage. The second terminal of transistor 380 is coupled to transistors 370, 375, and 385. The control terminal of transistor 380 is coupled to a third input of opposing buffer stage 300, which supplies the second control signal.

[0078] Transistor 385 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 385 is coupled to voltage source circuitry 330, 335, transistor 380, and a first input of opposing buffer stage 300, which supplies an inverted input voltage. The second terminal of transistor 385 is coupled to transistors 370, 375, and 380. The control terminal of transistor 385 is coupled to a fourth input of opposing buffer stage 300, which supplies a second inverted control signal.

[0079] exist Figure 3 In the example of , transistors 340, 360, 370, 380 are n-channel MOSFETs. Alternatively, transistors 340, 360, 370, 380 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Figure 3 In the example of FIG, transistors 345, 365, 375, 385 are p-channel MOSFETs. Alternatively, transistors 345, 365, 375, 385 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified N-type equivalent devices. Transistors 340, 345, 360, 365, 370, 375, 380, 385 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structures. Furthermore, transistors 340, 345, 360, 365, 370, 375, 380, 385 may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0080] Figure 4 is a schematic diagram of an example opposing buffer stage 400, which is Figure 1 、 2 and 3 are examples of opposing buffer stages 120, 205, 300. Figure 4 In the example of Figure 3 The buffer circuit system 305, 315, 320, Figure 3 resistor 310 , and switching circuit system 410 . Figure 4 The example buffer circuitry 305 includes Figure 3 The voltage source circuit systems 330, 335 and Figure 3 Transistors 340, 345. Figure 4 The example buffer circuitry 315 includes Figure 3 The voltage source circuit systems 350, 355 and Figure 3 Transistors 360 and 365. Figure 4 The example buffer circuitry 320 includes Figure 3 Transistors 370, 375. Figure 4 The example switching circuitry 410 includes a first example transistor 420 and a second example transistor 430 .

[0081] The opposing buffer stage 400 has a first input, a second input, a third input, a fourth input, a first output, a second output, a third output, and a fourth output. The first input of the opposing buffer stage 400 is configured to be coupled to Figure 1 The input stage 110 supplies the inverting input voltage (V IN_STAGE- The second input of the opposing buffer stage 400 is configured to be coupled to the input stage 110, which supplies the non-inverting input voltage (V IN_STAGE+ In some examples, the second input of the opposing buffer stage 400 is configured to be coupled to a reference input that supplies a reference voltage (V REF ). The third input of the opposing buffer stage 400 is configured to be coupled to Figure 2 The control signal generating circuit system 215 generates a second control signal (V OFF2 The fourth input of the opposing buffer stage 400 is configured to be coupled to the control signal generation circuitry 215, which supplies a second inverted control signal (~V OFF2 ). The first output of the opposing buffer stage 400 is configured to be coupled to Figure 1 and 2 The output stage 130, 210 supplies an inverting sink current (I SNK- The second output of the opposing buffer stage 400 is configured to be coupled to the output stage 130, 210, which receives a non-inverting source current (I SRC+ The third output of the opposing buffer stage 400 is configured to be coupled to an output stage 130, 210 that supplies a non-inverting sink current (I SNK+ The fourth output of the opposing buffer stage 400 is configured to be coupled to the output stage 130, 210, which receives the inverting source current (I SRC- ).

[0082] exist Figure 4 In the example of FIG. 4 , buffer circuitry 320 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first and second terminals of buffer circuitry 320 are coupled to buffer circuitry 315. The third terminal of buffer circuitry 320 is coupled to voltage source circuitry 330, 335, or more generally to buffer circuitry 305, and to a first input of opposing buffer stage 400, which supplies an inverting input voltage. The fourth and fifth terminals of buffer circuitry 320 are coupled to switch circuitry 410.

[0083] Switching circuitry 410 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of switching circuitry 410 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of switching circuitry 410 is coupled to a third input of opposing buffer stage 400, which supplies a second control signal. The third and fourth terminals of switching circuitry 410 are coupled to buffer circuitry 320. The fifth terminal of switching circuitry 410 is coupled to a fourth input of opposing buffer stage 400, which supplies a second inverted control signal. The sixth terminal of switching circuitry 410 is coupled to a common terminal, which supplies a common voltage. Switching circuitry 410 is an example of an alternative placement of switching circuitry 240 and 325.

[0084] and Figure 3 Unlike the example of FIG1 , switch circuitry 410 controls the supply of current to transistors 370, 375, or more generally, to buffer circuitry 320. Advantageously, when switch circuitry 410 is closed, this positioning of switch circuitry 410 reduces the impedance between buffer circuitry 305, 320. Advantageously, reducing the impedance between buffer circuitry 305, 320 increases the drive strength of the output of buffer circuitry 320 at the input of buffer circuitry 305. Advantageously, switch circuitry 410 reduces the power consumption of buffer circuitry 320 during normal operation of amplifier circuitry 100 in response to preventing power from being supplied to transistors 370, 375.

[0085] Transistor 420 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 420 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of transistor 420 is coupled to transistor 370. The control terminal of transistor 420 is coupled to a fourth input of opposing buffer stage 400 that supplies a second inverted control signal.

[0086] Transistor 430 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 430 is coupled to transistor 375. The second terminal of transistor 430 is coupled to a common terminal, which supplies a common voltage. The control terminal of transistor 430 is coupled to a third input of opposing buffer stage 400, which supplies a second control signal.

[0087] exist Figure 4 In the example of , transistors 340, 360, 370, 430 are n-channel MOSFETs. Alternatively, transistors 340, 360, 370, 430 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Figure 4In the example of FIG, transistors 345, 365, 375, 420 are p-channel MOSFETs. Alternatively, transistors 345, 365, 375, 420 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified N-type equivalent devices. Transistors 340, 345, 360, 365, 370, 375, 420, 430 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structure transistors. Furthermore, transistors 340, 345, 360, 365, 370, 375, 420, 430 may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0088] Figure 5 is a schematic diagram of an example opposing buffer stage 500, which is Figure 1 、 2 , 3 and 4 of the opposing buffer stages 120, 205, 300, 400. Figure 5 In the example of Figure 3 and 4 The buffer circuit system 305, 315, 320, Figure 3 and 4 Resistor 310, Figure 4 The switching circuit system 410, the first current mirror circuit system 510 and the second current mirror circuit system 520. Figure 5 The example buffer circuitry 305 includes Figure 3 and 4 The voltage source circuit systems 330, 335 and Figure 3 and 4 Transistors 340, 345. Figure 5 The example buffer circuitry 315 includes Figure 3 and 4 The voltage source circuit systems 350, 355 and Figure 3 and 4 Transistors 360 and 365. Figure 5 The example buffer circuitry 320 includes Figure 3 and 4 Transistors 370, 375. Figure 5 The example switching circuitry 410 includes Figure 4 Transistors 420 and 430. Figure 5 The example current mirror circuitry 510 includes a first example transistor 530 and a second example transistor 540 . Figure 5 The example current mirror circuitry 520 includes a first example transistor 550 and a second example transistor 560 .

[0089] The opposing buffer stage 500 has a first input, a second input, a third input, a fourth input, a first output, a second output, a third output, and a fourth output. The first input of the opposing buffer stage 500 is configured to be coupled to Figure 1 The input stage 110 supplies the inverting input voltage (V IN_STAGE- The second input of the opposing buffer stage 500 is configured to be coupled to the input stage 110, which supplies the non-inverting input voltage (V IN_STAGE+ In some examples, the second input of the opposing buffer stage 500 is configured to be coupled to a reference input that supplies a reference voltage (V REF ). The third input of the opposing buffer stage 500 is configured to be coupled to Figure 2 The control signal generating circuit system 215 generates a second control signal (V OFF2 The fourth input of the opposing buffer stage 500 is configured to be coupled to the control signal generation circuitry 215, which supplies a second inverted control signal (~V OFF2 ). The first output of the opposing buffer stage 500 is configured to be coupled to Figure 1 and 2 The output stage 130, 210 supplies an inverting sink current (I SNK- The second output of the opposing buffer stage 500 is configured to be coupled to the output stage 130, 210, which receives a non-inverting source current (I SRC+ The third output of the opposing buffer stage 500 is configured to be coupled to an output stage 130, 210 that supplies a non-inverting sink current (I SNK+ The fourth output of the opposing buffer stage 500 is configured to be coupled to the output stage 130, 210, which receives the inverting source current (I SRC- ).

[0090] exist Figure 5 In the example of FIG, switch circuitry 410 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of switch circuitry 410 is coupled to current mirror circuitry 510. The second terminal of switch circuitry 410 is coupled to a third input of opposing buffer stage 400, which supplies a second control signal. The third and fourth terminals of switch circuitry 410 are coupled to buffer circuitry 320. The fifth terminal of switch circuitry 410 is coupled to a fourth input of opposing buffer stage 400, which supplies a second inverted control signal. The sixth terminal of switch circuitry 410 is coupled to current mirror circuitry 520.

[0091] Current mirror circuitry 510 has a first terminal, a second terminal, and a third terminal. The first terminal of current mirror circuitry 510 is coupled to switch circuitry 410. The second terminal of current mirror circuitry 510 is coupled to buffer circuitry 305, 320, current mirror circuitry 520, and a first input of opposing buffer stage 500, which supplies an inverting input voltage. The third terminal of current mirror circuitry 510 is coupled to a power supply terminal, which supplies a power supply voltage.

[0092] Current mirror circuitry 520 has a first terminal, a second terminal, and a third terminal. The first terminal of current mirror circuitry 520 is coupled to switch circuitry 410. The second terminal of current mirror circuitry 520 is coupled to buffer circuitry 305, 320, current mirror circuitry 510, and a first input of opposing buffer stage 500, which supplies an inverted input voltage. The third terminal of current mirror circuitry 520 is coupled to a common terminal, which supplies a common potential.

[0093] The transistor 530 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 530 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal and the control terminal of the transistor 530 are coupled to the transistors 420 and 540.

[0094] Transistor 540 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 540 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 540 is coupled to voltage source circuitry 330, 335, transistors 370, 375, 560, and a first input of opposing buffer stage 500, which supplies an inverting input voltage. The control terminal of transistor 540 is coupled to transistors 420, 530.

[0095] The transistor 550 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of the transistor 550 are coupled to the transistors 430 and 560. The second terminal of the transistor 550 is coupled to a common terminal, which supplies a common potential.

[0096] Transistor 560 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 560 is coupled to voltage source circuitry 330, 335, transistors 370, 375, 540, and a first input of opposing buffer stage 500, which supplies an inverting input voltage. The second terminal of transistor 560 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 560 is coupled to transistors 430, 550.

[0097] exist Figure 5In the example of , transistors 340, 360, 370, 430, 550, 560 are n-channel MOSFETs. Alternatively, transistors 340, 360, 370, 430, 550, 560 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Figure 5 In the example of FIG. 3 , transistors 345, 365, 375, 420, 530, and 540 are p-channel MOSFETs. Alternatively, transistors 345, 365, 375, 420, 530, and 540 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified N-type equivalents. Transistors 340, 345, 360, 365, 370, 375, 420, 430, 530, 540, 550, and 560 may be depletion-mode devices, extended drain devices, enhancement-mode devices, native transistors, or other types of device structures. Furthermore, transistors 340 , 345 , 360 , 365 , 370 , 375 , 420 , 430 , 530 , 540 , 550 , 560 may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0098] and Figure 4 Unlike the example of , the buffer circuitry 320 and the current mirror circuitry 510, 520 are coupled to the input of the buffer circuitry 305. Figure 5 In the example of FIG, the current mirror circuit systems 510, 520 mirror the current conducted through the transistors 370, 375 to supply the source control current (I CTRL_SRC ) and absorbs the control current (I CTRL_SNK ). Advantageously, the additional current from current mirror circuitry 510, 520 and the current from transistors 370, 375 set the input of buffer circuitry 305. Advantageously, the size of transistors 370, 375 can be reduced in response to the additional current from current mirror circuitry 510, 520 providing additional drive strength. Advantageously, sizing the length and width of the channels of transistors 530, 540, 550, 560 by a ratio factor (n) allows current mirror circuitry 510, 520 to amplify the current of transistors 370, 375. Advantageously, the size of transistors 370, 375 can be further reduced by sizing transistors 530, 540, 550, 560 to amplify the current through transistors 370, 375. Advantageously, reducing the size of transistors 370, 375 improves the linear performance of opposing buffer stage 500 by reducing nonlinear parasitic capacitance at the first input of opposing buffer stage 500.

[0099] Figure 6is a schematic diagram of an example amplifier circuit system 600 including an example input stage 605 (which is Figure 1 ) and an example opposing buffer stage 610 (which is Figure 1 、 2 , 3, 4 and 5 of the opposing buffer stages 120, 205, 300, 400, 500 instances). Figure 6 The example input stage 605 includes an example transconductance circuit system 615, a first example current source circuit system 620, a first example transistor 625, a first example voltage source circuit system 630, a second example transistor 635, a second example voltage source circuit system 640, a second example current source circuit system 645, a third example transistor 650, a third example voltage source circuit system 655, a fourth example transistor 660 and a fourth example voltage source circuit system 665. Figure 6 The example opposing buffer stage 610 includes Figure 3 、 4 and 5 resistors 310, Figure 3 、 4 and the buffer circuit system 315 of 5, Figure 4 and 5 The switching circuit system 410, Figure 5 The current mirror circuit systems 510, 520, the first example buffer circuit system 668, the first example current source circuit system 672, the second example current source circuit system 676 and the second example buffer circuit system 680. Figure 6 The example buffer circuitry 315 includes Figure 3 、 4 and 5 voltage source circuit systems 350, 355 and Figure 3 、 4 and transistors 360, 365 of 5. Figure 6 The example switching circuitry 410 includes Figure 4 and 5 Transistors 420 and 430. Figure 6 The example current mirror circuit system 510 includes Figure 5 Transistors 530 and 540. Figure 6 The example current mirror circuit system 520 includes Figure 5 Transistors 550 and 560. Figure 6 The example buffer circuitry 668 includes a first example transistor 682 , a second example transistor 684 , a third example transistor 686 , and a fourth example transistor 688 . Figure 6 The example buffer circuitry 680 includes a first example transistor 690 and a second example transistor 692 .

[0100] The amplifier circuit system 600 has a first input, a second input, a first output, a second output, a third output, and a fourth output. The first input (also referred to as the non-inverting input) of the amplifier circuit system 600 is configured to be coupled to an external circuit system that supplies a non-inverting input signal (V IN+ The second input (also referred to as the inverting input) of the amplifier circuitry 600 is configured to be coupled to an external circuitry that supplies the inverting input signal (V IN- ). The first output of the amplifier circuit system 600 is configured to be coupled to Figure 1 and 2 The output stage 130, 210 supplies an inverting sink current (I SNK- The second output of the amplifier circuit system 600 is configured to be coupled to the output stage 130, 210, which receives a non-inverting source current (I SRC+ The third output of the amplifier circuit system 600 is configured to be coupled to an output stage 130, 210 that supplies a non-inverting sink current (I SNK+ ). The fourth output of the amplifier circuit system 600 is configured to be coupled to the output stage 130, 210, which receives the inverting source current (I SRC- ).exist Figure 6 In the example of , amplifier circuit system 600 includes input stage 605 and opposing buffer stage 610. However, in some examples, amplifier circuit system 600 includes additional stages, such as Figure 1 and 2 Output stages 130 , 210 .

[0101] Input stage 605 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of input stage 605 is coupled to a first input of amplifier circuitry 600, which supplies a non-inverting input signal. The second terminal of input stage 605 is coupled to a second input of amplifier circuitry 600, which supplies an inverting input signal. The third, fourth, and fifth terminals of input stage 605 are coupled to opposing buffer stage 610.

[0102] The opposing buffer stage 610 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, and an eighth terminal. The first, second, and third terminals of the opposing buffer stage 610 are coupled to the input stage 605. The fourth terminal of the opposing buffer stage 610 is coupled to a reference terminal of the opposing buffer stage 610, which supplies a fixed reference voltage as a non-inverting input voltage (V IN_STAGE+). A fifth terminal of opposing buffer stage 610 is coupled to a first output of amplifier circuitry 600, which sinks an inverting current. A sixth terminal of opposing buffer stage 610 is coupled to a second output of amplifier circuitry 600, which supplies a non-inverting current. A seventh terminal of opposing buffer stage 610 is coupled to a third output of amplifier circuitry 600, which sinks a non-inverting current. An eighth terminal of opposing buffer stage 610 is coupled to a fourth output of amplifier circuitry 600, which supplies an inverting current.

[0103] Transconductance circuit system 615 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of transconductance circuit system 615 is coupled to a first input of amplifier circuit system 600, which supplies a non-inverting input signal. The second terminal of transconductance circuit system 615 is coupled to a second input of amplifier circuit system 600, which supplies an inverting input signal. The third terminal of transconductance circuit system 615 is coupled to current source circuit system 620 and transistor 625. The fourth terminal of transconductance circuit system 615 is coupled to current source circuit system 645 and transistor 650.

[0104] The current source circuit system 620 has a first terminal and a second terminal. The first terminal of the current source circuit system 620 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of the current source circuit system 620 is coupled to the transconductance circuit system 615 and the transistor 625.

[0105] Transistor 625 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 625 is coupled to transconductance circuitry 615 and current source circuitry 620. The second terminal of transistor 625 is coupled to transistors 540 and 635. The control terminal of transistor 625 is coupled to voltage source circuitry 630.

[0106] The voltage source circuit system 630 has a first terminal and a second terminal. The first terminal of the voltage source circuit system 630 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of the voltage source circuit system 630 is coupled to the transistor 625.

[0107] Transistor 635 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 635 is coupled to transistors 540, 625. The second terminal of transistor 635 is coupled to transistors 660, 682, 684. The control terminal of transistor 635 is coupled to voltage source circuitry 640.

[0108] The voltage source circuit system 640 has a first terminal and a second terminal. The first terminal of the voltage source circuit system 640 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of the voltage source circuit system 640 is coupled to the transistor 635.

[0109] The current source circuit system 645 has a first terminal and a second terminal. The first terminal of the current source circuit system 645 is coupled to the transconductance circuit system 615 and the transistor 650. The second terminal of the current source circuit system 645 is coupled to a common terminal, which supplies a common potential.

[0110] Transistor 650 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 650 is coupled to transistors 560, 660. The second terminal of transistor 650 is coupled to transconductance circuitry 615 and current source circuitry 645. The control terminal of transistor 650 is coupled to voltage source circuitry 655.

[0111] The voltage supply circuit system 655 has a first terminal and a second terminal. The first terminal of the voltage supply circuit system 655 is coupled to the transistor 650. The second terminal of the voltage supply circuit system 655 is coupled to a common terminal, which supplies a common potential.

[0112] Transistor 660 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 660 is coupled to transistors 635, 682, and 684. The second terminal of transistor 660 is coupled to transistors 560 and 650. The control terminal of transistor 660 is coupled to voltage source circuitry 665. In some examples, transistors 635 and 660 can be referred to as injection cascode transistors or cascode circuitry.

[0113] The voltage supply circuit system 665 has a first terminal and a second terminal. The first terminal of the voltage supply circuit system 665 is coupled to the transistor 660. The second terminal of the voltage supply circuit system 665 is coupled to a common terminal, which supplies a common potential.

[0114] Buffer circuit system 668 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, an eighth terminal, a ninth terminal, and a tenth terminal. The first terminal of buffer circuit system 668 is coupled to transistors 635 and 660. The second terminal of buffer circuit system 668 is coupled to current source circuit system 672. The third terminal of buffer circuit system 668 is coupled to a power supply terminal, which supplies a power supply voltage. The fourth terminal of buffer circuit system 668 is coupled to the first output of amplifier circuit system 600, which sinks an inverting current. The fifth and sixth terminals of buffer circuit system 668 are coupled to buffer circuit system 680. The seventh terminal of buffer circuit system 668 is coupled to resistor 310. The eighth terminal of buffer circuit system 668 is coupled to the second output of amplifier circuit system 600, which supplies a non-inverting current. The ninth terminal of buffer circuit system 668 is coupled to a common terminal, which supplies a common potential. The tenth terminal of buffer circuit system 668 is coupled to current source circuit system 676.

[0115] The current source circuit system 672 has a first terminal and a second terminal. The first terminal of the current source circuit system 672 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of the current source circuit system 672 is coupled to the transistors 682, 686, 692.

[0116] The current source circuit system 676 has a first terminal and a second terminal. The first terminal of the current source circuit system 676 is coupled to the transistors 684, 688, 690. The second terminal of the current source circuit system 676 is coupled to a common terminal, which supplies a common potential.

[0117] Buffer circuitry 680 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. A first terminal of buffer circuitry 680 is coupled to voltage source circuitry 350, 355 and to the input of opposing buffer stage 610, which supplies the non-inverting input voltage. A second terminal of buffer circuitry 680 is coupled to current source circuitry 672 and transistors 682, 686. A third terminal of buffer circuitry 680 is coupled to transistor 420. A fourth terminal of buffer circuitry 680 is coupled to current source circuitry 676 and transistors 684, 688. A fifth terminal of buffer circuitry 680 is coupled to transistor 430.

[0118] Transistor 682 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 682 is coupled to current source circuitry 672 and transistors 686 and 692. The second terminal of transistor 682 is coupled to a common terminal that supplies a common potential. The control terminal of transistor 682 is coupled to transistors 635, 660, and 684.

[0119] Transistor 684 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 684 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of transistor 684 is coupled to current source circuitry 676 and transistors 688 and 690. The control terminal of transistor 684 is coupled to transistors 635, 660, and 682.

[0120] Transistor 686 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 686 is coupled to the first output of amplifier circuitry 600, which sinks an inverted current. The second terminal of transistor 686 is coupled to resistor 310 and transistor 688. The control terminal of transistor 686 is coupled to current source circuitry 672 and transistors 682 and 692.

[0121] Transistor 688 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 688 is coupled to resistor 310 and transistor 686. The second terminal of transistor 688 is coupled to the second output of amplifier circuitry 600, which supplies a non-inverting source current. The control terminal of transistor 688 is coupled to current source circuitry 676 and transistors 684 and 690.

[0122] Transistor 690 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 690 is coupled to transistor 420. The second terminal of transistor 690 is coupled to current source circuitry 676 and transistors 684 and 688. The control terminal of transistor 690 is coupled to voltage source circuitry 350 and 355, transistor 692, and an input of opposing buffer stage 610, which supplies the non-inverting input voltage.

[0123] Transistor 692 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 692 is coupled to current source circuitry 672 and transistors 682, 686. The second terminal of transistor 692 is coupled to transistor 430. The control terminal of transistor 692 is coupled to voltage source circuitry 350, 355, transistor 690, and an input of opposing buffer stage 610, which supplies the non-inverting input voltage.

[0124] exist Figure 6In the example of , transistors 360, 430, 550, 560, 650, 660, 684, 686, 690 are n-channel MOSFETs. Alternatively, transistors 360, 430, 550, 560, 650, 660, 684, 686, 690 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Figure 6 In the example of FIG. 3 , transistors 365, 420, 530, 540, 625, 635, 682, 688, and 692 are p-channel MOSFETs. Alternatively, transistors 365, 420, 530, 540, 625, 635, 682, 688, and 692 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified N-type equivalents. Transistors 360, 365, 420, 430, 530, 540, 550, 560, 625, 635, 650, 660, 682, 684, 686, 688, 690, and 692 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structures. Furthermore, transistors 360 , 365 , 420 , 430 , 530 , 540 , 550 , 560 , 625 , 635 , 650 , 660 , 682 , 684 , 686 , 688 , 690 , 692 may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0125] and Figure 5 Unlike the example of , current mirror circuitry 510, 520 is coupled to transistors 635, 660 of input stage 605. Figure 6 In the example of , transistors 635, 660 combine the current from current mirror circuitry 510, 520 and the current from transistors 625, 650 to set the input of buffer circuitry 668. Advantageously, transistors 635, 660 allow current mirror circuitry 510, 520 to drive the input of buffer circuitry 668 without increasing nonlinear capacitance at the input of buffer circuitry 668. Figure 5 Unlike the example of , transistors 690, 692 of buffer circuitry 680 are coupled between the control terminals of switch circuitry 410 and transistors 686, 688 of buffer circuitry 668. Figure 6In the example of FIG, transistors 682, 684 isolate transistors 690, 692 from the input of buffer circuitry 668. Advantageously, transistors 682, 684 can drive buffer circuitry 680 without adding nonlinear capacitance at the input of buffer circuitry 668. Advantageously, reducing the nonlinear capacitance at the input of buffer circuitry 668 improves the linear performance of amplifier circuitry 600.

[0126] Figure 7A is an example control signal generating circuit system 700 (which is Figure 2 Schematic diagram of an example of a control signal generating circuit system 215). Figure 7A In the example of FIG. 5 , the control signal generating circuitry 700 includes a first inverter circuitry 705 , a second inverter circuitry 710 , a delay circuitry 715 , and a third inverter circuitry 720 . Figure 7A The example inverter circuitry 705 includes a first example transistor 725 and a second example transistor 730 . Figure 7A The example inverter circuitry 710 includes a first example transistor 735 and a second example transistor 740 . Figure 7A The example delay circuitry 715 includes a first example transistor 745 , a second example transistor 750 , an example resistor 755 , an example capacitor 760 , a third example transistor 765 , and a fourth example transistor 770 . Figure 7A The example inverter circuitry 720 includes a first example transistor 775 and a second example transistor 780 .

[0127] The control signal generating circuit system 700 has an input, a first output, a second output, a third output, and a fourth output. The input of the control signal generating circuit system 700 is configured to be coupled to an external circuit system that supplies a reference control signal (V OFF0 ). The first output of the control signal generating circuit system 700 is configured to be coupled to Figure 2 The switch circuit system 260 receives a first inverted control signal (V OFF1 ). The second output of the control signal generating circuit system 700 is configured to be coupled to Figure 2 The switch circuit system 265 receives a first control signal (V OFF1 ). The third output of the control signal generating circuit system 700 is configured to be coupled to Figure 2 The switching circuit system 240 and Figure 3 、 4 , 5 and 6 transistors 380, 430, which receive a second control signal (V OFF2 ). The fourth output of the control signal generating circuit system 700 is configured to be coupled to Figure 2 The switching circuit system 240 and Figure 3 、 4 , 5 and 6 transistors 385, 420, which receive a second inverted control signal (~V OFF2 ).

[0128] Inverter circuitry 705 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of inverter circuitry 705 is coupled to an input of control signal generation circuitry 700, which supplies a reference control signal. The second terminal of inverter circuitry 705 is coupled to inverter circuitry 710 and a first output of control signal generation circuitry 700, which supplies a first inverted control signal. The third terminal of inverter circuitry 705 is coupled to a power supply terminal, which supplies a power supply voltage. The fourth terminal of inverter circuitry 705 is coupled to a common terminal, which supplies a common potential.

[0129] Inverter circuitry 710 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of inverter circuitry 710 is coupled to inverter circuitry 705 and a first output of control signal generation circuitry 700, the first output supplying a first inverted control signal. The second terminal of inverter circuitry 710 is coupled to delay circuitry 715 and a second output of control signal generation circuitry 700, the second output supplying the first control signal. The third terminal of inverter circuitry 710 is coupled to a power supply terminal supplying a power supply voltage. The fourth terminal of inverter circuitry 710 is coupled to a common terminal supplying a common potential.

[0130] Delay circuitry 715 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of delay circuitry 715 is coupled to inverter circuitry 710 and the second output of control signal generation circuitry 700, which supplies a first control signal. The second terminal of delay circuitry 715 is coupled to inverter circuitry 720 and the third output of control signal generation circuitry 700, which supplies a second control signal. The third terminal of delay circuitry 715 is coupled to a power supply terminal, which supplies a power supply voltage. The fourth terminal of delay circuitry 715 is coupled to a common terminal, which supplies a common potential.

[0131] Inverter circuitry 720 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of inverter circuitry 720 is coupled to delay circuitry 715 and a third output of control signal generation circuitry 700, which supplies a second control signal. The second terminal of inverter circuitry 720 is coupled to a fourth output of control signal generation circuitry 700, which supplies a second inverted control signal. The third terminal of inverter circuitry 720 is coupled to a power supply terminal, which supplies a power supply voltage. The fourth terminal of inverter circuitry 720 is coupled to a common terminal, which supplies a common potential.

[0132] Transistor 725 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 725 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 725 is coupled to transistors 730, 735, and 740, and to a first output of control signal generation circuitry 700, which supplies a first inverted control signal. The control terminal of transistor 725 is coupled to transistor 730 and to an input of control signal generation circuitry 700, which supplies a reference control signal.

[0133] Transistor 730 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 730 is coupled to transistors 725, 735, and 740 and to a first output of control signal generation circuitry 700, which supplies a first inverted control signal. The second terminal of transistor 730 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 730 is coupled to transistor 725 and to an input of control signal generation circuitry 700, which supplies a reference control signal.

[0134] Transistor 735 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 735 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 735 is coupled to transistors 740, 745, and 750 and a second output of control signal generation circuitry 700, which supplies a first control signal. The control terminal of transistor 735 is coupled to transistors 725, 730, and 740 and a first output of control signal generation circuitry 700, which supplies a first inverted control signal.

[0135] Transistor 740 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 740 is coupled to transistors 735, 745, and 750 and to a second output of control signal generation circuitry 700, which supplies a first control signal. The second terminal of transistor 740 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 740 is coupled to transistors 725, 730, and 735 and to a first output of control signal generation circuitry 700, which supplies a first inverted control signal.

[0136] Transistor 745 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 745 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of transistor 745 is coupled to resistor 755. The control terminal of transistor 745 is coupled to transistors 735, 740, and 750 and a second output of control signal generation circuitry 700 that supplies a first control signal.

[0137] Transistor 750 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 750 is coupled to resistor 755, capacitor 760, and transistors 765 and 770. The second terminal of transistor 750 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 750 is coupled to transistors 735, 740, and 745 and a second output of control signal generation circuitry 700, which supplies a first control signal.

[0138] Resistor 755 has a first terminal and a second terminal. The first terminal of resistor 755 is coupled to transistor 745. The second terminal of resistor 755 is coupled to transistors 750, 765, 770 and capacitor 760.

[0139] Capacitor 760 has a first terminal and a second terminal. The first terminal of capacitor 760 is coupled to transistors 750, 765, 770 and resistor 755. The second terminal of capacitor 760 is coupled to a common terminal that supplies a common potential. Figure 7A In the example of , resistor 755 and capacitor 760 are configured to have a timing constant that is proportional to the resistance of resistor 755 and the capacitance of capacitor 760 .

[0140] Transistor 765 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 765 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 765 is coupled to transistors 770, 775, and 780 and a third output of control signal generation circuitry 700, which supplies a second control signal. The control terminal of transistor 765 is coupled to transistors 750 and 770, resistor 755, and capacitor 760.

[0141] Transistor 770 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 770 is coupled to transistors 765, 775, and 780 and a third output of control signal generation circuitry 700, which supplies a second control signal. The second terminal of transistor 770 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 770 is coupled to transistors 750, 765, resistor 755, and capacitor 760.

[0142] Transistor 775 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 775 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of transistor 775 is coupled to transistor 780 and to a fourth output of control signal generation circuitry 700, which supplies a second inverted control signal. The control terminal of transistor 775 is coupled to transistors 765, 770, and 780 and to a third output of control signal generation circuitry 700, which supplies a second control signal.

[0143] Transistor 780 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 780 is coupled to transistor 775 and to a fourth output of control signal generation circuitry 700, which supplies a second inverted control signal. The second terminal of transistor 780 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 780 is coupled to transistors 765, 770, and 775 and to a third output of control signal generation circuitry 700, which supplies a second control signal.

[0144] exist Figure 7A In the example of , transistors 730, 740, 750, 770, 780 are n-channel MOSFETs. Alternatively, transistors 730, 740, 750, 770, 780 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Figure 7AIn the example of FIG, transistors 725, 735, 745, 765, 775 are p-channel MOSFETs. Alternatively, transistors 725, 735, 745, 765, 775 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified N-type equivalent devices. Transistors 725, 730, 735, 740, 745, 750, 765, 770, 775, 780 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structures. Furthermore, transistors 725, 730, 735, 740, 745, 750, 765, 770, 775, 780 may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0145] Figure 7B yes Figure 2 and 7A A timing diagram 785 of an example operation of the control signal generating circuitry 215, 700 is shown. Figure 7B In the example of FIG. 7 , the timing diagram 785 includes a first example control signal 790 (V OFF1 ) and the second control signal 795 (V OFF2 ). The first control signal 790 shows an example transition from a power-off state to normal operation. Figure 2 The second control signal 795 shows the state of the switching circuit system 260, 265 during the example transition from the power-off state to normal operation. Figure 2 、 3 , 4 and 5 of the switching circuit systems 240, 325, 410.

[0146] In the example operation of timing diagram 785, the transition from the power-down state to normal operation begins in response to the falling edge of the first control signal 790. Resistor 755 and capacitor 760 delay the falling edge of the first control signal 790 through the delay circuit system 715 to create a delay before generating the falling edge of the second control signal 795. The delay between the falling edges of the control signals 790, 795 allows the amplifier circuit systems 100, 200 to operate without being based on Figure 1 、 2, 3, 4, 5, and 6 opposing buffer stages 120, 205, 300, 400, 500, 610 have time to settle before the second inputs of the opposing buffer stages 120, 205, 300, 400, 500, 610 drive the first inputs of the opposing buffer stages 120, 205, 300, 400, 500, 610. Advantageously, the timing constant of resistor 755 and capacitor 760 creates a delay between the control signals 790, 795. Advantageously, the delay between the control signals 790, 795 reduces transient voltages at the output of the amplifier circuitry 100, 200 when transitioning from a powered-down state to normal operation.

[0147] Figure 8 is a flow diagram representing example machine-readable instructions or example operations 800 that may be used Figure 1 、 2 , 3, 4, 5 and 6 of the opposing buffer stages 120, 205, 300, 400, 500, 610 or more generally Figure 1 and 2 Implementations of the exemplary embodiments of the amplifier circuit systems 100, 200 may be performed, instantiated, and / or implemented. Figure 8 The example operations 800 begin at block 805, when Figure 2 and 7A The control signal generating circuit system 215, 700 determines whether the amplifier is in a power-off state. In some examples, Figure 7A The inverter circuit system 705 or more generally the control signal generating circuit system 215, 700 receives a reference control signal (V OFF0 ). In such an instance, the reference control signal is responsive to Figure 7A Inverter circuit systems 705, 710, 720 and Figure 7A The delay circuit system 715 controls the state of the amplifier circuit system 100, 200, generates a control signal (e.g., V OFF1 、~V OFF1 、V OFF2 、~V OFF2 ).

[0148] If the control signal generation circuitry 215, 700 determines that the amplifier is in the power-off state (eg, block 805 returns a "yes" result), then Figure 2 The switch circuitry 260, 265 turns off the output stage circuitry. (Block 810). In some examples, the inverter circuitry 705 generates a first inverted control signal (~V OFF1 ), its control Figure 2 The switch circuit system 260 and the inverter circuit system 710 generate a first control signal (V OFF1 ), its control Figure 2In example operation, in response to the reference control signal being in a first state (e.g., logic 1, logic high, etc.), the inverter circuitry 705 clears the first inverting control signal and the inverter circuitry 710 sets the first control signal. In such example operation, the first control signal closes the switch circuitry 265 to disable the first inverting control signal. Figure 2 transistor 275, and the first inverted control signal closes the switch circuit system 260 to disable Figure 2 transistor 270.

[0149] Figure 2 、 3 , 4, 5, and 6 buffer circuit systems 235, 320, 680 drive the first input of the opposing buffer stage to the potential of the second input. (Block 815). In some examples, the delay circuit system 715 generates a second control signal (V OFF2 ), which controls the switch circuitry 240, 325, 410, and the inverter circuitry 720 generates a second inverted control signal (~V OFF2 ), which may also control the switch circuitry 240, 325, 410. In example operation, in response to the first control signal being in a first state (e.g., logic 1, logic high, etc.), the delay circuitry 715 sets the second control signal and the inverter circuitry 720 clears the second inverted control signal. In such example operation, the second control signal closes the switch circuitry 240 or enables Figure 3 、 4 , 5 and 6 transistors 380, 430, and the second inverted control signal enables Figure 3 、 4 , 5, and 6. Advantageously, switch circuitry 240, 325, 410 configures buffer circuitry 235, 320, 680 to drive the first input of opposing buffer stage circuitry 120, 205, 300, 400, 500, 610 based on the second input of opposing buffer stage circuitry 120, 205, 300, 400, 500, 610 during the power-down state.

[0150] In some instances, for example Figure 4 , the switch circuit system 410 is constructed to control Figure 3 、 4The supply of current to transistors 370, 375, or more generally, buffer circuitry 320, by switching circuitry 410 reduces the impedance between buffer circuitry 305, 320. Advantageously, when switching circuitry 410 is closed, this positioning of switching circuitry 410 reduces the impedance between buffer circuitry 305, 320. Advantageously, reducing the impedance between buffer circuitry 305, 320 increases the drive strength of the output of buffer circuitry 320 at the input of buffer circuitry 305. Advantageously, switching circuitry 410 reduces the power consumption of buffer circuitry 320 during normal operation of amplifier circuitry 100 in response to preventing power from being supplied to transistors 370, 375.

[0151] In other examples, for example Figure 5 Configuring current mirror circuitry 510, 520 to supply additional current at the inverting input of opposing buffer stage 500 reduces the size of transistors 370, 375. In such an example, the size of transistors 530, 540, 550, 560 can be scaled to supply a current that is several times greater than the current from transistors 370, 375. For example, transistors 370, 375 can be reduced by a factor of a ratio factor (n) plus one in response to the ratio of the size of transistors 540, 560 to the ratio factor of transistors 370, 375, 530, 550 being one. Advantageously, using current mirror circuitry 510, 520 to supply a portion of the current required to set the inverting input of opposing buffer stage 500 reduces the size of transistors 370, 375. Advantageously, reducing the size of transistors 370, 375 increases the linearity of opposing buffer stage 500 in response to reducing the parasitic capacitance of the relatively large transistors between buffer circuitry 305, 320.

[0152] In yet another example, for example Figure 6 , the input stage 605 is constructed using Figure 6 The transistors 635, 660 combine the currents from the current mirror circuit systems 510, 520 to further improve the linearity of the amplifier circuit systems 100, 200. In some examples, the differential voltage (V IN_STAGE_DIFF )exist Figure 6690, 692, which causes buffer circuitry 680 to conduct current. In example operation, current mirror circuitry 510, 520 supplies current to transistors 635, 660 in response to transistors 690, 692 conducting current. In such example operation, transistors 635, 660 drive the inverting input voltage at the input of buffer circuitry 668, which reduces the differential voltage at the input of opposing buffer stage 610. Advantageously, using transistors 635, 660 to drive opposing buffer stage 610 does not add nearby parasitic capacitance at the inverting input of opposing buffer stage 610. In some examples, the operation of transistors 635, 660 can be referred to as injection cascode.

[0153] If the control signal generation circuitry 215, 700 determines that the amplifier is not in the power-down state (e.g., block 805 returns a "no" result) or control continues from block 815, the control signal generation circuitry 215, 700 determines whether the amplifier is leaving the power-down state (block 820). In some examples, the inverter circuitry 705, 710, 720 and the delay circuitry 715 update the control signals in response to changes in the reference control signal at the input of the control signal generation circuitry 215, 700. For example, the control signal generation circuitry 215, 700 may determine that the amplifier circuitry 100, 200 is leaving the power-down state in response to a falling edge of the reference control signal.

[0154] If the control signal generation circuitry 215, 700 determines that the amplifier is leaving the power down state (e.g., block 820 returns a “yes” result), the switch circuitry 260, 265 turns on the output stage circuitry. (Block 825). In some examples, the inverter circuitry 705 generates a first inverted control signal (~V OFF1 ), which controls the switch circuit system 260, and the inverter circuit system 710 generates a first control signal (V OFF1 ), which controls switch circuitry 265. In example operation, in response to the reference control signal being in a second state (e.g., logic zero, logic low, etc.), inverter circuitry 705 sets the first inverted control signal, and inverter circuitry 710 clears the first control signal. In such example operation, the first control signal turns off switch circuitry 265 to enable transistor 275, and the first inverted control signal turns off switch circuitry 260 to enable transistor 270.

[0155] The control signal generating circuitry 215, 700 allows the amplifier to stabilize. (Block 830). In some examples, Figure 7A The resistor 755 and Figure 7ACapacitor 760 forms a resistor-capacitor (RC) circuit with a resistor-capacitor time constant (also referred to as τ) that delays the falling edge. For example, the RC circuit of resistor 755 and capacitor 760 begins charging in response to the falling edge of the first control signal that enables Figure 7A transistor 745 and disable Figure 7A In such an example, capacitor 760 turns on transistor 770 and turns off transistor 765 after a delay proportional to the time it takes for capacitor 760 to charge. This delay between turning on transistors 745, 770 provides the amplifier circuitry 100, 200 with a time delay between turning on the inverter circuitry 705, 710. Figure 1 and 2 The output stages 130, 210 then provide time for stabilization.

[0156] The buffer circuitry 235, 320, 680 stops driving the first input of the opposing buffer stage. (Block 835). In some examples, the delay circuitry 715 generates a second control signal (V OFF2 ), which controls the switch circuitry 240, 325, 410, and the inverter circuitry 720 generates a second inverted control signal (~V OFF2 ), which may also control switch circuitry 240, 325, 410. In example operation, in response to the first control signal being in a second state (e.g., a logic zero, a logic low, etc.), delay circuitry 715 clears the second control signal and inverter circuitry 720 sets the second inverted control signal. In such example operation, the second control signal disconnects switch circuitry 240 or disables transistor 380, 430, and the second inverted control signal disconnects switch circuitry 240 or disables transistor 385, 420. Advantageously, switch circuitry 240, 325, 410 prevents buffer circuitry 235, 320, 680 from driving the first input of opposing buffer stage circuitry 120, 205, 300, 400, 500, 610 after a delay that allows amplifier circuitry 100, 200 time to settle. Advantageously, opening the switch circuitry 240 , 325 , 410 after allowing the amplifier circuitry 100 , 200 time to stabilize reduces voltage transients at the output of the amplifier circuitry 100 , 200 .

[0157] If the control signal generation circuitry 215, 700 determines that the amplifier has not left the power down state (eg, block 820 returns a "no" result) or control continues from block 835, then Figure 6The transconductance circuit system 615 receives an input voltage at the input of the input stage circuit system. (Block 840). In example operation, the transconductance circuit system 615 generates a current in response to the voltage difference between the inverting and non-inverting inputs of the amplifier circuit system 100. In such example operation, Figure 6 The transistors 625, 650 supply the current of the transconductance circuit system 615 to the input of the opposing buffer stage 120, 205, 300, 400, 500, 610. Figure 6 The difference between the currents of the current source circuit systems 620 and 645.

[0158] Figure 1 and 6 The input stages 110, 605 of the amplifier circuitry 100, 200, 600 generate a differential voltage based on the input voltage. (Block 845). In some examples, the current through the transistors 625, 635, 650, 660 and the transconductance of the transistors set the inputs of the opposing buffer stages 120, 205, 300, 400, 500, 610 to be proportional to the voltage difference between the inverting and non-inverting inputs of the amplifier circuitry 100, 200, 600. In other examples, for example, Figure 6 , one input of the opposing buffer stage 120 , 205 , 300 , 400 , 500 , 610 may be fixed, and the input stage 110 , 605 generates a differential voltage in response to setting a voltage at a second input of the opposing buffer stage 120 , 205 , 300 , 400 , 500 , 610 .

[0159] Figure 2 、 3 The buffer circuitry 220, 230, 305, 315, 668 of the 1, 2, 4, 5, and 6 stages generates a current proportional to the voltage at the input of the opposing buffer stage circuitry. (Block 850). In some examples, the buffer circuitry 220, 230, 305, 315, 668 generates an anti-phase sinking current (I ) in response to the differential voltage at the input of the opposing buffer stage 205, 300, 400, 500, 610. SNK- ), non-inverting source current (I SRC+ ), non-inverting absorption current (I SNK+ ) and the inverting source current (I SRC- ).

[0160] Figure 1 and 2 The output stages 130, 210 drive the output voltage in response to the current of the opposing buffer stage circuitry. (Block 855). In example operation, the buffer circuitry 220, 230, 305, 315, 668 Figure 2 The current mirror circuit system 245 absorbs the inverting and non-inverting sink currents and supplies the inverting and non-inverting source currents to Figure 2 The current mirror circuit system 250. In such an example operation, Figure 2 Class AB control circuit system 255 and Figure 2 Transistors 270, 275 generate an output voltage in response to the difference between the inverting and non-inverting sinking currents and the difference between the inverting and non-inverting sourcing currents. Advantageously, class AB control circuitry 255 linearly controls transistors 270, 275 to generate an analog output.

[0161] refer to Figure 8 The flowchart shown in describes an example method. However, implementation Figure 1 、 2 , 3, 4, 5 and 6 of the opposing buffer stages 120, 205, 300, 400, 500, 610 or more generally Figure 1 and 2 Many other methods of implementing the amplifier circuit systems 100 and 200 may also be used in the present disclosure. For example, the order of execution of the blocks may be changed, or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the fabrication process before, between, or after the blocks shown in the illustrated examples.

[0162] Figure 9 yes Figure 1 、 2 , 3, 4, 5 and 6 of the opposing buffer stages 120, 205, 300, 400, 500, 610 or more generally Figure 1 and 2 A timing diagram 900 of an example operation of the amplifier circuit system 100, 200 is shown. Figure 9 In the example of , timing diagram 900 includes a first example control signal 910 , a second example control signal 920 , an example uncompensated differential input voltage 930 , an example compensated differential input voltage 940 , an example uncompensated output voltage 950 , and an example compensated output voltage 960 .

[0163] The first control signal 910 shows an example transition from a power-off state to normal operation. Figure 2 The second control signal 920 shows the state of the switching circuit system 260, 265 during the example transition from the power-off state to normal operation. Figure 2 、 3 , 4, 5 and 6. The uncompensated differential input voltage 930 shows the state of the switching circuit systems 240, 325, 410 when the first input is not driven based on the second input (e.g., not performing Figure 8815), the voltage difference between the inverting and non-inverting voltages at the inputs of opposing buffer stages 120, 205, 300, 400, 500, 610. The compensated differential input voltage 940 shows the voltage difference between the inverting and non-inverting voltages at the inputs of opposing buffer stages 120, 205, 300, 400, 500, 610 when the first input is driven based on the second input (e.g., performing Figure 8 815), the voltage difference between the inverting and non-inverting voltages at the inputs of the opposing buffer stages 120, 205, 300, 400, 500, 610. The uncompensated output voltage 950 illustrates the output voltage of the amplifier circuitry 100, 200 in response to the uncompensated differential input voltage 930. The compensated output voltage 960 illustrates the output voltage of the amplifier circuitry 100, 200 in response to the compensated differential input voltage 940.

[0164] At a first time 970, in response to a falling edge of first control signal 910, the transition from the power-off state to normal operation begins. At first time 970, in response to second control signal 920 remaining set, compensated differential input voltage 940 remains at approximately zero volts. At a second time 980, second control signal 920 has a falling edge, which prevents buffer circuitry 235, 320, 680 from driving the first input of opposing buffer stage 120, 205, 300, 400, 500, 610. At approximately second time 980, uncompensated differential input voltage 930 is experiencing a transient spike. This transient in uncompensated differential input voltage 930 generates a transient voltage on uncompensated output voltage 950. However, between second time 980 and a third time 990, compensated differential input voltage 940 experiences a relatively small transient voltage. The relatively small transient voltage in compensated differential input voltage 940 generates a relatively small voltage transient on compensated output voltage 960. Advantageously, reducing the differential voltage at the inputs of opposing buffer stages 120 , 205 , 300 , 400 , 500 , 610 reduces voltage transients during the transition from a powered-down state to normal operation.

[0165] Figure 10 is a schematic diagram of an example amplifier circuit system 1000 including an example opposed buffer stage 1003 (which is Figure 1 、 2 , 3, 4, 5 and 6 of the opposing buffer stages 120, 205, 300, 400, 500, 610) and the example output stage 1006 (which is Figure 1 and 2 1 , 210 ). Figure 10 The example opposing buffer stage 1003 includes a first example buffer circuitry 1008 , a first example current source circuitry 1009 , a second example current source circuitry 1012 , an example resistor 1015 , and a second example buffer circuitry 1018 . Figure 10 The example buffer circuit system 1008 includes a first example transistor 1021 , a second example transistor 1024 , a third example transistor 1027 , and a fourth example transistor 1030 .

[0166] Figure 10 The example output stage 1006 includes a first example current mirror circuit system 1033, a second example current mirror circuit system 1036, a first example current source circuit system 1039, a second example current source circuit system 1042, a first example gate bias circuit system 1045, a second example gate bias circuit system 1048, an example class AB control circuit system 1051 and an example output driver circuit system 1054. Figure 10 The example current mirror circuit system 1033 includes a first example transistor 1057 and a second example transistor 1060 . Figure 10 The example current mirror circuit system 1036 includes a first example transistor 1063 and a second example transistor 1066 . Figure 10 The example gate bias circuitry 1045 includes a first example transistor 1069 and a second example transistor 1072 . Figure 10 The example gate bias circuitry 1048 includes a first example transistor 1075 and a second example transistor 1078 . Figure 10 The example class AB control circuitry 1051 includes a first example transistor 1081 and a second example transistor 1084 . Figure 10 The example output driver circuitry 1054 includes a first example transistor 1087 and a second example transistor 1090 .

[0167] The amplifier circuit system 1000 has a first input, a second input, and an output. The first input of the amplifier circuit system 1000 is configured to be coupled to Figure 1 and 6 The input stage 110, 605 supplies an input voltage (V IN_STAGE ). A second input of the amplifier circuit system 1000 is configured to be coupled to a reference input that supplies a reference voltage (V REF ). In some examples, the second input of the amplifier circuit system 1000 can be configured to receive a non-inverting input voltage, such as Figure 2 、 3 , 4 and 5. The output of amplifier circuit system 1000 is configured to be coupled to a downstream circuit system that receives the output voltage (V OUT ).exist Figure 10 In the example of , amplifier circuit system 1000 includes an opposing buffer stage 1003 and an output stage 1006. However, in some examples, amplifier circuit system 1000 includes additional stages, such as Figure 1 and 6 Input stage 110, 605.

[0168] Opposing buffer stage 1003 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, and an eighth terminal. The first terminal of opposing buffer stage 1003 is coupled to a first input of amplifier circuitry 1000, which supplies an input voltage. The second terminal of opposing buffer stage 1003 is coupled to a second input of amplifier circuitry 1000, which supplies a reference voltage. The third terminal of opposing buffer stage 1003 is coupled to a power supply terminal, which supplies a power supply voltage. The fourth, fifth, sixth, and seventh terminals of opposing buffer stage 1003 are coupled to output stage 1006. The eighth terminal of opposing buffer stage 1003 is coupled to a common terminal, which supplies a common potential.

[0169] Output stage 1006 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal. The first, second, third, and fourth terminals of output stage 1006 are coupled to opposing buffer stage 1003. A fifth terminal of output stage 1006 is coupled to a power supply terminal, which supplies a power supply voltage. A sixth terminal of output stage 1006 is coupled to a common terminal, which supplies a common potential. A seventh terminal of output stage 1006 is coupled to the output of amplifier circuitry 1000, which supplies an output voltage to downstream circuitry.

[0170] Buffer circuitry 1008 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, and an eighth terminal. The first terminal of buffer circuitry 1008 is coupled to a first input of amplifier circuitry 1000, which supplies an input voltage. The second terminal of buffer circuitry 1008 is coupled to current source circuitry 1009. The third terminal of buffer circuitry 1008 is coupled to current mirror circuitry 1033. The fourth terminal of buffer circuitry 1008 is coupled to gate bias circuitry 1045. The fifth terminal of buffer circuitry 1008 is coupled to resistor 1015. The sixth terminal of buffer circuitry 1008 is coupled to gate bias circuitry 1048. The seventh terminal of buffer circuitry 1008 is coupled to current mirror circuitry 1036. The eighth terminal of buffer circuitry 1008 is coupled to current source circuitry 1012.

[0171] The current source circuit system 1009 has a first terminal and a second terminal. The first terminal of the current source circuit system 1009 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of the current source circuit system 1009 is coupled to the transistors 1021 and 1027.

[0172] The current source circuit system 1012 has a first terminal and a second terminal. The first terminal of the current source circuit system 1012 is coupled to the transistors 1024, 1030. The second terminal of the current source circuit system 1012 is coupled to a common terminal, which supplies a common potential.

[0173] The resistor 1015 has a first terminal and a second terminal. The first terminal of the resistor 1015 is coupled to the transistors 1027, 1030. The second terminal of the resistor 1015 is coupled to the buffer circuitry 1018.

[0174] Buffer circuitry 1018 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of buffer circuitry 1018 is coupled to the second input of amplifier circuitry 1000, which supplies a reference voltage. The second terminal of buffer circuitry 1018 is coupled to resistor 1015. The third terminal of buffer circuitry 1018 is coupled to current mirror circuitry 1033, current source circuitry 1039, class AB control circuitry 1051, and output driver circuitry 1054. The fourth terminal of buffer circuitry 1018 is coupled to current mirror circuitry 1036, current source circuitry 1042, class AB control circuitry 1051, and output driver circuitry 1054.

[0175] Transistor 1021 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1021 is coupled to current source circuitry 1009 and transistor 1027. The second terminal of transistor 1021 is coupled to gate bias circuitry 1048 and class AB control circuitry 1051. The control terminal of transistor 1021 is coupled to transistor 1024 and to a first input of amplifier circuitry 1000, which supplies an inverting input voltage.

[0176] Transistor 1024 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1024 is coupled to gate bias circuitry 1045 and class AB control circuitry 1051. The second terminal of transistor 1024 is coupled to current source circuitry 1012 and transistor 1030. The control terminal of transistor 1024 is coupled to transistor 1021 and to a first input of amplifier circuitry 1000, which supplies an inverting input voltage.

[0177] Transistor 1027 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1027 is coupled to current mirror circuitry 1033. The second terminal of transistor 1027 is coupled to resistor 1015 and transistor 1030. The control terminal of transistor 1027 is coupled to current source circuitry 1009 and transistor 1021.

[0178] Transistor 1030 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1030 is coupled to resistor 1015 and transistor 1027. The second terminal of transistor 1030 is coupled to current mirror circuitry 1036. The control terminal of transistor 1030 is coupled to current source circuitry 1012 and transistor 1024.

[0179] Current mirror circuitry 1033 has a first terminal, a second terminal, and a third terminal. The first terminal of current mirror circuitry 1033 is coupled to buffer circuitry 1008. The second terminal of current mirror circuitry 1033 is coupled to buffer circuitry 1018, current source circuitry 1039, class AB control circuitry 1051, and output driver circuitry 1054. The third terminal of current mirror circuitry 1033 is coupled to a power supply terminal that supplies a power supply voltage.

[0180] Current mirror circuitry 1036 has a first terminal, a second terminal, and a third terminal. The first terminal of current mirror circuitry 1036 is coupled to buffer circuitry 1008. The second terminal of current mirror circuitry 1036 is coupled to buffer circuitry 1018, current source circuitry 1042, class AB control circuitry 1051, and output driver circuitry 1054. The third terminal of current mirror circuitry 1036 is coupled to a common terminal, which supplies a common potential.

[0181] Current source circuitry 1039 has a first terminal and a second terminal. The first terminal of current source circuitry 1039 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of current source circuitry 1039 is coupled to buffer circuitry 1018, current mirror circuitry 1033, class AB control circuitry 1051, and output driver circuitry 1054.

[0182] Current source circuitry 1042 has a first terminal and a second terminal. The first terminal of current source circuitry 1042 is coupled to buffer circuitry 1018, current mirror circuitry 1036, class AB control circuitry 1051, and output driver circuitry 1054. The second terminal of current source circuitry 1042 is coupled to a common terminal that supplies a common potential.

[0183] Gate bias circuitry 1045 has a first terminal and a second terminal. The first terminal of gate bias circuitry 1045 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of gate bias circuitry 1045 is coupled to buffer circuitry 1008 and class AB control circuitry 1051.

[0184] Gate bias circuitry 1048 has a first terminal and a second terminal. The first terminal of gate bias circuitry 1048 is coupled to buffer circuitry 1008 and class AB control circuitry 1051. The second terminal of gate bias circuitry 1048 is coupled to a common terminal that supplies a common potential.

[0185] Class AB control circuitry 1051 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of class AB control circuitry 1051 is coupled to buffer circuitry 1018, current mirror circuitry 1033, current source circuitry 1039, and output driver circuitry 1054. The second terminal of class AB control circuitry 1051 is coupled to buffer circuitry 1008 and gate bias circuitry 1045. The third terminal of class AB control circuitry 1051 is coupled to buffer circuitry 1008 and gate bias circuitry 1048. The fourth terminal of class AB control circuitry 1051 is coupled to buffer circuitry 1018, current mirror circuitry 1036, current source circuitry 1042, and output driver circuitry 1054.

[0186] Output driver circuitry 1054 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of output driver circuitry 1054 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of output driver circuitry 1054 is coupled to buffer circuitry 1018, current mirror circuitry 1033, current source circuitry 1039, and class AB control circuitry 1051. The third terminal of output driver circuitry 1054 is coupled to the output of amplifier circuitry 1000. The fourth terminal of output driver circuitry 1054 is coupled to buffer circuitry 1018, current mirror circuitry 1036, current source circuitry 1042, and class AB control circuitry 1051. The fifth terminal of output driver circuitry 1054 is coupled to a common terminal, which supplies a common potential.

[0187] The transistor 1057 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 1057 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal and the control terminal of the transistor 1057 are coupled to the transistors 1027 and 1060.

[0188] Transistor 1060 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1060 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of transistor 1060 is coupled to buffer circuitry 1018, current source circuitry 1039, and transistors 1081, 1084, and 1087. The control terminal of transistor 1060 is coupled to transistors 1027 and 1057.

[0189] The transistor 1063 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of the transistor 1063 are coupled to the transistors 1030 and 1066. The second terminal of the transistor 1063 is coupled to a common terminal, which supplies a common potential.

[0190] Transistor 1066 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1066 is coupled to buffer circuitry 1018, current source circuitry 1042, and transistors 1081, 1084, and 1090. The second terminal of transistor 1066 is coupled to a common terminal that supplies a common potential. The control terminal of transistor 1066 is coupled to transistors 1030 and 1063.

[0191] The transistor 1069 has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor 1069 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal and the control terminal of the transistor 1069 are coupled to the transistor 1072.

[0192] Transistor 1072 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1072 is coupled to transistor 1069. The second terminal and the control terminal of transistor 1072 are coupled to transistors 1024 and 1084.

[0193] Transistor 1075 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of transistor 1075 are coupled to transistors 1021 and 1081. The second terminal of transistor 1075 is coupled to transistor 1078.

[0194] The transistor 1078 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of the transistor 1078 are coupled to the transistor 1075. The second terminal of the transistor 1078 is coupled to a common terminal, which supplies a common potential.

[0195] Transistor 1081 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1081 is coupled to buffer circuitry 1018, current source circuitry 1039, and transistors 1060, 1084, and 1087. The second terminal of transistor 1081 is coupled to buffer circuitry 1018, current source circuitry 1042, and transistors 1066, 1084, and 1090. The control terminal of transistor 1081 is coupled to transistors 1021 and 1075.

[0196] Transistor 1084 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1084 is coupled to buffer circuitry 1018, current source circuitry 1039, and transistors 1060, 1081, and 1087. The second terminal of transistor 1084 is coupled to buffer circuitry 1018, current source circuitry 1042, and transistors 1066, 1081, and 1090. The control terminal of transistor 1084 is coupled to transistors 1024 and 1072.

[0197] Transistor 1087 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1087 is coupled to a power supply terminal that supplies a power supply voltage. The second terminal of transistor 1087 is coupled to transistor 1090 and the output of amplifier circuitry 1000. The control terminal of transistor 1087 is coupled to buffer circuitry 1018, current source circuitry 1039, and transistors 1060, 1081, and 1084.

[0198] Transistor 1090 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1090 is coupled to transistor 1087 and the output of amplifier circuitry 1000. The second terminal of transistor 1090 is coupled to a common terminal, which supplies a common potential. The control terminal of transistor 1090 is coupled to buffer circuitry 1018, current source circuitry 1042, and transistors 1066, 1081, and 1084.

[0199] exist Figure 10 In the example of , transistors 1024, 1027, 1063, 1066, 1075, 1078, 1081, 1090 are n-channel MOSFETs. Alternatively, transistors 1024, 1027, 1063, 1066, 1075, 1078, 1081, 1090 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Figure 10In the example of FIG. 1 , transistors 1021 , 1030 , 1057 , 1060 , 1069 , 1072 , 1084 , 1087 are p-channel MOSFETs. Alternatively, transistors 1021 , 1030 , 1057 , 1060 , 1069 , 1072 , 1084 , 1087 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified N-type equivalents. Transistors 1021 , 1024 , 1027 , 1030 , 1057 , 1060 , 1063 , 1066 , 1069 , 1072 , 1075 , 1078 , 1081 , 1084 , 1087 , 1090 may be depletion-mode devices, extended drain devices, enhancement-mode devices, native transistors, or other types of device structures. Furthermore, transistors 1021 , 1024 , 1027 , 1030 , 1057 , 1060 , 1063 , 1066 , 1069 , 1072 , 1075 , 1078 , 1081 , 1084 , 1087 , 1090 may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0200] Advantageously, transistor 1021 supplies current from current source circuitry 1009 to gate bias circuitry 1048. Advantageously, transistor 1021 biases gate bias circuitry 1048 in lieu of an additional current source. Advantageously, transistor 1024 supplies current from gate bias circuitry 1045 to current source circuitry 1012. Advantageously, transistor 1024 biases gate bias circuitry 1045 in lieu of an additional current source.

[0201] Figure 11 is a schematic diagram of an example amplifier circuit system 1100 including an example opposed buffer stage 1105 (which is Figure 1 、 2 , 3, 4, 5, 6 and 10 of the opposing buffer stages 120, 205, 300, 400, 500, 610, 1003) and an example output stage 1110 (which is Figure 1 、 2 and another example of output stages 130, 210, 1006 of 10). Figure 11 An example opposing buffer stage 1105 includes Figure 10 Current source circuit systems 1009, 1012, Figure 10 Resistor 1015, Figure 10 Buffer circuit system 1018 and example buffer circuit system 1115. Figure 11The example buffer circuitry 1115 includes a first example transistor 1120 , a second example transistor 1125 , a third example transistor 1130 , a fourth example transistor 1135 , a fifth example transistor 1140 , and a sixth example transistor 1145 .

[0202] Figure 11 An example output stage 1110 includes Figure 10 Current mirror circuit system 1033, 1036, Figure 10 Gate bias circuit system 1045, 1048, Figure 10 Class AB control circuit system 1051 and Figure 10 Output driver circuit system 1054. Figure 11 The example current mirror circuit system 1033 includes Figure 10 Transistors 1057 and 1060. Figure 11 The example current mirror circuit system 1036 includes Figure 10 Transistors 1063 and 1066. Figure 11 An example gate bias circuit system 1045 includes Figure 10 Transistors 1069 and 1072. Figure 11 An example gate bias circuit system 1048 includes Figure 10 Transistors 1075 and 1078. Figure 11 An example class AB control circuit system 1051 includes Figure 10 Transistors 1081 and 1084. Figure 11 The example output driver circuitry 1054 includes Figure 10 Transistors 1087 and 1090.

[0203] The amplifier circuit system 1100 has a first input, a second input, and an output. The first input of the amplifier circuit system 1100 is configured to be coupled to Figure 1 and 6 The input stage 110, 605 supplies an input voltage (V IN_STAGE ). A second input of the amplifier circuit system 1100 is configured to be coupled to a reference input that supplies a reference voltage (V REF The output of amplifier circuitry 1100 is configured to be coupled to downstream circuitry that receives the output voltage (V OUT ).exist Figure 11 In the example of , the amplifier circuit system 1100 includes an opposing buffer stage 1105 and an output stage 1110. However, in some examples, the amplifier circuit system 1100 includes additional stages, such as Figure 1 and 6 Input stage 110, 605.

[0204] Buffer circuit system 1115 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, and an eighth terminal. The first terminal of buffer circuit system 1115 is coupled to a first input of amplifier circuit system 1100, which supplies an input voltage. The second terminal of buffer circuit system 1115 is coupled to current source circuit system 1009. The third terminal of buffer circuit system 1115 is coupled to current mirror circuit system 1033. The fourth terminal of buffer circuit system 1115 is coupled to gate bias circuit system 1045. The fifth terminal of buffer circuit system 1115 is coupled to resistor 1015. The sixth terminal of buffer circuit system 1115 is coupled to gate bias circuit system 1048. The seventh terminal of buffer circuit system 1115 is coupled to current mirror circuit system 1036. The eighth terminal of buffer circuit system 1115 is coupled to current source circuit system 1012. Buffer circuit system 1115 is Figure 10 Another example of a buffer circuit system 1008.

[0205] Transistor 1120 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1120 is coupled to current source circuitry 1009 and transistors 1125 and 1140. The second terminal of transistor 1120 is coupled to current mirror circuitry 1036 and transistor 1145. The control terminal of transistor 1120 is coupled to transistors 1125, 1130, 1135 and a first input of amplifier circuitry 1100, which supplies an inverting input voltage.

[0206] Transistor 1125 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1125 is coupled to current source circuitry 1009 and transistors 1120 and 1140. The second terminal of transistor 1125 is coupled to gate bias circuitry 1048. The control terminal of transistor 1125 is coupled to transistors 1120, 1130, 1135 and a first input of amplifier circuitry 1100, which supplies an inverting input voltage.

[0207] Transistor 1130 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1130 is coupled to current mirror circuitry 1033 and transistor 1140. The second terminal of transistor 1130 is coupled to current source circuitry 1012 and transistors 1135 and 1145. The control terminal of transistor 1130 is coupled to transistors 1120, 1125, 1135, and a first input of amplifier circuitry 1100, which supplies an inverting input voltage.

[0208] Transistor 1135 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1135 is coupled to gate bias circuitry 1045. The second terminal of transistor 1135 is coupled to current source circuitry 1012 and transistors 1130 and 1145. The control terminal of transistor 1135 is coupled to transistors 1120, 1125, 1130, and a first input of amplifier circuitry 1100, which supplies an inverting input voltage.

[0209] Transistor 1140 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1140 is coupled to current mirror circuitry 1033 and transistor 1130. The second terminal of transistor 1140 is coupled to resistor 1015 and transistor 1145. The control terminal of transistor 1140 is coupled to current source circuitry 1009 and transistors 1120 and 1125.

[0210] Transistor 1145 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1145 is coupled to resistor 1015 and transistor 1140. The second terminal of transistor 1145 is coupled to current mirror circuitry 1036 and transistor 1120. The control terminal of transistor 1145 is coupled to current source circuitry 1012 and transistors 1130 and 1135.

[0211] exist Figure 11 In the example of , transistors 1063, 1066, 1075, 1078, 1081, 1090, 1130, 1135, 1140 are n-channel MOSFETs. Alternatively, transistors 1063, 1066, 1075, 1078, 1081, 1090, 1130, 1135, 1140 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Figure 11In the example of FIG. 1 , transistors 1057 , 1060 , 1069 , 1072 , 1084 , 1087 , 1120 , 1125 , 1145 are p-channel MOSFETs. Alternatively, transistors 1057 , 1060 , 1069 , 1072 , 1084 , 1087 , 1120 , 1125 , 1145 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified N-type equivalent devices. Transistors 1057, 1060, 1063, 1066, 1069, 1072, 1075, 1078, 1081, 1084, 1087, 1090, 1120, 1125, 1130, 1135, 1140, 1145 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structures. Furthermore, transistors 1057, 1060, 1063, 1066, 1069, 1072, 1075, 1078, 1081, 1084, 1087, 1090, 1120, 1125, 1130, 1135, 1140, 1145 may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0212] Advantageously, transistor 1120 supplies current from current source circuitry 1009 to current mirror circuitry 1036. Advantageously, transistor 1120 replaces Figure 10 1048. Advantageously, transistor 1125 supplies current from current source circuitry 1009 to gate bias circuitry 1048. Advantageously, transistor 1125 biases gate bias circuitry 1048 in lieu of an additional current source.

[0213] Advantageously, transistor 1130 supplies current from current mirror circuitry 1033 to current source circuitry 1012. Advantageously, transistor 1130 replaces Figure 10 1039. Advantageously, transistor 1135 supplies current from gate bias circuitry 1045 to current source circuitry 1012. Advantageously, transistor 1135 biases gate bias circuitry 1045 in lieu of an additional current source.

[0214] exist Figure 10 In the example of , transistors 1021, 1024 use current source circuitry 1009, 1012 to bias gate bias circuitry 1045, 1048. However, the input voltage modifies the current conduction of transistors 1021, 1024, which makes the bias current of gate bias circuitry 1045, 1048 dependent on the input voltage. Advantageously, in Figure 11In the example of FIG1 , current source circuitry 1009, 1012 is configured to bias both gate bias circuitry 1045, 1048 and class AB control circuitry 1051. In such an example, transistors 1120, 1125, 1130, 1135 are sized to proportionally distribute current from current source circuitry 1009, 1012 to either gate bias circuitry 1045, 1048 or current mirror circuitry 1033, 1036. Similar to the bias currents of transistors 1021, 1024, 1125, 1135, the bias currents of transistors 1120, 1130 also depend on the input voltage.

[0215] Advantageously, gate bias circuitry 1045, 1048 sets the voltage of the control terminals of transistors 1081, 1084, and bias currents mirrored by current mirror circuitry 1033, 1036, 1315, 1325 bias the source terminals of transistors 1081, 1084. In such an example, the ratio of the sizing of transistors 1120, 1125 and transistors 1130, 1135 can be set to cancel the signal dependency of the bias currents. To cancel the bias error due to the signal dependency of the currents flowing through transistors 1120, 1125, 1130, 1135, the first voltage error (v err1A ) is approximately equal to the second voltage error (v err1B ). The first voltage error represents a signal-dependent component of the voltage at the control terminal of transistor 1081, which is generated by a signal-dependent component of the bias current from transistor 1125 through transistors 1075 and 1078. The second voltage error represents a signal-dependent component of the voltage between the control terminal and the source terminal of transistor 1081, which is generated by a signal-dependent component of the bias current from transistor 1120 through current mirror circuitry 1036 and the transconductance of transistor 1081.

[0216] The first voltage error corresponds to a voltage variation at the control terminal of transistor 1081 in response to a signal-dependent component (i err1A ) multiplied by the transconductance (g) of transistors 1075 and 1078 m1 、g m2 The transconductance of the transistors 1075 and 1078 is related to the first total current (I 1A ) multiplied by the square root of the ratio of the width to the length of the channels of the transistors 1075 and 1078 ([W / L]1, [W / L]2). The first voltage error at the control terminal of the transistor 1081 is expressed using the following equation (1).

[0217]

[0218] The second voltage error corresponds to a voltage variation between the control terminal and the source terminal of transistor 1081 in response to a signal-dependent component (i ) of the source bias current from transistor 1120 mirrored by current mirror circuitry 1036. err1B ) multiplied by the transconductance of transistor 1081 (g m3 ). The signal-dependent component of the source bias current corresponds to the portion of the total signal-dependent bias current component through transistors 1120, 1125 compared to the ratio of the total current through transistors 1120, 1125. The ratio of the current through transistors 1120, 1125 corresponds to the ratio of the width to the length of the channel of transistors 1120, 1125 ([W / L] 1B , [W / L] 1A ). The transconductance of the transistor 1081 is proportional to the first total current (I 1B ) multiplied by the square root of the ratio of the width to the length of the channel of the transistor 1081 ([W / L]3). The first voltage error between the control terminal and the source terminal of the transistor 1081 is expressed by the following equation (2).

[0219]

[0220] As described above, in order to cancel the signal-dependent bias error on the source voltage of transistor 1081, the first voltage error must be set equal to the second voltage error. In such an instance, the voltage error generated by the signal-dependent bias current component is canceled. This cancellation of the first and second voltage errors is achieved by satisfying the following equation (3).

[0221]

[0222] The above equation (3) can be simplified to produce the following equation (4). Advantageously, adjusting the channel size of transistors 1075, 1078, 1081, 1120, 1125 to conform to equation (4) reduces signal errors caused by the dependency of the bias on the input voltage. Similarly, the following equation (5) provides the corresponding requirements for the channels of transistors 1069, 1072, 1084, 1130, 1135 ([W / L]4, [W / L]5, [W / L]6, [W / L] 2B , [W / L] 2A ). Alternatively, as Figure 12 As shown, in some examples, implementing the transistors of amplifier circuitry 1100 using BJTs eliminates the ratio dependency of equations (4) and (5).

[0223]

[0224] Figure 12 is a schematic diagram of an example amplifier circuit system 1200 including an example opposing buffer stage 1205 (which is Figure 1 、 2 , 3, 4, 5, 6, 10 and 11 of the opposing buffer stages 120, 205, 300, 400, 500, 610, 1003, 1105) and an example output stage 1210 (which is Figure 1 、 2 , 10 and 11 output stages 130, 210, 1006, 1110). Figure 12 An example opposing buffer stage 1205 includes Figure 10 Current source circuit systems 1009, 1012, Figure 10 Resistor 1015, Figure 11 The buffer circuit system 1115, the example buffer circuit system 1215, the first example current source circuit system 1220 and the second example current source circuit system 1225. Figure 12 An example buffer circuit system 1115 includes Figure 11 transistors 1120, 1125, 1130, 1135, 1140, and 1145. Figure 12 The example buffer circuitry 1215 includes a first example transistor 1230 , a second example transistor 1235 , a third example transistor 1240 , and a fourth example transistor 1245 .

[0225] Figure 12 An example output stage 1210 includes Figure 10 Current mirror circuit system 1033, 1036, Figure 10 Gate bias circuit system 1045, 1048, Figure 10 Class AB control circuit system 1051 and Figure 10 Output driver circuit system 1054. Figure 12 The example current mirror circuit system 1033 includes Figure 10 Transistors 1057 and 1060. Figure 12 The example current mirror circuit system 1036 includes Figure 10 Transistors 1063 and 1066. Figure 12 An example gate bias circuit system 1045 includes Figure 10 Transistors 1069 and 1072. Figure 12 An example gate bias circuit system 1048 includes Figure 10 Transistors 1075 and 1078. Figure 12 An example class AB control circuit system 1051 includes Figure 10 Transistors 1081 and 1084. Figure 12 The example output driver circuitry 1054 includes Figure 10 Transistors 1087 and 1090.

[0226] The amplifier circuit system 1200 has a first input, a second input, and an output. The first input of the amplifier circuit system 1200 is configured to be coupled to Figure 1 and 6 The input stage 110, 605 supplies an input voltage (V IN_STAGE ). A second input of the amplifier circuit system 1200 is configured to be coupled to a reference input that supplies a reference voltage (V REF The output of amplifier circuitry 1200 is configured to be coupled to downstream circuitry that receives the output voltage (V OUT ).exist Figure 12 In the example of , the amplifier circuit system 1200 includes an opposing buffer stage 1205 and an output stage 1210. However, in some examples, the amplifier circuit system 1200 includes additional stages, such as Figure 1 and 6 Input stage 110, 605.

[0227] Buffer circuitry 1215 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, and an eighth terminal. The first terminal of buffer circuitry 1215 is coupled to the second input of amplifier circuitry 1200, which supplies a reference voltage. The second terminal of buffer circuitry 1215 is coupled to current source circuitry 1220. The third terminal of buffer circuitry 1215 is coupled to current mirror circuitry 1033. The fourth terminal of buffer circuitry 1215 is coupled to gate bias circuitry 1045 and buffer circuitry 1115. The fifth terminal of buffer circuitry 1215 is coupled to resistor 1015. The sixth terminal of buffer circuitry 1215 is coupled to gate bias circuitry 1048 and class AB control circuitry 1051. The seventh terminal of buffer circuitry 1215 is coupled to current mirror circuitry 1036. The eighth terminal of buffer circuitry 1215 is coupled to current source circuitry 1225.

[0228] The current source circuit system 1220 has a first terminal and a second terminal. The first terminal of the current source circuit system 1220 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of the current source circuit system 1220 is coupled to the buffer circuit system 1215.

[0229] The current source circuit system 1225 has a first terminal and a second terminal. The first terminal of the current source circuit system 1225 is coupled to the buffer circuit system 1215. The second terminal of the current source circuit system 1225 is coupled to a common terminal, which supplies a common potential.

[0230] Transistor 1230 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1230 is coupled to current source circuitry 1220 and transistor 1240. The second terminal of transistor 1230 is coupled to gate bias circuitry 1048, class AB control circuitry 1051, and buffer circuitry 1115. The control terminal of transistor 1230 is coupled to transistor 1235 and a second input of amplifier circuitry 1200, which supplies a reference voltage.

[0231] Transistor 1235 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1235 is coupled to gate bias circuitry 1045, class AB control circuitry 1051, and buffer circuitry 1115. The second terminal of transistor 1235 is coupled to current source circuitry 1225 and transistor 1245. The control terminal of transistor 1235 is coupled to transistor 1230 and a second input of amplifier circuitry 1200, which supplies a reference voltage.

[0232] Transistor 1240 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1240 is coupled to current mirror circuitry 1033, class AB control circuitry 1051, and output driver circuitry 1054. The second terminal of transistor 1240 is coupled to resistor 1015 and transistor 1245. The control terminal of transistor 1240 is coupled to current source circuitry 1220 and transistor 1230.

[0233] Transistor 1245 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1245 is coupled to resistor 1015 and transistor 1240. The second terminal of transistor 1245 is coupled to current mirror circuitry 1036, class AB control circuitry 1051, and output driver circuitry 1054. The control terminal of transistor 1245 is coupled to current source circuitry 1225 and transistor 1235.

[0234] exist Figure 12In the example of , transistors 1063, 1066, 1075, 1078, 1081, 1090, 1130, 1135, 1140, 1235, 1240 are NPN BJTs. Alternatively, transistors 1063, 1066, 1075, 1078, 1081, 1090, 1130, 1135, 1140, 1235, 1240 may be n-channel FETs, n-channel IGBTs, n-channel JFETs, n-channel MOSFETs, or slightly modified p-type equivalent devices. Figure 12 In the example of FIG. 1 , transistors 1057 , 1060 , 1069 , 1072 , 1084 , 1087 , 1120 , 1125 , 1145 , 1230 , 1245 are PNP BJTs. Alternatively, transistors 1057 , 1060 , 1069 , 1072 , 1084 , 1087 , 1120 , 1125 , 1145 , 1230 , 1245 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, p-channel MOSFETs, or slightly modified N-type equivalent devices. Transistors 1057 , 1060 , 1063 , 1066 , 1069 , 1072 , 1075 , 1078 , 1081 , 1084 , 1087 , 1090 , 1120 , 1125 , 1130 , 1135 , 1140 , 1145 , 1230 , 1235 , 1240 , 1245 may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. In addition, transistors 1057, 1060, 1063, 1066, 1069, 1072, 1075, 1078, 1081, 1084, 1087, 1090, 1120, 1125, 1130, 1135, 1140, 1145, 1230, 1235, 1240, 1245 can be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0235] like Figure 12 As shown, or in instances where sizing of transistors 1120, 1125, 1130, 1135 in equations (4) and (5) cannot be achieved, using BJTs to implement the transistors of amplifier circuit system 1200 eliminates the bias dependency on the input voltage. Advantageously, using BJTs to implement amplifier circuit system 1200 does not require the sizing constraints of equations (4) and (5). Advantageously, as Figure 12As shown, transistors 1230, 1235 can additionally couple gate bias circuitry 1045, 1048 to current source circuitry 1220, 1225. Advantageously, the current of current source circuitry 1220, 1225 of buffer circuitry 1215 can be configured to provide additional bias current to gate bias circuitry 1045, 1048. Advantageously, the additional current from transistors 1230, 1235 increases the bias current of gate bias circuitry 1045, 1048, which improves immunity to bias disturbances.

[0236] Figure 13 is a schematic diagram of an example amplifier circuit system 1300 including an example opposed buffer stage 1305 (which is Figure 1 、 2 , 3, 4, 5, 6, 10, 11 and 12 of opposing buffer stages 120, 205, 300, 400, 500, 610, 1003, 1105, 1205) and an example output stage 1310 (which is Figure 1 、 2 , 10, 11 and 12 output stages 130, 210, 1006, 1110, 1210). Figure 13 An example opposing buffer stage 1305 includes Figure 10 Current source circuit systems 1009, 1012, Figure 10 The resistor 1015 and Figure 10 and 11 Buffer circuit systems 1018, 1115. Figure 13 An example buffer circuit system 1115 includes Figure 11 transistors 1120, 1125, 1130, 1135, 1140, and 1145.

[0237] Figure 13 An example output stage 1310 includes Figure 10 Gate bias circuit system 1045, 1048, Figure 10 AB class control circuit system 1051, first example current mirror circuit system 1315, first example capacitor 1320, second example current mirror circuit system 1325, second example capacitor 1330 and example output driver circuit system 1335. Figure 13 An example gate bias circuit system 1045 includes Figure 10 Transistors 1069 and 1072. Figure 13 An example gate bias circuit system 1048 includes Figure 10 Transistors 1075 and 1078. Figure 13 An example class AB control circuit system 1051 includes Figure 10 Transistors 1081 and 1084. Figure 13 The example current mirror circuit system 1315 includes a first example transistor 1340, a second example transistor 1345 and Figure 10 Transistors 1057 and 1060. Figure 13 The example current mirror circuit system 1325 includes a first example transistor 1350, a second example transistor 1355 and Figure 10 Transistors 1063 and 1066. Figure 13 An example output driver circuit system 1335 includes Figure 10 Transistors 1087, 1090, a first example capacitor 1360 and a second example capacitor 1365.

[0238] The amplifier circuit system 1300 has a first input, a second input, and an output. The first input of the amplifier circuit system 1300 is configured to be coupled to Figure 1 and 6 The input stage 110, 605 supplies an input voltage (V IN_STAGE ). A second input of the amplifier circuit system 1300 is configured to be coupled to a reference input that supplies a reference voltage (V REF The output of amplifier circuitry 1300 is configured to be coupled to downstream circuitry that receives the output voltage (V OUT ).exist Figure 13 In the example of , the amplifier circuit system 1300 includes an opposing buffer stage 1305 and an output stage 1310. However, in some examples, the amplifier circuit system 1300 includes additional stages, such as Figure 1 and 6 Input stage 110, 605.

[0239] Current mirror circuitry 1315 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of current mirror circuitry 1315 is coupled to transistor 1130. The second terminal of current mirror circuitry 1315 is coupled to transistor 1140. The third terminal of current mirror circuitry 1315 is coupled to buffer circuitry 1018, class AB control circuitry 1051, and output driver circuitry 1335. The fourth terminal of current mirror circuitry 1315 is coupled to capacitor 1320. The fifth terminal of current mirror circuitry 1315 is coupled to a power supply terminal, which supplies a power supply voltage.

[0240] Capacitor 1320 has a first terminal and a second terminal. The first terminal of capacitor 1320 is coupled to current mirror circuitry 1315. The second terminal of capacitor 1320 is coupled to capacitor 1330, output driver circuitry 1335, and the output of amplifier circuitry 1300.

[0241] Current mirror circuitry 1325 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of current mirror circuitry 1325 is coupled to transistor 1120. The second terminal of current mirror circuitry 1325 is coupled to transistor 1145. The third terminal of current mirror circuitry 1325 is coupled to buffer circuitry 1018, class AB control circuitry 1051, and output driver circuitry 1335. The fourth terminal of current mirror circuitry 1325 is coupled to capacitor 1330. The fifth terminal of current mirror circuitry 1325 is coupled to a common terminal, which supplies a common potential.

[0242] Capacitor 1330 has a first terminal and a second terminal. The first terminal of capacitor 1330 is coupled to current mirror circuitry 1325. The second terminal of capacitor 1330 is coupled to capacitor 1320, output driver circuitry 1335, and the output of amplifier circuitry 1300.

[0243] Output driver circuitry 1335 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of output driver circuitry 1335 is coupled to a power supply terminal, which supplies a power supply voltage. The second terminal of output driver circuitry 1335 is coupled to buffer circuitry 1018, class AB control circuitry 1051, and current mirror circuitry 1315. The third terminal of output driver circuitry 1335 is coupled to buffer circuitry 1018, class AB control circuitry 1051, and current mirror circuitry 1325. The fourth terminal of output driver circuitry 1335 is coupled to capacitors 1320 and 1330 and the output of amplifier circuitry 1300. The fifth terminal of output driver circuitry 1335 is coupled to a common terminal, which supplies a common potential.

[0244] Transistor 1340 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1340 is coupled to transistors 1057, 1060, and 1140. The second terminal and the control terminal of transistor 1340 are coupled to transistors 1130 and 1345.

[0245] Transistor 1345 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1345 is coupled to transistor 1060 and capacitor 1320. The second terminal of transistor 1345 is coupled to buffer circuitry 1018, class AB control circuitry 1051, and output driver circuitry 1335. The control terminal of transistor 1345 is coupled to transistors 1130 and 1340.

[0246] Transistor 1350 has a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of transistor 1350 are coupled to transistors 1120 and 1355. The second terminal of transistor 1350 is coupled to transistors 1063, 1066, and 1145.

[0247] Transistor 1355 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1355 is coupled to buffer circuitry 1018, class AB control circuitry 1051, and output driver circuitry 1335. The second terminal of transistor 1355 is coupled to transistor 1066 and capacitor 1330. The control terminal of transistor 1355 is coupled to transistors 1120 and 1350.

[0248] Capacitor 1360 has a first terminal and a second terminal. The first terminal of capacitor 1360 is coupled to buffer circuitry 1018 and transistors 1081, 1084, 1087, 1345. The second terminal of capacitor 1360 is coupled to transistors 1087, 1090, capacitor 1365, and an output terminal of amplifier circuitry 1300, which supplies an output voltage.

[0249] Capacitor 1365 has a first terminal and a second terminal. The first terminal of capacitor 1365 is coupled to transistors 1087, 1090, capacitor 1360, and the output of amplifier circuitry 1300, which supplies the output voltage. The second terminal of capacitor 1365 is coupled to buffer circuitry 1018 and transistors 1081, 1084, 1090, 1355.

[0250] exist Figure 13 In the example of , transistors 1063, 1066, 1075, 1078, 1081, 1090, 1130, 1135, 1140, 1350, 1355 are n-channel MOSFETs. Alternatively, transistors 1063, 1066, 1075, 1078, 1081, 1090, 1130, 1135, 1140, 1350, 1355 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or slightly modified p-type equivalent devices. Figure 13In the example of FIG. 1 , transistors 1057 , 1060 , 1069 , 1072 , 1084 , 1087 , 1120 , 1125 , 1145 , 1340 , 1345 are p-channel MOSFETs. Alternatively, transistors 1057 , 1060 , 1069 , 1072 , 1084 , 1087 , 1120 , 1125 , 1145 , 1340 , 1345 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified N-type equivalent devices. Transistors 1057 , 1060 , 1063 , 1066 , 1069 , 1072 , 1075 , 1078 , 1081 , 1084 , 1087 , 1090 , 1120 , 1125 , 1130 , 1135 , 1140 , 1145 , 1340 , 1345 , 1350 , 1355 may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. In addition, transistors 1057, 1060, 1063, 1066, 1069, 1072, 1075, 1078, 1081, 1084, 1087, 1090, 1120, 1125, 1130, 1135, 1140, 1145, 1340, 1345, 1350, 1355 can be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0251] In example operation, transistors 1340 and 1350 bias the control terminals of transistors 1345 and 1355 in response to bias currents from transistors 1120 and 1130. Transistors 1345 and 1355 are cascode transistors, which allow capacitors 1320 and 1330 to be coupled between the output of amplifier circuitry 1300 and transistors 1057, 1060, 1063, and 1066, which mirror the inverting sink current and the non-inverting source current. In some examples, capacitors 1320 and 1330 may be referred to as Ahuja compensation capacitors. Similar to the Miller compensation of capacitors 1360 and 1365, capacitors 1320 and 1330 provide frequency compensation for amplifier circuitry 1300. In such examples, the capacitance of capacitors 1320 and 1330 replaces some or all of the capacitance of capacitors 1360 and 1365. Advantageously, the use of capacitors 1320, 1330 improves the linearity of amplifier circuitry 1300 by enabling the capacitance of capacitors 1360, 1365 to be reduced or eliminated. Advantageously, the use of current source circuitry 1009, 1012 to bias transistors 1345, 1355 reduces the need for additional current sources for biasing transistors 1340, 1350. Advantageously, reducing the number of current source circuitry instances reduces power consumption, system-on-chip size, cost, complexity, etc. Advantageously, the use of current source circuitry 1009, 1012, rather than current from transistors 1140, 1145, to bias transistors 1345, 1355 increases the drain-to-source voltage of transistors 1140, 1145, thereby enabling the use of a lower supply voltage for amplifier circuitry 1300.

[0252] Figure 14 is a flow diagram representing example machine-readable instructions or example operations 1400 that may be used Figure 1 、 10 , 11, 12 and 13 of the opposing buffer stages 120, 1003, 1105, 1205, 1305, Figure 1 、 10 , 11, 12 and 13 output stages 130, 1006, 1110, 1210, 1310 or more generally Figure 1 、 10 , 11, 12 and 13 are performed, instantiated and / or implemented with the example embodiments of the amplifier circuit systems 100, 1000, 1100, 1200, 1300.

[0253] Figure 14 The example operation 1400 begins at block 1405 when the amplifier circuit system 100, 1000, 1100, 1200, 1300 receives an input voltage at an input of an input stage. In the example operation, Figure 6The transconductance circuit system 615 generates a current in response to the voltage difference between the inverting and non-inverting inputs of the amplifier circuit system 100, 1000, 1100, 1200, 1300. In such an example operation, Figure 6 The transistors 625, 650 supply the current of the transconductance circuit system 615 to the input of the opposing buffer stage 120, 205, 300, 400, 500, 610, 1003, 1105, 1205, 1305. Figure 6 The difference between the currents of the current source circuit systems 620 and 645.

[0254] Figure 1 and 6 The input stages 110, 605 generate a pair of differential voltages based on the input voltages. (Block 1410). In some examples, the current through the transistors 625, 635, 650, 660 and the transconductance of the transistors sets the inputs of the opposing buffer stages 120, 205, 300, 400, 500, 610, 1003, 1105, 1205, 1305 to be proportional to the voltage difference between the inverting and non-inverting inputs of the amplifier circuitry 100, 1000, 1100, 1200, 1300. In other examples, for example, Figure 6 , one input of the opposing buffer stage 120, 205, 300, 400, 500, 610, 1003, 1105, 1205, 1305 may be fixed, and the input stage 110, 605 generates a differential voltage in response to setting a voltage at a second input of the opposing buffer stage 120, 205, 300, 400, 500, 610, 1003, 1105, 1205, 1305.

[0255] Figure 10 、 11 The buffer circuit systems 1008, 1115 of 1111, 112, and 13 generate first and second currents using the first and second bias currents and a pair of differential voltages. (Block 1415). In example operation, Figure 10 、 11 , 12 and 13 transistors 1021, 1120, 1125 and Figure 10 、 11 , 12 and 13 of the current source circuit system 1009 is configured to form a current source circuit by offsetting the input voltage (V IN_STAGE ) to control Figure 10 、 11 , 12 and 13 of the transistor 1027, 1140 voltage source circuit system. For example, in some examples, such as Figure 3 、 4 and 5, the current source circuitry 1009 and transistors 1021, 1120, 1125 may be shown and described as voltage source circuitry, e.g. Figure 3 、 4 In such an example operation, transistors 1027, 1140 conduct reverse sink current (I SNK- ).

[0256] Similarly, Figure 10 、 11 , 12 and 13 transistors 1024, 1130, 1135 and Figure 10 、 11 , 12 and 13 of the current source circuit system 1012 is configured to form a current source circuit by offsetting the input voltage (V IN_STAGE ) to control Figure 10 、 11 , 12 and 13 of the transistor 1030, 1145 of the voltage source circuit system. For example, in some examples, such as Figure 3 、 4 and 5, the current source circuitry 1012 and transistors 1024, 1130, 1135 may be shown and described as voltage source circuitry, e.g. Figure 3 、 4 In such an example operation, transistors 1030, 1145 conduct a non-inverting source current (I SRC+ ).

[0257] Figure 10 、 11 The buffer circuit systems 1018, 1215 of 1, 12, and 13 generate third and fourth currents using the third and fourth bias currents and a pair of differential voltages. (Block 1420). In example operation, Figure 12 The transistor 1230 and Figure 12 The current source circuit system 1220 is configured to form a current source circuit by offsetting the reference voltage (V REF ) to control Figure 12 The voltage source circuit system of transistor 1240. For example, in some examples, such as Figure 3 、 4 and 5, the current source circuitry 1220 and transistor 1230 may be shown and described as voltage source circuitry, e.g. Figure 3 、 4 In such an example operation, transistor 1240 conducts a non-inverting sink current (I SNK+ ).

[0258] Similarly, Figure 12 The transistor 1235 and Figure 12 The current source circuit system 1225 is configured to form a current source circuit by offsetting the reference voltage (V REF ) to control Figure 12 The voltage source circuit system of transistor 1245. For example, in some examples, such as Figure 3 、 4 and 5, the current source circuitry 1225 and transistor 1235 may be shown and described as voltage source circuitry, e.g. Figure 3 、 4 In such an example operation, transistor 1245 conducts an inverted source current (I SRC- ). Figure 12 The buffer circuit system 1215 represents Figure 10 、 11 13. In some examples, opposing buffer stages 1003, 1105, 1205, 1305 can be modified to illustrate one or more components of buffer circuitry 1215 external to buffer circuitry 1018.

[0259] Figure 10 、 11 The gate bias circuitry 1045 of transistors 1024, 1135 biases the first gate using at least a portion of the second bias current. (Block 1425). In some examples, transistors 1024, 1135 couple the gate bias circuitry 1045 to the current source circuitry 1012. In such examples, the current source circuitry 1012 is coupled to the first gate via Figure 10 、 11 In the example operation, the current source circuit system 1012 will Figure 10 、 11 The control terminals of transistors 1084, 12, and 13 are biased to approximately the supply voltage (V DD ) minus the gate-to-source voltage of transistors 1069, 1072. Advantageously, using current source circuitry 1012 to bias transistor 1084 reduces the need for additional current sources for biasing transistors 1069, 1072. Advantageously, reducing the number of current source circuitry instances reduces power consumption, system-on-chip size, cost, complexity, etc.

[0260] Figure 10 、 11The gate bias circuitry 1048 of transistors 1021, 1125 and 1046 biases the second gate using at least a portion of the first bias current. (Block 1430). In some examples, transistors 1021, 1125 couple the gate bias circuitry 1048 to the current source circuitry 1009. In such examples, the current source circuitry 1009 is coupled to the gate bias circuitry 1048 via the gate bias circuitry 1048. Figure 10 、 11 In the example operation, the current source circuit system 1009 will Figure 10 、 11 , 12 and 13 are biased to a control terminal of transistor 1081 approximately equal to a common potential (V SS ) plus the gate-to-source voltage of transistors 1075, 1078. Advantageously, using current source circuitry 1009 to bias transistor 1081 reduces the need for additional current sources for biasing transistors 1075, 1078. Advantageously, reducing the number of current source circuitry instances reduces power consumption, system-on-chip size, cost, complexity, etc.

[0261] Figure 10 、 11 , 12 and 13 of the current mirror circuit system 1033, 1315 and Figure 10 、 11 The class AB control circuitry 1051 of 1033, 1315 uses at least a portion of the first bias current and the first and third currents to control the high-side output transistor. (Block 1435). In example operation, the current mirror circuitry 1033, 1315 mirrors at least the inverted sink current. In some embodiments, for example Figure 11 、 12 13, current mirror circuitry 1033, 1315 mirrors the inverted sink current through transistor 1140 and a portion of the current sunk by current source circuitry 1012. For example, transistor 1130 coupled to current source circuitry 1012 is coupled to current mirror circuitry 1033, 1315, which boosts the current at the output of current mirror circuitry 1033, 1315. In such an example, transistor 1130 or current source circuitry 1012 may be sized to replace Figure 10 1084. Advantageously, the use of current source circuitry 1012 and transistor 1130 to bias class AB control circuitry 1051 replaces the need for current source circuitry 1039. Advantageously, reducing the number of current source circuitry instances reduces system on chip size, cost, complexity, etc. In such example operation, transistors 1081, 1084 are set in response to the difference between the inverting and non-inverting sink currents. Figure 10、 11 , 12 and 13 are control terminals of transistor 1087.

[0262] Figure 10 、 11 The current mirror circuit systems 1036, 1325 of 1036, 1325 and the class AB control circuit system 1051 use at least a portion of the second bias current and the second and fourth currents to control the low-side output transistor. (Block 1440). In example operation, the current mirror circuit systems 1036, 1325 mirror at least the non-inverting source current. In some embodiments, for example Figure 11 、 12 13, current mirror circuitry 1036, 1325 mirrors the non-inverting source current through transistor 1145 and a portion of the current provided by current source circuitry 1009. For example, transistor 1120 coupled to current source circuitry 1009 is coupled to current mirror circuitry 1036, 1325, which boosts the current at the output of current mirror circuitry 1036, 1325. In such an example, transistor 1120 or current source circuitry 1009 may be sized to replace Figure 10 1084. Advantageously, the use of current source circuitry 1009 and transistor 1120 to bias class AB control circuitry 1051 replaces the need for current source circuitry 1042. Advantageously, reducing the number of current source circuitry instances reduces system on chip size, cost, complexity, etc. In such example operation, transistors 1081, 1084 are set in response to the difference between the inverting and non-inverting source currents. Figure 10 、 11 , 12 and 13 are control terminals of transistor 1090.

[0263] Control continues back to block 1405. Figure 14 The flowchart shown in describes an example method. However, implementation Figure 1 、 10 , 11, 12 and 13 of the opposing buffer stages 120, 1003, 1105, 1205, 1305 and Figure 1 、 10 , 11, 12 and 13 output stages 130, 1006, 1110, 1210, 1310 or more generally Figure 1 、 10Many other methods of the amplifier circuit systems 100, 1000, 1100, 1200, 1300 of FIG. 1 , 11, 12, and 13 may also be used in this specification. For example, the order of execution of the blocks may be changed, or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the fabrication process before, between, or after the blocks shown in the illustrated examples.

[0264] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open terms. Thus, whenever a claim uses any form of "including" or "comprising" (e.g., comprises, comprising, includes, including, having, etc.) as a preamble or in any type of claim recitation, additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or reference. As used herein, when the phrase "at least" is used as a transition term, such as in the preamble of a claim, it is open in the same manner that the terms "including" and "comprising" are open. The term "and / or" when used in the form, for example, A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) A only, (2) B only, (3) C only, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A and B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A or B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the implementation or execution of a process, instruction, act, activity, etc., the phrase "at least one of A and B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of a process, instruction, action, activity, etc., the phrase "at least one of A or B" refers to an embodiment that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0265] As used herein, singular references (e.g., "a / an," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of the objects described. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Moreover, although individual features may be included in different examples or claims, these features may potentially be combined, and their inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0266] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the Earth. A first part is above a second part if the second part has at least one portion between the Earth and the first part. Similarly, as used herein, a first part is "below" a second part when the first part is closer to the Earth than the second part. As mentioned above, a first part can be above or below a second part, with one or more of the following: with other parts in between, without other parts in between, with the first and second parts in contact, or with the first and second parts not in direct contact with each other.

[0267] As used in this patent, stating that any part (e.g., a layer, film, region, area, or plate) is in any manner located on another part (e.g., located on, positioned on, disposed on, or formed on, etc.) indicates that the referenced part is in contact with the other part, or that the referenced part is above the other part with one or more intermediate parts positioned therebetween.

[0268] As used herein, unless otherwise indicated, connection references (e.g., fitted, coupled, connected, and joined) may include intermediate members between the elements referenced by at least one of the connection reference or relative movement between those elements. Thus, connection references do not necessarily infer that two elements are directly connected or in fixed relation to each other. As used herein, stating that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0269] Unless otherwise specifically stated, descriptors such as "first," "second," and "third" are used herein without imposing or otherwise indicating a priority in a list, a physical order, an arrangement, or ordering in any manner, but are merely used as at least one of a label or arbitrary name to distinguish elements to facilitate understanding of the described examples. In some examples, the descriptor "first" may be used to refer to an element in a specific embodiment, while the same element may be referred to in the technical solution by a different descriptor such as "second" or "third." In such cases, such descriptors are used only to clearly identify those elements within the context of the discussion (e.g., within the claims), where the elements may, for example, otherwise share the same name.

[0270] As used herein, "approximately" and "about" modify the subject matter / value thereof to recognize the potential for variations that occur in real-world applications. For example, "approximately" and "about" may modify a dimension that may not be exact due to at least one of manufacturing tolerances or other real-world imperfections. For example, unless otherwise specified herein, "approximately" and "about" may indicate that such dimension may be within a tolerance range of + / - 10%.

[0271] As used herein, the phrase "communication," including variations thereof, encompasses one or a combination of direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication at at least one of periodic intervals, predetermined intervals, non-periodic intervals, or one-time events.

[0272] As used herein, "programmable circuitry" is defined as including at least one of: (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) that are constructed to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform one or more specific functions or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include a programmable microprocessor, such as a central processing unit (CPU), which can execute a first instruction to perform one or more operations or functions; a field programmable gate array (FPGA), which can be programmed with a second instruction to configure or structure the FPGA to instantiate one or more operations or functions corresponding to the first instruction; a graphics processor unit (GPU), which can execute a first instruction to perform one or more operations or functions; a digital signal processor (DSP), which can execute a first instruction to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers, which can execute a first instruction to perform one or more operations or functions; or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination thereof) and orchestration technology (e.g., an application programming interface (API)) that can distribute computing tasks to any one or more types of programmable circuitry among the multiple types of programmable circuitry that is suitable and available to perform the computing tasks.

[0273] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system-on-chip (SoC), etc.

[0274] In this description, the term "coupled" can encompass connections, communications, or signal paths that achieve a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not modify the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A.

[0275] A device that is "configured to" perform a task or function may be configured (e.g., at least one of programmed or hardwired) to perform the function when manufactured by the manufacturer or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or at least one of other additional or alternative functions. The configuration may be performed by at least one of firmware or software programming of the device, by at least one of the construction or layout of the hardware components and interconnections of the device, or by a combination thereof.

[0276] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection between or terminations of a device element, circuit element, integrated circuit, device, or other electronic device or semiconductor component.

[0277] In this specification and claims, a "circuitry" described may include one or more circuits. A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., at least one of a semiconductor die or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements or sources at or after the time of manufacture, for example, by at least one of an end user or a third party, to form the described structure.

[0278] The circuits described herein can be reconfigured to include replacement components to provide functionality that is at least partially similar to the functionality available before the component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in at least one of series or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described as a single component herein may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor. Although some elements of the described examples are included in the integrated circuit and other elements are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as being outside the integrated circuit may be included in the integrated circuit, and some features shown as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are at least one of: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; or (iv) incorporated in / on the same printed circuit board.

[0279] The use of the phrase "ground" in the foregoing description includes at least one of chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the value, or, if the value is zero, means a reasonable range of values ​​around zero.

[0280] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A device comprising: a first buffer circuit system having an input and an output; a second buffer circuitry having an input and an output; a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the output of the first buffer circuitry and the second terminal of the resistor being coupled to the output of the second buffer circuitry; a third buffer circuitry having an input and an output, the input of the third buffer circuitry being coupled to the input of the first buffer circuitry; as well as A switch circuit system has a first terminal and a second terminal, the first terminal of the switch circuit system is coupled to the input of the second buffer circuit system, and the second terminal of the switch circuit system is coupled to the output of the third buffer circuit system.

2. The apparatus of claim 1 , wherein the switching circuitry comprises: a first transistor having a first terminal and a second terminal; and a second transistor having a first terminal coupled to the output of the third buffer circuitry and the first terminal of the first transistor, and a second terminal coupled to the input of the second buffer circuitry and the second terminal of the first transistor.

3. The apparatus of claim 1 , wherein the first buffer circuitry further has a first control terminal and a second control terminal, and wherein the third buffer circuitry comprises: a first transistor having a first terminal and a control terminal, the control terminal of the first transistor coupled to the first control terminal of the first buffer circuitry; and A second transistor has a first terminal and a control terminal, the first terminal of the second transistor being coupled to the first terminal of the first transistor, the control terminal of the second transistor being coupled to the second control terminal of the first buffer circuitry.

4. The apparatus of claim 3 , wherein the first transistor further has a second terminal, the second transistor further has a second terminal, the first terminal of the first transistor is coupled to the input of the second buffer circuitry and the first terminal of the second transistor, and the switch circuitry comprises: a third transistor having a terminal coupled to the second terminal of the first transistor; and A fourth transistor has a terminal coupled to the second terminal of the second transistor.

5. The apparatus of claim 4 , wherein the terminal of the third transistor is a first terminal, the terminal of the fourth transistor is a first terminal, the third transistor further has a second terminal, the fourth transistor further has a second terminal, and the apparatus further comprises: a first current mirror circuitry having an input and an output, the input of the first current mirror circuitry being coupled to the second terminal of the third transistor; and a second current mirror circuit system having an input and an output, the input of the second current mirror circuit system being coupled to the second terminal of the fourth transistor, the output of the second current mirror circuit system being coupled to the input of the second buffer circuit system, the first terminal of the first transistor, the first terminal of the second transistor, and the output of the first current mirror circuit system.

6. The apparatus of claim 1 , further comprising: The second buffer circuit system comprises: a first transistor having a first terminal and a control terminal; a second transistor having a first terminal and a control terminal, the control terminal of the second transistor being coupled to the control terminal of the first transistor; a third transistor having a first terminal and a control terminal; as well as a fourth transistor having a first terminal and a control terminal, the first terminal of the fourth transistor being coupled to the first terminal of the third transistor; and The third buffer circuit system comprises: a fifth transistor having a first terminal and a control terminal, the first terminal of the fifth transistor being coupled to the first terminal of the first transistor and the control terminal of the third transistor; as well as a sixth transistor having a first terminal and a control terminal, the first terminal of the sixth transistor being coupled to the first terminal of the second transistor and the control terminal of the fourth transistor, the control terminal of the sixth transistor being coupled to the input of the first buffer circuitry and the control terminal of the fifth transistor.

7. The apparatus of claim 6 , wherein the first buffer circuitry further has a power supply terminal, The second buffer circuitry further has a power supply terminal, and the apparatus further comprises: current mirror circuitry having an input and an output, the input of the current mirror circuitry coupled to the second terminal of the switch circuitry; an input stage circuitry comprising a transistor having a first terminal coupled to the output of the current mirror circuitry and a second terminal coupled to the input of the second buffer circuitry; as well as An output stage circuit system has a first input and a second input, the first input of the output stage circuit system is coupled to the power supply terminal of the first buffer circuit system, and the second input of the output stage circuit system is coupled to the power supply terminal of the second buffer circuit system.

8. The apparatus of claim 7 , wherein the switch circuitry further has a control terminal, the output stage circuitry further has a control terminal, and the apparatus further comprises control circuitry comprising: a first inverter having an output; a second inverter having an input and an output, the input of the second inverter being coupled to the output of the first inverter; and A delay circuit system has an input and an output, the input of the delay circuit system is coupled to the control terminal of the output stage circuit system and the output of the second inverter, and the output of the delay circuit system is coupled to the control terminal of the switch circuit system.

9. The apparatus of claim 1 , wherein the first buffer circuitry further has a power supply terminal, and the apparatus further comprises: The second buffer circuit system comprises: a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal, the control terminal of the second transistor coupled to the first terminal of the switching circuitry and the control terminal of the first transistor; as well as a third transistor having a control terminal coupled to the first terminal of the first transistor and the first terminal of the second transistor; a current mirror circuit system having an input and an output, the input of the current mirror circuit system being coupled to the second terminal of the first transistor, the output of the current mirror circuit system being coupled to the power supply terminal of the first buffer circuit system; as well as Gate bias circuitry has a terminal coupled to the second terminal of the second transistor.

10. A device comprising: an input stage circuit system having an output; an opposed buffer stage circuitry having a first input, a second input, and an output; output stage circuitry having an input coupled to the output of the opposed buffer stage circuitry; buffer circuitry having an input and an output, the input of the buffer circuitry coupled to the first input of the opposing buffer stage circuitry; as well as A switch circuit system has a first terminal and a second terminal, the first terminal of the switch circuit system is coupled to the output of the buffer circuit system, and the second terminal of the switch circuit system is coupled to the output of the input stage circuit system and the second input of the opposing buffer stage circuit system.

11. The apparatus of claim 10, further comprising: current mirror circuitry having an input and an output, the input of the current mirror circuitry coupled to the second terminal of the switch circuitry; and The input stage circuitry includes a transistor having a first terminal coupled to the output of the current mirror circuitry and a second terminal coupled to the second input of the opposing buffer stage circuitry.

12. The apparatus of claim 10, wherein the switching circuitry comprises: a first transistor having a first terminal and a second terminal; and a second transistor having a first terminal and a second terminal, the first terminal of the second transistor being coupled to the output of the buffer circuitry and the first terminal of the first transistor, the second terminal of the second transistor being coupled to the output of the input stage circuitry, the second input of the opposing buffer stage circuitry, and the second terminal of the first transistor.

13. The apparatus of claim 10 , wherein the buffer circuitry has a first power supply terminal and a second power supply terminal, the output of the buffer circuitry is coupled to the output of the input stage circuitry and the second input of the opposing buffer stage circuitry, and the switch circuitry comprises: a first transistor having a terminal coupled to the first power supply terminal of the buffer circuitry; and A second transistor has a terminal coupled to the second power supply terminal of the buffer circuitry.

14. The apparatus of claim 13, further comprising: a first current mirror circuitry having an input and an output, the input of the first current mirror circuitry being coupled to the second terminal of the first transistor; as well as a second current mirror circuit system having an input and an output, the input of the second current mirror circuit system being coupled to the second terminal of the second transistor, the output of the second current mirror circuit system being coupled to the output of the input stage circuit system, the second input of the opposing buffer stage circuit system, the output of the buffer circuit system, and the output of the first current mirror circuit system.

15. The apparatus of claim 10, wherein the buffer circuitry is a first buffer circuitry and the opposing buffer stage circuitry comprises: a second buffer circuitry having an input, an output, and a power supply terminal, the input of the second buffer circuitry being coupled to the input of the first buffer circuitry, the power supply terminal of the second buffer circuitry being coupled to the first input of the output stage circuitry; and a third buffer circuit system having an input, an output, and a power supply terminal, the input of the third buffer circuit system being coupled to the output of the input stage circuit system and the output of the first buffer circuit system, the output of the third buffer circuit system being coupled to the output of the second buffer circuit system, and the power supply terminal of the third buffer circuit system being coupled to the second input of the output stage circuit system.

16. The apparatus of claim 10, wherein the switch circuitry further has a control terminal, the output stage circuitry further has a control terminal, and the apparatus further comprises control circuitry comprising: a first inverter having an output; a second inverter having an input and an output, the input of the second inverter being coupled to the output of the first inverter; and A delay circuit system has an input and an output, the input of the delay circuit system is coupled to the control terminal of the output stage circuit system and the output of the second inverter, and the output of the delay circuit system is coupled to the control terminal of the switch circuit system.

17. The apparatus of claim 10, further comprising: The opposing buffer stage circuit system comprises: a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal, the control terminal of the second transistor coupled to the second terminal of the switch circuitry, the output of the input stage circuitry, and the second input of the opposing buffer stage circuitry; as well as a third transistor having a first terminal and a control terminal, the control terminal of the third transistor being coupled to the first terminal of the first transistor and the first terminal of the second transistor; a current mirror circuitry having an input and an output, the input of the current mirror circuitry being coupled to the second terminal of the first transistor and the first terminal of the third transistor; gate bias circuitry having terminals; as well as A class AB control circuit system having a first terminal and a second terminal, wherein the first terminal of the class AB control circuit system is coupled to the output of the current mirror circuit system, and the second terminal of the class AB control circuit system is coupled to the second terminal of the second transistor and the terminal of the gate bias circuit system.

18. An apparatus comprising: an opposed buffer stage circuitry having a first input and a second input; a transistor having a first terminal and a second terminal; current mirror circuitry having an input and an output, the output of the current mirror circuitry coupled to the first terminal of the transistor; switching circuitry having a first terminal and a second terminal, the first terminal of the switching circuitry being coupled to the input of the current mirror circuitry; as well as A buffer circuit system having an input, an output and a power supply terminal, wherein the input of the buffer circuit system is coupled to the first input of the opposing buffer stage circuit system, the output of the buffer circuit system is coupled to the second input of the opposing buffer stage circuit system and the second terminal of the transistor, and the power supply terminal of the buffer circuit system is coupled to the second terminal of the switch circuit system.

19. The apparatus of claim 18, wherein the buffer circuitry further comprises a second power supply terminal, the transistor is a first transistor, the switch circuitry is a first switch circuitry, the current mirror circuitry is a first current mirror circuitry, and the apparatus further comprises: a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the second terminal of the first transistor, the second input of the opposing buffer stage circuitry, and the output of the buffer circuitry; a second current mirror circuitry having an input and an output, the output of the second current mirror circuitry being coupled to the second terminal of the second transistor; as well as A second switch circuit system has a first terminal and a second terminal, the first terminal of the second switch circuit system is coupled to the input of the second current mirror circuit system, and the second terminal of the second switch circuit system is coupled to the second power supply terminal of the buffer circuit system.

20. The apparatus of claim 19, wherein the first switching circuitry further has a control terminal, The second switching circuitry further has a control terminal, and the apparatus further comprises: a delay circuit system having an output; as well as An inverter having an input and an output, the input of the inverter being coupled to the control terminal of the second switching circuitry and the output of the delay circuitry, the output of the inverter being coupled to the control terminal of the first switching circuitry.

21. The apparatus of claim 19, wherein the buffer circuitry comprises: a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor being coupled to the second terminal of the first switch circuitry, the second terminal of the third transistor being coupled to the opposing buffer stage circuitry; and a fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor is coupled to the opposing buffer stage circuit system, the second terminal of the fourth transistor is coupled to the second terminal of the second switch circuit system, and the control terminal of the fourth transistor is coupled to the first input of the opposing buffer stage circuit system and the control terminal of the third transistor.

22. The apparatus of claim 18, wherein the buffer circuitry is a first buffer circuitry and the opposing buffer stage circuitry comprises: a second buffer circuitry having an input and an output, the input of the second buffer circuitry being coupled to the input of the first buffer circuitry; and A third buffer circuit system has an input and an output, the input of the third buffer circuit system being coupled to the second terminal of the transistor and the output of the first buffer circuit system, and the output of the third buffer circuit system being coupled to the output of the second buffer circuit system.

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