Multi-channel synchronous acquisition device based on FPGA (Field Programmable Gate Array)
By adopting a multi-channel synchronous acquisition device of block random access memory and DSP unit in FPGA, the problem of excessive resource occupation in multi-channel data acquisition is solved, the synchronous acquisition of digital and analog signals is realized, resource usage is reduced and a wider range of sampling rate configurations are supported.
Patent Information
- Application Number
- CN202510944530.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-09
- Publication Date
- 2025-09-16
AI Technical Summary
In the prior art of multi-channel data acquisition, the synchronous acquisition of digital and analog signals consumes too many resources, especially when channels with different sampling rates are difficult to achieve synchronization.
An FPGA-based multi-channel synchronous acquisition device is used to achieve synchronous acquisition through the block random access memory in the digital signal acquisition module and the DSP unit in the analog signal acquisition module. The digital signal adopts a delay alignment method, the analog signal adopts an extraction filtering method, and is synchronously processed through a multi-channel extractor and selector.
It realizes the synchronous acquisition of digital and analog signals under channels with different sampling rates, reduces the usage of FPGA resources, supports a wider range of sampling rate configurations, and ensures the synchronization characteristics of all channels.
Smart Images
Figure CN120658270A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a multi-channel data acquisition device, in particular to a multi-channel synchronous acquisition device based on FPGA. Background Art
[0002] The condition monitoring collector collects analog signals and digital signal pulses, such as speed pulses. There may be many channels on site, and each channel has a different sampling rate according to the measurement point requirements.
[0003] Usually, the sampling input is divided into digital signals and analog signals. For digital signals, it is equivalent to 1 bit, and for analog signals, it is equivalent to N bits. As a common implementation description, for example, to implement an 8-channel analog input, the ADC uses a 24-bit and 8-channel ADC, such as the SigmaDELTA architecture ADC. The SigmaDELTA architecture ADC causes a delay in its output, which is generally calculated based on the original sampling rate Fs of the ADC, 1 / FS = (sample); then the delay delayADC = N (sample).
[0004] The ADC uses the same sampling rate for all eight channels. This solution is used as an example, not limited to eight channels. A 100K sampling rate is used as an implementation example. For analog signals, the ADC output is FS = 100K, with a delay of N (samples). For digital signals, the output sampling clock is FD. As an implementation example, FS * 256 is used, which is 25.6M.
[0005] In order to align the digital signal with the analog signal, the digital signal needs to be delayed by N (sample). In the example, the digital signal sampling rate is 256*Fs, which means that the digital signal needs to be delayed by 256*N clk, where CLK=25.6M.
[0006] Existing technology generally stores 256*N bits of information in sequence into the FIFO. The digital input is equivalent to 1 bit of information, which is counted by CLK. When the count value reaches 256*N, it is output from the FIFO in sequence. The existing solution has the following defects: 1 bit of information is generally stored in discrete reg in FPGA. Considering that 256*N is relatively large, it will occupy more resources. Summary of the Invention
[0007] The purpose of the present invention is to provide a multi-channel synchronous acquisition device based on FPGA in order to overcome the defects of the above-mentioned prior art.
[0008] The purpose of the present invention can be achieved by the following technical solutions:
[0009] According to one aspect of the present invention, there is provided an FPGA-based multi-channel synchronous acquisition device, comprising a digital signal acquisition module and an analog signal acquisition module, wherein the digital signal acquisition module comprises a digital signal input terminal, a digital signal delay unit, and a digital signal output terminal connected in sequence, and the analog signal acquisition module comprises an analog signal input terminal, a first-level multi-channel decimator, a second-level multi-channel decimator, a selector, and an analog signal output terminal, wherein the analog signal input terminal, the first-level multi-channel decimator, the selector, and the analog signal output terminal are connected in sequence, and the first-level multi-channel decimator, the second-level multi-channel decimator, and the selector are connected in sequence;
[0010] The digital signal delay unit adopts a block random access memory in the FPGA, and the first-level multi-channel decimator and the second-level multi-channel decimator both adopt a DSP unit in the FPGA;
[0011] The delay time of the digital signal delay unit is configured to be the same as the extraction time of the multi-channel extractor, so that the digital signal and the analog signal are collected synchronously.
[0012] As a preferred technical solution, the first-level multi-channel extractor and the second-level multi-channel extractor are multi-channel extractors with the same structure.
[0013] As a preferred technical solution, the multi-channel extractor includes channel data buffer units, channel coefficient buffer units, an arbitration unit, a multiplier-adder unit and an extraction result output unit. The input end of the arbitration unit is respectively connected to the channel data buffer unit and the channel coefficient buffer unit, the output end of the arbitration unit is connected to the input end of the multiplier-adder unit, and the output end of the multiplier-adder unit is connected to the extraction result output unit.
[0014] As a preferred technical solution, the multi-channel decimator adopts a four-channel decimator, and every four channels share one multiplier-accumulator unit.
[0015] As a preferred technical solution, there are four channel data buffer units and four channel coefficient buffer units, and the two are in one-to-one correspondence.
[0016] As a preferred technical solution, each of the channel data buffer units is connected to the analog signal input terminal via a buffer write control unit.
[0017] As a preferred technical solution, the arbitration unit is a circular arbiter, which buffers the requests of each channel.
[0018] As a preferred technical solution, the analog signal acquisition modules are provided with two, for a total of eight channels.
[0019] As a preferred technical solution, the digital signal acquisition module is provided with two channels in total.
[0020] As a preferred technical solution, the coefficient orders of the first-stage multi-channel decimator and the second-stage multi-channel decimator are both even numbers.
[0021] Compared with the prior art, the present invention has the following advantages:
[0022] 1) The present invention realizes synchronous acquisition and filtering of digital and analog signals in the case of multiple channels. Different processing methods are adopted for digital signals and analog signals. The digital signal adopts the delay alignment method, and the analog signal adopts the decimation filtering method. When the digital signal and the analog signal are configured with different sampling rates for each channel, the synchronization characteristics of all channels of the digital signal and the analog signal can still be guaranteed.
[0023] 2) The present invention can use an independent sampling rate for each channel and continuously process all channel data. Multi-level decimation can support scaling factors from the highest to the lowest sampling rate, thereby making the present invention more widely applicable.
[0024] 3) The present invention reduces FPGA resource usage by reusing DSP units;
[0025] 4) The present invention adopts edge time recording for digital signals and outputs them in alignment with analog delay, thereby reducing the use of FPGA resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 It is a structural schematic diagram of the present invention;
[0027] Figure 2 Schematic diagram of the digital signal acquisition module of the present invention;
[0028] Figure 3 Schematic diagram of the analog signal acquisition module of the present invention;
[0029] Figure 4 is a schematic diagram of a four-channel decimator of the present invention;
[0030] Figure 5 Schematic diagram of extracted data of a primary multi-channel decimator and a secondary multi-channel decimator of the present invention;
[0031] Figure 6 Schematic diagram of the analog signal output terminal of the present invention. DETAILED DESCRIPTION
[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0033] like Figure 1 As shown, the FPGA-based multi-channel synchronous acquisition device of the present invention includes a digital signal acquisition module 1 and an analog signal acquisition module 2. The digital signal acquisition module 1 includes a digital signal input terminal 11, a digital signal delay unit 12, and a digital signal output terminal 13 connected in sequence. The analog signal acquisition module 2 includes an analog signal input terminal 21, a first-level multi-channel decimator 22, a second-level multi-channel decimator 23, a selector 24, and an analog signal output terminal 25. The analog signal input terminal 21, the first-level multi-channel decimator 22, the selector 24, and the analog signal output terminal 25 are connected in sequence. The first-level multi-channel decimator 22, the second-level multi-channel decimator 23, and the selector 24 are connected in sequence.
[0034] The digital signal delay unit 12 uses a block random access memory in the FPGA, and the first-level multi-channel extractor 22 and the second-level multi-channel extractor 23 both use a DSP unit in the FPGA; the delay time of the digital signal delay unit is configured to be the same as the extraction time of the multi-channel extractor, thereby synchronously collecting digital signals and analog signals.
[0035] That is, the present invention realizes synchronous acquisition and filtering of digital signals and analog signals in the case of multiple channels, adopts different processing methods for digital signals and analog signals, uses the delay alignment method for digital signals, and adopts the extraction filtering method for analog signals. When the digital signals and analog signals are configured with different sampling rates for each channel, the synchronization characteristics of all channels of digital signals and analog signals can still be guaranteed.
[0036] This embodiment is described by taking 8 analog channels and 2 digital channels as an example.
[0037] The present invention takes into account the sparseness of actual digital input pulses, such as speed pulses, which usually have a frequency of <1K. For digital signals, it is only necessary to record the moments of the rising and falling edges.
[0038] like Figure 2As shown, the digital signal delay unit 12 of the present invention is specifically as follows: the left side is a multi-bit FIFO, for example, 32 bits, the upper 31 bits of t1 are used as the count value, and the lower bit is used as the rising edge or falling edge mark. If a rising edge or a falling edge event occurs, t(n) is entered into the FIFO. The monitor checks the empty flag of the FIFO. If it is not empty, it reads out 32 bits and uses the upper 32 bits as t. Then, it compares whether the counter T=t+(256*N) is established. If it is established, the rising edge or falling edge of the signal is output. Such a FIFO can be conveniently implemented using the blockRAM block of the FPGA, which saves FPGA resources. The depth of the FIFO can be determined according to the sparseness of the signal. Generally, 128 can meet the 1K digital signal frequency.
[0039] like Figure 3 As shown, the analog signal acquisition module of the present invention is to realize different sampling rates of 8-channel simulation and perform decimation on the ADC of the original sampling rate. The original sampling rate is 100K. For example, to realize a sampling frequency of 10K, a 10:1 decimation filter FIR can be used. Generally speaking, the order of this FIR is around several hundred. As an example for convenient implementation, the present invention realizes a filter with a maximum coefficient of 1000. This coefficient can realize a maximum decimation of about 20:1 or less. Taking into account the actual possible lower sampling rate, the present invention uses a two-stage structure for multiple decimation to achieve a higher decimation multiple.
[0040] 8-channel analog input uses 24-bit data, and the filter coefficients also use 24 bits. As the FIR multiplication and addition unit, the present invention designs an accumulator unit that accumulates 24bit*24bit to 56bit. The DSP unit in a general FPGA is 18bit*18bit. The present invention uses 4 FPGA DSP units to implement a 24bit*24bit multiplication and addition unit.
[0041] As a high bit multiplier-accumulator (MAC), a practical example, the MAC unit of the present invention operates at 100M,
[0042] Given the scarcity of FPGA DSP resources, if two independent MAC units are assigned to each channel, 8*2*4=64 18*18 DSP units are required. However, the present invention takes into account the actual computing power required and adopts a MAC unit shared by every four channels. This requires a total of four MAC units, or 16 18*18 DSP units.
[0043] The first and second stages of the 4-channel decimator use the same design. Figure 3 Some connections are omitted, only channels 1 and 8 are connected.
[0044] The purpose of using two stages is mainly for feasibility considerations: to achieve, for example, 100:1 extraction, the coefficient order of a single-stage extraction FIR filter is very high, possibly as high as tens of thousands, and storing a large number of coefficients will bring resource pressure. In the case of two stages, the coefficient order can be controlled below 1000, so that the maximum coefficient of the two stages is only 2000, reducing the coefficient storage resource pressure.
[0045] The 8-channel output also adopts the same design, and the output channels can be selected from the first-stage extraction or the second-stage extraction.
[0046] The following is a description of the channel extractor and output device:
[0047] like Figure 4 As shown, it is a block diagram of a 4-channel decimator, which includes a 4-channel data buffer unit, a 4-channel coefficient buffer unit, an arbitration unit, a multiplier-adder unit, and an extraction result output unit. The input end of the arbitration unit is connected to the 4-channel data buffer unit and the 4-channel coefficient buffer unit respectively, the output end of the arbitration unit is connected to the input end of the multiplier-adder unit, and the output end of the multiplier-adder unit is connected to the extraction result output unit.
[0048] like Figure 5 As shown, if the channel output is selected from the first stage, as an example here, the coefficient length of the selected unit is recorded as M1. If the selected output stage is the second stage, then the coefficient length of the selected unit is recorded as M2, and the extraction ratio of the second stage front stage is selected as D1.
[0049] It can be seen that the first level of extraction affects the M1 sampling points before the D sampling points, that is, these points participate in the filtering calculation;
[0050] The second-level extraction affects a total of M2*D1 before and after. Record M1 or M2*D1 as L, select the largest affected range Lmax among the 8 channels, and then the D of a sampling point on the original data axis must satisfy D>(Lmax / 2).
[0051] By selecting a suitable D, the (D)th sampling point of the original ADC output is determined as the output starting point of the solution.
[0052] In order to realize the D moment of the first data output of the first level mapping to the original data
[0053] The first calculation needs to start at time (D+(M1 / 2));
[0054] Then the second calculation starts at time (D+(M1 / 2))+D1, where D1 is the decimation rate of the selected first level, and then the third calculation starts at time (D+(M1 / 2))+2*D1.
[0055] ...and so on
[0056] The Nth calculation starts at time (D+(M1 / 2))+(N-1)*D1.
[0057] Figure 4 The block diagram needs to control the multiplier-accumulator unit to complete the calculation
[0058] X(N)*C0+X(N-1)*C1+....+X(N-M1)*C(M1)
[0059] Where X is the data buffer in the block diagram; C is the coefficient buffer; and the corresponding address subscripts are in (). According to the FIR filter principle diagram, for example, to achieve 2:1 decimation; assuming the sampling frequency is fs, the actual cutoff frequency is fc, and the normalized cutoff frequency is fcm, fcm = fc / (fs / 2); the channel frequency fpm = fp / (fs / 2), the FIR filter composed of coefficients C0...C(M1) needs to meet the normalized frequency fpm = 0.4 and fcm = 0.5. After the filter satisfies the above passband and cutoff frequency, the sampling rate of the original data can be directly reduced from fs to fs / 2 without losing any valid information or causing aliasing.
[0060] The above is the situation of the first level. If the second level is not selected, the above calculation can be used.
[0061] If the second level is selected, the feed of the second level needs to be considered, so the feed time will be advanced. If the second level is selected, the first point of the second level also needs to correspond to the time D of the original data axis, so the feed time is advanced by (M2*D1 / 2).
[0062] That is, the first feed lower-level calculation starts at time (D+(M1 / 2))-(M2*D1) / 2.
[0063] Note that M2 and M1 must be even numbers to ensure that the feed time and output time coincide on the discrete time axis extracted by D1.
[0064] The arbitration unit usage rights are arbitrated according to the feed time and output time. In order to avoid congestion caused by all channels initiating req at a certain time, the arbitration unit uses a round-robin arbiter and buffers req, with 8 levels of req buffering for each channel, that is, arbitration is initiated again when req arbitration is not completed.
[0065] like Figure 6 As shown, the analog signal output terminal of the present invention is specifically:
[0066] For analog channels, the first output data is at time D on the original data axis. To align the output time D+X, X>Lmax / 2 must be satisfied. Select the appropriate time X to output the signal data.
[0067] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.
Claims
1. A multi-channel synchronous acquisition device based on FPGA, characterized in that: The digital signal acquisition module comprises a digital signal acquisition module and an analog signal acquisition module, wherein the digital signal acquisition module comprises a digital signal input terminal, a digital signal delay unit, and a digital signal output terminal connected in sequence; the analog signal acquisition module comprises an analog signal input terminal, a first-level multi-channel decimator, a second-level multi-channel decimator, a selector, and an analog signal output terminal, wherein the analog signal input terminal, the first-level multi-channel decimator, the selector, and the analog signal output terminal are connected in sequence; and the first-level multi-channel decimator, the second-level multi-channel decimator, and the selector are connected in sequence; The digital signal delay unit adopts a block random access memory in the FPGA, and the first-level multi-channel decimator and the second-level multi-channel decimator both adopt a DSP unit in the FPGA; The delay time of the digital signal delay unit is configured to be the same as the extraction time of the multi-channel extractor, so that the digital signal and the analog signal are collected synchronously.
2. The FPGA-based multi-channel synchronous acquisition device according to claim 1, characterized in that: The first-level multi-channel extractor and the second-level multi-channel extractor are multi-channel extractors with the same structure.
3. The FPGA-based multi-channel synchronous acquisition device according to claim 1, characterized in that: The multi-channel extractor includes a channel data buffer unit, a channel coefficient buffer unit, an arbitration unit, a multiplier-adder unit and an extraction result output unit. The input end of the arbitration unit is respectively connected to the channel data buffer unit and the channel coefficient buffer unit, the output end of the arbitration unit is connected to the input end of the multiplier-adder unit, and the output end of the multiplier-adder unit is connected to the extraction result output unit.
4. The FPGA-based multi-channel synchronous acquisition device according to claim 3, characterized in that: The multi-channel decimator adopts a four-channel decimator, and every four channels share one multiplier-accumulator unit.
5. The FPGA-based multi-channel synchronous acquisition device according to claim 4, characterized in that: There are four channel data buffer units and four channel coefficient buffer units, and the two correspond to each other one by one.
6. The FPGA-based multi-channel synchronous acquisition device according to claim 4, characterized in that: Each of the channel data buffer units is connected to the analog signal input terminal via a buffer write control unit.
7. The FPGA-based multi-channel synchronous acquisition device according to claim 4, characterized in that: The arbitration unit is a round-robin arbiter, which buffers requests from each channel.
8. The FPGA-based multi-channel synchronous acquisition device according to claim 1, characterized in that: The analog signal acquisition module is provided with two, for a total of eight channels.
9. The FPGA-based multi-channel synchronous acquisition device according to claim 1, characterized in that: The digital signal acquisition module is provided with two channels.
10. The FPGA-based multi-channel synchronous acquisition device according to claim 1, characterized in that: The coefficient orders of the first-stage multi-channel decimator and the second-stage multi-channel decimator are both even numbers.