Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, the semiconductor substrate comprises a first region, a second region, an x direction and a y direction, the x direction and the y direction are perpendicular to each other, a plurality of fin structures extending along the x direction and a plurality of gate structures extending along the y direction are formed on the surface of the semiconductor substrate, and the first region and the second region are perpendicular to each other. The gate structure covers part of the semiconductor substrate and the fin structure; the first source-drain groove and the second source-drain groove are located in the fin structures on the two sides, in the x direction, of the gate structures of the first area and the second area respectively, the width of the first source-drain groove is larger than that of the second source-drain groove, and the depth of the first source-drain groove is smaller than that of the second source-drain groove; and the source-drain layer is located in the first source-drain groove and the second source-drain groove. According to the invention, the growth defects of source and drain epitaxy in FINFET devices integrated with different types can be effectively controlled and reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Currently, in FINFET devices, the fin structure in the source and drain regions is typically etched away to form source and drain trenches, and then epitaxial growth is used to form source and drain layers in the source and drain trenches. This epitaxial growth process can employ a selective epitaxial growth process, whereby the source and drain layers (typically silicon germanium) are formed only on the exposed fin structure and semiconductor substrate (typically silicon) surfaces, preventing the growth of source and drain layers on other non-silicon surfaces.

[0003] However, in some semiconductor processes that integrate different device types, the dimensions of the different device types may differ. For example, the source and drain trenches in an SRAM device are generally narrower than those in a logic device. Therefore, the amount of source and drain epitaxial growth in an SRAM device is generally less than that in a logic device. This can cause the source and drain trenches of the SRAM device to overgrow during epitaxial growth, leading to source and drain growth defects in the SRAM device.

[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to effectively control and reduce the growth defects of source and drain epitaxy in FINFET devices that integrate different types. Summary of the Invention

[0005] The present application provides a semiconductor structure and a method for forming the same, which can effectively control and reduce the growth defects of source and drain epitaxy in FINFET devices integrating different types.

[0006] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region and mutually perpendicular x and y directions, a surface of the semiconductor substrate being formed with a plurality of fin structures extending along the x direction and a plurality of gate structures extending along the y direction, the gate structures partially covering the semiconductor substrate and the fin structures; forming a first source-drain trench and a second source-drain trench in the fin structures on both sides of the plurality of gate structures in the first region and the second region along the x direction, respectively, the width of the first source-drain trench being greater than the width of the second source-drain trench, and the depth of the first source-drain trench being less than the depth of the second source-drain trench; and epitaxially growing a source-drain layer in the first source-drain trench and the second source-drain trench.

[0007] In some embodiments of the present application, an isolation structure located between adjacent fin structures is further formed on the surface of the semiconductor substrate, and a top surface of the isolation structure is lower than a top surface of the fin structure.

[0008] In some embodiments of the present application, after the first source-drain trench and the second source-drain trench are formed, a top surface of the isolation structure in the first region is higher than a top surface of a portion of the isolation structure in the second region.

[0009] In some embodiments of the present application, the surface area of ​​the fin structure at the bottom and sidewalls of the first source / drain trench is equal to the surface area of ​​the fin structure at the bottom and sidewalls of the second source / drain trench.

[0010] In some embodiments of the present application, the volume of the first source-drain trench is equal to the volume of the second source-drain trench.

[0011] Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate including a first region and a second region and mutually perpendicular x- and y-directions, a surface of the semiconductor substrate having a plurality of fin structures extending along the x-direction and a plurality of gate structures extending along the y-direction formed thereon, the gate structures partially covering the semiconductor substrate and the fin structures; first source-drain trenches and second source-drain trenches, respectively located in the fin structures on both sides of the plurality of gate structures in the first region and the second region along the x-direction, the width of the first source-drain trench being greater than the width of the second source-drain trench, and the depth of the first source-drain trench being less than the depth of the second source-drain trench; and a source-drain layer located in the first source-drain trench and the second source-drain trench.

[0012] In some embodiments of the present application, an isolation structure located between adjacent fin structures is further formed on the surface of the semiconductor substrate, and a top surface of the isolation structure is lower than a top surface of the fin structure.

[0013] In some embodiments of the present application, a top surface of the isolation structure in the first region is higher than a top surface of a portion of the isolation structure in the second region.

[0014] In some embodiments of the present application, the surface area of ​​the fin structure at the bottom and sidewalls of the first source / drain trench is equal to the surface area of ​​the fin structure at the bottom and sidewalls of the second source / drain trench.

[0015] In some embodiments of the present application, the volume of the first source-drain trench is equal to the volume of the second source-drain trench.

[0016] The present application provides a semiconductor structure and a method for forming the same, which can effectively control and reduce the growth defects of source and drain epitaxy in FINFET devices integrating different types. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0018] Figures 1 to 12 Schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0020] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0021] Figures 1 to 12 The following is a structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail with reference to the accompanying drawings.

[0022] refer to Figure 1 、 Figure 2 and Figure 3 As shown, Figure 1 For top view, Figure 2 For the Figure 1 The longitudinal section at the dotted line AA, Figure 3 For the Figure 1 A longitudinal cross-sectional view taken along the dashed line BB is provided. A semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a first region 101 and a second region 102, and mutually perpendicular x and y directions. A plurality of fin structures 110 extending along the x direction and a plurality of gate structures 120 extending along the y direction are formed on the surface of the semiconductor substrate 100. The gate structures 120 partially cover the semiconductor substrate 100 and the fin structures 110.

[0023] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0024] In some embodiments of the present application, the semiconductor structure described in the present application is a semiconductor structure that integrates different types of devices. The first region 101 and the second region 102 are respectively used to form different types of devices. Specifically, the source and drain trench widths of the devices in the first region 101 and the second region 102 are different. For example, the first region 101 may be used to form a general logic device (logic device), and the second region 102 may be used to form an SRAM device. The source and drain trench width in the SRAM device is smaller than the source and drain trench in the logic device. It should be noted that the "width" mentioned in this application refers to the width of the attached Figure 1 The size in the x direction.

[0025] In some embodiments of the present application, the fin structures 110 and the semiconductor substrate 100 are both made of silicon. The fin structures 110 are formed by etching the semiconductor substrate 100. The number of fins 110 is not limited herein; the figures illustrate three fin structures 110 per region as an example.

[0026] In some embodiments of the present application, the number of the plurality of gate structures 120 is not limited. For the sake of simplicity, the drawings illustrate only one gate structure 120 in each region. The gate structure 120 is made of polysilicon or the like.

[0027] In some embodiments of the present application, an isolation structure 130 is further formed on the surface of the semiconductor substrate 100 and is located between adjacent fin structures 110. The top surface of the isolation structure 130 is lower than the top surface of the fin structure 110. The isolation structure 130 is used to isolate adjacent fin structures 110 and to isolate adjacent first regions 101 and second regions 102.

[0028] In some embodiments of the present application, the isolation structure 130 is made of silicon oxide.

[0029] refer to Figures 4 to 9As shown, a first source-drain trench 140 and a second source-drain trench 150 are respectively formed in the fin structure 110 on both sides of the several gate structures 120 in the first region 101 and the second region 102 along the x-direction, wherein the width of the first source-drain trench 140 is greater than the width of the second source-drain trench 150, and the depth of the first source-drain trench 140 is less than the depth of the second source-drain trench 150.

[0030] Specifically, refer to Figure 4 、 Figure 5 and Figure 6 As shown, Figure 4 For top view, Figure 5 For the Figure 4 The longitudinal section at the dotted line AA, Figure 6 For the Figure 4 A longitudinal cross-sectional view at the middle dashed line BB. First source-drain trenches 140 are formed in the fin structure 110 on both sides of the gate structure 120 in the first region 101 along the x-direction. The bottom of the first source-drain trench 140 is flush with the top surface of the isolation structure 130 .

[0031] In some embodiments of the present application, a method for forming the first source-drain trench 140 includes: forming a first optical diffusion layer (ODL) on the semiconductor substrate 100, covering the semiconductor substrate 100, the fin structure 110, the gate structure 120, and the isolation structure 130; forming a patterned first photoresist layer on a surface of the first light diffusion layer, wherein the patterned first photoresist layer defines a position of the first source-drain trench 140 (specifically, the patterned first photoresist layer has a first opening extending along the y-direction, the position of the first opening coincides with the position of the first source-drain trench 140 in the y-direction, and the position of the first opening coincides with the position of the gate structure 120 in the x-direction); etching the first light diffusion layer and the fin structure 110 using the patterned first photoresist layer as a mask to form the first source-drain trench 140; and removing the patterned first photoresist layer and the first light diffusion layer.

[0032] refer to Figure 7 、 Figure 8 and Figure 9 As shown, Figure 7 For top view, Figure 8 For the Figure 7 The longitudinal section at the dotted line AA, Figure 9 For the Figure 7 Second source-drain trenches 150 are formed in the fin structure 110 on both sides of the gate structure 120 in the second region 102 along the x-direction. The bottom of the second source-drain trenches 150 is lower than the bottom of the first source-drain trenches 150 .

[0033] In some embodiments of the present application, the method for forming the second source-drain trench 150 includes: forming a second light diffusion layer covering the semiconductor substrate 100, the fin structure 110, the gate structure 120 and the isolation structure 130 on the semiconductor substrate 100; forming a patterned second photoresist layer on the surface of the second light diffusion layer, the patterned second photoresist layer defining the position of the second source-drain trench 150 (specifically, the patterned second photoresist layer has a second opening extending along the y-direction, the position of the second opening coincides with the position of the second source-drain trench 150 in the y-direction, and the position of the second opening coincides with the position of the gate structure 120 in the x-direction); etching the second light diffusion layer and the fin structure 110 using the patterned second photoresist layer as a mask to form the second source-drain trench 150; and removing the patterned second photoresist layer and the second light diffusion layer.

[0034] refer to Figure 9 As shown, the width of the first source-drain trench 140 is greater than the width of the second source-drain trench 150, and the depth of the first source-drain trench 140 is less than the depth of the second source-drain trench 150. The "width" refers to the dimension in the x-direction in a top view.

[0035] Continue to refer Figure 9 As shown, in some embodiments of the present application, after forming the first source-drain trench 140 and the second source-drain trench 150, refer to Figure 8 As shown, the top surface of the isolation structure 130 in the first region 101 is higher than the top surface of a portion of the isolation structure 130 in the second region 102 .

[0036] In conventional processes, the second source-drain trench 150 in the second region 102 is narrower than the first source-drain trench 140 in the first region 101, but has the same depth. Therefore, the subsequent source-drain epitaxial growth amount in the second source-drain trench 150 is less than the source-drain epitaxial growth amount in the first source-drain trench 140. This causes the second source-drain trench 150 to overgrow during the source-drain epitaxial growth, thereby generating source-drain growth defects in the second region 102. To address this problem, in the technical solution of the present application, the first source-drain trench 140 and the second source-drain trench 150 are formed in steps, so that the depth of the first source-drain trench 140 is less than the depth of the second source-drain trench 150, thereby reducing the difference in the subsequent epitaxial growth amount of the first source-drain trench 140 and the second source-drain trench 150, thereby reducing the epitaxial growth defects in the second region 102.

[0037] Furthermore, in order to further reduce epitaxial growth defects in the second region 102, the difference in subsequent epitaxial growth between the first source / drain trench 140 and the second source / drain trench 150 can be further reduced. For example, in some embodiments of the present application, the dimensions of the first source / drain trench 140 and the second source / drain trench 150 are controlled so that the surface area of ​​the fin structure 110 at the bottom and sidewalls of the first source / drain trench 140 is equal to the surface area of ​​the fin structure 110 at the bottom and sidewalls of the second source / drain trench 150 and / or the volume of the first source / drain trench 140 is equal to the volume of the second source / drain trench 150.

[0038] In some embodiments of the present application, the first source-drain trench 140 and the second source-drain trench 150 have the same size in the y direction, so that the product of the width and depth of the first source-drain trench 140 can be equal to the product of the width and depth of the second source-drain trench 150.

[0039] refer to Figure 10 、 Figure 11 and Figure 12 As shown, Figure 10 For top view, Figure 11 For the Figure 10 The longitudinal section at the dotted line AA, Figure 12 For the Figure 10 A source / drain layer 160 is formed by epitaxial growth in the first source / drain trench 140 and the second source / drain trench 150. Since the epitaxial growth amounts of the first source / drain trench 140 and the second source / drain trench 150 are similar, epitaxial growth defects in the second region 102 are reduced.

[0040] In some embodiments of the present application, the source / drain layer 160 is made of silicon germanium.

[0041] The present application provides a method for forming a semiconductor structure, which can effectively control and reduce the growth defects of source and drain epitaxy in FINFET devices integrating different types.

[0042] The embodiment of the present application further provides a semiconductor structure, referring to Figure 10 、 Figure 11 and Figure 12As shown, it includes: a semiconductor substrate 100, the semiconductor substrate 100 includes a first region 101 and a second region 102 and mutually perpendicular x and y directions, a plurality of fin structures 110 extending along the x direction and a plurality of gate structures 120 extending along the y direction are formed on the surface of the semiconductor substrate 100, and the gate structures 120 cover part of the semiconductor substrate 100 and the fin structures 110; a first source-drain trench 140 and a second source-drain trench 150, respectively located in the fin structures 110 on both sides of the plurality of gate structures 120 in the first region 101 and the second region 102 along the x direction, the width of the first source-drain trench 140 is greater than the width of the second source-drain trench 150, and the depth of the first source-drain trench 140 is less than the depth of the second source-drain trench 150; a source-drain layer 160, located in the first source-drain trench 140 and the second source-drain trench 150.

[0043] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0044] In some embodiments of the present application, the semiconductor structure described in the present application is a semiconductor structure that integrates different types of devices. The first region 101 and the second region 102 are respectively used to form different types of devices. Specifically, the source and drain trench widths of the devices in the first region 101 and the second region 102 are different. For example, the first region 101 can be used to form a general logic device, and the second region 102 can be used to form an SRAM device. The source and drain trench width in the SRAM device is smaller than the source and drain trench in the logic device. It should be noted that the "width" mentioned in the present application refers to the dimension in the x-direction in the top view.

[0045] In some embodiments of the present application, the fin structures 110 and the semiconductor substrate 100 are both made of silicon. The fin structures 110 are formed by etching the semiconductor substrate 100. The number of fins 110 is not limited herein; the figures illustrate three fin structures 110 per region as an example.

[0046] In some embodiments of the present application, the number of the plurality of gate structures 120 is not limited. For the sake of simplicity, the drawings illustrate only one gate structure 120 in each region. The gate structure 120 is made of polysilicon or the like.

[0047] In some embodiments of the present application, an isolation structure 130 is further formed on the surface of the semiconductor substrate 100 and is located between adjacent fin structures 110. The top surface of the isolation structure 130 is lower than the top surface of the fin structure 110. The isolation structure 130 is used to isolate adjacent fin structures 110 and to isolate adjacent first regions 101 and second regions 102.

[0048] In some embodiments of the present application, the isolation structure 130 is made of silicon oxide.

[0049] refer to Figure 12 As shown, the width of the first source-drain trench 140 is greater than the width of the second source-drain trench 150, and the depth of the first source-drain trench 140 is less than the depth of the second source-drain trench 150. The "width" refers to the dimension in the x-direction in a top view.

[0050] Continue to refer Figure 11 As shown, the top surface of the isolation structure 130 in the first region 101 is higher than the top surface of a portion of the isolation structure 130 in the second region 102 .

[0051] In conventional processes, the second source-drain trench 150 in the second region 102 is narrower than the first source-drain trench 140 in the first region 101, but has the same depth. Therefore, the subsequent source-drain epitaxial growth amount in the second source-drain trench 150 is less than the source-drain epitaxial growth amount in the first source-drain trench 140. This causes the second source-drain trench 150 to overgrow during the source-drain epitaxial growth, thereby generating source-drain growth defects in the second region 102. To address this problem, in the technical solution of the present application, the first source-drain trench 140 and the second source-drain trench 150 are formed in steps, so that the depth of the first source-drain trench 140 is less than the depth of the second source-drain trench 150, thereby reducing the difference in the subsequent epitaxial growth amount of the first source-drain trench 140 and the second source-drain trench 150, thereby reducing the epitaxial growth defects in the second region 102.

[0052] Furthermore, in order to further reduce epitaxial growth defects in the second region 102, the difference in subsequent epitaxial growth between the first source / drain trench 140 and the second source / drain trench 150 can be further reduced. For example, in some embodiments of the present application, the dimensions of the first source / drain trench 140 and the second source / drain trench 150 are controlled so that the surface area of ​​the fin structure 110 at the bottom and sidewalls of the first source / drain trench 140 is equal to the surface area of ​​the fin structure 110 at the bottom and sidewalls of the second source / drain trench 150 and / or the volume of the first source / drain trench 140 is equal to the volume of the second source / drain trench 150.

[0053] In some embodiments of the present application, the first source-drain trench 140 and the second source-drain trench 150 have the same size in the y direction, so that the product of the width and depth of the first source-drain trench 140 can be equal to the product of the width and depth of the second source-drain trench 150.

[0054] In some embodiments of the present application, the source / drain layer 160 is made of silicon germanium.

[0055] The present application provides a semiconductor structure and a method for forming the same, which can effectively control and reduce the growth defects of source and drain epitaxy in FINFET devices integrating different types.

[0056] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0057] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may also be present.

[0058] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0059] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0060] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region and mutually perpendicular x and y directions, wherein a plurality of fin structures extending along the x direction and a plurality of gate structures extending along the y direction are formed on a surface of the semiconductor substrate, the gate structures partially covering the semiconductor substrate and the fin structures; forming first source-drain trenches and second source-drain trenches in the fin structures on both sides of the plurality of gate structures in the first region and the second region along the x-direction, respectively, wherein the width of the first source-drain trench is greater than the width of the second source-drain trench, and the depth of the first source-drain trench is less than the depth of the second source-drain trench; A source-drain layer is formed by epitaxial growth in the first source-drain trench and the second source-drain trench.

2. The method for forming a semiconductor structure according to claim 1, wherein: An isolation structure located between adjacent fin structures is further formed on the surface of the semiconductor substrate, and a top surface of the isolation structure is lower than a top surface of the fin structure.

3. The method for forming a semiconductor structure according to claim 2, wherein: After the first source-drain trench and the second source-drain trench are formed, a top surface of the isolation structure in the first region is higher than a top surface of a portion of the isolation structure in the second region.

4. The method for forming a semiconductor structure according to claim 1, wherein: The surface area of ​​the fin structure at the bottom and sidewalls of the first source / drain trench is equal to the surface area of ​​the fin structure at the bottom and sidewalls of the second source / drain trench.

5. The method for forming a semiconductor structure according to claim 1, wherein: The volume of the first source-drain trench is equal to the volume of the second source-drain trench.

6. A semiconductor structure, characterized in that include: A semiconductor substrate comprising a first region and a second region and mutually perpendicular x and y directions, wherein a surface of the semiconductor substrate is formed with a plurality of fin structures extending along the x direction and a plurality of gate structures extending along the y direction, wherein the gate structures partially cover the semiconductor substrate and the fin structures; First source-drain trenches and second source-drain trenches are respectively located in the fin structures on both sides of the plurality of gate structures in the first region and the second region along the x-direction, wherein the width of the first source-drain trench is greater than the width of the second source-drain trench, and the depth of the first source-drain trench is less than the depth of the second source-drain trench; The source-drain layer is located in the first source-drain trench and the second source-drain trench.

7. The semiconductor structure according to claim 6, wherein: An isolation structure located between adjacent fin structures is further formed on the surface of the semiconductor substrate, and a top surface of the isolation structure is lower than a top surface of the fin structure.

8. The semiconductor structure according to claim 7, wherein: A top surface of the isolation structure in the first region is higher than a top surface of a portion of the isolation structure in the second region.

9. The semiconductor structure according to claim 6, wherein: The surface area of ​​the fin structure at the bottom and sidewalls of the first source / drain trench is equal to the surface area of ​​the fin structure at the bottom and sidewalls of the second source / drain trench.

10. The semiconductor structure according to claim 6, wherein: The volume of the first source-drain trench is equal to the volume of the second source-drain trench.

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