Storage array and preparation method thereof, memory and electronic equipment

Abstract

The embodiment of the invention provides a memory array and a preparation method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and is used for improving the anti-interference capability of a memory unit and improving the reliability of the memory. The memory array includes a plurality of memory cells including ferroelectric capacitors. The ferroelectric capacitor includes a first electrode, a second electrode, a ferroelectric layer, and an induction layer. The ferroelectric layer is located between the first electrode and the second electrode. An induction layer is arranged between the first electrode and the ferroelectric layer, and / or an induction layer is arranged between the second electrode and the ferroelectric layer. Wherein the material of the induction layer is spontaneously polarized. The storage array is applied to the electronic equipment so as to improve the performance of the electronic equipment.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory array and a preparation method thereof, a memory and an electronic device. Background Art

[0002] With the application and integration of new technologies such as the Internet of Things and artificial intelligence, electronic devices are required to collect, transmit, and calculate large amounts of data, placing higher demands on the performance of their internal memory. Ferroelectric memory has attracted widespread attention due to its advantages such as high read and write speeds, non-volatility, good cycle performance, low power consumption, and device fabrication process compatibility with complementary metal oxide semiconductor (CMOS) technology.

[0003] Ferroelectric memory consists of multiple memory cells, each containing a transistor and a ferroelectric capacitor. During operation, the ferroelectric capacitors in two adjacent memory cells easily interfere with each other, resulting in a weak anti-interference capability of the memory cells and poor reliability. Summary of the Invention

[0004] Embodiments of the present application provide a memory array and a method for manufacturing the same, a memory, and an electronic device, for improving the anti-interference capability of a memory unit and improving the reliability of the memory.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a memory array is provided. The memory array includes multiple memory cells, each of which includes a ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode, a ferroelectric layer, and an inductive layer. The first electrode and the second electrode are disposed opposite each other. The ferroelectric layer is located between the first electrode and the second electrode. An inductive layer is provided between the first electrode and the ferroelectric layer, and / or an inductive layer is provided between the second electrode and the ferroelectric layer. The material of the inductive layer is spontaneously polarized.

[0007] In the ferroelectric capacitor provided in the embodiments of the present application, an induction layer is provided between the first electrode and the ferroelectric layer, and / or an induction layer is provided between the second electrode and the ferroelectric layer. The material of the induction layer is capable of spontaneous polarization, so that an electric field can be generated both inside and outside the induction layer. Under the guidance of the external electric field of the induction layer, the polar axis of the ferroelectric domain in the ferroelectric layer can be deflected toward the direction of the electric field formed by the first electrode and the second electrode.

[0008] Thus, when a voltage is applied to the first electrode and the second electrode, the angle between the polar axis orientations of the multiple ferroelectric domains in the ferroelectric layer and the electric field direction of the externally applied electric field can be small or even zero, and the voltage applied to the first electrode and the second electrode can relatively easily change the polarization state of the ferroelectric domains. The ferroelectric capacitor can have a relatively concentrated flipping electric field, thereby alleviating the problem of interference electric fields generated when writing data to a memory cell, where the electric field strength of the interference electric field is greater than the coercive electric field strength of the ferroelectric capacitor in the adjacent memory cell, thereby affecting the storage state of the adjacent memory cell, thereby improving the operating stability of the memory cell and the memory array.

[0009] At the same time, the embodiment of the present application sets an induction layer in the ferroelectric capacitor so that the polar axis orientation in the ferroelectric layer is concentratedly distributed in the direction of the electric field formed by the first electrode and the second electrode. It can also increase the residual polarization strength of the ferroelectric capacitor, thereby delaying the fatigue period of the ferroelectric capacitor, increasing the storage number of the ferroelectric capacitor, ensuring the storage window of the ferroelectric capacitor after multiple storages, improving the reliability of the ferroelectric capacitor, and further ensuring the accuracy of the read and write operations of the storage unit using the ferroelectric capacitor, thereby improving the performance of the memory.

[0010] In some embodiments, the material of the induction layer spontaneously polarizes along a predetermined direction, and the predetermined direction is parallel to the direction of the electric field formed by the first electrode and the second electrode. Thus, after the material in the induction layer spontaneously polarizes, the directions of the internal electric field and the external electric field generated in the induction layer can both be parallel to the direction of the electric field formed by the first electrode and the second electrode. The external electric field of the induction layer can easily adjust the polar axis orientation in the ferroelectric layer, so that the polar axis orientation of the majority of ferroelectric domains in the ferroelectric layer tends to be along the direction of the electric field formed by the first electrode and the second electrode, thereby optimizing the spontaneous polarization effect of the ferroelectric layer.

[0011] In some embodiments, the material of the induction layer includes wurtzite III nitride. Wurtzite III nitride can be spontaneously polarized along the c-axis. The material of the induction layer includes wurtzite III nitride, so that the induction layer can have an internal electric field and an external electric field, and the directions of the internal electric field and the external electric field are both parallel to the direction of the electric field formed by the first electrode and the second electrode, thereby enabling the induction layer to effectively improve the polar axis orientation in the ferroelectric layer.

[0012] In some embodiments, the material of the induction layer includes at least one of aluminum nitride, gallium nitride, aluminum gallium nitride, aluminum scandium nitride, and aluminum boron nitride.

[0013] In some embodiments, the thickness of the induction layer is greater than or equal to 1 nanometer and less than or equal to 5 nanometers.

[0014] This ensures that the thickness of the induction layer is not too small, effectively adjusting the polar axis orientation of the ferroelectric layer, improving the ferroelectric capacitor's anti-interference capability and reducing the switching electric field range of the ferroelectric capacitor. Furthermore, the thickness of the induction layer is not too large, minimizing its impact on the overall size of the ferroelectric capacitor, which helps ensure the number of memory cells in the memory array.

[0015] In some embodiments, the first electrode and the second electrode are both plate-shaped, and the first electrode and the second electrode are parallel to each other, and the induction layer is parallel to the first electrode. In this way, the structure of the ferroelectric capacitor is relatively simple, and the preparation process of the ferroelectric capacitor can also be relatively simple.

[0016] In some embodiments, the first electrode is plate-shaped, the second electrode is columnar, the second electrode extends through the first electrode, and the ferroelectric layer and the inductive layer are disposed around the second electrode. This, on the one hand, reduces the area occupied by the ferroelectric capacitor within a plane, allowing a larger number of ferroelectric capacitors per unit area of ​​the memory, thereby improving the memory's storage density. Furthermore, the three-dimensional structure of the ferroelectric capacitor facilitates the three-dimensionalization of the memory and the feasibility of stacking the memory with a chip.

[0017] In a second aspect, a method for fabricating a memory array is provided, comprising: forming a first electrode; forming a ferroelectric layer; forming a second electrode; and forming an induction layer, wherein the material of the induction layer exhibits spontaneous polarization. The first electrode and the second electrode are disposed opposite each other, the ferroelectric layer is located between the first and second electrodes, the induction layer is disposed between the first electrode and the ferroelectric layer, and / or the induction layer is disposed between the second electrode and the ferroelectric layer.

[0018] In a third aspect, a memory is provided, which includes the memory array and the controller described in any one of the above embodiments, and the controller is electrically connected to the memory array.

[0019] In a fourth aspect, an electronic device is provided, which includes a circuit board and the memory as described in the above embodiment, wherein the memory is located on the circuit board and electrically connected to the circuit board.

[0020] Among them, the technical effects brought about by any design method in the second to fourth aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of this application.

[0022] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0027] Figure 6 A schematic structural diagram of a ferroelectric capacitor provided in an embodiment of the present application;

[0028] Figure 7 A schematic cross-sectional view of a ferroelectric capacitor provided in an embodiment of the present application;

[0029] Figure 8 A schematic structural diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0030] Figure 9 A schematic structural diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0031] Figure 10 A schematic structural diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0032] Figure 11 A schematic structural diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0033] Figure 12 A polar axis orientation distribution probability diagram provided in an embodiment of the present application;

[0034] Figure 13 An electric hysteresis loop diagram provided in an embodiment of the present application;

[0035] Figure 14 An anti-interference test result diagram provided in an embodiment of the present application;

[0036] Figure 15 A schematic diagram of the partial structure of a wurtzite III nitride provided in an embodiment of the present application;

[0037] Figure 16 A schematic diagram of the three-dimensional structure of a storage array provided in an embodiment of the present application;

[0038] Figure 17 A schematic structural diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0039] Figure 18 A schematic structural diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0040] Figure 19 for Figure 18 A schematic cross-sectional view of the ferroelectric capacitor shown at AA';

[0041] Figure 20 A schematic diagram of the three-dimensional structure of another storage array provided in an embodiment of the present application;

[0042] Figure 21 A flow chart for preparing a ferroelectric capacitor provided in an embodiment of the present application;

[0043] Figure 22 A diagram showing the preparation state of a ferroelectric capacitor corresponding to step S300 provided in an embodiment of the present application;

[0044] Figure 23 A diagram showing the preparation state of a ferroelectric capacitor corresponding to step S100 provided in an embodiment of the present application;

[0045] Figure 24 A diagram showing the preparation state of a ferroelectric capacitor corresponding to step S400 provided in an embodiment of the present application;

[0046] Figure 25 A diagram showing the preparation state of a ferroelectric capacitor corresponding to step S200 provided in an embodiment of the present application;

[0047] Figure 26 This is a diagram of the preparation state of the ferroelectric capacitor corresponding to step S300 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0049] In the embodiments of the present application, "up", "down", "left" and "right" are not limited to being defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts. They are used for relative descriptions and clarifications, and may change accordingly according to changes in the orientation of the components in the drawings.

[0050] In the embodiments of the present application, unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that the specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner. In the description of the present application, unless otherwise stated, "multiple" means two or more.

[0051] In the embodiments of the present application, exemplary embodiments are described with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams as idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0052] An embodiment of the present application provides an electronic device. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. Among them, consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, game consoles, cameras, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (for example, soymilk machines, sweeping robots), set-top boxes, etc. Vehicle-mounted electronic products include car navigation systems, car high-density digital video discs (DVDs), car automatic assisted driving systems, navigation and infotainment systems, powertrains, and battery management systems, etc. Financial terminal products include automated teller machines (ATMs), POS (Point of Sales) self-service terminals, etc. The embodiments of the present application do not impose any particular restrictions on the specific form of the electronic device.

[0053] Figure 1 Schematic diagram of the structure of an electronic device 100 provided in an embodiment of the present application. Figure 1 As shown, the electronic device 100 may include a bus 110 and a system on chip (SOC) 120 connected to the bus 110. The SOC 120 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 120 may include an application processor (AP) 121 for processing applications, a graphics processing unit (GPU) 122 for processing image data, and a first random access memory (RAM) 123 for caching high-speed data. The first RAM 123 may be a static random access memory (SRAM), etc. The above-mentioned AP 121, GPU 122 and first RAM 123 may be integrated into one die, or may be separately provided in multiple dies.

[0054] For example Figure 1 As shown, the electronic device 100 may further include a second RAM 130 connected to the SOC 120 via the bus 110. The second RAM 130 may be a dynamic random access memory (DRAM). The second RAM 130 may be used to store volatile data, such as temporary data generated by the SOC 120. The storage capacity of the second RAM 130 is generally greater than that of the first RAM 123, but the read speed is generally slower than that of the first RAM 123.

[0055] In addition, the electronic device 100 may further include a communication chip 140 and a power management chip 150 connected to the SOC 120 via the bus 110. The communication chip 140 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 150 may be used to power other chips. In one embodiment, the SOC 120 and the second RAM 130 may be packaged in a single package structure, such as a 2.5D (dimension) or 3D package, to achieve faster inter-chip data transmission rates.

[0056] Figure 2 A circuit block diagram of a memory 200 that can be used in an electronic device is provided in an embodiment of the present application. In one embodiment, the memory 200 can be Figure 1 The first RAM 123 in the SOC 120 may also be the second RAM 130. The embodiment of the present application does not limit the application scenario of the memory 200. In one possible implementation, the memory 200 may also be a RAM provided outside the SOC 120. The present application does not limit the location of the memory 200 in the electronic device or its positional relationship with the SOC 120.

[0057] In some examples, the electronic device 100 may include a circuit board, and the memory 200 is located on the circuit board and connected to the circuit board.

[0058] like Figure 2 As shown, the memory 200 includes a memory array 210 . In addition, the memory 200 may further include a controller 220 for accessing the memory array 210 , wherein the controller 220 is used to control read and write operations of the memory array 210 .

[0059] It can be understood that the memory 200 may include at least one memory array 210 , that is, the memory 200 may include one or more memory arrays 210 .

[0060] The memory array 210 and the controller 220 have various possible packaging structures. For example, the memory array 210 and the controller 220 may be two independent chips, each integrated on a substrate. For example, the memory array 210 and the controller 220 may be electrically connected via metal traces arranged on the substrate. In this structure, since the memory array 210 and the controller 220 are two independent chips, the memory array 210 may be referred to as a stand-alone memory.

[0061] Alternatively, the memory array 210 and the controller 220 are stacked. For example, the memory array 210 and the controller 220 may be connected to each other through a through silicon via (TSV) or a redistribution layer (RDL).

[0062] Alternatively, the memory array 210 and the controller 220 are integrated into the same chip, and the chip is integrated on a substrate. Therefore, the memory array 210 can be called an embedded memory.

[0063] In some examples, such as Figure 3 As shown, the memory array 210 may include a plurality of memory cells 211, wherein each memory cell 211 may be used to store 1 bit (bit) or multiple bits of data. The memory array 210 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 211 is electrically connected to a corresponding word line and bit line. Different memory cells 211 may be electrically connected via word lines and bit lines. One or more of the above-mentioned word lines and bit lines are used to select the memory cell 211 to be read or written in the memory array by receiving a control level output by a control circuit, thereby realizing data read and write operations.

[0064] The controller 220 in the memory may include Figure 3 One or more circuit structures of the decoder 221 , driver 222 , timing controller 223 , buffer 224 or input / output driver 225 are shown.

[0065] exist Figure 3In the structure of the memory 200 shown, the decoder 221 is used to decode according to the received address to determine the storage unit 211 that needs to be accessed. The driver 222 is used to control the level of the signal line according to the decoding result generated by the decoder 221, thereby achieving access to the specified storage unit 211. The buffer 224 is used to cache the read data, for example, it can be cached using a first-in first-out (FIFO) method. The timing controller 223 is used to control the timing of the buffer 224 and control the driver 222 to drive the signal lines in the storage array 210. The input and output driver 225 is used to drive the transmission signal, such as driving the received data signal and driving the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0066] The memory array 210 , decoder 221 , driver 222 , timing controller 223 , buffer 224 and input / output driver 225 may be integrated into one chip or integrated into multiple chips.

[0067] The memory involved in this application can be a ferroelectric random access memory (FeRAM), a ferroelectric field-effect transistor (FeFET) memory, a ferroelectric tunnel junction (FTJ) memory, or a resistive random access memory (RRAM).

[0068] Figure 4 and Figure 5 FIG2 shows a circuit structure diagram of two possible storage arrays 210 provided in an embodiment of the present application. Figure 4 and Figure 5 As shown, the memory array 210 may include a plurality of memory cells 211. The memory cell 211 includes a transistor 10 and a ferroelectric capacitor 20. The memory array may further include word lines WL, bit lines BL, and source lines SL. Figure 4 Four memory cells 211 in the memory array 210 are shown. In the memory cell 211, the first end of the ferroelectric capacitor 20 is connected to the first electrode of the transistor 10, the second end of the ferroelectric capacitor 20 is connected to the source line SL, the second electrode of the transistor 10 is connected to the bit line BL, and the control end (e.g., gate) of the transistor 10 is connected to the word line WL.

[0069] Figure 5 Also shown are four memory cells 211 in the memory array 210. Figure 4The difference between the memory cell 211 shown is that in the memory cell 211, the first end of the ferroelectric capacitor 20 is connected to the control end (e.g., the gate) of the transistor 10, the second end of the ferroelectric capacitor 20 is connected to the word line WL, the first electrode of the transistor 10 is connected to the source line SL, and the second electrode of the transistor 10 is connected to the bit line BL.

[0070] It is understandable that Figure 4 and Figure 5 The number of storage cells 211 shown does not limit the number of storage cells 211 in the storage array 210 provided in the embodiment of the present application. The number of storage cells 211 in the storage array 210 provided in the embodiment of the present application can be designed according to actual needs. The structure of the storage cells 211 in the embodiment of the present application is not limited to Figure 4 and Figure 5 In the structure shown, a single memory cell 211 may also include a plurality of transistors 10 and a plurality of ferroelectric capacitors 20 .

[0071] Figure 6 The figure below is a schematic diagram of the structure of a ferroelectric capacitor 20'. Ferroelectric capacitor 20' includes a first electrode 21', a second electrode 22', and a ferroelectric layer 23' located between the first and second electrodes 21', 22'. Ferroelectric layer 23' comprises a ferroelectric material that exhibits spontaneous polarization. Spontaneous polarization is a polarization state caused by the internal structure of a crystal. Within a certain temperature range, the centers of positive and negative charges within a unit cell do not coincide, forming a dipole moment and exhibiting polarity. This polarization phenomenon, which exists in the absence of an external electric field, is called spontaneous polarization.

[0072] like Figure 7 As shown, the ferroelectric layer 23' contains orthorhombic (O phase), tetragonal (T phase), and monoclinic (M phase) unit cells. Under the influence of an external electric field, the central atoms in the O phase unit cells can deviate from their equilibrium point and remain in a low-energy state. When the external electric field is reversed, the central atoms in the O phase unit cells can move to another low-energy state under the influence of the reversed external electric field. The ferroelectric layer 23' can generate two polarization states in opposite directions, causing the ferroelectric capacitor 20' to charge and discharge, allowing the ferroelectric capacitor 20' to achieve a "0" or "1" storage state.

[0073] The ferroelectric layer 23' has a plurality of ferroelectric domains, and the polar axes of crystals in the same ferroelectric domain are oriented in the same direction. Figure 7 The black arrows in FIG show the polar axis orientation of multiple ferroelectric domains. Figure 7As shown, the polar axes of the multiple ferroelectric domains in the ferroelectric layer 23' are randomly distributed. Thus, when a voltage is applied to the first electrode 21' and the second electrode 22', the direction of the applied electric field is parallel to the thickness direction of the ferroelectric layer 23' and has an angle with the polar axes of the multiple ferroelectric domains.

[0074] In this case, an electric field significantly greater than the coercive field strength must be applied to the ferroelectric capacitor 20' to achieve the polarity reversal required for storage. Consequently, when writing data to a memory cell, an interfering electric field greater than the coercive field strength of the ferroelectric capacitor in the adjacent memory cell may be generated, affecting the accuracy and reliability of the adjacent memory cell. The coercive field strength is the reverse electric field strength required to restore the polarization strength of the ferroelectric material to zero.

[0075] To address this issue, related technologies use electric field wake-up to adjust the polar axis orientation in the ferroelectric layer. Specifically, by applying a voltage to a first electrode and a second electrode, a wake-up process is performed to achieve subtle changes in the ferroelectric layer's crystal structure, interchanging the polar axes, and thereby optimizing the polar axis orientation. This shifts the polar axis orientation in the ferroelectric layer from a random distribution to a concentrated distribution parallel to the direction of the electric field formed by the first and second electrodes.

[0076] However, although the electric field awakening method can provide additional driving force to achieve the optimization of polar axis orientation, the external electric field method requires the introduction of additional steps in the preparation process of ferroelectric capacitors, which increases the production cost of ferroelectric capacitors and reduces the preparation efficiency of ferroelectric capacitors.

[0077] The crystal structure, polar axis orientation, and phase ratio (O phase / T phase / M phase) in the ferroelectric layer are affected by the lattice matching between the ferroelectric layer and the first and second electrodes, as well as the stress applied to the ferroelectric layer by the first and second electrodes. Therefore, another related technology utilizes the large difference in thermal expansion coefficients between the material of the ferroelectric layer and the materials of the first and second electrodes. Through rapid temperature ramping processes such as rapid thermal annealing (RTP), stress is applied to achieve a specific polar axis orientation, thereby transforming the polar axis orientation in the ferroelectric layer from a random distribution to a concentrated distribution parallel to the direction of the electric field formed by the first and second electrodes.

[0078] However, the method of applying external stress to adjust the polar axis orientation in the ferroelectric layer may have the problem of poor process compatibility. Since the film layer and heat treatment process are complex in the actual production process of ferroelectric capacitors, there are long and slow stages of heating, holding and cooling, so there may be a problem that the ferroelectric layer has completed crystallization before RTP. After the ferroelectric layer is crystallized, the method of external stress adjustment cannot achieve the optimization of polar axis orientation. In addition, the interface mismatch between the first electrode and the ferroelectric layer, as well as the interface mismatch between the second electrode and the ferroelectric layer, may also lead to interface defects such as dangling bonds, which will damage the performance of the ferroelectric capacitor.

[0079] Based on the above problems, Figure 8 As shown, the embodiment of the present application provides a ferroelectric capacitor 20, which includes a first electrode 21, a second electrode 22 and a ferroelectric layer 23. The first electrode 21 and the second electrode 22 are arranged opposite to each other, and the ferroelectric layer 23 is located between the first electrode 21 and the second electrode 22.

[0080] The materials of the first electrode 21 and the second electrode 22 may each include at least one of a metal, a conductive oxide, and a conductive nitride. Examples of metals include W (tungsten), Pt (platinum), Sr (strontium), Ru (ruthenium), La (lanthanum), Mn (manganese), Ti (titanium), Au (gold), Ag (silver), Al (aluminum), and the like. Examples of conductive oxides include TiO (titanium oxide), NbO (niobium oxide), RuO2 (ruthenium oxide), IrO (iridium oxide), ITO (indium tin oxide), AZO (aluminum-doped zinc oxide), FTO (fluorine-doped tin oxide), and the like. Examples of conductive nitrides include TiN (titanium nitride), TiAlN (titanium aluminum nitride), WN (tungsten nitride), and TaN (tantalum nitride). The material of the first electrode 21 may be the same as or different from that of the second electrode 22.

[0081] In some examples, such as Figure 8 As shown, the second electrode 22 can be a single-layer structure. In other examples, such as Figure 9 As shown, the second electrode 22 may be a multi-layer structure. Figure 9 The second electrode 22 having a double-layer structure is used as an example for illustration.

[0082] like Figure 9 As shown, the second electrode 22 may include a first sublayer 22a and a second sublayer 22b, wherein the first sublayer 22a is located on a side of the second sublayer 22b away from the ferroelectric layer 23. The material of the first sublayer 22a is different from the material of the second sublayer 22b. For example, the material of the first sublayer 22a may be tungsten, and the material of the second sublayer 22b may be titanium nitride.

[0083] Compared with tungsten, titanium nitride is easier to grow (or deposit) on the ferroelectric layer 23. Therefore, in the second electrode 22 provided in the embodiment of the present application, the material of the first sublayer 22a is tungsten, and the material of the second sublayer 22b is titanium nitride. The second sublayer 22b is closer to the ferroelectric layer 23 than the first sublayer 22a, which can make the connection relationship between the second electrode 22 and the ferroelectric layer 23 more stable, thereby helping to improve the structural stability of the ferroelectric capacitor 20.

[0084] In some examples, the thickness of the first electrode 21 can be greater than or equal to 5 nanometers and less than or equal to 100 nanometers. For example, the thickness of the first electrode 21 can be 5 nanometers, 10 nanometers, 20 nanometers, 30 nanometers, 50 nanometers, 70 nanometers, 80 nanometers, 100 nanometers, etc.

[0085] In some examples, the thickness of the second electrode 22 can be greater than or equal to 5 nanometers and less than or equal to 100 nanometers. For example, the thickness of the second electrode 22 can be 5 nanometers, 10 nanometers, 20 nanometers, 30 nanometers, 50 nanometers, 70 nanometers, 80 nanometers, 100 nanometers, etc. In the case where the second electrode 22 includes a first sublayer 22a and a second sublayer 22b, the thickness of the first sublayer 22a can be greater than or equal to 5 nanometers and less than or equal to 60 nanometers, and the thickness of the second sublayer 22b can be greater than or equal to 5 nanometers and less than or equal to 30 nanometers.

[0086] In some examples, the material of ferroelectric layer 23 may include a hafnium oxide-based material and a doping element. The hafnium oxide-based material may include hafnium oxide or hafnium zirconium oxide. The doping element may include at least one of zirconium (Zr), lanthanum (La), aluminum (Al), titanium (Ti), and niobium (Nb).

[0087] See Figures 8 to 11 The ferroelectric capacitor 20 may further include an induction layer 24, wherein the material of the induction layer 24 is spontaneously polarized. Figure 8 and Figure 9 As shown, the inductive layer 24 may be located between the first electrode 21 and the ferroelectric layer 23. Alternatively, as shown in FIG. Figure 10 As shown, the inductive layer 24 may be located between the second electrode 22 and the ferroelectric layer 23. Alternatively, as Figure 11 As shown, an induction layer 24 is provided between the first electrode 21 and the ferroelectric layer 23 , and an induction layer 24 is also provided between the second electrode 22 and the ferroelectric layer 23 .

[0088] In the ferroelectric capacitor 20 provided in the embodiment of the present application, an induction layer 24 is provided between the first electrode 21 and the ferroelectric layer 23, and / or, an induction layer 24 is provided between the second electrode 22 and the ferroelectric layer 23. The material of the induction layer 24 is capable of spontaneous polarization, so that an electric field can be generated both inside and outside the induction layer 24. Under the guidance of the external electric field of the induction layer 24, the polar axis of the ferroelectric domain in the ferroelectric layer 23 can be deflected toward the direction of the electric field formed by the first electrode 21 and the second electrode 22.

[0089] The polar axis orientation of the ferroelectric layer of the ferroelectric capacitor with the induction layer and the ferroelectric layer of the ferroelectric capacitor without the induction layer was analyzed by the precession electron diffraction (PED) method. Figure 12 The test results are shown. Figure 12 (a) is a distribution probability diagram of different polar axis orientations in the ferroelectric layer when no induction layer is set. Figure 12 (b) is a distribution probability diagram of different polar axis orientations in the ferroelectric layer when an induction layer is set. Figure 12 The horizontal axis represents the cosine value of the angle between the polar axis orientation and the direction of the electric field formed by the first electrode and the second electrode, and the vertical axis represents the distribution probability of the polar axis orientation corresponding to different cosine values. It can be understood that when the cosine value of the angle is 1, the angle between the polar axis orientation and the direction of the electric field formed by the first electrode and the second electrode is 0 degrees, and the polar axis orientation is parallel to the direction of the electric field formed by the first electrode and the second electrode. When the cosine value of the angle is 0, the angle between the polar axis orientation and the direction of the electric field formed by the first electrode and the second electrode is 90 degrees, and the polar axis orientation is perpendicular to the direction of the electric field formed by the first electrode and the second electrode.

[0090] By observation Figure 12 From (a) in the figure, it can be seen that when no induction layer is set, the polar axis orientations in the ferroelectric layer are randomly distributed, and the distribution probabilities of different polar axis orientations are approximately the same. Figure 12 As can be seen from (b) in the figure, when the induction layer is provided, the distribution probability of the polar axes in the ferroelectric layer being oriented parallel to the direction of the electric field formed by the first electrode and the second electrode is the highest, and the distribution probability of the polar axes oriented close to the direction of the electric field formed by the first electrode and the second electrode is also relatively high. In the embodiment of the present application, the induction layer 24 is provided in the ferroelectric capacitor 20 to effectively change the polar axis orientation of multiple ferroelectric domains in the ferroelectric layer 23, thereby optimizing the spontaneous polarization effect of the ferroelectric layer 23.

[0091] In this way, when voltage is applied to the first electrode 21 and the second electrode 22, the angle between the polar axis orientation of multiple ferroelectric domains in the ferroelectric layer 23 and the electric field direction of the external electric field can be small or even zero, and the voltage applied to the first electrode 21 and the second electrode 22 can more easily change the polarization state of the ferroelectric domain.

[0092] Figure 13 The hysteresis loop L1 of the ferroelectric capacitor without the induction layer and the hysteresis loop L2 of the ferroelectric capacitor with the induction layer are shown. The horizontal axis represents the electric field strength applied to the ferroelectric layer, the unit is "MV / cm", and the vertical axis represents the polarization strength of the ferroelectric layer, the unit is "μC / cm 2 ”.

[0093] Comparing hysteresis loops L1 and L2, we can see that when the degree of change in electric field intensity is the same, the degree of change in the polarization intensity of hysteresis loop L1 is smaller, while the degree of change in the polarization intensity of hysteresis loop L2 is larger. When the maximum polarization intensity is reached, the electric field intensity of hysteresis loop L1 is greater than that of hysteresis loop L2. The electric field intensity range corresponding to hysteresis loop L2 is smaller than that corresponding to hysteresis loop L1.

[0094] Therefore, the embodiment of the present application sets an induction layer 24 in the ferroelectric capacitor 20, so that the polar axis orientation in the ferroelectric layer 23 is concentratedly distributed in the direction of the electric field formed by the first electrode 21 and the second electrode 22. It can also make the ferroelectric capacitor 20 have a more concentrated flipping electric field, thereby improving the interference electric field generated when writing data to the storage unit, and the electric field strength of the interference electric field is greater than the coercive electric field strength of the ferroelectric capacitor in the adjacent storage unit, which affects the storage state of the adjacent storage unit, thereby improving the working stability of the storage unit 211 and the storage array 210.

[0095] In the embodiment of the present application, an induction layer 24 is provided in the ferroelectric capacitor 20, so that the polar axis orientation in the ferroelectric layer 23 is concentratedly distributed in the direction of the electric field formed by the first electrode 21 and the second electrode 22, and the residual polarization strength of the ferroelectric capacitor 20 can also be increased. Figure 13 As shown, the intersection of the hysteresis loop L1 and the vertical axis represents the residual polarization intensity Pr1 of the ferroelectric capacitor without an induction layer, and the intersection of the hysteresis loop L2 and the vertical axis represents the residual polarization intensity Pr2 of the ferroelectric capacitor with an induction layer, and the residual polarization intensity Pr2 is greater than the residual polarization intensity Pr1.

[0096] The larger residual polarization strength of the ferroelectric capacitor 20 is beneficial to delaying the fatigue period of the ferroelectric capacitor 20, increasing the number of storage times of the ferroelectric capacitor 20, ensuring the storage window of the ferroelectric capacitor 20 after multiple storages, improving the reliability of the ferroelectric capacitor 20, and further ensuring the accuracy of the read and write operations of the storage unit 211 using the ferroelectric capacitor 20, thereby improving the performance of the memory 200.

[0097] Figure 14 (c) shows the residual polarization intensity of the ferroelectric capacitor without the induction layer in the "initial state" and "after the interference test". Figure 14 (d) shows the residual polarization intensity of the ferroelectric capacitor with an induction layer in the "initial state" and "after the interference test". Comparing (c) and (d), it can be seen that the initial residual polarization intensity of the ferroelectric capacitor with and without the induction layer is the same, but after the interference test, the residual polarization intensity of the ferroelectric capacitor with the induction layer is greater than the residual polarization intensity of the ferroelectric capacitor without the induction layer. It can be seen that the provision of the induction layer 24 in the embodiment of the present application can also improve the anti-interference performance of the ferroelectric capacitor 20 and ensure the reliability of the ferroelectric capacitor 20.

[0098] In some embodiments, the material of the induction layer 24 can spontaneously polarize along a predetermined direction, which is parallel to the direction of the electric field formed by the first electrode 21 and the second electrode 22. Thus, after the material in the induction layer 24 spontaneously polarizes, the directions of the internal electric field and the external electric field generated in the induction layer 24 can both be parallel to the direction of the electric field formed by the first electrode 21 and the second electrode 22. The external electric field of the induction layer 24 can relatively easily adjust the polar axis orientation in the ferroelectric layer 23, so that the polar axis orientation of more ferroelectric domains in the ferroelectric layer 23 tends to be along the direction of the electric field formed by the first electrode 21 and the second electrode 22, thereby optimizing the spontaneous polarization effect of the ferroelectric layer 23.

[0099] In some examples, the material of the induction layer 24 may include wurtzite III-nitride. For example, the material of the induction layer 24 may include at least one of aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum scandium nitride (AlScN), and aluminum boron nitride (AlBN).

[0100] Because the crystal structure has a three-dimensional periodicity in spatial arrangement, each crystal can have a crystal axis system containing three crystal axes. The three crystal axes are parallel to the basis vectors that reflect the three-dimensional periodicity and can be called the a-axis, b-axis, and c-axis. The c-axis is placed in an upright direction. Figure 15 The local structure diagram of wurtzite III nitride. Figure 15As shown in the figure, in wurtzite III nitrides, nitrogen atoms are connected to atoms such as Al and Ga through covalent bonds. The metal-nitride covalent bond length parallel to the c-axis is longer than the covalent bonds extending along the other three directions. As a result, in wurtzite III nitrides, the positive and negative charge centers do not coincide, generating an electric field in the material that points from the positive charge center to the negative charge center, also known as the spontaneous polarization electric field, Esp.

[0101] Wurtzite III-nitride can be spontaneously polarized along the c-axis. The material of the induction layer 24 includes wurtzite III-nitride, so that the induction layer 24 can generate an internal electric field and an external electric field, and the directions of the internal electric field and the external electric field are parallel to the directions of the electric field formed by the first electrode 21 and the second electrode 22, thereby enabling the induction layer 24 to effectively improve the polar axis orientation in the ferroelectric layer 23.

[0102] In some embodiments, the thickness of the induction layer 24 can be greater than or equal to 1 nanometer and less than or equal to 5 nanometers. For example, the thickness of the induction layer 24 can be 1 nanometer, 2 nanometers, 3 nanometers, 4 nanometers, 5 nanometers, etc. In this way, the thickness of the induction layer 24 is not too small, so that the induction layer 24 can effectively adjust the polar axis orientation in the ferroelectric layer 23, improve the anti-interference capability of the ferroelectric capacitor 20, and reduce the switching electric field range of the ferroelectric capacitor 20. At the same time, the thickness of the induction layer 24 is not too large, so that the induction layer 24 is not likely to affect the overall size of the ferroelectric capacitor, which is beneficial for ensuring the number of memory cells 211 in the memory array 210.

[0103] In some embodiments, as Figure 11 As shown, the first electrode 21 and the second electrode 22 can both be plate-shaped, and the first electrode 21 and the second electrode 22 are parallel, and the induction layer 24 is parallel to the first electrode 21 or the second electrode 22. In this way, the structure of the ferroelectric capacitor 20 is relatively simple, and the preparation process of the ferroelectric capacitor 20 can also be relatively simple.

[0104] In this case, if Figure 16 As shown, the memory array 210 composed of the memory cells 211 using the ferroelectric capacitor 20 can be a two-dimensional structure. Figure 16 As shown, the memory array 210 includes a plurality of memory cells 211, as well as a plurality of word lines WL and a plurality of bit lines BL. The plurality of word lines WL extend along a first direction X and are arranged along a second direction Y. The plurality of bit lines BL extend along the second direction Y and are arranged along the first direction X. In a third direction Z, the plurality of memory cells 211 are located between the word lines WL and the bit lines BL and are arranged in a single layer, arranged in multiple rows and columns in a plane defined by the first direction X and the second direction Y. In this case, the memory array 210 has a simple structure and is easy to manufacture.

[0105] Figure 17 This is a schematic structural diagram of another ferroelectric capacitor 20 provided in an embodiment of the present application. Figure 18 This is a schematic structural diagram of another ferroelectric capacitor 20 provided in an embodiment of the present application. Figure 19 for Figure 18 The cross-sectional view of the ferroelectric capacitor 20 is shown at AA'. Figure 17 The first electrode 21 can be plate-shaped, the second electrode 22 can be columnar, the second electrode 22 penetrates the first electrode 21, and the ferroelectric layer 23 and the inductive layer 24 are both disposed around the second electrode 22. In this case, the ferroelectric capacitor 20 is a three-dimensional structure.

[0106] The ferroelectric layer 23 and the inductive layer 24 are both arranged around the second electrode 22, so that in the circumferential direction of the second electrode 22, the ferroelectric layer 23 and the inductive layer 24 are opposite to each other at all places, so that the external electric field generated by the inductive layer 24 can optimize the polar axis of the ferroelectric layer 23 at different positions in the circumferential direction of the second electrode 22, thereby improving the spontaneous polarization effect of the ferroelectric layer 23.

[0107] For some examples, see Figure 18 In the case where the second electrode 22 includes a first sublayer 22a and a second sublayer 22b, the first sublayer 22a may be a cylinder, and the second sublayer 22b may be a hollow cylinder, wrapping at least part of the side surface of the first sublayer 22a. Figure 18 In the figure, the second sub-layer 22b wraps part of the side surface of the first sub-layer 22a as an example for illustration.

[0108] In some examples, the height of the first sublayer 22a can be greater than or equal to the height of the ferroelectric layer 23, and / or the height of the second sublayer 22b can be greater than or equal to the height of the ferroelectric layer 23. This configuration can facilitate connection of the second electrode 22 to other devices (e.g., ferroelectric capacitors, transistors, etc.). Figure 18 An example is given in which the heights of the first sub-layer 22 a and the second sub-layer 22 b are both greater than or equal to the height of the ferroelectric layer 23 .

[0109] In some examples, such as Figure 18 As shown, the height of the first sub-layer 22a can be greater than or equal to the height of the second sub-layer 22b. This arrangement can facilitate the connection of the first sub-layer 22a with other devices.

[0110] In some examples, such as Figure 17 and Figure 18As shown, the ferroelectric capacitor 20 may include a plurality of first electrodes 21, and a second electrode 22 extends through the plurality of first electrodes 21. The plurality of first electrodes 21 are parallel to each other and insulated from each other. In this case, the ferroelectric capacitor 20 may further include an insulating layer 25, which is located between two adjacent first electrodes 21. Figure 17 and Figure 18 In the figure, the ferroelectric capacitor 20 including two first electrodes 21 is used as an example for illustration.

[0111] It is understood that the material of the insulating layer 25 is an insulating material. For example, the material of the insulating layer 25 may include silicon oxide. In the embodiment of the present application, there is no limitation on the thickness of the insulating layer 25 and it can be designed according to actual needs.

[0112] In some examples, such as Figure 19 As shown, the cross-sectional shapes of the first electrode 21, the ferroelectric layer 23, and the inductive layer 24 can all be circular, and the cross-sectional shape of the second electrode 22 can be circular. Of course, the cross-sectional shapes of the first electrode 21, the ferroelectric layer 23, and the inductive layer 24 are not limited to circular, and can also be other shapes such as square rings or semicircular rings. The cross-sectional shape of the second electrode 22 is also not limited to circular, and can also be other shapes such as rectangular or triangular.

[0113] This, on the one hand, reduces the area occupied by the ferroelectric capacitor 20 in a plane, allowing the memory 200 to have more ferroelectric capacitors 20 (memory cells 210) per unit area, thereby improving the storage density of the memory 200. Furthermore, the three-dimensional structure of the ferroelectric capacitor 20 also facilitates the three-dimensionalization of the memory 200 and the feasibility of stacking the memory 200 with a chip.

[0114] In some examples, such as Figure 17 and Figure 18 As shown, the ferroelectric capacitor 20 may further include a connection layer 26, which is parallel to the first electrode 21 and connected to the second electrode 22. The connection layer 26 is made of a conductive material.

[0115] The connection layer 26 may be located on one side of the first electrode 21. If the ferroelectric capacitor 20 includes multiple first electrodes 21, the connection layer 26 may be located on the same side of the multiple first electrodes 21. Alternatively, if the ferroelectric capacitor 20 includes multiple first electrodes 21, the connection layer 26 may be located between two adjacent first electrodes 21. If the ferroelectric capacitor 20 includes an insulating layer 25, an insulating layer 25 is also provided between the connection layer 26 and the first electrode 21.

[0116] In the embodiment of the present application, a connection layer 26 is provided in the ferroelectric capacitor 20 to facilitate connection between the ferroelectric capacitor 20 and other devices (eg, a ferroelectric capacitor, a transistor, etc.), thereby improving the connection stability between the ferroelectric capacitor 20 and other devices.

[0117] Figure 20 FIG. 2 shows a schematic diagram of a three-dimensional structure of a storage array 210 provided in an embodiment of the present application. Figure 20 As shown, the memory array 210 includes a plurality of memory cells 211, as well as a plurality of word lines WL and a plurality of bit lines BL. The plurality of word lines WL extend along a first direction X and are arranged along a second direction Y. The plurality of bit lines BL extend along a second direction Y and are arranged along the first direction X. In a third direction Z, the memory cells 211 are located between the word lines WL and the bit lines BL. The plurality of memory cells 211 in the memory array 210 are not only arranged in a plurality of rows and columns in a plane constructed by the first direction X and the second direction Y, but are also arranged in multiple layers in the third direction Z. In this case, the number of memory cells 211 in the memory array 210 is large, and the storage density of the memory array 210 is high.

[0118] The present application provides a method for preparing a memory array. Figure 21 As shown, the preparation method includes steps S100 to S400.

[0119] S100 , forming a first electrode 21 .

[0120] For example, a physical vapor deposition (PVD) process may be used to form the first electrode 21 on the substrate 101 (eg, a silicon wafer). The thickness of the first electrode 21 may be, for example, 50 nanometers.

[0121] For example, the material of the first electrode 21 may include at least one of metal, conductive oxide, and conductive nitride. For example, the material of the first electrode 21 may be tungsten.

[0122] S200 , forming a ferroelectric layer 23 .

[0123] For example, the ferroelectric layer 23 may be formed by atomic layer deposition (ALD) at a temperature of 280 degrees Celsius. The thickness of the ferroelectric layer 23 may be, for example, 8 nanometers.

[0124] For example, the material of the ferroelectric layer 23 may include a hafnium oxide-based material and a doping element. For example, the material of the ferroelectric layer 23 may be hafnium zirconium oxide (HfZrO).

[0125] S300 , forming the second electrode 22 , wherein the ferroelectric layer 23 is located between the first electrode 22 and the first electrode 21 .

[0126] For example, a chemical vapor deposition (CVD) process may be used to form the second electrode 22. The thickness of the second electrode 22 may be, for example, 30 nanometers.

[0127] For example, the material of the second electrode 22 may include at least one of metal, conductive oxide, and conductive nitride. For example, the material of the second electrode 22 may be tungsten.

[0128] In some examples, the second electrode 22 and the first electrode 21 can be made of the same material. Thus, the thermal expansion coefficient of the first electrode 21 is the same as the thermal expansion coefficient of the second electrode 22, and the difference in thermal expansion coefficient between the first electrode 21 and the ferroelectric layer 23 is the same as the difference in thermal expansion coefficient between the second electrode 22 and the ferroelectric layer 23. During the subsequent thermal annealing process, the first electrode 21 and the second electrode 22 exert the same stress on the ferroelectric layer 23, thereby ensuring a balanced force on the ferroelectric layer 23.

[0129] S400 , forming an induction layer 24 . The material of the induction layer 24 is spontaneously polarized. The induction layer 24 is provided between the first electrode 21 and the ferroelectric layer 23 , and / or the induction layer 24 is provided between the second electrode 22 and the ferroelectric layer 23 .

[0130] For example, the induction layer 24 may be formed by atomic layer deposition at a temperature of 300 degrees Celsius. The thickness of the induction layer 24 may be, for example, 2 nanometers.

[0131] In some examples, such as Figure 21 As shown, the induction layer 24 can be formed after forming the first electrode 21 (step S100) and before forming the ferroelectric layer 23 (step S200). In this way, the induction layer 24 can selectively crystallize the ferroelectric layer 23 during its crystallization process, improve the polar axis orientation of the multiple ferroelectric domains in the ferroelectric layer 23, and make the polar axis orientation in the ferroelectric layer 23 approach the direction of the electric field formed by the first electrode 21 and the second electrode 22. At the same time, before forming the ferroelectric layer 23, forming the induction layer 24 on the first electrode 21 can also separate the first electrode 21 from the ferroelectric layer 23, thereby preventing the ferroelectric layer 23 from being affected by the template effect of the material in the first electrode 21, thereby ensuring the spontaneous polarization performance of the ferroelectric layer 23.

[0132] Furthermore, after the inductive layer 24 separates the first electrode 21 from the ferroelectric layer 23, the first electrode 21 does not directly contact the ferroelectric layer 23. The inductive layer 24 can also reduce the impact of uncertainties during the growth of the ferroelectric layer. Therefore, when selecting the material for the first electrode, there is no need to consider conditions such as lattice matching and adhesion between the first electrode 21 and the ferroelectric layer 23. This expands the range of materials available for the first electrode 21 and improves the scalability of the fabrication process and material system of the ferroelectric capacitor 20.

[0133] In other examples, the inductive layer 24 may be formed after forming the ferroelectric layer 23 and before forming the second electrode 22. In still other examples, the inductive layer 24 may be formed after forming the first electrode 21 and before forming the ferroelectric layer 23, and the inductive layer 24 may be formed after forming the ferroelectric layer 23 and before forming the second electrode 22.

[0134] The preparation method provided in the embodiment of the present application forms an induction layer 24 before or after forming the ferroelectric layer 23, so that the polar axes of multiple ferroelectric domains in the ferroelectric layer 23 tend to extend along the direction of the electric field formed by the first electrode 21 and the second electrode 22. This reduces the angle between the polar axis orientation of the ferroelectric domains in the ferroelectric layer 23 and the direction of the electric field, making it easier for the ferroelectric domains to flip their polarization state under the drive of the electric field between the first electrode 21 and the second electrode 22. The flipping electric field corresponding to the ferroelectric capacitor 20 is more concentrated. During the operation of a ferroelectric capacitor 20, the adjacent ferroelectric capacitors 20 are less likely to be interfered with, thereby improving the anti-interference performance of the memory cell 211 and the memory array 210 where the ferroelectric capacitor 20 is located, thereby improving the performance of the memory 200.

[0135] Moreover, the embodiment of the present application can form the induction layer 24 and the ferroelectric layer 23 through an atomic layer deposition process with mature technology, simple operation and low cost. It does not need to obtain and improve the polar axis orientation of the ferroelectric layer 23 through an epitaxial growth process with high process difficulty, high production cost, low production efficiency and demanding selection of electrode materials and substrate materials, so that the preparation process of the ferroelectric capacitor 20 is relatively simple and the performance of the ferroelectric capacitor 20 is more superior.

[0136] In some embodiments, when the second electrode 22 includes a first sublayer 22a and a second sublayer 22b, as shown in FIG. Figure 22 As shown, step S300 may include step S310 and step S320.

[0137] S310 , forming a second sub-layer 22 b on a side of the ferroelectric layer 23 away from the first electrode 21 .

[0138] For example, a physical vapor deposition process can be used to form the second sublayer 22b on the side of the ferroelectric layer 23 away from the first electrode 21. The thickness of the second sublayer 22b can be, for example, 5 nanometers. For example, the material of the second sublayer 22b can include titanium nitride.

[0139] S320 , forming a first sub-layer 22 a on a side of the second sub-layer 22 b away from the first electrode 21 .

[0140] For example, a chemical vapor deposition process can be used to form the first sublayer 22a on a side of the second sublayer 22b away from the first electrode 21. The thickness of the first sublayer 22a can be, for example, 30 nanometers. For example, the material of the second sublayer 22b can include tungsten.

[0141] It is understandable that the size of the ferroelectric capacitor 20 varies to meet actual needs. Therefore, during the formation of the first electrode 21, the second electrode 22, the ferroelectric layer 23, and the inductive layer 24, the sizes of the first electrode 21, the second electrode 22, the ferroelectric layer 23, and the inductive layer 24 can be adjusted using a photolithography process.

[0142] In some embodiments, as Figure 17 As shown, the first electrode 21 can be a planar electrode, and the second electrode 22 can be a columnar electrode. The second electrode 22 penetrates the first electrode 21, and the ferroelectric layer 23 and the inductive layer 24 are both located between the first electrode 21 and the second electrode 22. The inductive layer 24 and the ferroelectric layer 23 are both arranged around the second electrode 22.

[0143] In this case, if Figure 23 As shown, step S100 may include step S110 and step S120.

[0144] S110: Form a plurality of alternately stacked dielectric layers 102 and a plurality of conductive layers 103. The embodiment of the present application does not limit the number and thickness of the dielectric layers 102 and the conductive layers 103, and can be designed according to actual needs. Figure 23 The formation of three dielectric layers 102 and three conductive layers 103 is taken as an example for illustration.

[0145] Exemplarily, the dielectric layer 102 is made of an insulating material, such as silicon oxide or silicon nitride, etc. The conductive layer 103 may be made of at least one of metal, conductive oxide, and conductive nitride, such as tungsten.

[0146] S120 , etching the plurality of dielectric layers 102 and the plurality of conductive layers 103 to form a groove M. The remaining portion of the etched conductive layer 103 serves as the first electrode 21 , and the remaining portion of the dielectric layer 102 serves as the insulating layer 25 .

[0147] The groove M may penetrate the entire conductive layer 103, or the groove M may penetrate part of the conductive layers 103 among the multiple conductive layers 103. Figure 23 As shown, when etching stops on the conductive layer 103, the unetched conductive layer 103 can be used as a connection layer 26 to connect multiple ferroelectric capacitors or connect ferroelectric capacitors and transistors.

[0148] In the embodiment of the present application, there is no limitation on the opening size, opening shape and depth of the groove M, and the groove M can be designed according to actual needs. For example, the groove M can be a columnar groove.

[0149] For example, a photolithography process and a dry etching process can be used to etch the dielectric layers 102 and the conductive layer 103. Since the dry etching process is anisotropic etching, the depth of the groove M can be larger and the opening size can be smaller, thereby reducing the projection size of the groove M on the plane.

[0150] In some embodiments, as Figure 24 As shown, step S400 may include forming an induction layer 24 on the sidewalls of the groove M. The induction layer 24 contacts the first electrode 21. The induction layer 24 may completely cover the sidewalls of the groove M and a portion of the bottom wall of the groove M. Alternatively, the induction layer 24 may completely cover the sidewalls and the bottom wall of the groove M.

[0151] like Figure 25 As shown, step S200 may include forming a ferroelectric layer 23 on the sidewall of the groove M.

[0152] In some examples, when the induction layer 24 is formed on the sidewall of the groove M, the ferroelectric layer 23 is located on a side of the induction layer 24 away from the first electrode 21 .

[0153] In other examples, when the induction layer 24 is not formed on the sidewalls of the groove M, the ferroelectric layer 23 contacts the first electrode 21. In this case, the ferroelectric layer 23 can completely cover the sidewalls of the groove M and a portion of the bottom wall of the groove M. Alternatively, the ferroelectric layer 23 can completely cover the sidewalls and the bottom wall of the groove M.

[0154] like Figure 26 As shown, step S300 may include forming a conductive material in the groove M to form the second electrode 22 .

[0155] In some examples, such as Figure 26 As shown, the second electrode 22 may be entirely located in the groove M. In this case, the height of the second electrode 22 may be less than or equal to the depth of the groove M.

[0156] For other examples, see Figure 17, a portion of the second electrode 22 is located in the groove M, and another portion of the second electrode 22 is located outside the groove M. In this case, the height of the second electrode 22 can be greater than the depth of the groove M. This arrangement facilitates the connection of the second electrode 22 to other devices.

[0157] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0158] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that: comprising a plurality of memory cells, said memory cells comprising ferroelectric capacitors; The ferroelectric capacitor comprises: a first electrode and a second electrode disposed opposite to each other; a ferroelectric layer located between the first electrode and the second electrode; An induction layer is provided between the first electrode and the ferroelectric layer, and / or an induction layer is provided between the second electrode and the ferroelectric layer; wherein the material of the induction layer is spontaneously polarized.

2. The storage array according to claim 1, wherein: The material of the induction layer is spontaneously polarized along a predetermined direction, and the predetermined direction is parallel to a direction of an electric field formed by the first electrode and the second electrode.

3. The storage array according to claim 1 or 2, wherein: The material of the induction layer includes wurtzite III-nitride.

4. The storage array according to any one of claims 1 to 3, wherein: The material of the induction layer includes at least one of aluminum nitride, gallium nitride, aluminum gallium nitride, aluminum scandium nitride and aluminum boron nitride.

5. The storage array according to any one of claims 1 to 4, wherein: The thickness of the induction layer is greater than or equal to 1 nanometer and less than or equal to 5 nanometers.

6. The storage array according to any one of claims 1 to 5, wherein: The first electrode and the second electrode are both plate-shaped, and the first electrode is parallel to the second electrode; the induction layer is parallel to the first electrode.

7. The storage array according to any one of claims 1 to 5, wherein: The first electrode is in a plate shape, the second electrode is in a column shape, the second electrode passes through the first electrode, and the ferroelectric layer and the induction layer are both arranged around the second electrode.

8. A method for preparing a storage array, characterized in that: include: forming a first electrode; forming a ferroelectric layer; forming a second electrode; forming an induction layer, wherein the material of the induction layer is spontaneously polarized; The first electrode and the second electrode are arranged opposite to each other, and the ferroelectric layer is located between the first electrode and the second electrode; an induction layer is provided between the first electrode and the ferroelectric layer, and / or the induction layer is provided between the second electrode and the ferroelectric layer.

9. A memory, characterized in that: include: The storage array according to any one of claims 1 to 7; A controller is electrically connected to the storage array.

10. An electronic device, characterized in that: include: circuit boards; The memory according to claim 9, wherein the memory is located on the circuit board and is electrically connected to the circuit board.

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