Storage array, manufacturing method thereof, memory and electronic equipment

Abstract

The invention provides a storage array, a manufacturing method thereof, a memory and electronic equipment, a connector in the storage array comprises a bit line and a plurality of side electrodes, and the side electrodes are arranged on the two opposite sides of the bit line in the first direction; a storage layer is arranged between the bit line and each side electrode; the side electrode, the corresponding storage layer and the corresponding part of bit line form a storage capacitor; the connector further comprises a plate line, a word line and a plurality of access channels arranged at intervals, each access channel and each side electrode are correspondingly arranged in a stacked mode in the third direction, the first end of each access channel is connected with the corresponding side electrode, and the second end of each access channel is connected with the plate line; the access channel, the word line, the partial plate line, and the corresponding side electrode form an access transistor. The access channels and the side electrodes are arranged in a stacked mode, three-dimensional stacking of the storage capacitors and the access transistors is achieved, the storage density of the storage array is improved, and therefore the storage capacity of the storage array is improved.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a storage array, a manufacturing method thereof, a memory, and an electronic device. Background Art

[0002] Ferroelectric memory has advantages such as high speed, good durability, and non-volatility. Traditional ferroelectric memory has a 1T1C structure, in which a memory cell includes an access transistor and a storage capacitor. One end of the storage capacitor is connected to the bit line, the other end of the storage capacitor is connected to the first electrode of the access transistor, the second electrode of the access transistor is connected to the plate line, and the control electrode of the access transistor is connected to the word line. Based on this structure, a memory array with a ladder cell structure has been derived. The second electrode of each access transistor is connected to the same plate line, one end of each storage capacitor is connected to the same bit line, and the control electrodes of different access transistors are connected to different word lines, so that the memory cells form a ladder-like structure after being connected. However, current memory arrays with ladder cell structures mostly use a horizontally arranged planar capacitor structure, which limits the improvement of storage density. Summary of the Invention

[0003] The present application provides a memory array, a manufacturing method thereof, a memory, and an electronic device, which are used to improve the storage density of the memory array and increase the storage capacity of the memory.

[0004] In a first aspect, an embodiment of the present application provides a memory array, which includes a connector; the connector includes: a bit line and a plurality of spaced-apart side electrodes, each side electrode is arranged on opposite sides of the bit line along a first direction, and each side electrode located on the same side of the bit line is arranged along a second direction, the first direction intersects with the second direction, for example but not limited to, the first direction is perpendicular to the second direction, and the bit line extends along the second direction; a storage layer is provided between the bit line and each side electrode; the side electrode, the storage layer corresponding to the side electrode, and the bit line corresponding to the side electrode form a storage capacitor; the connector also includes: a plate line, a word line, and a plurality of spaced-apart access channels, each access channel is stacked corresponding to each side electrode along a third direction, the third direction is perpendicular to the first direction and the second direction respectively, that is, the first direction and the second direction constitute a first plane, and the third direction is perpendicular to the first plane; a first end of the access channel is connected to the corresponding side electrode, and a second end of each access channel is connected to the plate line; the word line is insulated from the access channel; the access channel, the word line, part of the plate line, and the corresponding side electrode form an access transistor.

[0005] Among them, an access transistor and a corresponding storage capacitor constitute a storage unit, and the connector includes multiple storage units. When there are multiple side electrodes, there are multiple corresponding storage capacitors; when there are multiple access channels, there are multiple corresponding storage transistors; therefore, the connector can include multiple access transistors and multiple storage capacitors, and thus the connector includes multiple storage units; when some bit lines form storage capacitors, one end of each storage capacitor is connected to the bit line; when the access channel is correspondingly arranged and connected to the side electrode, the other end of the storage capacitor is connected to the first electrode of the access transistor; when some plate lines form access transistors, the second electrode of each access transistor is connected to the plate line; combined with the word line being insulated from the access channel, and the word line being used to form the control electrode of the access transistor, the connection between each access transistor and each storage capacitor is realized, and the connector can also have a ladder cell structure. Moreover, when the side electrodes are arranged on both sides of the bit line and the access channels are stacked corresponding to the side electrodes, a three-dimensional stacking of the storage capacitor and the access transistor is achieved, forming a three-dimensional structure connector, thereby transforming the storage array from a two-dimensional structure to a three-dimensional structure, improving the storage density of the storage array, and thus improving the storage capacity of the storage array.

[0006] In addition, in the connector, although the storage capacitor and the access transistor are stacked three-dimensionally, part of the bit line serves as one end of the storage capacitor, and the side electrode serves as the other end of the storage capacitor. The side electrode is arranged in a planar manner on the side of the bit line, so that the originally horizontally arranged storage capacitor is transformed into a vertical arrangement, reducing the space occupied by the storage capacitor in the horizontal direction and making full use of the space in the vertical direction. This not only improves the storage density of the storage array, but also avoids the influence of the curvature effect on the electrical properties of the storage capacitor, thereby improving the performance of the storage array.

[0007] Optionally, in the interconnect, the word lines, plate lines, and bit lines can be arranged along a third direction, with the word lines located between the plate lines and the bit lines. Since the word lines are insulated from the access channels, and the access channels are respectively connected to the plate lines and side electrodes disposed on the sides of the bit lines, locating the word lines between the plate lines and the bit lines facilitates connection of the access channels to the plate lines and the side electrodes, preventing the word lines from interfering with the plate lines. Furthermore, the word lines have first through-holes extending along the third direction, with the access channels passing through the first through-holes. This allows the word lines to surround the access channels, fully utilizing the space in the third direction and improving the structural compactness of the interconnect, thereby increasing the storage density of the memory array. Furthermore, when insulating the word lines from the access channels, a first insulating layer can be disposed between the word lines and the access channels to physically isolate the access channels from the word lines. It should be understood that the first insulating layer can also be considered to be located within the first through-holes.

[0008] Optionally, the connector may further include: a reset control line and a reset channel, wherein the reset channel and the bit line are stacked along a third direction, a first end of the reset channel being connected to the bit line, and a second end of the reset channel being connected to the plate line; the reset control line being insulated from the reset channel; and the reset channel, the reset control line, a portion of the plate line, and a portion of the bit line forming a reset transistor. When the reset transistor is turned on, the plate line and the bit line are short-circuited, so that the voltages in the plate line and the bit line are the same. When each access transistor is turned on, the voltages across each storage capacitor are made the same, thereby releasing the voltage at the connection node between the access transistor and the storage capacitor, eliminating crosstalk, and improving the accuracy of data storage and reading while increasing storage density, thereby enhancing the performance of the storage array.

[0009] The reset control line includes a second through-hole extending along a third direction. The reset channel passes through the second through-hole, allowing the reset control line to surround the reset channel. This helps reduce structural interference of the reset control line with the word lines, bit lines, and plate lines. Furthermore, a second insulating layer is provided between the reset control line and the reset channel. This second insulating layer physically isolates the reset channel from the reset control line, thereby achieving insulation between the reset control line and the reset channel. It should be understood that the second insulating layer can also be considered to be located within the second through-hole.

[0010] In addition, the reset control line and the word line can be set in the same layer, that is, the reset control line and the word line are located in the same layer. In this way, the space in the film layer where the word line is located can be fully utilized to set the reset control line, which is beneficial to reducing the height of the connector and increasing the stacking density of the connector, thereby increasing the storage density of the memory array.

[0011] Optionally, the number of connectors included in the memory array can be one, two, three, four, or more, and can be specifically configured based on actual needs and is not specifically limited herein. When multiple connectors are provided, at least some of the connectors can be arranged in parallel on the same layer, for example, all of the connectors can be arranged in parallel on the same layer; or, some of the connectors can be arranged in parallel on the same layer, while some of the connectors can be arranged in different layers. This allows for three-dimensional stacking of the connectors, fully utilizing space in the third direction and improving the storage density of the memory array. For two adjacent connectors located in the same layer, the word lines in the two connectors are connected in a corresponding manner. Regardless of whether the connectors are located in the same layer or in different layers, the structures are substantially identical, so the number of word lines in two adjacent connectors in the same layer is the same. In this case, the word lines in the two connectors can be connected in a one-to-one correspondence, reducing the number of word lines in the memory array and simplifying the structure of the memory array. Of course, when the connectors include reset transistors, for two adjacent connectors located in the same layer, the reset control lines in the two connectors are connected. This can reduce the number of reset control lines in the memory array and simplify the structure of the memory array.

[0012] Optionally, when multiple connectors are provided, the connectors may further include: a bit line auxiliary line, a gate control line, and a gate channel, wherein the gate channel and the bit line are stacked along a third direction, the first end of the gate channel is connected to the bit line, and the second end of the gate channel is connected to the bit line auxiliary line; the bit line auxiliary line and the gate control line are provided in different layers; the gate control line is insulated from the gate channel; and the gate channel, the gate control line, a portion of the bit line, and the bit line auxiliary line form a gate transistor. When the gate transistor is turned on, the signal in the bit line auxiliary line can be transmitted to the corresponding bit line. When an access transistor in the corresponding connector is turned on and the corresponding plate line has an appropriate voltage, data can be stored in the corresponding storage capacitor or data stored in the storage capacitor can be read, thereby achieving precise control of the corresponding storage cell, realizing data storage and reading, and realizing the function of the storage array.

[0013] The bit line auxiliary lines of each connector are connected to reduce the number of bit line auxiliary lines provided in the memory array and simplify the structure of the memory array. Furthermore, the bit line auxiliary lines are provided in different layers from the bit lines, word lines, and plate lines. For example, when the bit lines, word lines, and plate lines are arranged along the third direction, the bit line auxiliary lines are located on the side of the plate lines away from the word lines. In this case, the length of the gate channel in the third direction is greater than the length of the access channel in the third direction; or, the bit line auxiliary lines are located between the plate lines and the word lines. In this case, the length of the gate channel in the third direction is less than the length of the access channel in the third direction. The specific configuration can be based on actual needs and is not limited here.

[0014] Furthermore, the gate control lines are provided on the same layer as the word lines. This allows the gate control lines to be fully utilized in the film layer where the word lines reside. This helps reduce the height of the connectors, increases the packing density of the connectors, and improves the storage density of the memory array. It should be understood that the height of the connectors can be considered as the length of the connectors in the third direction.

[0015] Furthermore, for the selection control lines in two adjacent connectors in the same layer: first, the two selection control lines can be insulated to avoid interference between the two selection transistors; second, the shapes of the two selection control lines can be specially set to fully utilize the space in the film layer where the word lines are located, increase the compactness of the structure, and thus improve the storage density of the memory array. For example, if these two gate control lines are respectively recorded as the first gate control line and the second gate control line, the second gate control line includes a first part and a second part that are connected, and the extension direction of at least part of the first gate control line is parallel to the extension direction of the first part, and the extension direction of the second part intersects with the extension direction of the first part, so that the projection of the second gate control line on the first plane is similar to the shape of "L", and the first gate control line is arranged between the word line and the second gate control line, so that the second gate control line partially surrounds the first gate control line, so that the space in the film layer where the word line is located can be fully utilized to set the two gate control lines; of course, the setting method of the two gate control lines is not limited to this, and can also be other setting methods. As long as the setting method can make full use of the space and increase the structural density, it belongs to the protection scope of the embodiment of the present application.

[0016] Furthermore, the gate control line includes a third through-hole extending along a third direction, and the gate channel passes through the third through-hole, so that the gate control line is arranged around the gate channel to reduce the interference of the gate control line on other signal lines. In addition, to achieve insulation between the gate channel and the gate control line, a third insulating layer can be provided between the gate channel and the gate control line, thereby achieving physical isolation between the gate channel and the gate control line. It should be understood that the third insulating layer can also be considered to be located within the third through-hole.

[0017] In a second aspect, embodiments of the present application further provide a memory device, which is a device for storing information. The memory device comprises: any of the memory arrays described in the first aspect above, and a controller, the memory array being electrically connected to the controller. Specifically, the controller can access the memory array, read data from the memory array, or write data to the memory array. Because the memory array has a high storage density, the memory device including the memory array also has a high storage density and a large storage capacity.

[0018] It should be understood that since the principle of the memory solving the problem is similar to the principle of the aforementioned storage array solving the problem, the implementation and technical effects of the memory can refer to the implementation and technical effects of the aforementioned storage array, and the repeated parts will not be repeated.

[0019] In a third aspect, embodiments of the present application further provide an electronic device comprising: any of the memories described in the second aspect and a circuit board, the memory being electrically connected to the circuit board. Because the memories described in embodiments of the present application have a high storage density and a large storage capacity, the electronic device including the memories has improved performance.

[0020] It should be understood that since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the aforementioned memory, the implementation and technical effects of the electronic device can refer to the implementation and technical effects of the aforementioned memory, and the repeated parts will not be repeated.

[0021] In a fourth aspect, an embodiment of the present application further provides a method for manufacturing a memory array, which can be used to manufacture a memory array as described in any embodiment of the first aspect above, and the manufacturing method may include: forming a bit line on a substrate; forming a memory layer on the substrate with the bit line formed; forming a plurality of spaced-apart side electrodes on the memory layer; wherein each side electrode is arranged on opposite sides of the bit line along a first direction, and each side electrode located on the same side of the bit line is arranged along a second direction, the first direction intersects with the second direction, and the bit line extends along the second direction; the side electrode, the memory layer corresponding to the side electrode, and the bit line corresponding to the side electrode form a storage capacitor; an access channel is formed on each side electrode; wherein a first end of the access channel is connected to the corresponding side electrode; the access channel and the side electrode are stacked correspondingly along a third direction, and the third direction is perpendicular to the first direction and the second direction respectively; forming a word line and a plate line respectively, wherein the word line is insulated from the access channel; the second end of each access channel is connected to the plate line; the access channel, the word line, part of the plate line, and the corresponding side electrode form an access transistor. In this way, a memory array with a higher storage density can be manufactured, thereby increasing the storage capacity of the memory array.

[0022] Optionally, the process of forming a bit line may include: step 1.1, sequentially forming a first dielectric layer and a second dielectric layer on a substrate; step 1.2, etching the first dielectric layer and a portion of the second dielectric layer to form a first trench extending along a second direction; step 1.3, depositing a first conductive layer such that the sidewalls of the first trench, the bottom of the first trench, and the area above the first dielectric layer are all covered with the first conductive layer; and step 1.4, etching the first conductive layer such that the first conductive layer at the bottom of the first trench and above the first dielectric layer is etched away, leaving only the first conductive layer on the sidewalls of the first trench. In this case, each first conductive layer on the sidewall of the first trench constitutes a bit line. It should be understood that the first dielectric layer and the second dielectric layer can be made of different materials. The specific materials can be selected based on actual needs and are not specifically limited herein.

[0023] Optionally, the process of forming the storage layer may include: step 2.1, removing the first dielectric layer by etching to expose the second dielectric layer; step 2.2, depositing the storage layer, wherein the storage layer covers the bit line and the exposed second dielectric layer.

[0024] Optionally, the process of forming a plurality of spaced-apart side electrodes may include: step 3.1, depositing a second conductive layer so that the second conductive layer covers the storage layer; step 3.2, etching the second conductive layer to retain only the second conductive layer on the side and etching away the second conductive layer at other locations; step 3.3, depositing a first dielectric material to fill the gaps between the second conductive layers with the first dielectric material; step 3.4, etching the filled first dielectric material to form pores extending along the first direction, with the second conductive layer on the side exposed in the pores; etching the exposed second conductive layer on the side to obtain a plurality of side electrodes arranged along the second direction. Furthermore, after forming the side electrodes, the process may further include: filling the gaps with the first dielectric material to form a first dielectric layer, with the side electrodes, storage layer, and bit lines embedded in the first dielectric layer; chemically polishing the upper surface of the first dielectric layer to expose the top of the storage layer and the side electrodes; and then, sequentially depositing the second dielectric layer and the first dielectric layer to obtain a block.

[0025] Optionally, the process of forming the access channel may include: step 4.1, etching the first dielectric layer, the second dielectric layer, and the first dielectric layer, arranged sequentially from top to bottom of the block, with the substrate side of the block as the bottom of the block and the opposite side as the top of the block, to form multiple channels, each channel exposing a side electrode; step 4.2, depositing semiconductor material into each channel so that the semiconductor material fills each channel; then performing chemical polishing to remove the semiconductor material above the topmost first dielectric layer to prevent the semiconductor material in each channel from being connected, and the semiconductor pillars formed by the semiconductor material in the channel are connected to the corresponding side electrodes, so that the semiconductor pillars can serve as access channels. Further, after forming the access channel, the process may also include: etching away the top first dielectric layer to expose the second dielectric layer and a portion of each semiconductor pillar; and sequentially depositing an insulating material and a conductive material such that the insulating material covers the exposed second dielectric layer and the exposed semiconductor pillars, and the conductive material covers the insulating material; wherein the insulating material serves as the first insulating layer, and the conductive material can be used to form word lines.

[0026] Optionally, the process of forming word lines and plate lines may include: step 5.1, using a first dielectric material to fill the gaps between the semiconductor pillars to form a first dielectric layer that wraps the semiconductor pillars; then, etching the first dielectric layer to form a second trench along the first direction, wherein the second trench exposes the conductive material located above the second dielectric layer; etching the conductive material to form a plurality of conductive portions spaced apart, each conductive portion being considered a word line; step 5.2, filling the second trench with the first dielectric material, and chemically polishing the top of the first dielectric material to expose the top of the semiconductor pillar; step 5.3, When depositing the conductive material in the above steps, the conductive material and the insulating material will cover the top of the semiconductor column, so the insulating material and the conductive material on the top of the semiconductor column can be etched to expose the semiconductor, and more conductive material can be etched away; step 5.4, use the first dielectric material to fill the gap left after etching, and chemically polish the first dielectric material on the top to expose the top of the semiconductor column; then continue to deposit the conductive material, and pattern the conductive material to obtain a plurality of plate lines, each plate line is connected to the top of the corresponding access channel, and the plate line and the word line are insulated by the first dielectric material.

[0027] Optionally, when the connector includes a reset transistor, a reset control line can also be formed when forming a word line. That is, among the conductive portions formed, some conductive portions are used to form the word line, and some conductive portions are used to form the reset control line. Furthermore, when forming the access channel, a reset channel can also be formed. That is, among the channels formed, some channels expose the bit line, and the semiconductor material filled in these channels that expose the bit line can form the reset channel, while some channels expose the side electrodes, and the semiconductor material filled in these channels that expose the side electrodes can form the access channel.

[0028] Optionally, when the connector includes a gate transistor, a gate control line may also be formed when forming a word line. That is, among the conductive portions formed, some conductive portions are used to form the word line, and some conductive portions are used to form the gate control line. Furthermore, when forming the access channel, a partial structure in the gate channel may also be formed. That is, among the channels formed, some channels may expose the bit line, and the semiconductor material filled in these channels that expose the bit line may form a partial structure in the gate channel. Some channels may expose the side electrodes, and the semiconductor material filled in these channels that expose the side electrodes may form the access channel. Furthermore, when patterning is performed to form plate lines, the tops of some semiconductor pillars are connected to the plate lines, while the tops of the remaining semiconductor pillars are exposed and not connected to the plate lines. A first dielectric material is then deposited to form a first dielectric layer to cover each plate line. The first dielectric layer is etched to form a plurality of holes, which expose the tops of the semiconductor pillars not connected to the plate lines. Semiconductor material is then deposited to fill the holes. Chemical polishing is then used to remove the semiconductor material on the first dielectric layer, thereby disconnecting the semiconductor pillars not connected to the plate lines from each other. At this point, the semiconductor pillars not connected to the plate lines form a gate channel. Conductive material is then deposited and patterned to form a bit line auxiliary line, which is connected to the top of the gate channel.

[0029] It should be understood that since the principle of solving the problem of manufacturing a storage array by this manufacturing method is similar to the principle of solving the problem by the aforementioned storage array, the implementation and technical effects of this manufacturing method can refer to the implementation and technical effects of the aforementioned storage array, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0032] Figure 3 A circuit diagram of a memory array provided in an embodiment of the present application;

[0033] Figure 4 A three-dimensional schematic diagram of a storage array provided in an embodiment of the present application;

[0034] Figure 5 A cross-sectional view of an access transistor provided in an embodiment of the present application;

[0035] Figure 6 A three-dimensional schematic diagram of another storage array provided in an embodiment of the present application;

[0036] Figure 7 A circuit diagram of another memory array provided in an embodiment of the present application;

[0037] Figure 8 A three-dimensional schematic diagram of another storage array provided in an embodiment of the present application;

[0038] Figure 9 A circuit diagram of another memory array provided in an embodiment of the present application;

[0039] Figure 10 A flowchart of manufacturing a storage array provided in an embodiment of the present application;

[0040] FIG11( a ) is a structural diagram of another storage array during the manufacturing process provided by an embodiment of the present application;

[0041] FIG11( b ) is a structural diagram of another storage array during the manufacturing process provided by an embodiment of the present application;

[0042] FIG11( c ) is a structural diagram of another storage array during the manufacturing process provided by an embodiment of the present application;

[0043] FIG11( d ) is a structural diagram of another storage array during the manufacturing process provided by an embodiment of the present application;

[0044] FIG11( e ) is a structural diagram of another storage array during the manufacturing process provided by an embodiment of the present application;

[0045] FIG11( f ) is a structural diagram of another memory array during the manufacturing process provided by an embodiment of the present application;

[0046] FIG11( g) is a structural diagram of another storage array during the manufacturing process provided by an embodiment of the present application;

[0047] FIG11( h) is a structural diagram of another memory array during the manufacturing process provided by an embodiment of the present application;

[0048] FIG11( i) is a structural diagram of another memory array during the manufacturing process provided by an embodiment of the present application;

[0049] FIG11( j) is a structural diagram of another memory array during the manufacturing process provided by an embodiment of the present application;

[0050] FIG11( k ) is a structural diagram of another storage array during the manufacturing process provided by an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.

[0052] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrating relative positional relationships and do not represent true proportions.

[0053] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, its application scenario is first explained below.

[0054] The technical solutions provided in the embodiments of this application can be widely applied in various electronic devices, which may include various terminal devices and electronic components. Terminal devices include, but are not limited to, smartphones, smart TVs, smart TV set-top boxes, smart watches, personal computers (PCs), wearable devices, and smart broadband devices. Electronic components include, but are not limited to, wireless networks, fixed networks, servers, and other telecommunications equipment, which are not listed here.

[0055] Figure 1 The schematic diagram of the structure of the electronic device is shown as an example. Figure 1 As shown, the electronic device includes: a housing 100 , and a circuit board 200 and a memory 300 disposed in the housing 100 , wherein the memory 300 is connected to the circuit board 200 . Figure 2 The following is a schematic diagram illustrating the internal structure of a memory applicable to an embodiment of the present application. It should be understood that the memory m3 shown in the figure is only an example, and the memory m3 may have more or fewer components than shown in the figure, may combine two or more components, or may have different component configurations. The various components shown in the figure can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits. Figure 2 A detailed introduction to each component in memory m3:

[0056] like Figure 2As shown, the memory m3 may include a storage array m3-1 and a controller m3-2. The storage array m3-1 is used to store data and is a matrix array composed of multiple storage cells arranged in rows and columns. Each storage cell can be used to store one or more bits of binary data, such as "0" and / or "1". The multiple storage cells can be located on different tracks of the same disk or on different disks, without specific limitation. The controller m3-2 is used to read or write data in the storage array m3-1 and is a device with control capabilities. The controller m3-2 can be connected to the storage array m3-1, and the connection method can be, for example, a bus connection. The controller m3-2 may include multiple functional components, such as, but not limited to, a driving circuit, a decoding circuit, and an amplifier circuit. These functional components may be provided as separate devices, implemented in one device, or provided in at least two devices in any combination, without specific limitation.

[0057] Continue to refer to Figure 2 As shown, the controller m3-2 can also be connected to an external device m4, which can be, for example, a read / write device or a processor. When reading / writing data, the external device m4 can send a read / write request to the controller m3-2, which carries the row address information and column address information of the target storage unit to be read / written. The controller m3-2 decodes the row address information in the read / write request to determine the row where the target storage unit is located, and turns on all storage units corresponding to the row where the target storage unit is located by decoding the selection signal. Then, the controller m3-2 decodes the column address information in the read / write request to obtain the column where the target storage unit is located, and then reads the data stored in the target storage unit at the column and sends it to the external device m4, or writes the data to be written sent by the external device m4 into the target storage unit at the column.

[0058] although Figure 2 Not shown in the figure, the memory m3 may also include other components, such as a main memory data register (Memory Data Register, MDR) and a main memory address register (Memory Address Register, MAR), etc., which are not described here in detail.

[0059] There are many types of memory, such as ferroelectric memory, which has the advantages of fast speed, good durability, and non-volatility. The traditional ferroelectric memory is a 1T1C structure. Figure 3As shown, memory cell D0 includes an access transistor M0 and a storage capacitor C0. One end of storage capacitor C0 is connected to bit line BL, the other end of storage capacitor C0 is connected to the second electrode of access transistor M0, the first electrode of access transistor M0 is connected to plate line PL, and the control electrode of access transistor M0 is connected to word line WL. Based on this structure, a ladder cell memory array has been derived. The second electrode of each access transistor M0 is connected to the same plate line PL, one end of each storage capacitor C0 is connected to the same bit line BL, and the control electrodes of different access transistors M0 are connected to different word lines WL, so that the memory cells D0 form a ladder-like structure after being connected. However, current ladder cell memory arrays mostly use a horizontally arranged planar capacitor structure, which limits the improvement of storage density.

[0060] Based on this, an embodiment of the present application provides a storage array that can improve the storage density of the storage array and increase the storage capacity of the storage array.

[0061] Figure 4 A schematic diagram of the structure of a storage array according to an embodiment of the present application is shown as an example. Figure 4 As shown, Figure 4 (a) in FIG. 1 shows a three-dimensional schematic diagram of a single connector 10. Figure 4 (b) in FIG. 1 shows a three-dimensional schematic diagram of a single access channel 13 and a word line WL. Figure 4 (c) in the figure shows a three-dimensional schematic diagram of the bit line BL and each side electrode 11. The memory array includes a connector 10. The connector 10 may include: a bit line BL and a plurality of spaced side electrodes 11. Each side electrode 11 is disposed on opposite sides of the bit line BL along a first direction (i.e., the y direction). The side electrodes 11 on the same side of the bit line BL are arranged along a second direction (i.e., the x direction). The first direction intersects the second direction, for example, but not limited to, the first direction is perpendicular to the second direction, and the bit line BL extends along the second direction. A storage layer 12 is disposed between the bit line BL and each side electrode 11. The side electrodes 11 and the side electrodes 11 are disposed on opposite sides of the bit line BL. The storage layer 12 corresponding to the surface electrode 11 and the bit line BL corresponding to the side electrode 11 form a storage capacitor C0; and the connector 10 may further include: a plate line PL, a word line WL and a plurality of access channels 13 arranged at intervals, each access channel 13 and each side electrode 11 are stacked correspondingly along a third direction (i.e., z direction), for example, the number of access channels 13 and the side electrodes 11 are the same and they are arranged one-to-one, the third direction is perpendicular to the first direction and the second direction respectively, that is, the first direction and the second direction constitute a first plane (i.e., a horizontal plane), and the third direction is perpendicular to the first plane; the first end of the access channel 13 (e.g., Figure 4 The lower end of the access channel 13 shown in FIG) is connected to the corresponding side electrode 11, and the second end of each access channel 13 (as shown in FIG) is connected to the corresponding side electrode 11. Figure 4 The upper end of the access channel 13 shown in FIG is connected to the plate line PL; the access channel 13, the word line WL, part of the plate line PL, and the corresponding side electrode 11 form an access transistor ( Figure 4 not shown).

[0062] Among them, an access transistor and a corresponding storage capacitor C0 constitute a storage unit ( Figure 4 (not shown), in this case, interconnect 10 includes multiple memory cells. When multiple side electrodes 11 are provided, multiple storage capacitors C0 are provided accordingly; when multiple access channels 13 are provided, multiple storage transistors are provided accordingly. Therefore, interconnect 10 can include multiple access transistors and multiple storage capacitors C0, and thus multiple memory cells. When a portion of bit lines BL form storage capacitors C0, one end of each storage capacitor C0 is connected to bit line BL. When access channels 13 are provided and connected to side electrodes 11, the other end of storage capacitor C0 is connected to the first electrode of the access transistor. When a portion of plate line PL forms an access transistor, the second electrode of each access transistor is connected to plate line PL. In addition, word line WL is insulated from access channel 13, and word line WL is used to form the control electrode of the access transistor. This achieves the connection between each access transistor and each storage capacitor C0, and can also make interconnect 10 have a ladder cell structure. Moreover, when the side electrodes 11 are arranged on both sides of the bit line BL and the access channels 13 are stacked corresponding to the side electrodes 11, a three-dimensional stacking of the storage capacitor C0 and the access transistor is achieved, forming a three-dimensional structure connector 10, thereby transforming the storage array from a two-dimensional structure to a three-dimensional structure, improving the storage density of the storage array, and thus improving the storage capacity of the storage array.

[0063] In addition, in the connector 10, although the storage capacitor C0 and the access transistor are stacked three-dimensionally, part of the bit line BL serves as one end of the storage capacitor C0, and the side electrode 11 serves as the other end of the storage capacitor C0, and the side electrode 11 is arranged in a planar manner on the side of the bit line BL, so that the originally horizontally arranged storage capacitor C0 is transformed into a vertical arrangement, reducing the space occupied by the storage capacitor C0 in the horizontal direction and making full use of the space in the vertical direction. This not only improves the storage density of the storage array, but also avoids the influence of the curvature effect on the electrical properties of the storage capacitor C0, thereby improving the performance of the storage array.

[0064] Continue to refer to Figure 4As shown, in the connector 10, the word line WL, the plate line PL and the bit line BL can be arranged along the third direction (i.e., the z direction), and the word line WL is located between the plate line PL and the bit line BL; since the word line WL is insulated from the access channel 13, and the access channel 13 is respectively connected to the plate line PL and the side electrode 11 provided on the side of the bit line BL, the word line WL is provided between the plate line PL and the bit line BL, so that the access channel 13 can be connected to the plate line PL and the side electrode 11 more conveniently, thereby avoiding the positional interference of the word line WL on the plate line PL. In addition, referring to Figure 5 In the cross-sectional view of the access transistor M0 shown, a first through-hole T1 is provided in the word line WL, extending along the third direction. The access channel 13 passes through the first through-hole T1, allowing the word line WL to surround the access channel 13. This fully utilizes the space in the third direction, improves the structural compactness of the interconnect 10, and thereby increases the storage density of the memory array. Furthermore, when insulating the word line WL from the access channel 13, a first insulating layer 14 can be provided between the word line WL and the access channel 13 to physically isolate the access channel 13 from the word line WL. It should be understood that the first insulating layer 14 can also be considered to be located within the first through-hole T1.

[0065] The number of connectors 10 included in the storage array can be one, two, three, four or more, and can be set according to actual needs, and is not specifically limited here. Figure 6 As shown, Figure 6 In the figure, only two connectors are used as an example for illustration, where (a) shows a three-dimensional schematic diagram of the two connectors, and (b) shows a cross-sectional view of the selection transistor M1. When there are multiple connectors, at least some of the connectors 10 can be arranged in the same layer and in parallel, for example: all connectors 10 are arranged in the same layer and in parallel; or, some connectors are arranged in the same layer and in parallel, and some connectors are arranged in different layers. This can achieve three-dimensional stacking of the connectors, fully utilizing the space in the third direction and improving the storage density of the memory array. Among them, for two adjacent connectors located in the same layer, the word lines WL in the two connectors are correspondingly connected; whether the connectors are located in the same layer or in different layers, the structure is basically the same, so the number of word lines WL in the two adjacent connectors in the same layer is the same. In this case, the word lines WL in the two connectors can be arranged to be connected one-to-one, reducing the number of word lines WL in the memory array and simplifying the structure of the memory array.

[0066] Continue to refer to Figure 6 As shown, when a plurality of connectors are provided, the connector may further include: a bit line auxiliary line GBL, a gate control line KL and a gate channel 15, the gate channel 15 and the bit line BL are stacked along the third direction, and the first end of the gate channel 15 (such as Figure 6The lower end of the gate channel 15 shown in FIG) is connected to the bit line BL, and the second end of the gate channel 15 (as shown in FIG) is connected to the bit line BL. Figure 6 The upper end of the gate channel 15 shown in FIG is connected to the bit line auxiliary line GBL; the bit line auxiliary line GBL and the gate control line KL are arranged in different layers; the gate control line KL is insulated from the gate channel 15; the gate channel 15, the gate control line KL, part of the bit line BL, and the bit line auxiliary line GBL form a gate transistor M1. The corresponding circuit structure is shown in FIG. Figure 7 As shown, taking the top selection transistor M1 as an example, when the selection transistor M1 is turned on, the signal in the bit line auxiliary line GBL can be transmitted to the corresponding bit line (i.e., BL1). When the leftmost access transistor M0 in the corresponding connector is turned on and the corresponding plate line (i.e., PL1) has a suitable voltage, data can be stored in the leftmost storage capacitor C0 or the data stored in the storage capacitor C0 can be read, thereby achieving precise control of the leftmost storage unit, realizing data storage and reading, and realizing the function of the storage array.

[0067] Continue to refer to Figure 6As shown, the gate control line KL is provided in the same layer as the word line WL, that is, the gate control line KL and the word line WL are located in the same layer. This allows the space in the film layer where the word line WL is located to be fully utilized to provide the gate control line KL, which helps to reduce the height of the connector 10, and can also increase the packing density of the connector 10, thereby improving the storage density of the memory array. It should be understood that the height of the connector 10 can be regarded as the length of the connector 10 in the third direction. Furthermore, with respect to the gate control lines KL in two adjacent connectors 10 located in the same layer: first, these two gate control lines KL can be insulated to prevent interference between the two gate transistors; second, the shape of these two gate control lines KL can be specially configured to fully utilize the space in the film layer where the word line WL is located, increase the compactness of the structure, and thus improve the storage density of the memory array. For example, if the two gate control lines KL are respectively recorded as the first gate control line KL and the second gate control line KL, the second gate control line KL includes a first part and a second part that are connected, and the extension direction of at least part of the first gate control line KL is parallel to the extension direction of the first part, and the extension direction of the second part intersects with the extension direction of the first part, so that the projection of the second gate control line KL on the first plane is similar to the shape of "L", and the first gate control line KL is arranged between the word line WL and the second gate control line KL, so that the second gate control line KL partially surrounds the first gate control line KL, so that the space in the film layer where the word line WL is located can be fully utilized to set the two gate control lines KL; of course, the setting method of the two gate control lines KL is not limited to this, and can also be other setting methods. As long as the setting method can make full use of the space and increase the structural density, it belongs to the protection scope of the embodiment of the present application. Furthermore, the gate control line KL includes a third through hole T3 extending along a third direction (i.e., the z-direction). The gate channel 15 passes through the third through hole T3, so that the gate control line KL is disposed around the gate channel 15 to reduce the positional interference of the gate control line KL with other signal lines. Furthermore, to insulate the gate channel 15 from the gate control line KL, a third insulating layer 16 can be disposed between the gate channel 15 and the gate control line KL. The third insulating layer 16 physically isolates the gate channel 15 from the gate control line KL. It should be understood that the third insulating layer 16 can also be considered to be located within the third through hole T3.

[0068] Furthermore, the bit line auxiliary lines GBL of each connecting body 10 are connected to reduce the number of bit line auxiliary lines GBL provided in the memory array and simplify the structure of the memory array. Furthermore, the bit line auxiliary lines GBL are provided at different layers from the bit lines BL, word lines WL, and plate lines PL. For example, when the bit lines BL, word lines WL, and plate lines PL are arranged along the third direction, the bit line auxiliary lines GBL are located on the side of the plate lines PL away from the word lines WL. Figure 6As shown in , at this time, the length of the selection channel 15 in the third direction is greater than the length of the access channel 13 in the third direction; or, the bit line auxiliary line GBL is located between the plate line PL and the word line WL, which is not shown in the figure. At this time, the length of the selection channel 15 in the third direction is less than the length of the access channel 13 in the third direction; the specific setting can be based on actual needs and is not limited here.

[0069] It should be understood that in Figure 7 In the circuit diagram shown in FIG, n connectors 10 are included, and the plate lines in each connector 10 are represented as PL1 to PLn, where 1 to n represent the plate line numbers, so as to easily identify which connector 10 each plate line corresponds to. Figures 4 to 6 For convenience, PL is used to represent the plate line. Similarly, the bit lines in each connecting body 10 are represented as BL1 to BLn, 1 to n are the numbers of the bit lines, so that it is easy to distinguish which connecting body 10 each bit line corresponds to. Figures 4 to 6 For convenience, BL is used to represent the bit line. The gate control lines in each connection body 10 are represented as KL1 to KLn, 1 to n represent the number of the gate control line, so that it is easy to distinguish which connection body 10 each gate control line corresponds to. Figures 4 to 6 For convenience, KL is used to represent the gate control line. When each connection body 10 includes m memory cells, the word lines are represented as WL1 to WLm, where 1 to m represent the word line numbers, so that each word line corresponds to which memory cell. Figures 4 to 6 For convenience, WL is used to represent word line.

[0070] Figure 8 and Figure 9 A schematic diagram of another storage array structure according to an embodiment of the present application is shown. Figure 8 and Figure 9 As shown, the structure of the storage array provided in this embodiment is similar to that in the aforementioned embodiment. Figures 4 to 7 The structure of the memory array in any of the embodiments shown is basically similar, except that the connector may further include a reset transistor M2. Figure 8 As shown, Figure 8 (a) is a three-dimensional schematic diagram of a storage array using two connectors as an example. Figure 8 (b) is a cross-sectional view of the reset transistor M2. The connector may further include a reset control line XL and a reset channel 17. The reset channel 17 and the bit line BL are stacked along the third direction. The first end of the reset channel 17 (eg Figure 8 The lower end of the reset channel 17 shown in FIG) is connected to the bit line BL, and the second end of the reset channel 17 (as shown in FIG) is connected to the bit line BL. Figure 8The upper end of the reset channel 17 shown in FIG is connected to the plate line PL; the reset control line XL is insulated from the reset channel 17; the reset channel 17, the reset control line XL, a portion of the plate line PL, and a portion of the bit line BL form the reset transistor M2. Figure 9 In the circuit diagram shown, taking the top connector as an example, when the reset transistor M2 is turned on, the plate line PL and the bit line BL are short-circuited, making the voltages on the plate line PL and the bit line BL the same. When each access transistor M0 is turned on, the voltages across each storage capacitor C0 can be made the same, thereby releasing the voltage at the connection node A between the access transistor M0 and the storage capacitor C0, eliminating crosstalk, and improving the accuracy of data storage and reading while increasing storage density, thereby improving the performance of the memory array. It should be understood that in order to simplify the structure, Figure 9 Only one connection node A is shown in the figure, but in actual situations, each storage unit includes a connection node A.

[0071] Continue to refer to Figure 8 As shown, the reset control line XL and the word line WL can be set in the same layer, that is, the reset control line XL and the word line WL are located in the same layer. In this way, the space in the film layer where the word line WL is located can be fully utilized to set the reset control line XL, which is beneficial to reducing the height of the connector 10 and increasing the stacking density of the connector 10, thereby increasing the storage density of the memory array.

[0072] Furthermore, the reset control line XL includes a second through-hole T2 extending along a third direction (i.e., the z-direction). The reset channel 17 passes through the second through-hole T2, allowing the reset control line XL to surround the reset channel 17. This helps reduce the structural interference of the reset control line XL with the word line WL, bit line BL, and plate line PL. Furthermore, a second insulating layer 18 is provided between the reset control line XL and the reset channel 17. This second insulating layer 18 physically isolates the reset channel 17 from the reset control line XL, thereby achieving insulation between the reset control line XL and the reset channel 17. It should be understood that the second insulating layer 18 can also be considered to be located within the second through-hole T2.

[0073] In addition, for two adjacent connecting bodies in the same layer, the reset control lines XL in the two connecting bodies are connected, which can reduce the number of reset control lines XL in the memory array and simplify the structure of the memory array.

[0074] It should be understood that the storage array in this embodiment is similar to the above embodiment. Figures 4 to 7 For similarities in the structure of the storage array in any of the embodiments shown, reference can be made to the relevant introduction in the aforementioned embodiments, and repeated details will not be repeated.

[0075] Figure 10 、 Figure 11(a) to Figure 11(k)A flowchart of a method for manufacturing a storage array according to an embodiment of the present application is shown as an example. Figure 10 、 Figure 11(a) to Figure 11(k) As shown, the manufacturing method of the storage array may include:

[0076] S1001, forming a bit line on a substrate;

[0077] The specific implementation process of S1001 may include: step 1.1, referring to Figure 11(a), using but not limited to silicon nitride material and silicon oxide material, sequentially forming a silicon nitride layer and a silicon oxide layer on the substrate; step 1.2, etching the silicon oxide layer and a portion of the silicon nitride layer to form a first trench extending along the x-direction; step 1.3, using but not limited to TiN material to deposit a TiN layer, so that the sidewalls of the first trench, the bottom of the first trench, and the silicon oxide layer are covered with TiN; step 1.4, using but not limited to dry etching, etching the TiN layer, so that the TiN layer at the bottom of the first trench and the silicon oxide layer are etched away, leaving only the TiN layer on the sidewalls of the first trench, at this time, the TiN layer on each sidewall of the first trench is a bit line, obtaining the structure shown in Figure 11(b); step 1.5, using an etching process to remove the silicon oxide layer to expose the silicon nitride layer.

[0078] It should be understood that the implementation process of S1001 is not limited to the above process, and can also be other production processes that can implement S1001. The specific settings can be made according to actual needs and are not limited here.

[0079] S1002, forming a storage layer on the substrate having the bit lines formed thereon;

[0080] The specific implementation process of S1002 may include, as shown in FIG11( c ), depositing a ferroelectric layer using, but not limited to, a ferroelectric material. The ferroelectric layer serves as a storage layer, and the storage layer covers the bit lines and the exposed silicon nitride layer. The ferroelectric material may be, but is not limited to, a hafnium-based ferroelectric material or other ferroelectric materials, which are not specifically limited herein.

[0081] S1003, forming a plurality of spaced-apart side electrodes on the storage layer; wherein the side electrodes are arranged along a first direction on opposite sides of the bit line, and the side electrodes on the same side of the bit line are arranged along a second direction, the first direction intersects the second direction, and the bit line extends along the second direction; the side electrodes, the storage layer corresponding to the side electrodes, and the bit line corresponding to the side electrodes form a storage capacitor;

[0082] The specific implementation process of S1003 may include: step 3.1, using but not limited to TiN material to deposit a TiN layer, so that the TiN layer covers the storage layer; step 3.2, using but not limited to dry etching, etching the TiN layer, retaining only the TiN layer on the side, and etching away the TiN layer in other positions, to obtain the structure shown in Figure 11 (d); step 3.3, depositing silicon oxide material, and filling the gaps between the TiN layers with silicon oxide material; step 3.4, using but not limited to dry etching, etching the filled silicon oxide material to etch out pores extending along the y direction, and exposing the TiN layer on the side in the pores; The TiN layer on the exposed side is etched by, but not limited to, wet etching to obtain a plurality of side electrodes arranged along the x-direction, thereby obtaining the structure shown in FIG11(e); it should be noted that in order to clearly illustrate the side electrodes in FIG11(e), the filled silicon oxide material is not shown; in step 3.5, the gaps are filled by, but not limited to, silicon oxide material to form a silicon oxide layer, and the side electrodes, storage layer and bit lines are all embedded in the silicon oxide layer; in step 3.6, the upper surface of the silicon oxide layer is chemically polished to expose the ferroelectric layer and the top of the side electrode; thereafter, a silicon nitride layer and a silicon oxide layer are sequentially deposited to obtain the structure shown in FIG11(f).

[0083] It should be understood that the implementation process of S1003 is not limited to the above process, and can also be other production processes that can implement S1003. The specific settings can be made according to actual needs and are not limited here.

[0084] S1004, forming an access channel on each side electrode; wherein a first end of the access channel is connected to the corresponding side electrode; the access channel and the side electrode are stacked correspondingly along a third direction, and the third direction is perpendicular to the first direction and the second direction respectively;

[0085] The specific implementation process of S1004 may include: step 4.1, etching the silicon oxide layer, silicon nitride layer and silicon oxide layer arranged from top to bottom in FIG11(f) to form a plurality of channels, each channel exposing the side electrode; step 4.2, using but not limited to polysilicon material, depositing polysilicon into each channel so that the polysilicon fills each channel; then performing chemical polishing to grind off the polysilicon layer above the top silicon oxide layer to avoid the polysilicon material in each channel from being connected, and the polysilicon column formed by the polysilicon material in the channel is connected to each other. The side electrodes are connected correspondingly, so the polysilicon pillars can be used as access channels to obtain the structure shown in Figure 11(g); Step 4.3, the top silicon oxide layer is etched away to expose the silicon nitride layer and a portion of each polysilicon pillar to obtain the structure shown in Figure 11(h); Step 4.4, an insulating material and a first conductive material are deposited in sequence so that the insulating material covers the exposed silicon nitride layer and the exposed polysilicon pillars, and the first conductive material covers the insulating material; wherein the insulating material serves as the first insulating layer, and the first conductive material can be used to make word lines.

[0086] It should be understood that the implementation process of S1004 is not limited to the above process, and can also be other production processes that can implement S1004. The specific settings can be made according to actual needs and are not limited here.

[0087] S1005, forming word lines and plate lines respectively, wherein the word lines are insulated from the access channels; the second end of each access channel is connected to the plate line; the access channel, the word line, part of the plate line, and the corresponding side electrodes form an access transistor.

[0088] The specific implementation process of S1005 may include: step 5.1, using silicon oxide material to fill the gaps between the polysilicon pillars to form a silicon oxide layer that wraps the polysilicon pillars; then, etching the silicon oxide layer to form a second groove along the y direction, exposing the first conductive material located on the silicon nitride layer in the second groove; etching the first conductive material to form a plurality of conductive portions spaced apart, each conductive portion can be regarded as a word line, to obtain the structure shown in FIG11(i); step 5.2, using silicon oxide material to fill the second groove, and chemically polishing the silicon oxide material on the top to expose the top of the polysilicon pillar; step 5.3, since the first conductive material is deposited in the above step 4.4, the first conductive material is The material and the insulating material will cover the top of the polysilicon column, so the insulating material and the first conductive material on the top of the polysilicon column can be etched to expose the polysilicon, and the first conductive material can be etched away more to obtain the structure shown in Figure 11(j), which only shows the structure of part of the polysilicon column and the word line; Step 5.4, use silicon oxide material to fill the gap left after etching, and chemically polish the silicon oxide material on the top to expose the top of the polysilicon column; then continue to deposit the second conductive material, and pattern the second conductive material to obtain a plurality of plate lines, each plate line is connected to the top of the corresponding access channel, and the plate line and the word line are insulated by the silicon oxide material, to obtain the structure shown in Figure 11(k).

[0089] It should be understood that the implementation process of S1005 is not limited to the above process, and can also be other production processes that can implement S1005. The specific settings can be made according to actual needs and are not limited here.

[0090] The memory array produced by the above method can not only realize the three-dimensional stacking of access transistors and storage capacitors, improve storage density and storage capacity, but can also be implemented based on mature process technology and has high feasibility.

[0091] In another method for manufacturing a memory array according to an embodiment of the present application, the manufacturing method in this embodiment is the same as that in the aforementioned embodiment. Figure 10 、 Figure 11(a) to Figure 11(k) The production methods shown are basically similar, with the following differences:

[0092] 1. In the aforementioned embodiment Figure 10 、 Figure 11(a) to Figure 11(k) In step 5.1 of the manufacturing method shown, a reset control line can also be formed when forming the word line, that is, among the conductive parts formed, some conductive parts are used to form the word line, and some conductive parts are used to form the reset control line.

[0093] 2. In the aforementioned embodiment Figure 10 、 Figure 11(a) to Figure 11(k)In step 4.2 of the manufacturing method shown, a reset channel can also be formed when forming the access channel; that is: among the formed channels, part of the channels expose the bit lines, and the polysilicon material filled in these channels that expose the bit lines can form the reset channel, and part of the channels expose the side electrodes, and the polysilicon material filled in these channels that expose the side electrodes can form the access channel.

[0094] It should be understood that the manufacturing method of the storage array in this embodiment is similar to that in the previous embodiment. Figure 10 、 Figure 11(a) to Figure 11(k) The similarities of the manufacturing method of the memory array shown can be found in the related introduction of the aforementioned embodiment, and the repeated parts will not be repeated here.

[0095] In another method for manufacturing a memory array according to an embodiment of the present application, the manufacturing method in this embodiment is the same as that in the aforementioned embodiment. Figure 10 、 Figure 11(a) to Figure 11(k) The production methods shown are basically similar, with the following differences:

[0096] 1. In the aforementioned embodiment Figure 10 、 Figure 11(a) to Figure 11(k) In step 5.1 of the manufacturing method shown, when forming the word line, the gate control line can also be formed, that is, among the conductive parts formed, some conductive parts are used to form the word line, and some conductive parts are used to form the gate control line.

[0097] 2. In the aforementioned embodiment Figure 10 、 Figure 11(a) to Figure 11(k) In step 4.2 of the manufacturing method shown, when forming the access channel, a partial structure in the selection channel can also be formed; that is: in each channel formed, part of the channel exposes the bit line, and the polysilicon material filled in these channels that expose the bit line can form a partial structure in the selection channel, and part of the channel exposes the side electrode, and the polysilicon material filled in these channels that expose the side electrode can form the access channel.

[0098] 3. In the aforementioned embodiment Figure 10 、 Figure 11(a) to Figure 11(k)In step 5.4 of the manufacturing method shown, during patterning, the tops of some polysilicon pillars are connected to the plate lines, and the tops of the remaining polysilicon pillars are exposed and not connected to the plate lines; then, silicon oxide material is deposited to form a silicon oxide layer to cover each plate line, and the silicon oxide layer is etched to obtain multiple holes, which expose the tops of the polysilicon pillars not connected to the plate lines, and polysilicon material is deposited to fill the holes. Then, chemical polishing is used to remove the polysilicon material on the silicon oxide layer, so that the polysilicon pillars not connected to the plate lines are disconnected from each other. At this time, the polysilicon pillars not connected to the plate lines form a selection channel; thereafter, a third conductive material is deposited and patterned to obtain a bit line auxiliary line, and the bit line auxiliary line is connected to the top of the selection channel.

[0099] It should be understood that the manufacturing method of the storage array in this embodiment is similar to that in the previous embodiment. Figure 10 、 Figure 11(a) to Figure 11(k) The similarities of the manufacturing method of the memory array shown can be found in the related introduction of the aforementioned embodiment, and the repeated parts will not be repeated here.

[0100] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include such modifications and variations.

Claims

1. A storage array, characterized in that: including connectors; The connector includes: a bit line and a plurality of spaced-apart side electrodes, wherein the side electrodes are arranged on opposite sides of the bit line along a first direction, and the side electrodes on the same side of the bit line are arranged along a second direction, the first direction intersects the second direction, and the bit line extends along the second direction; a storage layer is provided between the bit line and each of the side electrodes; the side electrodes, the storage layer corresponding to the side electrodes, and the bit line corresponding to the side electrodes form a storage capacitor; The connector further includes: a plate line, a word line, and a plurality of access channels arranged at intervals, wherein each of the access channels is stacked correspondingly with each of the side electrodes along a third direction, wherein the third direction is perpendicular to the first direction and the second direction, respectively; a first end of the access channel is connected to the corresponding side electrode, and a second end of each of the access channels is connected to the plate line; the word line is insulated from the access channel; the access channel, the word line, a portion of the plate line, and the corresponding side electrode form an access transistor.

2. The storage array according to claim 1, wherein: The word line, the plate line and the bit line are arranged along the third direction, and the word line is located between the plate line and the bit line. The word line has a first through hole penetrating along the third direction, and the access channel passes through the first through hole.

3. The storage array according to claim 1 or 2, wherein: The connector further includes: a reset control line and a reset channel, wherein the reset channel and the bit line are stacked along the third direction, a first end of the reset channel is connected to the bit line, and a second end of the reset channel is connected to the plate line; the reset control line is insulated from the reset channel; The reset channel, the reset control line, a portion of the plate line, and a portion of the bit line form a reset transistor.

4. The storage array according to claim 3, wherein: The reset control line has a second through hole extending along the third direction, and the reset channel passes through the second through hole.

5. The storage array according to claim 3 or 4, wherein: The reset control line and the word line are arranged in the same layer.

6. The storage array according to any one of claims 1 to 5, wherein: There are multiple connectors, and at least some of the connectors are arranged in the same layer and in parallel; The word lines in two adjacent connectors in the same layer are connected correspondingly.

7. The storage array according to claim 6, wherein: The connector further includes: a bit line auxiliary line, a gate control line, and a gate channel, wherein the gate channel and the bit line are stacked along the third direction, a first end of the gate channel is connected to the bit line, and a second end of the gate channel is connected to the bit line auxiliary line; the bit line auxiliary line and the gate control line are arranged in different layers; and the gate control line is insulated from the gate channel; The gate channel, the gate control line, a portion of the bit line, and the bit line auxiliary line form a gate transistor.

8. The storage array according to claim 7, wherein: The bit line auxiliary lines of the connectors are connected, and the bit line auxiliary lines are respectively arranged in different layers from the bit lines, the word lines, and the plate lines.

9. The storage array according to claim 7 or 8, wherein: The gate control line and the word line are arranged in the same layer.

10. A memory, characterized in that: include: The storage array according to any one of claims 1 to 9, and a controller; wherein the storage array is electrically connected to the controller.

11. An electronic device, characterized in that: include: The memory according to claim 10, and a circuit board; the memory is electrically connected to the circuit board.

12. A method for manufacturing a storage array, characterized in that: include: forming a bit line over the substrate; forming a memory layer on the substrate having the bit lines formed thereon; A plurality of spaced-apart side electrodes are formed on the storage layer; wherein the side electrodes are arranged on opposite sides of the bit line along a first direction, and the side electrodes on the same side of the bit line are arranged along a second direction, the first direction intersects the second direction, and the bit line extends along the second direction; the side electrodes, the storage layer corresponding to the side electrodes, and the bit line corresponding to the side electrodes form a storage capacitor; An access channel is formed on each of the side electrodes; wherein a first end of the access channel is connected to the corresponding side electrode; the access channel and the side electrode are stacked correspondingly along a third direction, and the third direction is perpendicular to the first direction and the second direction respectively; A word line and a plate line are formed respectively, wherein the word line is insulated from the access channel; the second end of each access channel is connected to the plate line; the access channel, the word line, part of the plate line, and the corresponding side electrode form an access transistor.

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