Manufacturing method of semiconductor structure and MRAM (Magnetic Random Access Memory)

Abstract

The invention provides a manufacturing method of a semiconductor structure and an MRAM (Magnetic Random Access Memory). The method comprises the following steps: providing a substrate; forming a plurality of MTJ structures arranged at intervals on the exposed surface of the substrate; forming a first initial preparation protection layer and a second initial preparation protection layer which are sequentially superposed on the surfaces and the side surfaces, far away from the substrate, of the MTJ structures; removing part of the second initial preparation protection layer, at least enabling the surface, away from the substrate, of the first initial preparation protection layer to be exposed, and obtaining a plurality of preparation grooves; removing a part of the first initial preparation protection layer along the preparation groove, at least enabling the surface, away from the substrate, of each MTJ structure to be exposed, and obtaining a plurality of grooves; and filling each groove with a first metal material to obtain a plurality of top electrodes. The problem that in the prior art, due to the fact that a top conductive through hole alignment window is narrow in the MRAM preparation process, through hole offset is likely to occur, and the device performance is affected is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a semiconductor structure and an MRAM (Magnetic Random Access Memory). Background Art

[0002] Magnetic random access memory (MRI) is a new type of non-volatile memory with the advantages of high-speed reading and writing, long endurance and low power consumption.

[0003] The existing mainstream MRAM preparation scheme has a narrow top conductive via alignment window, which is prone to via offset and affects device performance. Summary of the Invention

[0004] The main purpose of the present application is to provide a method for manufacturing a semiconductor structure and an MRAM, so as to at least solve the problem in the prior art of preparing MRAM that, due to the narrow alignment window of the top conductive via, via offset is prone to occur, which affects the device performance.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate; forming a plurality of spaced MTJ (Magnetic tunnel junction) structures on an exposed surface of the substrate; forming a first initial preliminary protective layer and a second initial preliminary protective layer stacked in sequence on the surfaces and sides of the plurality of MTJ structures away from the substrate, wherein the materials of the first initial preliminary protective layer and the second initial preliminary protective layer are different; removing a portion of the second initial preliminary protective layer to expose at least the surface of the first initial preliminary protective layer away from the substrate, thereby obtaining a plurality of spaced preliminary grooves, and the remaining second initial preliminary protective layer forms a second preliminary protective layer; removing a portion of the first initial preliminary protective layer along the preliminary grooves to expose at least the surface of each MTJ structure away from the substrate, thereby obtaining a plurality of spaced grooves, and the remaining first initial preliminary protective layer forms a first preliminary protective layer; filling a first metal material in each of the grooves to obtain a plurality of spaced top electrodes.

[0006] Optionally, after obtaining a plurality of spaced-apart top electrodes, the method further includes: sequentially removing a portion of the second preliminary protective layer and a portion of the first preliminary protective layer between each of the MTJ structures to expose a portion of the substrate, thereby obtaining a plurality of spaced-apart second protective layers and a first protective layer.

[0007] Optionally, removing part of the second initial preliminary protective layer includes: using a first self-aligned etching process to etch the second initial preliminary protective layer, the etching gas of the first self-aligned etching process includes at least one of fluorine-containing gas, Cl2, BCl3, Ar and HBr, and removing part of the first initial preliminary protective layer along the preliminary groove, including: using a second self-aligned etching process to etch the first initial preliminary protective layer from the preliminary groove, the etching gas of the second self-aligned etching process includes fluorine-containing gas, and removing part of the second preliminary protective layer and part of the first preliminary protective layer between each of the MTJ structures in sequence, including: using a third self-aligned etching process to etch part of the second preliminary protective layer and part of the first preliminary protective layer between each of the MTJ structures in sequence, the etching gas of the third self-aligned etching process includes at least one of fluorine-containing gas, Cl2, BCl3, Ar and HBr.

[0008] Optionally, after forming a first initial preliminary protective layer and a second initial preliminary protective layer stacked in sequence on the surface and side of the multiple MTJ structures away from the substrate, and before removing part of the second initial preliminary protective layer and part of the first initial preliminary protective layer in sequence, the method also includes: forming a first dielectric layer on the surface of the second initial preliminary protective layer away from the substrate.

[0009] Optionally, ES de >ES dc , ES de >1, ES ce >ES cb , ES ce >1, among which ES de It represents the ratio of the etching rate of the first dielectric layer to the etching rate of the top electrode under the same etching conditions, ES dc It represents the ratio of the etching rate of the first dielectric layer to the etching rate of the second preliminary protective layer under the same etching conditions, ES ce It represents the ratio of the etching rate of the second preliminary protective layer to the etching rate of the top electrode under the same etching conditions, ES cb It represents the ratio of the etching rate of the second preliminary protective layer to the etching rate of the first preliminary protective layer under the same etching conditions.

[0010] Optionally, a first dielectric layer is formed on the surface of the second initial preliminary protective layer away from the substrate, including: forming a preliminary dielectric layer on the surface of the second initial preliminary protective layer away from the substrate; using a planarization process to remove part of the preliminary dielectric layer so that the surface of the remaining preliminary dielectric layer away from the substrate is flat, and the remaining preliminary dielectric layer forms the first dielectric layer.

[0011] Optionally, a first metal material is filled in each of the grooves to obtain a plurality of spaced-apart top electrodes, including: filling the first metal material in each of the grooves to obtain a preliminary top electrode; using a planarization process to remove part of the preliminary top electrode so that the first dielectric layer is exposed away from the surface of the substrate, and the remaining preliminary top electrodes form a plurality of spaced-apart top electrodes.

[0012] Optionally, a portion of the second initial preliminary protective layer is removed to expose at least the surface of the first initial preliminary protective layer away from the substrate, including: removing a portion of the second initial preliminary protective layer to expose the surface and a portion of the side of the first initial preliminary protective layer away from the substrate, and removing a portion of the first initial preliminary protective layer along the preliminary groove to expose at least the surface of each MTJ structure away from the substrate, including: removing a portion of the first initial preliminary protective layer along the preliminary groove to expose the surface and a portion of the side of each MTJ structure away from the substrate.

[0013] Optionally, after obtaining a plurality of top electrodes spaced apart from each other, the method further comprises: forming top metal connections on surfaces of the top electrodes away from the substrate in a one-to-one correspondence.

[0014] According to another aspect of the present application, an MRAM is provided, comprising: a semiconductor structure manufactured by any of the above-mentioned methods for manufacturing a semiconductor structure.

[0015] Applying the technical solution of the present application, first a substrate is provided, and a plurality of spaced MTJ structures are formed on the exposed surface of the substrate. Then, a first initial preliminary protective layer and a second initial preliminary protective layer of different materials are stacked in sequence on the surfaces and sides of the plurality of MTJ structures away from the substrate. Then, part of the second initial preliminary protective layer is removed to expose at least the surface of the first initial preliminary protective layer away from the substrate to obtain a plurality of preliminary grooves. The remaining second initial preliminary protective layer forms a second preliminary protective layer. Then, part of the first initial preliminary protective layer is removed from the preliminary grooves to expose at least the surface of each MTJ structure away from the substrate to obtain a plurality of grooves. The remaining first initial preliminary protective layer forms a first preliminary protective layer. Finally, a first metal material is filled in each groove to obtain a plurality of spaced top electrodes. Compared with the problem in the prior art of preparing MRAM, in which the top conductive through-hole alignment window is narrow, resulting in the phenomenon that through-hole offset affects the performance of the device, the present application forms a first initial preliminary protective layer and a second initial preliminary protective layer stacked in sequence on the surface and side of multiple MTJ structures away from the substrate, removes part of the second initial preliminary protective layer, at least exposing the surface of the first initial preliminary protective layer away from the substrate, ensuring that the width of the obtained preliminary groove is larger than the width of the MTJ structure, and then removes part of the first initial preliminary protective layer from the preliminary groove, at least exposing the surface of each MTJ structure away from the substrate, ensuring that the width of the final groove is larger than the width of the MTJ structure, thereby ensuring that the window of the obtained top electrode is larger, that is, the top interconnect metal alignment window is larger, and when the top metal connection is subsequently made, the lithography overlay accuracy window is larger, ensuring that the offset range of the through-hole offset is larger, and ensuring better performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0017] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application is shown;

[0018] Figures 2 to 14 A schematic structural diagram of the semiconductor structure manufacturing method according to the present application after each process step is shown.

[0019] The above drawings include the following reference numerals:

[0020] 10. Substrate; 11. Second dielectric layer; 12. Bottom metal connection; 13. Bottom metal barrier layer; 14. Third dielectric layer; 131. Bottom metal via; 15. Prepared bottom electrode; 16. Prepared MTJ stack layer; 17. Prepared mask layer; 18. Mask layer; 19. MTJ stack layer; 20. Bottom electrode; 21. First initial prepared protective layer; 22. Second initial prepared protective layer; 23. First dielectric layer; 24. Prepared groove; 25. Second prepared protective layer; 26. Groove; 27. First prepared protective layer; 28. Prepared top electrode; 29. ​​Top electrode; 30. Second protective layer; 31. First protective layer; 32. Top metal connection; 33. MTJ structure. DETAILED DESCRIPTION

[0021] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0022] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0023] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element or intervening elements may be present. Moreover, in the specification and claims, when it is described that an element is "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

[0024] As described in the background, in the prior art, during the preparation of MRAM, due to the narrow alignment window of the top conductive via, via offset is prone to occur, which affects device performance. To address the above problem, embodiments of the present application provide a method for manufacturing a semiconductor structure and an MRAM.

[0025] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0026] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application. Figure 1 As shown, the method includes the following steps:

[0027] Step S201, providing a substrate;

[0028] Step S202, as Figure 3 As shown, a plurality of MTJ structures 33 spaced apart are formed on the exposed surface of the substrate;

[0029] Step S203, as Figure 3 As shown, a first initial preliminary protective layer 21 and a second initial preliminary protective layer 22 are sequentially stacked on the surface and side of the plurality of MTJ structures 33 away from the substrate, and the materials of the first initial preliminary protective layer 21 and the second initial preliminary protective layer 22 are different;

[0030] Specifically, the second initial preliminary protective layer can be a single-layer film structure or a laminated structure. Similarly, the first initial preliminary protective layer can be a single-layer film structure or a laminated structure. In actual application, those skilled in the art can flexibly set the specific structures of the first initial preliminary protective layer and the second initial preliminary protective layer according to actual needs, and this application does not impose specific restrictions on this. In one embodiment of the present application, the first initial preliminary protective layer and the second initial preliminary protective layer are respectively single-layer film structures.

[0031] Step S204, as Figure 4 and Figure 5 As shown, a portion of the second initial preliminary protective layer 22 is removed to expose at least the surface of the first initial preliminary protective layer 21 away from the substrate, thereby obtaining a plurality of spaced preliminary grooves 24 , and the remaining second initial preliminary protective layer 22 forms a second preliminary protective layer 25 ;

[0032] Specifically, at least the surface of the first initial preliminary protective layer away from the substrate is exposed, including: exposing the surface of the first initial preliminary protective layer away from the substrate and exposing the surface and part of the side surface of the first initial preliminary protective layer away from the substrate.

[0033] Step S205, as Figure 5 and Figure 6 As shown, a portion of the first initial preliminary protective layer 21 is removed along the preliminary groove 24 to expose at least the surface of each MTJ structure 33 away from the substrate, thereby obtaining a plurality of grooves 26 spaced apart. The remaining first initial preliminary protective layer 21 forms a first preliminary protective layer 27.

[0034] Specifically, at least exposing the surface of each MTJ structure away from the substrate includes: exposing the surface of each MTJ structure away from the substrate and exposing the surface and part of the side surface of each MTJ structure away from the substrate.

[0035] Step S206, as Figure 8 As shown, the first metal material is filled in each of the above grooves to obtain a plurality of top electrodes 29 arranged at intervals.

[0036] Filling techniques include, but are not limited to, CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), and ECP (Electro Chemical Plating).

[0037] Through the above embodiments, a substrate is first provided, and a plurality of spaced MTJ structures are formed on the exposed surface of the substrate. Then, a first initial preliminary protective layer and a second initial preliminary protective layer of different materials stacked in sequence are formed on the surfaces and sides of the plurality of MTJ structures away from the substrate. Then, part of the second initial preliminary protective layer is removed, so that at least the surface of the first initial preliminary protective layer away from the substrate is exposed, thereby obtaining a plurality of preliminary grooves. The remaining second initial preliminary protective layer forms a second preliminary protective layer. Then, part of the first initial preliminary protective layer is removed from the preliminary grooves, so that at least the surface of each MTJ structure away from the substrate is exposed, thereby obtaining a plurality of grooves. The remaining first initial preliminary protective layer forms a first preliminary protective layer. Finally, a first metal material is filled in each groove to obtain a plurality of spaced top electrodes. Compared with the problem in the prior art of preparing MRAM, in which the top conductive through-hole alignment window is narrow, resulting in the phenomenon that through-hole offset affects the performance of the device, the present application forms a first initial preliminary protective layer and a second initial preliminary protective layer stacked in sequence on the surface and side of multiple MTJ structures away from the substrate, removes part of the second initial preliminary protective layer, at least exposing the surface of the first initial preliminary protective layer away from the substrate, ensuring that the width of the obtained preliminary groove is larger than the width of the MTJ structure, and then removes part of the first initial preliminary protective layer from the preliminary groove, at least exposing the surface of each MTJ structure away from the substrate, ensuring that the width of the final groove is larger than the width of the MTJ structure, thereby ensuring that the window of the obtained top electrode is larger, that is, the top interconnect metal alignment window is larger, and when the top metal connection is subsequently made, the lithography overlay accuracy window is larger, ensuring that the offset range of the through-hole offset is larger, and ensuring better performance of the device.

[0038] In addition, due to the presence of the double protective layers of the first preliminary protective layer and the second preliminary protective layer, even if the top metal connection with a large etching offset is over-etched in the subsequent etching, it will not affect the MTJ structure; at the same time, it ensures that the distance between the MTJ structure and the top metal connection is relatively far. During the subsequent operation of the semiconductor structure, the current interference between the internal MTJ structure and the top metal connection is relatively small, ensuring better performance of the device.

[0039] Specifically, the material of the above-mentioned first initial preliminary protective layer is a dielectric material, and the above-mentioned dielectric material includes but is not limited to nitrogen-doped carbide (NDC), SiN, SiO2, SiON, SiCN and SiOC. The material of the above-mentioned second initial preliminary protective layer can be the above-mentioned dielectric material or a second metal material, and the above-mentioned second metal material includes but is not limited to Ru, TiN, TaN, Ta and Al2O3.

[0040] like Figure 3 As shown, the thickness between the surface of the first initial preliminary protective layer 21 away from the substrate and the surface of the MTJ structure 33 away from the substrate is H1, the width of the first initial preliminary protective layer 21 away from the substrate is W1, and the width is the length in the thickness direction perpendicular to the substrate. The thickness between the surface of the second initial preliminary protective layer 22 away from the substrate and the surface of the first initial preliminary protective layer 21 away from the substrate is H2, and the width of the second initial preliminary protective layer 22 away from the substrate is W2, W2>W1. Specifically,

[0041] like Figure 5 As shown, the depth between the opening of the preliminary groove 24 and the surface of the first initial preliminary protective layer 21 away from the substrate is H3, the maximum width of the preliminary groove 24 is W3, and the direction of the depth is parallel to the thickness of the substrate. Specifically, W3=W2.

[0042] like Figure 5 and Figure 6 As shown, the depth between the opening of the groove 26 and the surface of the MTJ structure 33 away from the substrate minus H3 is H4, and the maximum width of the groove 26 located on the surface of the MTJ structure 33 away from the substrate and the surface of the first preliminary protection layer 27 away from the substrate is W4. Specifically, W4=W1.

[0043] Specifically, each of the above-mentioned grooves is filled with the above-mentioned first metal material; the above-mentioned first metal material includes but is not limited to Al, TiAl, Cu, TiN, TaN, Ta, W, CoWP and a combination material, and the above-mentioned combination material is an alloy composed of Cu, TiN, TaN, Ta and W.

[0044] In an optional solution, the material of the second preliminary protective layer includes the second metal material. After obtaining a plurality of top electrodes spaced apart, the method further includes: Figure 8 and Figure 9 As shown, portions of the second preliminary protective layer 25 and the first preliminary protective layer 27 between the MTJ structures 33 are sequentially removed to expose portions of the substrate, thereby obtaining a plurality of spaced second protective layers 30 and first protective layers 31. In this embodiment, portions of the second preliminary protective layer and the first preliminary protective layer between the MTJ structures are sequentially removed to expose portions of the substrate, thereby obtaining a plurality of spaced second protective layers and first protective layers. By removing portions of the preliminary protective layer between the MTJ structures, it is ensured that the MTJ structures are not affected or interfered with each other, thereby further ensuring better performance of the device.

[0045] Specifically, when the material of the above-mentioned second preliminary protective layer includes the above-mentioned second metal material, part of the above-mentioned second preliminary protective layer and part of the above-mentioned first preliminary protective layer between each of the above-mentioned MTJ structures are removed in sequence to ensure that the various MTJ structures are not affected or interfered with each other; when the material of the above-mentioned second preliminary protective layer does not include the above-mentioned second metal material, it can be removed or not.

[0046] In other embodiments, Figure 2 As shown, the base includes a substrate 10, a second dielectric layer 11, a bottom metal connection 12 located in the second dielectric layer 11, a bottom metal barrier layer 13, a third dielectric layer 14, and a bottom metal via 131 penetrating the third dielectric layer 14 and the bottom metal barrier layer 13, which are stacked in sequence. The surface of the bottom metal connection 12 away from the substrate 10 is flush with the surface of the second dielectric layer 11 away from the substrate 10, the surface of the bottom metal connection 12 close to the substrate 10 is flush with the surface of the second dielectric layer 11 close to the substrate 10, the surface of the bottom metal via 131 away from the substrate 10 is flush with the surface of the third dielectric layer 14 away from the substrate 10, and the surface of the bottom metal via 131 close to the substrate 10 is flush with the surface of the bottom metal barrier layer 13 close to the substrate 10.

[0047] In other embodiments, a plurality of MTJ structures spaced apart are formed on the exposed surface of the substrate, including: Figure 2As shown, a preliminary bottom electrode 15, a preliminary MTJ stack layer 16 and a preliminary mask layer 17 are sequentially stacked on the surface of the third dielectric layer 14 away from the substrate 10; Figure 3 As shown, the above-mentioned preliminary mask layer, the above-mentioned preliminary MTJ stack layer and the above-mentioned preliminary bottom electrode are patterned in sequence, so that part of the above-mentioned third dielectric layer 14 is exposed, the remaining above-mentioned preliminary mask layer forms a plurality of spaced mask layers 18, the remaining above-mentioned preliminary MTJ stack layer forms a plurality of spaced MTJ stack layers 19, and the remaining above-mentioned preliminary bottom electrode forms a plurality of spaced bottom electrodes 20. The above-mentioned bottom electrodes 20, the above-mentioned MTJ stack layer 19 and the above-mentioned mask layer 18 correspond to each other to form the above-mentioned MTJ structure 33. In this embodiment, first, a preliminary bottom electrode, a preliminary MTJ stack layer and a preliminary mask layer are stacked in sequence on the surface of the third dielectric layer away from the substrate, and then the preliminary mask layer, the preliminary MTJ stack layer and the preliminary bottom electrode are patterned in sequence, so that part of the third dielectric layer is exposed, thereby obtaining a plurality of sequentially stacked bottom electrodes, MTJ stack layers and mask layers. By setting the mask layer, it is ensured that the MTJ stack layer is not over-etched in the subsequent process, the morphology of the MTJ stack layer is ensured to be good, and the device performance is further ensured to be good.

[0048] Specifically, a preliminary bottom electrode, a preliminary MTJ stack layer, and a preliminary mask layer are sequentially deposited on the surface of the third dielectric layer away from the substrate. Specifically, the mask layer is a hard mask, and the MTJ stack layer includes a reference layer, a tunnel layer, and a free layer sequentially stacked in a direction away from the substrate, such as Figure 2 As shown, the thickness of the preliminary mask layer 17 is H0. Specifically,

[0049] In other embodiments, a first initial preliminary protective layer and a second initial preliminary protective layer are sequentially stacked on the surface and side of the plurality of MTJ structures away from the substrate, including: Figure 3 As shown, a first initial preliminary protection layer 21 and a second initial preliminary protection layer 22 are sequentially formed on the surface of the third dielectric layer 14 away from the substrate 10 , and on the surfaces and side surfaces of the plurality of MTJ structures 33 away from the substrate 10 .

[0050] In other embodiments, removing part of the second initial preliminary protective layer includes: using a first self-aligned etching process to etch the second initial preliminary protective layer, the etching gas of the first self-aligned etching process includes at least one of fluorine-containing gas, Cl2, BCl3, Ar and HBr, removing part of the first initial preliminary protective layer along the preliminary groove, including: using a second self-aligned etching process to etch the first initial preliminary protective layer from the preliminary groove, the etching gas of the second self-aligned etching process includes fluorine-containing gas, and removing part of the second preliminary protective layer and part of the first preliminary protective layer between each of the MTJ structures in turn, including: using a third self-aligned etching process to etch part of the second preliminary protective layer and part of the first preliminary protective layer between each of the MTJ structures in turn, the etching gas of the third self-aligned etching process includes at least one of fluorine-containing gas, Cl2, BCl3, Ar and HBr. Compared with the prior art of first photolithography and then etching, in this embodiment, a first self-aligned etching process is used to etch the second initial preliminary protective layer, a second self-aligned etching process is used to etch the first initial preliminary protective layer, and a third self-aligned etching process is used to sequentially etch part of the second preliminary protective layer and part of the first preliminary protective layer between each MTJ structure, thereby ensuring that fewer masks are used in the process of manufacturing the semiconductor structure, ensuring lower process costs, ensuring shorter process time, and ensuring higher process efficiency.

[0051] Specifically, the above-mentioned fluorine-containing gases include but are not limited to CF4, CHF3, CH2F2, C4F8, C4F6, NF3 and SF6.

[0052] According to some exemplary embodiments of the present application, after forming a first initial preliminary protective layer and a second initial preliminary protective layer stacked sequentially on the surface and side of the plurality of MTJ structures away from the substrate, before sequentially removing a portion of the second initial preliminary protective layer and a portion of the first initial preliminary protective layer, the method further includes: Figure 4 As shown, a first dielectric layer 23 is formed on the surface of the second initial preliminary protective layer 22 away from the substrate. In this embodiment, the first dielectric layer is formed on the surface of the second initial preliminary protective layer away from the substrate to provide insulation and protection, thereby ensuring better performance of the resulting device.

[0053] Specifically, the first dielectric layer is deposited on a surface of the second initial preliminary protective layer away from the substrate, and the first dielectric layer and the second initial preliminary protective layer are made of different materials.

[0054] In an exemplary embodiment of the present application, ES de >ES dc , ES de >1, ESce >ES cb , ES ce >1, among which ES de It represents the ratio of the etching rate of the first dielectric layer to the etching rate of the top electrode under the same etching conditions, ES dc It represents the ratio of the etching rate of the first dielectric layer to the etching rate of the second preliminary protective layer under the same etching conditions, ES ce It represents the ratio of the etching rate of the second preliminary protective layer to the etching rate of the top electrode under the same etching conditions, ES cb represents the ratio of the etching rate of the second preliminary protective layer to the etching rate of the first preliminary protective layer under the same etching conditions. In this embodiment, by utilizing the relationship between the etching selectivities, it is ensured that the top electrode will not be removed during the sequential etching of the portion of the second preliminary protective layer and the portion of the first preliminary protective layer between the MTJ structures, thereby minimizing the possibility of accidental etching of the top electrode and ensuring a good etching effect. This further ensures a larger window for the top electrode and further ensures the good quality of the subsequent MTJ structure.

[0055] In other embodiments, ES cb >ES cd >1, ES ba >ES bd >1, ES ba >ES bc >1, among which ES cb It represents the ratio of the etching rate of the second preliminary protective layer to the etching rate of the first preliminary protective layer under the same etching conditions, ES cd It represents the ratio of the etching rate of the second preliminary protective layer to the etching rate of the first dielectric layer under the same etching conditions, ES ba It represents the ratio of the etching rate of the first preliminary protective layer to the etching rate of the mask layer under the same etching conditions, ES bd It represents the ratio of the etching rate of the first preliminary protective layer to the etching rate of the first dielectric layer under the same etching conditions, ES bc represents the ratio of the etching rate of the first preliminary protective layer to the etching rate of the second preliminary protective layer under the same etching conditions. In this embodiment, the relationship between the etching selectivities ensures that both the preliminary groove and the groove can be well etched, avoiding over-etching, ensuring a good etching effect, further ensuring a larger window for the subsequently obtained top electrode, and further ensuring good quality of the subsequent MTJ structure.

[0056] The material of the second preliminary protective layer includes the second metal material, and ES de >ES dc , ESde >1、ES ce >ES cb , ES ce >1、ES be >ES bd and ES be >1, the second preliminary protection layer and the first preliminary protection layer between the MTJ structures 33 are removed in sequence, so that part of the substrate is exposed and the top electrode 29 is not over-etched, and the following is obtained: Figure 9 The material of the second preliminary protective layer includes the second metal material and satisfies ES de >ES dc , ES de >1、ES ce >ES cb and ES ce >1, does not meet ES be >ES bd and ES be >1, the second preliminary protection layer and the first preliminary protection layer between the MTJ structures 33 are removed in sequence, so that part of the substrate is exposed and part of the top electrode 29 is over-etched, so as to obtain the following Figure 12 The structure shown. Among them, ES be It represents the ratio of the etching rate of the first preliminary protection layer to the etching rate of the top electrode under the same etching conditions.

[0057] According to other exemplary embodiments of the present application, forming a first dielectric layer on the surface of the second initial preliminary protective layer away from the substrate includes: forming a preliminary dielectric layer on the surface of the second initial preliminary protective layer away from the substrate; using a planarization process to remove a portion of the preliminary dielectric layer so that the remaining surface of the preliminary dielectric layer away from the substrate is flat, and the remaining preliminary dielectric layer forms the first dielectric layer. In this embodiment, the preliminary dielectric layer is first formed on the surface of the second initial preliminary protective layer away from the substrate, and then a planarization process is used to remove a portion of the preliminary dielectric layer, ensuring that the upper surface of the obtained first dielectric layer is flat, in preparation for the subsequent formation of the groove.

[0058] Specifically, the above-mentioned planarization process can be a back etching process, or a chemical mechanical polishing, or a combination of the back etching process and the chemical mechanical polishing process, or other processes that can make the upper surface of the first dielectric layer flat. In actual application, technical personnel in this field can flexibly select a suitable planarization process according to actual needs, and this application does not impose specific restrictions on this.

[0059] In other embodiments, the first metal material is filled in each of the above grooves to obtain a plurality of top electrodes arranged at intervals, including: Figure 7 As shown, the first metal material is filled in each of the grooves to obtain a preliminary top electrode 28; Figure 8 As shown, a planarization process is used to remove a portion of the prepared top electrode, exposing the first dielectric layer 23 away from the surface of the substrate. The remaining prepared top electrode forms a plurality of spaced top electrodes 29. In this embodiment, a first metal material is first filled into each groove to form a prepared top electrode. A planarization process is then used to remove a portion of the prepared top electrode to form a plurality of spaced top electrodes. This ensures that there is no conductive path between the obtained top electrodes, further ensuring that the MTJ structures are not interfered with or affected by each other, and further ensuring better device performance.

[0060] Specifically, the top electrode corresponds to the MTJ structure one by one.

[0061] In other embodiments, after forming a first dielectric layer on the surface of the second initial preliminary protective layer away from the substrate, and before removing a portion of the second initial preliminary protective layer, the method further includes: removing a portion of the first dielectric layer to expose the surface of the second initial preliminary protective layer away from the substrate.

[0062] In some other optional solutions of the present application, a portion of the second initial preliminary protective layer is removed to expose at least the surface of the first initial preliminary protective layer away from the substrate, including: Figure 5 As shown, a portion of the second initial preliminary protective layer is removed to expose the surface and a portion of the side surface of the first initial preliminary protective layer 21 away from the substrate, and a portion of the first initial preliminary protective layer is removed along the preliminary groove to expose at least the surface of each MTJ structure away from the substrate, including: Figure 6 As shown, a portion of the first initial preliminary protective layer is removed along the preliminary groove to expose the surface and a portion of the side surfaces of each MTJ structure 33 away from the substrate. In this embodiment, a portion of the second initial preliminary protective layer is removed to expose the surface and a portion of the side surfaces of the first initial preliminary protective layer away from the substrate, further ensuring a larger window for the preliminary groove. A portion of the first initial preliminary protective layer is removed along the preliminary groove to expose the surface and a portion of the side surfaces of each MTJ structure away from the substrate, further ensuring a larger window for the resulting groove, thereby further ensuring a larger window for the subsequent top electrode, further ensuring a larger lithography overlay accuracy window when subsequently fabricating the top metal connection, further ensuring a larger offset range for the through-hole offset, and further ensuring better device performance.

[0063] In some further optional solutions of the present application, after obtaining a plurality of top electrodes spaced apart, the above method further includes: Figure 11 and Figure 14 As shown, top metal connections 32 are formed one-to-one on the surface of the top electrode 29 away from the substrate. In this embodiment, top metal connections are formed one-to-one on the surface of the top electrode away from the substrate to prepare for the subsequent manufacture of semiconductor devices. Figure 11 is with Figure 9 The corresponding structure; Figure 14 is with Figure 12 The corresponding structure.

[0064] In other embodiments, part of the second preliminary protective layer and part of the first preliminary protective layer between each of the MTJ structures are removed in sequence to expose part of the substrate, thereby obtaining a plurality of spaced second protective layers and first protective layers, including: removing part of the second preliminary protective layer and part of the first preliminary protective layer between each of the MTJ structures in sequence to expose part of the third dielectric layer, thereby obtaining a plurality of spaced second protective layers and first protective layers; and backfilling the dielectric material at the position of the exposed third dielectric layer.

[0065] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method for manufacturing the semiconductor structure of the present application will be described in detail below with reference to specific embodiments.

[0066] This embodiment relates to a specific method for manufacturing a semiconductor structure, comprising the following steps:

[0067] Step S1: Figure 2 As shown, a substrate is provided, which includes a substrate 10, a second dielectric layer 11, a bottom metal connection 12 located in the second dielectric layer 11, a bottom metal barrier layer 13, a third dielectric layer 14, and a bottom metal via 131 penetrating the third dielectric layer 14 and the bottom metal barrier layer 13, wherein a surface of the bottom metal connection 12 away from the substrate 10 is flush with a surface of the second dielectric layer 11 away from the substrate 10, a surface of the bottom metal connection 12 close to the substrate 10 is flush with a surface of the second dielectric layer 11 close to the substrate 10, a surface of the bottom metal via 131 away from the substrate 10 is flush with a surface of the third dielectric layer 14 away from the substrate 10, and a surface of the bottom metal via 131 close to the substrate 10 is flush with a surface of the bottom metal barrier layer 13 close to the substrate 10;

[0068] Step S2: Figure 2 As shown, a preliminary bottom electrode 15, a preliminary MTJ stack layer 16 and a preliminary mask layer 17 are sequentially stacked on the surface of the third dielectric layer 14 away from the substrate 10;

[0069] Step S3: Figure 3 As shown, the preliminary mask layer, the preliminary MTJ stack layer and the preliminary bottom electrode are patterned in sequence, so that part of the third dielectric layer 14 is exposed, the remaining preliminary mask layer forms a plurality of mask layers 18 spaced apart, the remaining preliminary MTJ stack layer forms a plurality of MTJ stack layers 19 spaced apart, and the remaining preliminary bottom electrode forms a plurality of bottom electrodes 20 spaced apart. The bottom electrodes 20, the MTJ stack layer 19 and the mask layer 18 correspond to each other to form an MTJ structure 33, and a first initial preliminary protective layer 21 and a second initial preliminary protective layer 22 are sequentially formed on the surface of the third dielectric layer 14 away from the substrate 10, the surfaces of the plurality of MTJ structures 33 away from the substrate 10 and the side surfaces;

[0070] Step S4: Figure 4 As shown, a first dielectric layer 23 is formed on the surface of the second initial preliminary protection layer 22 away from the substrate 10;

[0071] Step S5: Figure 5 As shown, part of the second initial preliminary protective layer is removed so that the surface of the first initial preliminary protective layer 21 away from the substrate 10 and part of the side surface are exposed, thereby obtaining a plurality of spaced preliminary grooves 24, and the remaining second initial preliminary protective layer forms a second preliminary protective layer 25;

[0072] Step S6: Figure 6 As shown, part of the first initial preliminary protective layer is removed along the preliminary grooves to expose the surface of each mask layer 18 away from the substrate 10 and part of the side surface, thereby obtaining a plurality of grooves 26 spaced apart. The remaining first initial preliminary protective layer forms a first preliminary protective layer 27.

[0073] Step S7: Figure 7 As shown, a first metal material is filled in each groove 26 to obtain a preliminary top electrode 28;

[0074] Step S8: Figure 8 As shown, a planarization process is used to remove part of the prepared top electrode, so that the first dielectric layer 23 is exposed away from the surface of the substrate 10, and the remaining prepared top electrode forms a plurality of top electrodes 29 spaced apart;

[0075] Step S9: The material of the second preliminary protective layer includes a conductive material, and ES de >ES dc , ES de >1、ES ce >ES cb , ES ce >1、ES be >ES bd and ES be>1, the second preliminary protection layer and the first preliminary protection layer between the MTJ structures 33 are removed in sequence, so that part of the substrate is exposed and the top electrode 29 is not over-etched, and the following is obtained: Figure 9 The structure shown; the material of the second preliminary protective layer includes a conductive material and meets ES de >ES dc , ES de >1、ES ce >ES cb and ES ce >1, does not meet ES be >ES bd and ES be >1, the second preliminary protection layer and the first preliminary protection layer between the MTJ structures 33 are removed in sequence, so that part of the substrate is exposed and part of the top electrode 29 is over-etched, and the following is obtained: Figure 12 The structure shown;

[0076] Step S10: Figure 11 and Figure 14 As shown, Figure 11 and Figure 9 Correspondingly, Figure 14 and Figure 12 Correspondingly, top metal wiring 32 is formed on the surface of the top electrode 29 away from the substrate 10 in a one-to-one correspondence.

[0077] Figure 10 For Figure 9 The top view of the corresponding structure, Figure 13 For Figure 12 Top view of the corresponding structure.

[0078] An embodiment of the present application further provides an MRAM, comprising: a semiconductor structure manufactured by any of the above-mentioned semiconductor structure manufacturing methods.

[0079] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0080] 1) In the manufacturing method of the semiconductor structure of the present application, a substrate is first provided, and a plurality of spaced MTJ structures are formed on the exposed surface of the substrate. Then, a first initial preliminary protective layer and a second initial preliminary protective layer of different materials stacked in sequence are formed on the surfaces and sides of the plurality of MTJ structures away from the substrate. Then, part of the second initial preliminary protective layer is removed to expose at least the surface of the first initial preliminary protective layer away from the substrate to obtain a plurality of preliminary grooves. The remaining second initial preliminary protective layer forms a second preliminary protective layer. Then, part of the first initial preliminary protective layer is removed from the preliminary grooves to expose at least the surface of each MTJ structure away from the substrate to obtain a plurality of grooves. The remaining first initial preliminary protective layer forms a first preliminary protective layer. Finally, a first metal material is filled in each groove to obtain a plurality of spaced top electrodes. Compared with the problem in the prior art of preparing MRAM, in which the top conductive through-hole alignment window is narrow, resulting in the phenomenon that through-hole offset affects the performance of the device, the present application forms a first initial preliminary protective layer and a second initial preliminary protective layer stacked in sequence on the surface and side of multiple MTJ structures away from the substrate, removes part of the second initial preliminary protective layer, at least exposing the surface of the first initial preliminary protective layer away from the substrate, ensuring that the width of the obtained preliminary groove is larger than the width of the MTJ structure, and then removes part of the first initial preliminary protective layer from the preliminary groove, at least exposing the surface of each MTJ structure away from the substrate, ensuring that the width of the final groove is larger than the width of the MTJ structure, thereby ensuring that the window of the obtained top electrode is larger, that is, the top interconnect metal alignment window is larger, and when the top metal connection is subsequently made, the lithography overlay accuracy window is larger, ensuring that the offset range of the through-hole offset is larger, and ensuring better performance of the device.

[0081] 2) The MRAM of the present application includes a semiconductor structure manufactured by a method for manufacturing a semiconductor structure. In the manufacturing method, a substrate is first provided, and a plurality of spaced MTJ structures are formed on the exposed surface of the substrate. Then, a first initial preliminary protective layer and a second initial preliminary protective layer of different materials are stacked in sequence on the surfaces and sides of the plurality of MTJ structures away from the substrate. Then, part of the second initial preliminary protective layer is removed, so that at least the surface of the first initial preliminary protective layer away from the substrate is exposed, thereby obtaining a plurality of preliminary grooves. The remaining second initial preliminary protective layer forms a second preliminary protective layer. Then, part of the first initial preliminary protective layer is removed from the preliminary grooves, so that at least the surface of each MTJ structure away from the substrate is exposed, thereby obtaining a plurality of grooves. The remaining first initial preliminary protective layer forms a first preliminary protective layer. Finally, a first metal material is filled in each groove to obtain a plurality of spaced top electrodes. Compared with the problem in the prior art of preparing MRAM, in which the top conductive through-hole alignment window is narrow, resulting in the phenomenon that through-hole offset affects the performance of the device, the present application forms a first initial preliminary protective layer and a second initial preliminary protective layer stacked in sequence on the surface and side of multiple MTJ structures away from the substrate, removes part of the second initial preliminary protective layer, at least exposing the surface of the first initial preliminary protective layer away from the substrate, ensuring that the width of the obtained preliminary groove is larger than the width of the MTJ structure, and then removes part of the first initial preliminary protective layer from the preliminary groove, at least exposing the surface of each MTJ structure away from the substrate, ensuring that the width of the final groove is larger than the width of the MTJ structure, thereby ensuring that the window of the obtained top electrode is larger, that is, the top interconnect metal alignment window is larger, and when the top metal connection is subsequently made, the lithography overlay accuracy window is larger, ensuring that the offset range of the through-hole offset is larger, and ensuring better performance of the device.

[0082] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of MTJ structures spaced apart from each other on the exposed surface of the substrate; forming a first initial preliminary protective layer and a second initial preliminary protective layer stacked sequentially on the surface and side of the plurality of MTJ structures away from the substrate, wherein the first initial preliminary protective layer and the second initial preliminary protective layer are made of different materials; removing a portion of the second initial preliminary protective layer to expose at least the surface of the first initial preliminary protective layer away from the substrate, thereby obtaining a plurality of spaced preliminary grooves, with the remaining second initial preliminary protective layer forming a second preliminary protective layer; removing a portion of the first initial preliminary protective layer along the preliminary grooves to expose at least the surface of each MTJ structure away from the substrate, thereby obtaining a plurality of grooves arranged at intervals, and the remaining first initial preliminary protective layer forming a first preliminary protective layer; The first metal material is filled in each of the grooves to obtain a plurality of top electrodes arranged at intervals.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: After obtaining a plurality of top electrodes spaced apart from each other, the method further includes: Part of the second preliminary protection layer and part of the first preliminary protection layer between the MTJ structures are removed in sequence to expose part of the substrate, thereby obtaining a plurality of second protection layers and first protection layers that are spaced apart.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: Removing a portion of the second initial preliminary protective layer includes: The second initial preliminary protective layer is etched using a first self-aligned etching process, wherein the etching gas of the first self-aligned etching process includes at least one of a fluorine-containing gas, Cl2, BCl3, Ar, and HBr, and a portion of the first initial preliminary protective layer is removed along the prepared groove, comprising: A second self-aligned etching process is used to etch the first initial preliminary protective layer from the preliminary groove, wherein the etching gas of the second self-aligned etching process includes a fluorine-containing gas. Sequentially removing a portion of the second preliminary protection layer and a portion of the first preliminary protection layer between the MTJ structures, comprising: A third self-aligned etching process is used to sequentially etch part of the second preliminary protective layer and part of the first preliminary protective layer between each of the MTJ structures. The etching gas of the third self-aligned etching process includes at least one of fluorine-containing gas, Cl2, BCl3, Ar and HBr.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: After forming a first initial preliminary protective layer and a second initial preliminary protective layer stacked sequentially on the surfaces and side surfaces of the plurality of MTJ structures away from the substrate, and before sequentially removing a portion of the second initial preliminary protective layer and a portion of the first initial preliminary protective layer, the method further includes: A first dielectric layer is formed on a surface of the second initial preliminary protection layer away from the substrate.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: ES de >ES dc , ES de >1, ES ce >ES cb , ES ce >1, among which ES de It represents the ratio of the etching rate of the first dielectric layer to the etching rate of the top electrode under the same etching conditions, ES dc It represents the ratio of the etching rate of the first dielectric layer to the etching rate of the second preliminary protective layer under the same etching conditions, ES ce It represents the ratio of the etching rate of the second preliminary protective layer to the etching rate of the top electrode under the same etching conditions, ES cb It represents the ratio of the etching rate of the second preliminary protective layer to the etching rate of the first preliminary protective layer under the same etching conditions.

6. The method for manufacturing a semiconductor structure according to claim 4, wherein: Forming a first dielectric layer on a surface of the second initial preliminary protective layer away from the substrate comprises: forming a preliminary dielectric layer on a surface of the second initial preliminary protective layer away from the substrate; A planarization process is adopted to remove a portion of the preliminary dielectric layer, so that a surface of the remaining preliminary dielectric layer away from the substrate is planarized, and the remaining preliminary dielectric layer forms the first dielectric layer.

7. The method for manufacturing a semiconductor structure according to claim 4, wherein: Filling the first metal material in each of the grooves to obtain a plurality of top electrodes spaced apart, comprising: Filling the first metal material in each of the grooves to obtain a preliminary top electrode; A planarization process is adopted to remove part of the prepared top electrode, so that the first dielectric layer is exposed away from the surface of the substrate, and the remaining prepared top electrode forms a plurality of spaced top electrodes.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: Removing a portion of the second initial preliminary protective layer to expose at least a surface of the first initial preliminary protective layer away from the substrate comprises: removing a portion of the second initial preliminary protective layer so that the surface of the first initial preliminary protective layer away from the substrate and a portion of the side surface are exposed; Removing a portion of the first initial preliminary protection layer along the preliminary groove to expose at least a surface of each MTJ structure away from the substrate, comprising: A portion of the first initial preliminary protection layer is removed along the preliminary groove, so that a surface of each MTJ structure away from the substrate and a portion of a side surface are exposed.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: After obtaining a plurality of top electrodes spaced apart from each other, the method further includes: Top metal connections are formed on the surface of the top electrode away from the substrate in a one-to-one correspondence.

10. An MRAM, characterized in that: include: A semiconductor structure manufactured using the semiconductor structure manufacturing method according to any one of claims 1 to 9.

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