Magnetic storage device

Abstract

Provided is a magnetic memory device capable of improving operation performance. A magnetic memory device according to an embodiment includes: a memory cell including a variable resistance element and a selector element; a power supply circuit that supplies a first voltage to the memory cell; a first switch that is connected between the memory cell and the power supply circuit and that sets the memory cell and the power supply circuit to a connected state or a disconnected state; a second switch that is connected between the ground voltage node and the memory cell and sets the ground voltage node and the memory cell to a connected state or a disconnected state; a comparator that compares the voltage of the memory cell with a second voltage lower than the first voltage, and outputs a first signal when the voltage of the memory cell is lower than the second voltage; a delay circuit that delays the first signal output from the comparator for a first delay time and outputs a second signal; a sense amplifier that compares the voltage of the memory cell with a third voltage; and a third switch that is connected between the memory cell and the sense amplifier and sets the memory cell and the sense amplifier to a connected state or a disconnected state.

Description

Technical Field

[0001] Embodiments of the present invention relate to a magnetic storage device. Background Art

[0002] A magnetic storage device (MRAM: Magnetoresistive Random Access Memory) using a magnetoresistive effect element as a storage element is known. Summary of the Invention

[0003] Provided is a magnetic storage device capable of improving operating performance.

[0004] A magnetic storage device according to an embodiment includes: a storage cell including a variable resistance element and a selector element; a first power supply circuit that supplies a first voltage to the storage cell; a first switch connected between the storage cell and the first power supply circuit to set the storage cell to a connected state or a disconnected state; a second switch connected between a ground voltage node to which a ground voltage is supplied and the storage cell to set the ground voltage node to a connected state or a disconnected state; a comparator that compares the voltage of the storage cell with a second voltage lower than the first voltage and outputs a first signal when the voltage of the storage cell is lower than the second voltage; a delay circuit that delays the first signal output from the comparator by a first delay time and outputs a second signal; a sense amplifier that compares the voltage of the storage cell with a third voltage; and a third switch connected between the storage cell and the sense amplifier to set the storage cell to a connected state or a disconnected state. In a read operation, the first switch is set to a connected state, the second switch is set to a disconnected state, and the memory cell is charged to the first voltage. After the memory cell is charged to the first voltage, the first switch is set to a disconnected state, the second switch is set to a connected state, and the charge charged to the memory cell is discharged. Based on the second signal, the third switch is set to a disconnected state, and the voltage of the memory cell is compared with the third voltage by the sense amplifier to determine the data stored in the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 This is a block diagram showing the configuration of a storage system including a magnetic storage device according to an embodiment.

[0006] Figure 2 1 is a circuit diagram showing the configuration of a memory cell array included in the magnetic storage device according to the embodiment.

[0007] Figure 3 It is a perspective view showing the structure of a memory cell array included in the magnetic storage device according to the embodiment.

[0008] Figure 4 is a cross-sectional view of a memory cell in a memory cell array according to an embodiment.

[0009] Figure 5 This is a circuit diagram showing the configuration of a read circuit included in the magnetic storage device according to the embodiment.

[0010] Figure 6 A diagram showing a configuration example of a delay circuit in a readout circuit according to an embodiment.

[0011] Figure 7 Graphs showing changes in voltage of a memory cell during a read operation of the magnetic storage device according to the embodiment.

[0012] Figure 8 This is a flowchart showing the flow of a read operation of the magnetic storage device according to the embodiment.

[0013] Figures 9 to 12 1 is a diagram illustrating the state of switches and the flow of current during a read operation according to the embodiment.

[0014] Label Description

[0015] 1…magnetic storage device, 2…memory controller, 11…memory cell array, 12…input / output circuit, 13…control circuit, 14…row selection circuit, 15…column selection circuit, 16…write circuit, 17…read circuit, 20…conductive layer, 21…conductive layer, 30…lower electrode, 31…selector material layer, 32…upper electrode, 40…ferromagnetic layer, 41…non-magnetic layer, 42…ferromagnetic layer, 51…power supply circuit, 52…power supply circuit, 53…delay circuit, C1…capacitive element, R1…resistive element, S1…precharge switch, S2…synchronous switch, S3…sense amplifier switch DETAILED DESCRIPTION

[0016] The following embodiments are described with reference to the accompanying drawings. In the following description, components having the same function and configuration are denoted by common reference numerals. The embodiments described below illustrate devices and methods for embodying the technical concepts of the embodiments and do not limit the materials, shapes, structures, and arrangements of the components to those described below.

[0017] (Implementation Method)

[0018] First, an example of a storage system including the magnetic storage device according to the embodiment will be described. Figure 1: is a block diagram showing the configuration of a storage system MS including a magnetic storage device according to an embodiment.

[0019] like Figure 1 As shown, the storage system MS includes a magnetic storage device 1 and a memory controller 2. The magnetic storage device 1 operates under the control of the memory controller 2. The memory controller 2 can instruct the magnetic storage device 1 to perform read and write operations in response to a request (or command) from an external host device.

[0020] 1. Structure of magnetic storage device

[0021] Next, refer to Figure 1 , the structure of the magnetic storage device 1 according to the embodiment will be described.

[0022] Magnetic storage device 1 is a type of resistance change memory. It is a storage device that uses an MTJ (Magnetic Tunnel Junction) element as a memory cell. An MTJ element utilizes the magnetoresistance effect of a magnetic tunnel junction. An MTJ element is also called a magnetoresistance element.

[0023] The magnetic storage device 1 includes, for example, a memory cell array 11 , an input / output circuit 12 , a control circuit 13 , a row selection circuit 14 , a column selection circuit 15 , a write circuit 16 , and a read circuit 17 .

[0024] The memory cell array 11 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. Figure 1 Figure 1 shows a set of memory cells MC, word lines WL, and bit lines BL. Memory cells MC can store data in a nonvolatile manner. Memory cells MC are connected between a word line WL and a bit line BL and are associated with a row and column pair. A row address is assigned to the word line WL. A column address is assigned to the bit line BL. One or more memory cells MC can be specified by selecting a row and one or more columns.

[0025] The input / output circuit 12 is connected to the memory controller 2 and is responsible for communication between the magnetic storage device 1 and the memory controller 2. The input / output circuit 12 transmits the control signal CNT and command CMD received from the memory controller 2 to the control circuit 13. The input / output circuit 12 also transmits the row address and column address included in the address signal ADD received from the memory controller 2 to the row select circuit 14 and the column select circuit 15, respectively. The input / output circuit 12 transmits the data DAT (write data) received from the memory controller 2 to the write circuit 16. The input / output circuit 12 transmits the data DAT (read data) received from the read circuit 17 to the memory controller 2.

[0026] The control circuit 13 controls the overall operation of the magnetic storage device 1. For example, the control circuit 13 executes read operations, write operations, and the like based on the control signal CNT and the command CMD. For example, during a write operation, the control circuit 13 supplies a voltage and a control signal for writing data to the write circuit 16. Furthermore, during a read operation, the control circuit 13 supplies a voltage and a control signal for reading data to the read circuit 17.

[0027] The row selection circuit 14 is connected to a plurality of word lines WL. The row selection circuit 14 selects one word line WL specified by a row address. The selected word line WL is electrically connected to, for example, a driver circuit (not shown).

[0028] The column selection circuit 15 is connected to a plurality of bit lines BL. The column selection circuit 15 selects one or more bit lines BL specified by a column address. The selected bit line BL is electrically connected to, for example, a driver circuit (not shown).

[0029] The write circuit 16 supplies a voltage for writing data to the column select circuit 15 based on control of the control circuit 13 and data DAT (write data) received from the input / output circuit 12. When a current based on the write data flows through the memory cell MC, desired data is written to the memory cell MC.

[0030] The readout circuit 17 includes a sense amplifier. Under the control of the control circuit 13, the readout circuit 17 supplies voltages for data reading to the row select circuit 14 and the column select circuit 15. The sense amplifier determines the data stored in the selected memory cell MC based on the voltage or current of the word line WL and the selected memory cell MC. The readout circuit 17 then transmits data DAT (readout data) corresponding to the determination result to the input / output circuit 12. The readout circuit 17 will be described in detail later.

[0031] 1.1 Circuit Structure of Memory Cell Array

[0032] Reference Figure 2An example of a circuit configuration of the memory cell array 11 included in the magnetic storage device 1 according to the embodiment will be described. Figure 2 2 is a circuit diagram showing the configuration of a memory cell array 11 included in the magnetic storage device 1 . Figure 2 WL0 and WL1 among a plurality of word lines WL, and BL0 and BL1 among a plurality of bit lines BL are extracted and shown.

[0033] like Figure 2 As shown, one memory cell MC is connected between WL0 and BL0, between WL0 and BL1, between WL1 and BL0, and between WL1 and BL1. A plurality of memory cells MC are arranged in a matrix in the memory cell array 11, for example.

[0034] Each memory cell MC includes a variable resistance element VR and a selector element SE. The variable resistance element VR and the selector element SE are connected in series between the associated bit line BL and word line WL. For example, one end of the variable resistance element VR is connected to the bit line BL. The other end of the variable resistance element VR is connected to one end of the selector element SE. The other end of the selector element SE is connected to the word line WL. In addition, the connection relationship between the variable resistance element VR and the selector element SE between the bit line BL and the word line WL can also be reversed. That is, one end of the variable resistance element VR is connected to the word line WL, and the other end of the variable resistance element VR is connected to one end of the selector element SE. The other end of the selector element SE can also be connected to the bit line BL.

[0035] The variable resistance element VR corresponds to the MTJ element (i.e., magnetoresistive element). The variable resistance element VR can store data in a non-volatile manner based on its resistance value. For example, a memory cell MC including the variable resistance element VR in a high resistance state stores data "1." A memory cell MC including the variable resistance element VR in a low resistance state stores data "0." The allocation of data associated with the resistance value of the variable resistance element VR can also be set in other ways. The resistance state of the variable resistance element VR can change according to the current flowing through the variable resistance element VR.

[0036] The selector element SE is, for example, a bidirectional diode. The selector element SE functions as a selector that controls the supply of current to the associated variable resistance element VR. Specifically, the selector element SE included in a memory cell MC enters the OFF state when the voltage applied to the memory cell MC is lower than the threshold voltage of the selector element SE, and enters the ON state when the voltage applied to the memory cell MC is greater than the threshold voltage of the selector element SE. The selector element SE in the OFF state functions as an insulator with a high resistance value. When the selector element SE is in the OFF state, the flow of current between the word line WL and the bit line BL connected to the memory cell MC is suppressed. The selector element SE in the ON state functions as a conductor with a low resistance value. When the selector element SE is in the ON state, current flows between the word line WL and the bit line BL connected to the memory cell MC. In other words, the selector element SE can switch whether current flows or not according to the magnitude of the voltage applied to the memory cell MC, regardless of the direction of the current flow. Alternatively, other elements such as transistors may be used as the selector element SE.

[0037] 1.2 Structure of Memory Cell Array

[0038] Reference Figure 3 An example of the structure of the memory cell array 11 included in the magnetic storage device 1 according to the embodiment will be described. Figure 3 This is a stereoscopic diagram showing the structure of the memory cell array 11 of the magnetic storage device 1. In the following description, an XYZ orthogonal coordinate system is used. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the direction perpendicular to the surface of the semiconductor substrate used to form the magnetic storage device 1. The term "lower" and its derivatives and related terms indicate the position of the smaller coordinate on the Z axis. The term "upper" and its derivatives and related terms indicate the position of the larger coordinate on the Z axis. In the stereoscopic diagram, hatching is added as appropriate. The hatching added to the stereoscopic diagram is not necessarily related to the raw materials and characteristics of the components to which the hatching is added. In the stereoscopic diagram and the cross-sectional view, the illustration of the components such as the interlayer insulating film is omitted.

[0039] like Figure 3 As shown, the memory cell array 11 includes a plurality of conductive layers 20 , a plurality of conductive layers 21 , and a plurality of memory cells MC.

[0040] Each of the plurality of conductive layers 20 has a portion extending in the X direction. The plurality of conductive layers 20 are arranged in the Y direction and are separated from each other. Each conductive layer 20 serves as a word line WL.

[0041] Each of the plurality of conductive layers 21 has a portion extending in the Y direction. The plurality of conductive layers 21 are arranged in the X direction and are separated from each other. Each conductive layer 21 serves as a bit line BL.

[0042] A wiring layer comprising multiple conductive layers 21 is provided above a wiring layer comprising multiple conductive layers 20. A memory cell MC is provided at each intersection of the multiple conductive layers 20 and 21. In other words, each memory cell MC is provided between associated word lines WL and bit lines BL. Each memory cell MC has a columnar structure. In this example, a selector element SE is provided above the conductive layer 20. A variable resistance element VR is provided above the selector element SE. A conductive layer 21 is provided above the variable resistance element VR.

[0043] Furthermore, while the variable resistance element VR is illustrated as being positioned above the selector element SE, this is not limiting. Depending on the circuit configuration of the memory cell array 11, the variable resistance element VR may also be positioned below the selector element SE. Furthermore, other elements or conductive layers may be interposed between the memory cell MC and the conductive layer 20. Similarly, other elements or conductive layers may be interposed between the memory cell MC and the conductive layer 21. The conductive layers 20 and 21 may each be referred to as "wiring."

[0044] 1.3 Cross-sectional structure of storage unit

[0045] Reference Figure 4 An example of memory cells MC included in the memory cell array 11 included in the magnetic storage device 1 according to the embodiment will be described. Figure 4 1 is a cross-sectional view of a memory cell MC included in the memory cell array 11 .

[0046] like Figure 4 As shown, the memory cell MC has a structure in which a lower electrode 30 , a selector material layer 31 , an upper electrode 32 , a ferromagnetic layer 40 , a nonmagnetic layer 41 , and a ferromagnetic layer 42 are stacked in this order from the conductive layer 20 upward (in the Z direction).

[0047] That is, the lower electrode 30 is provided above the conductive layer 20 (in the Z direction). The selector material layer 31 is provided above the lower electrode 30. The upper electrode 32 is provided above the selector material layer 31. The ferromagnetic layer 40 is provided above the upper electrode 32. The nonmagnetic layer 41 is provided above the ferromagnetic layer 40. The ferromagnetic layer 42 is provided above the nonmagnetic layer 41. The conductive layer 21 is provided above the ferromagnetic layer 42.

[0048] In other words, the nonmagnetic layer 41 is provided between the ferromagnetic layer 40 and the ferromagnetic layer 42. The ferromagnetic layer 40 is provided between the nonmagnetic layer 41 and the upper electrode 32. The upper electrode 32 is provided between the ferromagnetic layer 40 and the selector material layer 31. The selector material layer 31 is provided between the upper electrode 32 and the lower electrode 30. The lower electrode 30 is provided between the selector material layer 31 and the conductive layer 20. Furthermore, the ferromagnetic layer 42 is provided between the nonmagnetic layer 41 and the conductive layer 21.

[0049] The set of the lower electrode 30 , the selector material layer 31 , and the upper electrode 32 corresponds to the selector element SE. The set of the ferromagnetic layer 40 , the nonmagnetic layer 41 , and the ferromagnetic layer 42 corresponds to the variable resistance element VR.

[0050] The ferromagnetic layers 40 and 42 are each made of a ferromagnetic material and have a magnetization direction perpendicular to the film surface. In the magnetic storage device 1, for example, the magnetization direction of the ferromagnetic layer 40 is fixed, while the magnetization direction of the ferromagnetic layer 42 is variable. In this case, the ferromagnetic layer 40 functions as a reference layer of the MTJ element, and the ferromagnetic layer 42 functions as a storage layer of the MTJ element. The non-magnetic layer 41 is made of an insulator such as MgO and functions as a tunnel barrier layer. The ferromagnetic layers 40 and 42, together with the non-magnetic layer 41, form a magnetic tunnel junction. Such a variable resistance element VR functions as a perpendicular magnetization type MTJ element that utilizes the TMR (tunneling magnetoresistance) effect.

[0051] The ferromagnetic layer 40 contains, for example, at least one element selected from iron (Fe), cobalt (Co), and nickel (Ni). The nonmagnetic layer 41 contains, for example, an oxide of at least one element or compound selected from magnesium (Mg), aluminum (Al), zinc (Zn), titanium (Ti), and LSM (Lanthanum-strontium-manganese). The ferromagnetic layer 42 contains, for example, at least one element selected from iron (Fe), cobalt (Co), and nickel (Ni).

[0052] The variable resistor element VR can assume either a low resistance state or a high resistance state depending on the relative relationship between the magnetization directions of the ferromagnetic layers 40 and 42. Furthermore, the variable resistor element VR stores data based on the magnetization direction of the ferromagnetic layer 42 (storage layer). For example, when the magnetization directions of the reference layer and the storage layer are antiparallel (AP state), the variable resistor element VR is in a high resistance state (data "1"). On the other hand, when the magnetization directions of the reference layer and the storage layer are parallel (P state), the variable resistor element VR is in a low resistance state (data "0").

[0053] In this example, the variable resistor element VR enters the AP state when a write current flows from the ferromagnetic layer 40 toward the ferromagnetic layer 42, and enters the P state when a write current flows from the ferromagnetic layer 42 toward the ferromagnetic layer 40. This writing method, which injects spin torque into the storage layer and reference layer by passing a write current through the variable resistor element VR to control the magnetization direction of the storage layer, is called a spin injection writing method. The variable resistor element VR is configured so that the magnetization direction of the ferromagnetic layer 40 does not change when a current of a magnitude sufficient to reverse the magnetization direction of the ferromagnetic layer 42 flows through the variable resistor element VR.

[0054] In addition, in this specification, "variable magnetization direction" means that the magnetization direction can be changed by the write current. "Fixed magnetization direction" means that the magnetization direction will not be changed by the write current. In the variable resistance element VR, the configuration of the storage layer and the reference layer can also be swapped. In addition, the variable resistance element VR can also have other layers. For example, the variable resistance element VR can also have a shift cancel layer (shift cancel layer) that suppresses the influence of the leakage magnetic field of the reference layer, an SAF (Synthetic Anti-Ferromagnetic) structure, etc. In the following, the memory cell MC including the variable resistance element VR in the AP state is referred to as the memory cell MC in the AP state, and the memory cell MC including the variable resistance element VR in the P state is referred to as the memory cell MC in the P state.

[0055] 1.4 Readout Circuit Configuration

[0056] Reference Figure 5 An example of the circuit configuration of the read circuit 17 included in the magnetic storage device 1 according to the embodiment will be described. Figure 5 2 is a circuit diagram showing the configuration of the readout circuit 17 . Figure 5 The read circuit 17 , a pair of bit lines BL and word lines WL included in the memory cell array 11 , and memory cells MC are shown.

[0057] like Figure 5As shown, the readout circuit 17 includes a sense amplifier SA, a comparator CP, a power supply circuit 51 , a power supply circuit 52 , a delay circuit 53 , a precharge switch S1 , a synchronous switch S2 , and a sense amplifier switch S3 .

[0058] The power supply circuit 51 is connected to the word line WL via the precharge switch S1. A node supplied with the ground voltage VSS is connected to the power supply circuit 51. Hereinafter, the node supplied with the ground voltage VSS is referred to as a ground voltage VSS node.

[0059] The word line WL is connected to the sense amplifier SA via the sense amplifier switch S3 , and the reference voltage Vref is supplied to the sense amplifier SA.

[0060] The word line WL is also connected to the negative input terminal (or inverting input terminal) of the comparator CP. The positive input terminal (or non-inverting input terminal) of the comparator CP is connected to the power supply circuit 52. The power supply circuit 52 is connected to the ground voltage VSS node.

[0061] The output terminal of the comparator CP is connected to the input terminal of the delay circuit 53. The output terminal of the delay circuit 53 is connected to the control terminal of the synchronous switch S2 and the control terminal of the sense amplifier switch S3.

[0062] The bit line BL is connected to a ground voltage VSS node via a synchronous switch S2 .

[0063] A memory cell MC is connected between a word line WL and a bit line BL. A memory cell MC includes a selector element SE and a variable resistance element VR connected in series. Specifically, one end of the selector element SE is connected to the word line WL, and the other end of the selector element SE is connected to one end of the variable resistance element VR. Furthermore, the other end of the variable resistance element VR is connected to the bit line BL.

[0064] When reading data stored in a memory cell MC, the sense amplifier SA is configured to compare the voltage Vm of the memory cell MC with a reference voltage Vref and determine the data stored in the memory cell MC based on the comparison result. Here, the voltage Vm of the memory cell MC can be understood as, for example, a voltage generated by the charge applied to the memory cell MC (or the selector element) or a voltage generated by the charge applied to the memory cell MC (or the selector element) and the word line WL. In all cases, the voltage of the memory cell MC is referred to below.

[0065] Reference voltage Vref is a voltage used as a threshold when determining whether data is "0" or "1." For example, when voltage Vm of memory cell MC is greater than or equal to Vref, sense amplifier SA outputs a voltage corresponding to data "1." On the other hand, when voltage Vm of memory cell MC is less than Vref, sense amplifier SA outputs a voltage corresponding to data "0." Sense amplifier SA is provided, for example, for each word line WL.

[0066] The comparator CP is configured to compare the voltage Vm of the memory cell MC with the comparison voltage Va during a read operation, and to determine the timing for discharge to begin in the memory cell MC (hereinafter referred to as the discharge start timing) based on the comparison result. The comparison voltage Va is a voltage used as a threshold in determining the discharge start timing. For example, when the voltage Vm of the memory cell MC is greater than Va, the comparator CP outputs a signal indicating that discharge has not yet begun, such as a low-level voltage (hereinafter referred to as "L"). On the other hand, when the voltage Vm of the memory cell MC is less than Va, the comparator CP outputs a signal indicating that discharge has begun, i.e., the discharge start timing, such as a high-level voltage (hereinafter referred to as "H") higher than "L". Furthermore, the comparator CP is provided, for example, for each word line WL.

[0067] The power supply circuit 51 supplies a precharge voltage Vpc to the memory cell MC, charging the memory cell MC, that is, the selector element SE and the word line WL to the precharge voltage Vpc. The precharge voltage Vpc is a voltage charged to the memory cell MC during a read operation.

[0068] The power supply circuit 52 supplies the comparator CP with a comparison voltage Va. The comparison voltage Va is a voltage lower than the precharge voltage Vpc and as close to the precharge voltage Vpc as possible. That is, Va=k·Vpc, k<1, and k is a value as close to 1 as possible.

[0069] After the memory cell MC is charged to the precharge voltage Vpc, the charge in the memory cell MC is discharged, and the voltage held in the memory cell MC when the discharge current stops flowing is set to the hold voltage Vh.

[0070] The delay circuit 53 delays the input voltage by a predetermined delay time and outputs the delayed voltage. Figure 6 is a diagram showing an example of the configuration of the delay circuit 53. For example, Figure 6 As shown in (a), the delay circuit 53 has an even number of inverters IV connected in series. Figure 6 As shown in (b), the structure includes two inverters IV, and a resistor element R1 and a capacitor element C1 connected between these inverters.

[0071] The delay time of the delay circuit 53 is set to be shorter than the time from the discharge start timing of the memory cell MC to the time when the voltage of the memory cell MC drops to the hold voltage Vh due to the discharge.

[0072] Furthermore, when the resistance component of the memory cell MC (or selector element SE) is R and the capacitance component is C, the delay time of the delay circuit 53 is set to be less than or equal to three times the time constant that can be expressed by RC. Furthermore, when the resistance component of the memory cell MC (or selector element SE) and the word line WL is R and the capacitance component is C, the delay time of the delay circuit 53 can also be set to be less than or equal to three times the time constant that can be expressed by RC.

[0073] The precharge switch S1 is a switch that switches between supplying and stopping the precharge voltage Vpc to the memory cell MC based on the control of the control circuit 13. The precharge switch S1 is connected between the word line WL (or the memory cell MC) and the power supply circuit 51. Based on the control of the control circuit 13, the precharge switch S1 sets the connection between the word line WL and the power supply circuit 51 to one of a connected state (or a closed state) and a disconnected state (or an open state). For example, when the precharge switch S1 is set to the connected state, the precharge voltage Vpc is supplied from the power supply circuit 51 to the memory cell MC. On the other hand, when the precharge switch S1 is set to the disconnected state, the supply of the precharge voltage Vpc from the power supply circuit 51 to the memory cell MC is stopped. The precharge switch S1 includes, for example, an n-type MOS field-effect transistor.

[0074] Synchronous switch S2 switches between discharging charge from memory cell MC and stopping the discharge of charge based on the output signal of delay circuit 53. Synchronous switch S2 is connected between bit line BL (or memory cell MC) and the ground voltage VSS node. Based on the output signal of delay circuit 53, synchronous switch S2 sets the connection between bit line BL and the ground voltage VSS node to either a connected state or a disconnected state. For example, when synchronous switch S2 is connected, a discharge current flows from memory cell MC to the ground voltage VSS node, discharging the charge stored in memory cell MC. On the other hand, when synchronous switch S2 is disconnected, no discharge current flows from memory cell MC to the ground voltage VSS node, stopping the discharge of the charge stored in memory cell MC. Synchronous switch S2 comprises, for example, an n-type MOS field-effect transistor.

[0075] The sense amplifier switch S3 is set to a disconnected state when data is being read from the memory cell MC based on the output signal of the delay circuit 53. On the other hand, it is set to a connected state when data is not being read from the memory cell MC. The sense amplifier switch S3 is connected between the word line WL (or the memory cell MC) and the sense amplifier SA. Based on the output signal of the delay circuit 53, the sense amplifier switch S3 sets the connection between the word line WL and the sense amplifier SA to either a connected state or a disconnected state. The sense amplifier switch S3 includes, for example, an n-type MOS field-effect transistor.

[0076] Furthermore, the relationship between the input and output of the positive and negative input terminals of comparator CP, the number of inverter stages included in delay circuit 53, and the polarity of the voltages at which precharge switch S1, synchronization switch S2, and sense amplifier switch S3 are connected or disconnected can be arbitrarily set as long as the configuration ensures proper operation. For example, if the relationship between the input and output of the positive and negative input terminals of comparator CP is reversed, the number of inverter stages in delay circuit 53 is set to an odd number.

[0077] 2. Reading Operation of Magnetic Storage Device

[0078] Reference Figure 7 , a read operation of the magnetic storage device 1 according to the embodiment will be described. Figure 7 1 is a diagram showing changes in the voltage of the memory cell MC during the read operation of the magnetic memory device 1. Figure 7 In FIG, the horizontal axis represents time, and the vertical axis represents the voltage Vm of the memory cell MC. The voltage Vm of the memory cell MC is the voltage charged to (or held by) the memory cell MC (or the selector element SE) and the word line WL, and is the voltage obtained by subtracting the voltage of the bit line BL from the voltage of the word line WL.

[0079] Here, the case of reading data stored in two memory cells MCa and MCb is described. Memory cells MCa and MCb can be the same memory cell read in different read cycles, or they can be different memory cells connected to different word lines. The read operation is controlled by control circuit 13 or read circuit 17.

[0080] When reading from memory cell MCa, read circuit 17 charges memory cell MCa to precharge voltage Vpc and then discharges the charge stored in memory cell MCa. The time when voltage Vm of memory cell MCa drops from voltage Vpc to voltage Va (i.e., time t2a) is detected as the time when discharge starts (i.e., discharge start timing). Read circuit 17 reads from memory cell MCa after a predetermined delay time (or discharge time) A has elapsed from the discharge start timing (i.e., time t3a).

[0081] When reading from memory cell MCb, read circuit 17 charges memory cell MCb to precharge voltage Vpc and then discharges the charge stored in memory cell MCb. The discharge start timing is detected as the time when voltage Vm of memory cell MCb drops from voltage Vpc to voltage Va (i.e., time t2b). Read circuit 17 reads from memory cell MCb after a predetermined delay time (or discharge time) B has elapsed from the discharge start timing (i.e., time t3b). Delay time B is the same as delay time A.

[0082] In response to time t2a when discharge starts from memory cell MCa or time t2b when discharge starts from memory cell MCb, read circuit 17 adjusts time t3a or t3b when read is performed, respectively, so that the time from the time discharge starts to the time read is the same. This reduces variations in the interval (or time) from the discharge start timing to the time read is performed (hereinafter referred to as the read execution timing) caused by variations in discharge start timing, and makes the interval from the discharge start timing the same (or constant). This allows the amount of discharge current from memory cells in the same resistance state (high resistance state or low resistance state) to be substantially the same, reducing read errors for memory cells in the same resistance state.

[0083] also, Figure 7 The voltages of memory cells MCa and MCb at times t4a and t4b are shown as the aforementioned hold voltage Vh. Hold voltage Vh is the voltage obtained by maintaining the connection state of synchronous switch S2 until the discharge current stops flowing during the discharge process after the memory cell MCa or MCb is charged to the precharge voltage Vpc. The hold voltages Vh of memory cells MCa and MCb are substantially equal.

[0084] The delay time A is set to a time (or interval) shorter than the time t2a - t4a. As described above, time t2a is the discharge start timing in the memory cell MCa. Time t4a is the time when the voltage Vm of the memory cell MCa reaches the hold voltage Vh.

[0085] Similarly, the delay time B is set to a time shorter than the time t2b-t4b. Time t2b is the discharge start timing in the memory cell MCb. Time t4b is the time when the voltage Vm of the memory cell MCb reaches the hold voltage Vh.

[0086] Below, refer to Figures 7 to 12 , the read operation of the magnetic storage device 1 according to the embodiment will be described in detail. Figure 8 This is a flowchart showing the flow of the read operation of the magnetic storage device 1 . Figures 9 to 12A diagram showing the state of switches and the flow of current during a read operation.

[0087] First, the read operation on the memory cell MCa will be described.

[0088] The read circuit 17 charges the memory cell MCa (and the word line WL) to the precharge voltage Vpc (S1). Specifically, at time t0, as shown in FIG. Figure 9 As shown, the control circuit 13 sets the precharge switch S1 and the sense amplifier switch S3 to a connected state (i.e., closed state) and sets the synchronization switch S2 to a disconnected state (i.e., open state). As a result, the precharge voltage Vpc is supplied from the power supply circuit 51 to the memory cell MCa (and the word line WL), and the memory cell MCa (and the word line WL) is charged to the precharge voltage Vpc.

[0089] Next, the read circuit 17 starts discharging the precharge voltage Vpc charged to the memory cell MCa (and the word line WL) (S2). Specifically, at time t1, as shown in FIG. Figure 10 As shown, the read circuit 17 sets the precharge switch S1 to the disconnected state and the synchronization switch S2 to the connected state. The sense amplifier switch S3 remains connected. As a result, the precharge voltage Vpc is stopped from being supplied to the memory cell MCa (and the word line WL). Figure 11 As shown, the discharge current Id starts to flow from the memory cell MCa (and the word line WL), and the voltage Vm of the memory cell MCa gradually drops from the precharge voltage Vpc.

[0090] Next, the read circuit 17 detects the timing when the voltage Vm of the memory cell MCa becomes lower than the voltage Va (i.e., the discharge start timing) (S3). Figure 11 As shown, discharge current Id flows from the memory cell (and word line WL) via bit line BL to the ground voltage VSS node. Furthermore, at time t2a, comparator CP detects the discharge start timing when voltage Vm of memory cell MCa falls below voltage Va. When voltage Vm of memory cell MCa falls below voltage Va, comparator CP switches its output signal from "L" to "H" and outputs "H."

[0091] Next, the read circuit 17 stops discharging from the memory cell MCa (and the word line WL) after a predetermined delay time A has elapsed from the discharge start timing of the memory cell MCa (S4). Specifically, the output signal "H" of the comparator CP is input to the delay circuit 53. The delay circuit 53 delays the received signal "H" by a predetermined delay time A and then outputs it to the control terminals of the synchronous switch S2 and the sense amplifier switch S3. Figure 12As shown, upon receiving an "H" signal, synchronous switch S2 transitions from a connected state to a disconnected state. Similarly, upon receiving an "H" signal, sense amplifier switch S3 transitions from a connected state to a disconnected state. Consequently, at time t3a, discharge from memory cell MCa (and word line WL) ceases, and the voltage Vm of memory cell MCa at this time is held by sense amplifier SA.

[0092] Furthermore, the read circuit 17 reads the memory cell MCa ( S5 ). Specifically, the sense amplifier SA compares the voltage Vm of the memory cell MCa at time t3a with the reference voltage Vref, and determines the data stored in the memory cell MCa based on the comparison result.

[0093] Next, the read operation on the memory cell MCb will be described.

[0094] The read circuit 17 charges the memory cell MCb (and the word line WL) to the precharge voltage Vpc (S1). Specifically, at time t0, as shown in FIG. Figure 9 As shown, the control circuit 13 connects the precharge switch S1 and the sense amplifier switch S3 and disconnects the synchronization switch S2. As a result, the power supply circuit 51 supplies the precharge voltage Vpc to the memory cell MCb (and the word line WL), and the memory cell MCb (and the word line WL) is charged to the precharge voltage Vpc.

[0095] Next, the read circuit 17 starts discharging the precharge voltage Vpc charged to the memory cell MCb (and the word line WL) (S2). Specifically, at time t1, as shown in FIG. Figure 10 As shown, the read circuit 17 sets the precharge switch S1 to the disconnected state and the synchronization switch S2 to the connected state. The sense amplifier switch S3 remains connected. As a result, the precharge voltage Vpc is stopped from being supplied to the memory cell MCb (and the word line WL). Figure 11 As shown, the discharge current Id starts to flow from the memory cell MCb (and the word line WL), and the voltage Vm of the memory cell MCb gradually drops from the precharge voltage Vpc.

[0096] Next, the read circuit 17 detects the discharge start timing (S3) when the voltage Vm of the memory cell MCb becomes lower than the voltage Va. Figure 11 As shown, discharge current Id flows from the memory cell (and word line WL) via bit line BL to the ground voltage VSS node. Furthermore, at time t2b, comparator CP detects the discharge start timing when voltage Vm of memory cell MCb falls below voltage Va. When voltage Vm of memory cell MCb falls below voltage Va, comparator CP switches its output signal from "L" to "H" and outputs "H."

[0097] Next, the read circuit 17 stops discharging from the memory cell MCb (and the word line WL) after a predetermined delay time B has elapsed from the discharge start timing of the memory cell MCb (S4). Specifically, the output signal "H" of the comparator CP is input to the delay circuit 53. The delay circuit 53 delays the received signal "H" by a predetermined delay time B and then outputs it to the control terminals of the synchronous switch S2 and the sense amplifier switch S3. Figure 12 As shown, upon receiving an "H" signal, synchronous switch S2 transitions from a connected state to a disconnected state. Similarly, upon receiving an "H" signal, sense amplifier switch S3 transitions from a connected state to a disconnected state. Consequently, at time t3b, discharge from memory cell MCb (and word line WL) ceases, and the voltage Vm of memory cell MCb at this time is held by sense amplifier SA.

[0098] Furthermore, the read circuit 17 reads data from the memory cell MCb ( S5 ). Specifically, the sense amplifier SA compares the voltage Vm of the memory cell MCb at time t3b with the reference voltage Vref, and determines the data stored in the memory cell MCb based on the comparison result.

[0099] As described above, read circuit 17 adjusts the read execution timing to time t3a or t3b, respectively, in accordance with the discharge start timing (time t2a) in memory cell MCa or the discharge start timing (time t2b) in memory cell MCb. This reduces variations in the delay time (or discharge time) from the discharge start timing to the read execution timing caused by variations in the discharge start timing. Consequently, the discharge time from the discharge start timing to the read execution timing in memory cells MCa and MCb can be made substantially equal.

[0100] 3. Effects of implementation methods

[0101] According to the magnetic storage device 1 of the embodiment, it is possible to reduce read errors in a read operation and improve operating performance.

[0102] Hereinafter, the effects of the embodiment will be described.

[0103] For example, when reading a memory cell in a magnetic storage device, when a command is issued to start discharging the voltage charged to the memory cell, the time from the issuance of the discharge start command to the actual start of discharge of the memory cell may vary depending on the read cycle or the memory cell being read. On the other hand, the time from the issuance of the discharge start command to the execution of the read is set to be constant. Therefore, even if the variable resistance element is in the same resistance state (high resistance state or low resistance state), the read voltage of the memory cell may vary depending on the timing of the actual start of discharge of the memory cell. As a result, read errors may sometimes occur.

[0104] To address this issue, the embodiment includes a circuit for detecting the discharge start timing in a memory cell MC (and word line WL), such as a comparator CP and a power supply circuit 52, and a delay circuit 53 for delaying the discharge start detection signal by a predetermined delay time (or discharge time). This allows the timing for executing a read operation to be set after the predetermined delay time has elapsed from the actual discharge start timing of the target memory cell MC. Therefore, even if the discharge start timing of a memory cell MC varies, the discharge time from the actual discharge start timing to the read execution timing can be set to a constant value. This reduces read errors during the read operation and improves operational performance.

[0105] Furthermore, in the embodiment, the amount of accumulated current flowing to the variable resistance element (for example, MTJ element) VR of the memory cell MC during the read operation can be reduced, thereby suppressing read disturb.

[0106] Furthermore, in the embodiment, as described above, the accumulated current flowing through the variable resistance element VR can be reduced, thereby reducing the current load on the variable resistance element VR during the read operation and extending the life of the variable resistance element VR before fatigue.

[0107] In addition, in an embodiment, in the read operation, during the discharge after the memory cell MC (and the word line WL) is charged to the precharge voltage Vpc, the discharge current Id is stopped midway and the reading is performed. Therefore, compared with the case where the reading is performed after the voltage of the memory cell MC reaches the holding voltage Vh without stopping the discharge current, the time required for the read operation can be shortened.

[0108] As described above, according to the magnetic storage device 1 of the embodiment, the operating performance can be improved.

[0109] 4. Others

[0110] In this specification, "connection" means electrical connection, and does not exclude the presence of other elements therebetween. The non-magnetic layer 41 may also be referred to as an "oxide layer." The elements contained in each layer of the MTJ element can be measured, for example, by electron energy loss spectroscopy (EELS) performed using a scanning transmission electron microscope (STEM).

[0111] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and / or their variations are included within the scope and spirit of the invention, and are included within the invention set forth in the claims and their equivalents.

Claims

1. A magnetic storage device comprising: a memory cell comprising a variable resistance element and a selector element; a first power supply circuit for supplying a first voltage to the memory cell; a first switch connected between the storage unit and the first power supply circuit, and configured to set the storage unit and the first power supply circuit to either a connected state or a disconnected state; a second switch connected between a ground voltage node to which a ground voltage is supplied and the memory cell, and setting the connection between the ground voltage node and the memory cell to either a connected state or a disconnected state; a comparator that compares the voltage of the memory cell with a second voltage lower than the first voltage and outputs a first signal when the voltage of the memory cell is lower than the second voltage; a delay circuit that delays the first signal output from the comparator by a first delay time and outputs a second signal; a sense amplifier that compares the voltage of the memory cell with a third voltage; as well as a third switch connected between the memory cell and the sense amplifier, and setting the memory cell and the sense amplifier to either a connected state or a disconnected state; In the reading action, The first switch is set to a connected state, the second switch is set to a disconnected state, and the memory cell is charged to the first voltage. After the memory cell is charged to the first voltage, the first switch is set to a disconnected state and the second switch is set to a connected state, and the charge charged in the memory cell is discharged. The third switch is set to an OFF state according to the second signal, and the voltage of the memory cell is compared with the third voltage by the sense amplifier to determine data stored in the memory cell.

2. The magnetic storage device according to claim 1, The second switch is set to an OFF state according to the second signal, and discharge of the charge stored in the memory cell is stopped.

3. The magnetic storage device according to claim 1, After the memory cell is charged to the first voltage, the second switch is set to a connected state to discharge the charge charged in the memory cell. When the discharge stops, the voltage held in the memory cell is set to a fourth voltage. The second voltage is lower than the first voltage and higher than the fourth voltage.

4. The magnetic storage device according to claim 3, The first delay time of the delay circuit is shorter than a time period from when the comparator outputs the first signal to when the voltage of the memory cell drops to the fourth voltage due to the discharge.

5. The magnetic storage device according to claim 1, When the resistance component of the memory cell is R and the capacitance component is C, The first delay time of the delay circuit is equal to or less than three times a time constant that can be expressed by RC.

6. The magnetic storage device according to claim 1, further comprising a first wiring and a second wiring, The memory cell is connected between the first wiring and the second wiring. The first wiring is connected to the first switch, and the second wiring is connected to the second switch. The voltage of the memory cell includes a voltage held by the first wiring.

7. The magnetic storage device according to claim 6, When the resistance component of the memory cell and the first wiring is R and the capacitance component is C, The first delay time of the delay circuit is equal to or less than three times a time constant that can be expressed by RC.

8. The magnetic storage device according to claim 1, In the read operation for the first and second storage cells, When the time from when the comparator compares the voltage of the first storage cell with the second voltage and outputs the first signal to when the third switch is set to the cut-off state is defined as a first time, and the time from when the comparator compares the voltage of the second storage cell with the second voltage and outputs the first signal to when the third switch is set to the cut-off state is defined as a second time, The first time is equal to the second time.

9. The magnetic storage device according to claim 1, further comprising: a first wiring line extending in a first direction and connected to the selector element; and a second wiring extending in a second direction intersecting the first direction and connected to the variable resistance element; The first switch is connected between the first wiring and the first power supply circuit. The second switch is connected between the second wiring and the ground voltage node. When the first switch is set to the connected state, the first voltage is supplied from the first power supply circuit to the selector element and the first wiring, and the selector element and the first wiring are charged to the first voltage. When the second switch is set to the connected state, the charge stored in the selector element and the first wiring is discharged via the second wiring.

10. The magnetic storage device according to claim 1, The selector element includes a bidirectional diode.

11. The magnetic storage device according to claim 1, The first switch, the second switch, and the third switch include MOS field effect transistors.

12. The magnetic storage device according to claim 1, The delay circuit includes an even number of inverters connected in series.

13. The magnetic storage device according to claim 1, The delay circuit includes a first inverter, a second inverter, and a resistor and a capacitor connected between the first inverter and the second inverter.

14. The magnetic storage device according to claim 1, The variable resistance element includes an MTJ element, ie, a magnetic tunnel junction element.

15. The magnetic storage device according to claim 14, The MTJ element includes a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer disposed between the first ferromagnetic layer and the second ferromagnetic layer.

16. The magnetic storage device according to claim 15, The first ferromagnetic layer contains at least one element selected from iron (Fe), cobalt (Co), and nickel (Ni). The non-magnetic layer comprises an oxide of at least one element or compound selected from magnesium (Mg), aluminum (Al), zinc (Zn), titanium (Ti), and lanthanum strontium manganese (LSM). The second ferromagnetic layer includes at least one element selected from the group consisting of iron (Fe), cobalt (Co), and nickel (Ni).

17. The magnetic storage device according to claim 15, The first ferromagnetic layer and the second ferromagnetic layer each have an easy magnetization axis direction perpendicular to the film surface. The magnetization direction of the first ferromagnetic layer is fixed. The second ferromagnetic layer is configured so that its magnetization direction is more easily reversed than that of the first ferromagnetic layer.

18. The magnetic storage device according to claim 1, further comprising: a first conductive layer provided to extend in a first direction; and a second conductive layer extending in a second direction intersecting the first direction and provided apart from the first conductive layer; The memory cell is provided between the first conductive layer and the second conductive layer.

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