Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a substrate, the substrate comprises a first region and a second region, a plurality of first metal layers are formed in the substrate, and mask layers are formed on the surfaces of the substrate and the first metal layers; a first opening for exposing the first metal layer in the first region is formed in the mask layer; the bottom electrode is located in the first opening and does not fill the first opening; the resistance change layer is located on the surface of the bottom electrode and the side wall of the first opening and does not fill the first opening; the top electrode is located on the surface of the resistive layer and fills the first opening, and the bottom electrode, the resistive layer and the top electrode form a memory unit. The problem of poor etching precision can be avoided, and the quality of the interlayer dielectric layer can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The current method for forming an RRAM structure generally involves first depositing the bottom electrode, resistive layer, heat exchange layer (TEL), and top electrode materials, and then etching the bottom electrode, resistive layer, heat exchange layer (TEL), and top electrode materials to form a memory cell consisting of the bottom electrode, resistive layer, heat exchange layer (TEL), and top electrode. However, due to the relatively thick thickness of the bottom electrode, resistive layer, heat exchange layer (TEL), and top electrode, they block the overlay alignment signals of the previous layer, resulting in poor etching process accuracy. In addition, the relatively thick thickness of the bottom electrode, resistive layer, heat exchange layer (TEL), and top electrode easily creates voids in the interlayer dielectric layer when forming the dielectric layer covering the memory cell.

[0003] Therefore, it is necessary to provide a more effective and reliable technical solution to avoid the problem of poor etching accuracy and improve the quality of the interlayer dielectric layer. Summary of the Invention

[0004] The present application provides a semiconductor structure and a method for forming the same, which can avoid the problem of poor etching accuracy and improve the quality of the interlayer dielectric layer.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region, a plurality of first metal layers formed in the substrate, a mask layer formed on the surfaces of the substrate and the first metal layers, a first opening formed in the mask layer exposing the first metal layer in the first region; forming a bottom electrode that does not fill the first opening in the first opening; and sequentially forming a resistive layer and a top electrode that fills the first opening on the surface of the bottom electrode and on the sidewalls of the first opening, the bottom electrode, the resistive layer, and the top electrode constituting a memory cell.

[0006] In some embodiments of the present application, the base includes a semiconductor substrate and a dielectric layer located on a surface of the semiconductor substrate, and the first metal layer is located in the dielectric layer.

[0007] In some embodiments of the present application, the thickness of the mask layer is equal to the sum of the thicknesses of the bottom electrode, the resistive layer, and the top electrode.

[0008] In some embodiments of the present application, the method for forming a bottom electrode that does not fill the first opening in the first opening includes: forming a bottom electrode material layer that does not fill the first opening at the bottom and side walls of the first opening and on the surface of the mask layer; forming a sacrificial layer that fills the first opening on the surface of the bottom electrode material layer; grinding the sacrificial layer and the bottom electrode material layer until the surface of the mask layer is exposed; etching the bottom electrode material layer on the side walls of the first opening to form the bottom electrode, and the surface of the bottom electrode is flush with the bottom surface of the sacrificial layer; and removing the sacrificial layer.

[0009] In some embodiments of the present application, in the etching process of etching the bottom electrode material layer on the sidewall of the first opening to form the bottom electrode, the etching selectivity of the etching process to the bottom electrode material layer and the mask layer and the sacrificial layer is greater than 10.

[0010] In some embodiments of the present application, the method of sequentially forming a resistive layer on the surface of the bottom electrode and the sidewall of the first opening and a top electrode filling the first opening includes: sequentially forming a resistive material layer and a top electrode material layer filling the first opening on the surface of the bottom electrode, the sidewall of the first opening and the surface of the mask layer; and grinding the top electrode material layer and the resistive material layer until the surface of the mask layer is exposed to form the resistive layer and the top electrode.

[0011] In some embodiments of the present application, the method for forming the semiconductor structure also includes: forming an interlayer dielectric layer covering the mask layer and the memory unit on the surface of the mask layer, a second opening and a third opening respectively formed in the interlayer dielectric layer exposing the top electrode and the first metal layer in the second region; and forming a second metal layer electrically connecting the top electrode and the first metal layer in the second region in the second opening and the third opening respectively.

[0012] In some embodiments of the present application, the interlayer dielectric layer has a double-layer structure, and the interlayer dielectric layer includes a TEOS layer and a BD layer sequentially located on the surface of the mask layer and covering the mask layer and the memory unit.

[0013] Another aspect of the present application also provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region, a plurality of first metal layers formed in the substrate, a mask layer formed on the surface of the substrate and the first metal layer, a first opening formed in the mask layer exposing the first metal layer in the first region; a bottom electrode, located in the first opening but not filling the first opening; a resistive layer, located on the surface of the bottom electrode and the sidewall of the first opening and not filling the first opening; a top electrode, located on the surface of the resistive layer and filling the first opening, wherein the bottom electrode, the resistive layer and the top electrode constitute a memory cell.

[0014] In some embodiments of the present application, the base includes a semiconductor substrate and a dielectric layer located on a surface of the semiconductor substrate, and the first metal layer is located in the dielectric layer.

[0015] In some embodiments of the present application, the thickness of the mask layer is equal to the sum of the thicknesses of the bottom electrode, the resistive layer, and the top electrode.

[0016] In some embodiments of the present application, the material of the bottom electrode includes titanium nitride, and the material of the mask layer includes NDC.

[0017] In some embodiments of the present application, the semiconductor structure further includes: an interlayer dielectric layer located on the surface of the mask layer, covering the mask layer and the memory unit, and a second opening and a third opening respectively formed in the interlayer dielectric layer for exposing the top electrode and the first metal layer in the second region; a second metal layer located in the second opening and the third opening, respectively electrically connecting the top electrode and the first metal layer in the second region.

[0018] In some embodiments of the present application, the interlayer dielectric layer has a double-layer structure, and the interlayer dielectric layer includes a TEOS layer and a BD layer sequentially located on the surface of the mask layer and covering the mask layer and the memory unit.

[0019] The present application provides a semiconductor structure and a method for forming the same, which can avoid the problem of poor etching accuracy and improve the quality of the interlayer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The following figures describe in detail exemplary embodiments disclosed in this application. Like reference numerals denote similar structures throughout the several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are provided for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0021] in:

[0022] Figures 1 to 10 Schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0024] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0025] Figures 1 to 10 The following is a structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail with reference to the accompanying drawings.

[0026] refer to Figure 1 As shown, a substrate is provided, which includes a first area 101 and a second area 102, and several first metal layers 120 are formed in the substrate. A mask layer 130 is formed on the surface of the substrate and the first metal layer 120, and a first opening 131 is formed in the mask layer 130 to expose the first metal layer 120 in the first area 101.

[0027] In some embodiments of the present application, the base includes a semiconductor substrate 100 and a dielectric layer 110 located on the surface of the semiconductor substrate 100, and the first metal layer 120 is located in the dielectric layer 110. The semiconductor substrate 100 may include active devices formed in a semiconductor front-end process.

[0028] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0029] In some embodiments of the present application, the first region 101 is used to form a memory cell, and the second region 102 is used to form a metal interconnection structure.

[0030] In some embodiments of the present application, the dielectric layer 110 is made of silicon oxide or the like. The dielectric layer 110 is used to form a metal interconnect structure in a portion of a back-end process. The metal interconnect structure is composed of several metal layers and vias, and the first metal layer 120 is any metal layer (except the last metal layer) in the metal interconnect structure in the back-end process.

[0031] In some embodiments of the present application, the number of the first metal layers 120 can be arbitrary. The present application only takes one first metal layer 120 in the first region 101 and one first metal layer 120 in the second region 102 as an example.

[0032] Continue to refer Figure 1 As shown, a mask layer 130 is formed on the surface of the substrate (specifically, the dielectric layer 110) and the first metal layer 120. First openings 131 are formed in the mask layer 130 to expose the first metal layer 120 in the first region 101. The first openings 131 are used to form memory cells, so the number and size of the first openings 131 are set according to the number and size of the required memory cells.

[0033] In some embodiments of the present application, the material of the mask layer 130 includes NDC (nitrogen-doped silicon carbide). In some embodiments of the present application, the thickness of the mask layer 130 can be consistent with the required thickness of the memory cell, that is, the thickness of the mask layer 130 is equal to the sum of the thicknesses of the bottom electrode, the resistive layer, and the top electrode, for example, approximately 60 nanometers or 55 to 65 nanometers. However, considering that the mask layer 130 may be damaged in subsequent processes, the thickness of the mask layer 130 can be increased according to the process, for example, to 70 to 80 nanometers.

[0034] refer to Figures 2 to 6 As shown, a bottom electrode 141 is formed in the first opening 131 , but does not completely fill the first opening 131 .

[0035] refer to Figure 2 As shown, a bottom electrode material layer 141a that does not fill the first opening 131 is formed on the bottom and sidewalls of the first opening 131 and the surface of the mask layer 130. The material of the bottom electrode material layer 141a includes titanium nitride.

[0036] refer to Figure 3 As shown, a sacrificial layer 150 is formed on the surface of the bottom electrode material layer 141a to fill the first opening 131. The material of the sacrificial layer 150 includes silicon oxide.

[0037] refer to Figure 4 As shown, the sacrificial layer 150 and the bottom electrode material layer 141 a are polished by a chemical mechanical polishing process until the surface of the mask layer 130 is exposed.

[0038] refer to Figure 5 As shown, the bottom electrode material layer 141 a on the sidewall of the first opening 131 is etched to form the bottom electrode 141 , and the surface of the bottom electrode 141 is flush with the bottom surface of the sacrificial layer 150 .

[0039] In some embodiments of the present application, in the etching process of etching the bottom electrode material layer on the sidewall of the first opening to form the bottom electrode, the etching selectivity of the etching process to the bottom electrode material layer and the mask layer and the sacrificial layer is greater than 10.

[0040] In some embodiments of the present application, the material of the bottom electrode material layer includes titanium nitride, the material of the sacrificial layer includes silicon oxide, and the material of the mask layer includes NDC.

[0041] In the present application, a portion of the bottom electrode material layer is removed by selective etching. This is a self-aligned etching process and does not require a photomask, thus saving a photomask.

[0042] refer to Figure 6 The sacrificial layer 150 is removed.

[0043] The technical solution of this application is Figures 2 to 6 The bottom electrode 141 is formed by the method shown. The surface of the bottom electrode 141 formed in this way is smoother, and no residue remains on the sidewall of the first opening 131 , thereby improving the reliability of the memory.

[0044] refer to Figure 7 and Figure 8 As shown, a resistive layer 142 and a top electrode 143 filling the first opening 131 are sequentially formed on the surface of the bottom electrode 141 and the sidewall of the first opening 131 . The bottom electrode 141 , the resistive layer 142 and the top electrode 143 constitute a memory unit 140 .

[0045] refer to Figure 7 As shown, a resistive material layer 142a and a top electrode material layer 143a filling the first opening 131 are sequentially formed on the surface of the bottom electrode 141, the sidewalls of the first opening 131, and the surface of the mask layer 130. The resistive material layer 142a includes HfO2 and Ta2O5. The top electrode material layer 143a includes TiN, TaN, W, Ti, Ta, Al, Ir, Cu, etc.

[0046] In some embodiments of the present application, a heat exchange material layer 144a may be formed between the resistive material layer 142a and the top electrode material layer 143a. The heat exchange material layer 144a may be made of TaOx, Ta, etc., where x is any positive integer.

[0047] refer to Figure 8 As shown, the top electrode material layer 143 a and the resistive material layer 142 a are ground until the surface of the mask layer 130 is exposed to form the resistive layer 142 and the top electrode 143 .

[0048] In some embodiments of the present application, a heat exchange layer 144 may be formed between the resistive layer 142 and the top electrode 143. The heat exchange layer 144 is also part of the memory unit 140. The heat exchange layer is made of TaOx, Ta, etc., where x is any positive integer.

[0049] In the technical solution of the present application, the memory cells 140 are formed in the first openings 131, eliminating the need for photolithography, thereby avoiding the problem of poor etching accuracy. Furthermore, the mask layer 130 has been pre-formed to fill the spaces between adjacent memory cells 140, thereby preventing the formation of voids between adjacent memory cells 140.

[0050] refer to Figure 9 As shown, an interlayer dielectric layer 160 is formed on the surface of the mask layer 130 to cover the mask layer 130 and the memory cell 140. A second opening 171 and a third opening 172 are formed in the interlayer dielectric layer 160 to expose the top electrode 143 and the first metal layer 120 in the second region 102, respectively. The second opening 171 and the third opening 172 can be formed by simultaneous etching or by step etching.

[0051] In some embodiments of the present application, the interlayer dielectric layer 160 has a double-layer structure, and includes a TEOS layer 161 and a BD layer 162, which are sequentially located on the surface of the mask layer 130 and cover the mask layer 130 and the memory cell 140. TEOS refers to silicon oxide formed by a TEOS process (tetraethyl orthosilicate), and BD refers to black diamond.

[0052] refer to Figure 10 As shown, a second metal layer 180 electrically connecting the top electrode 141 and the first metal layer 120 in the second region 102 is formed in the second opening 171 and the third opening 172. The second metal layer 180 and the first metal layer 120 in the second region 102 constitute a metal interconnect structure of the logic region.

[0053] In some embodiments of the present application, the material of the second metal layer 180 includes tungsten or copper.

[0054] The present application provides a method for forming a semiconductor structure, which can avoid the problem of poor etching accuracy and improve the quality of an interlayer dielectric layer.

[0055] The embodiment of the present application further provides a semiconductor structure, referring to Figure 10As shown, it includes: a substrate, the substrate includes a first area 101 and a second area 102, a plurality of first metal layers 120 are formed in the substrate, a mask layer 130 is formed on the surface of the substrate and the first metal layer 120, and a first opening 131 is formed in the mask layer 130 to expose the first metal layer 120 in the first area 101; a bottom electrode 141 is located in the first opening 131 but does not fill the first opening 131; a resistive layer 142 is located on the surface of the bottom electrode 141 and the sidewall of the first opening 131 and does not fill the first opening 131; a top electrode 143 is located on the resistive layer 142 The surface is filled with the first opening 131, and the bottom electrode 141, the resistive layer 142 and the top electrode 143 constitute a memory unit 140; the interlayer dielectric layer 160 is located on the surface of the mask layer 130 and covers the mask layer 130 and the memory unit 140, and the interlayer dielectric layer 160 is respectively formed with a second opening 171 and a third opening 172 exposing the top electrode 143 and the first metal layer 120 in the second region 102; the second metal layer 180 is located in the second opening 171 and the third opening 172 and is respectively electrically connected to the top electrode 143 and the first metal layer 120 in the second region 102.

[0056] In some embodiments of the present application, the base includes a semiconductor substrate 100 and a dielectric layer 110 located on the surface of the semiconductor substrate 100, and the first metal layer 120 is located in the dielectric layer 110. The semiconductor substrate 100 may include active devices formed in a semiconductor front-end process.

[0057] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0058] In some embodiments of the present application, the first region 101 is used to form a memory cell, and the second region 102 is used to form a metal interconnection structure.

[0059] In some embodiments of the present application, the dielectric layer 110 is made of silicon oxide or the like. The dielectric layer 110 is used to form a metal interconnect structure in a portion of a back-end process. The metal interconnect structure is composed of several metal layers and vias, and the first metal layer 120 is any metal layer (except the last metal layer) in the metal interconnect structure in the back-end process.

[0060] In some embodiments of the present application, the number of the first metal layers 120 can be arbitrary. The present application only takes one first metal layer 120 in the first region 101 and one first metal layer 120 in the second region 102 as an example.

[0061] Continue to refer Figure 1 As shown, a mask layer 130 is formed on the surface of the substrate (specifically, the dielectric layer 110) and the first metal layer 120. First openings 131 are formed in the mask layer 130 to expose the first metal layer 120 in the first region 101. The first openings 131 are used to form memory cells, so the number and size of the first openings 131 are set according to the number and size of the required memory cells.

[0062] In some embodiments of the present application, the material of the mask layer 130 includes NDC (nitrogen-doped silicon carbide). In some embodiments of the present application, the thickness of the mask layer 130 can be consistent with the required thickness of the memory cell, that is, the thickness of the mask layer 130 is equal to the sum of the thicknesses of the bottom electrode 141, the resistive layer 142, and the top electrode 143, for example, approximately 60 nanometers or 55 to 65 nanometers. However, considering that the mask layer 130 may be damaged in subsequent processes, the thickness of the mask layer 130 can be increased according to the process, for example, to 70 to 80 nanometers.

[0063] In some embodiments of the present application, the material of the bottom electrode 141 includes titanium nitride, the material of the resistive layer 142 includes HfO2 or Ta2O5, and the material of the top electrode 143 includes TiN, TaN, W, Ti, Ta, Al, Ir, Cu, etc.

[0064] In some embodiments of the present application, a heat exchange layer 144 may be formed between the resistive layer 142 and the top electrode 143. The heat exchange layer 144 is also part of the memory unit 140. The heat exchange layer is made of TaOx, Ta, etc., where x is any positive integer.

[0065] In the technical solution of the present application, the memory cells 140 are formed in the first openings 131, eliminating the need for photolithography, thereby avoiding the problem of poor etching accuracy. Furthermore, the mask layer 130 has been pre-formed to fill the spaces between adjacent memory cells 140, thereby preventing the formation of voids between adjacent memory cells 140.

[0066] In some embodiments of the present application, the interlayer dielectric layer 160 has a double-layer structure, and includes a TEOS layer 161 and a BD layer 162, which are sequentially located on the surface of the mask layer 130 and cover the mask layer 130 and the memory cell 140. TEOS refers to silicon oxide formed by a TEOS process (tetraethyl orthosilicate), and BD refers to black diamond.

[0067] In some embodiments of the present application, the material of the second metal layer 180 includes tungsten or copper.

[0068] The present application provides a semiconductor structure and a method for forming the same, which can avoid the problem of poor etching accuracy and improve the quality of the interlayer dielectric layer.

[0069] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0070] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may also be present.

[0071] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0072] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0073] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, a plurality of first metal layers formed in the substrate, a mask layer formed on surfaces of the substrate and the first metal layers, the mask layer having a first opening formed therein exposing the first metal layers in the first region; forming a bottom electrode in the first opening that does not completely fill the first opening; A resistive layer and a top electrode filling the first opening are sequentially formed on the surface of the bottom electrode and the sidewall of the first opening. The bottom electrode, the resistive layer and the top electrode constitute a memory unit.

2. The method for forming a semiconductor structure according to claim 1, wherein: The base includes a semiconductor substrate and a dielectric layer located on the surface of the semiconductor substrate, and the first metal layer is located in the dielectric layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the mask layer is equal to the sum of the thicknesses of the bottom electrode, the resistive layer, and the top electrode.

4. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming a bottom electrode in the first opening that does not completely fill the first opening includes: forming a bottom electrode material layer that does not fill the first opening on the bottom and sidewalls of the first opening and on the surface of the mask layer; forming a sacrificial layer filling the first opening on the surface of the bottom electrode material layer; Grinding the sacrificial layer and the bottom electrode material layer until the surface of the mask layer is exposed; Etching the bottom electrode material layer on the sidewall of the first opening to form the bottom electrode, wherein the surface of the bottom electrode is flush with the bottom surface of the sacrificial layer; The sacrificial layer is removed.

5. The method for forming a semiconductor structure according to claim 4, wherein: In an etching process for etching the bottom electrode material layer on the sidewall of the first opening to form the bottom electrode, an etching selectivity ratio of the etching process to the bottom electrode material layer, the mask layer, and the sacrificial layer is greater than 10.

6. The method for forming a semiconductor structure according to claim 1, wherein: The method of sequentially forming a resistive switching layer on the surface of the bottom electrode and the sidewall of the first opening and a top electrode filling the first opening includes: forming a resistive material layer and a top electrode material layer filling the first opening in sequence on the surface of the bottom electrode, the sidewall of the first opening and the surface of the mask layer; The top electrode material layer and the resistive material layer are ground until the surface of the mask layer is exposed to form the resistive layer and the top electrode.

7. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: forming an interlayer dielectric layer covering the mask layer and the memory cell on a surface of the mask layer, wherein a second opening and a third opening exposing the top electrode and the first metal layer in the second region are respectively formed in the interlayer dielectric layer; A second metal layer electrically connecting the top electrode and the first metal layer in the second region is formed in the second opening and the third opening, respectively.

8. The method for forming a semiconductor structure according to claim 7, wherein: The interlayer dielectric layer is a double-layer structure, and the interlayer dielectric layer includes a TEOS layer and a BD layer which are sequentially located on the surface of the mask layer and cover the mask layer and the memory unit.

9. A semiconductor structure, characterized in that include: A substrate, the substrate comprising a first region and a second region, a plurality of first metal layers formed in the substrate, a mask layer formed on surfaces of the substrate and the first metal layers, the mask layer having a first opening formed therein to expose the first metal layers in the first region; a bottom electrode, located in the first opening but not completely filling the first opening; a resistive switching layer, located on the surface of the bottom electrode and the sidewall of the first opening and not filling the first opening; A top electrode is located on the surface of the resistive layer and fills the first opening. The bottom electrode, the resistive layer and the top electrode constitute a memory unit.

10. The semiconductor structure according to claim 9, wherein: The base includes a semiconductor substrate and a dielectric layer located on the surface of the semiconductor substrate, and the first metal layer is located in the dielectric layer.

11. The semiconductor structure according to claim 9, wherein: The thickness of the mask layer is equal to the sum of the thicknesses of the bottom electrode, the resistive layer, and the top electrode.

12. The semiconductor structure according to claim 9, wherein The material of the bottom electrode includes titanium nitride, and the material of the mask layer includes NDC.

13. The semiconductor structure according to claim 9, wherein: Also includes: an interlayer dielectric layer, located on a surface of the mask layer and covering the mask layer and the memory cell, wherein a second opening and a third opening are formed in the interlayer dielectric layer, respectively exposing the top electrode and the first metal layer in the second region; The second metal layer is located in the second opening and the third opening and is electrically connected to the top electrode and the first metal layer in the second region respectively.

14. The semiconductor structure according to claim 13, wherein: The interlayer dielectric layer is a double-layer structure, and the interlayer dielectric layer includes a TEOS layer and a BD layer which are sequentially located on the surface of the mask layer and cover the mask layer and the memory unit.

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